Ultrafast, 4 ns Single-Supply Comparators Data Sheet AD8611/AD8612 FEATURES PIN CONFIGURATIONS 4 ns propagation delay at 5 V V+ 1 8 QA Single-supply operation: 3 V to 5 V IN+ 2 AD8611 7 QA 1La0t0c hM fHuzn icntpiount INV–– 34 (NToOt Pto V SIEcWale) 65 GLANTDCH 06010-001 Figure 1. 8-Lead Narrow Body SOIC APPLICATIONS (R-8) High speed timing V+ 1 8 QA Clock recovery and clock distribution AD8611 IN+ 2 7 QA Line receivers TOP VIEW DPhigaistea ld ceotmecmtourns ications INV–– 34 (Not to Scale) 65 GLANTDCH 06010-002 Figure 2. 8-Lead MSOP High speed sampling (RM-8) Read channel detection PCMCIA cards QA 1 14 QB Zero-crossing detector QA 2 13 QB High speed analog-to-digital converter (ADC) GND 3 AD8612 12 GND TOP VIEW Upgrade for LT1394 and LT1016 designs LEA 4 (Not to Scale) 11 LEB V– 5 10 V+ INA– 6 9 INB– INA+ 7 8 INB+ 06010-003 Figure 3. 14-Lead TSSOP (RU-14) GENERAL DESCRIPTION The AD8611/AD8612 are single and dual 4 ns comparators The AD8611 has the same pinout as the LT1016 and LT1394, with latch function and complementary output. The latch is not with lower supply current and a wider common-mode input functional if V is less than 4.3 V. range, which includes the negative supply rail. CC Fast 4 ns propagation delay makes the AD8611/AD8612 good The AD8611/AD8612 are specified over the industrial temper- choices for timing circuits and line receivers. Propagation delays ature range (−40°C to +85°C). The AD8611 is available in both for rising and falling signals are closely matched and tracked over 8-lead MSOP and narrow 8-lead SOIC surface-mount packages. temperature. This matched delay makes the AD8611/AD8612 The AD8612 is available in a 14-lead TSSOP surface-mount good choices for clock recovery because the duty cycle of the package. output matches the duty cycle of the input. Rev. B Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Tel: 781.329.4700 ©2000–2016 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com

AD8611/AD8612 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Optimizing High Speed Performance ..................................... 10 Applications ....................................................................................... 1 Upgrading the LT1394 and LT1016 ......................................... 10 Pin Configurations ........................................................................... 1 Maximum Input Frequency and Overdrive ............................ 10 General Description ......................................................................... 1 Output Loading Considerations ............................................... 10 Revision History ............................................................................... 2 Using the Latch to Maintain a Constant Output .................... 11 Specifications ..................................................................................... 3 Input Stage and Bias Currents .................................................. 11 Absolute Maximum Ratings ............................................................ 5 Using Hysteresis ......................................................................... 11 Thermal Resistance ...................................................................... 5 Clock Timing Recovery ............................................................. 12 ESD Caution .................................................................................. 5 A 5 V, High Speed Window Comparator ................................ 12 Pin Configurations and Function Descriptions ........................... 6 Outline Dimensions ....................................................................... 16 Typical Performance Characteristics ............................................. 7 Ordering Guide .......................................................................... 17 Applications Information .............................................................. 10 REVISION HISTORY 12/2016—Rev. A to Rev. B Changes to Input Voltage Parameter, Table 3 ............................... 5 Added Input Current Parameter, Table 3 ...................................... 5 Deleted Endnote 1, Table 3 .............................................................. 5 Updated Outline Dimensions ....................................................... 17 Changes to Ordering Guide .......................................................... 18 8/2006—Rev. 0 to Rev. A Updated Format .................................................................. Universal Added No Latch if V < 4.3 V ......................................... Universal CC Changes to Pin Names ....................................................... Universal Added Pin Configurations and Function Descriptions Page ..... 6 Changes to Table 8 .......................................................................... 12 Changes to Figure 26 ...................................................................... 12 Changes to Ordering Guide .......................................................... 17 4/2000—Revision 0: Initial Version Rev. B | Page 2 of 20

Data Sheet AD8611/AD8612 SPECIFICATIONS V+ = 5.0 V, V− = V = 0 V, T = 25°C, unless otherwise noted. GND A Table 1. Parameter Symbol Test Conditions/Comments Min Typ Max Unit INPUT CHARACTERISTICS Offset Voltage V 1 7 mV OS −40°C ≤ T ≤ +85°C 8 mV A Offset Voltage Drift ΔV /ΔT 4 μV/°C OS Input Bias Current I V = 0 V –6 –4 μA B CM I −40°C ≤ T ≤ +85°C –7 –4.5 μA B A Input Offset Current I V = 0 V ±4 μA OS CM Input Common-Mode Voltage Range V 0.0 3.0 V CM Common-Mode Rejection Ratio CMRR 0 V ≤ V ≤ 3.0 V 55 85 dB CM Large Signal Voltage Gain A R = 10 kΩ 3000 V/V VO L Input Capacitance C 3.0 pF IN LATCH ENABLE INPUT Logic 1 Voltage Threshold V V > 4.3 V 2.0 1.65 V IH CC Logic 0 Voltage Threshold V V > 4.3 V 1.60 0.8 V IL CC Logic 1 Current I V > 4.3 V, V = 3.0 V –1.0 –0.3 μA IH CC LH Logic 0 Current I V > 4.3 V, V = 0.3 V –5 –2.7 μA IL CC LL Latch Enable Pulse Width t V > 4.3 V 3 ns PW(E) CC Setup Time t V > 4.3 V 0.5 ns S CC Hold Time t V > 4.3 V 0.5 ns H CC DIGITAL OUTPUTS Logic 1 Voltage V I = 50 μA, ΔV > 250 mV 3.0 3.35 V OH OH IN Logic 1 Voltage V I = 3.2 mA, ΔV > 250 mV 2.4 3.4 V OH OH IN Logic 0 Voltage V I = 3.2 mA, ΔV > 250 mV 0.25 0.4 V OL OL IN DYNAMIC PERFORMANCE Input Frequency f 400 mV p-p sine wave 100 MHz MAX Propagation Delay t 200 mV step with 100 mV overdrive1 4.0 5.5 ns P −40°C ≤ T ≤ +85°C 5 ns A Propagation Delay t 100 mV step with 5 mV overdrive 5 ns P Differential Propagation Delay (Rising Propagation Delay vs. Δt 100 mV step with 100 mV overdrive1 0.5 2.0 ns P Falling Propagation Delay) Rise Time 20% to 80% 2.5 ns Fall Time 80% to 20% 1.1 ns POWER SUPPLY Power Supply Rejection Ratio PSRR 4.5 V ≤ V+ ≤ 5.5 V 55 73 dB V+ Supply Current2 I+ 5.7 10 mA −40°C ≤ T ≤ +85°C 10 A Ground Supply Current2 I V = 0 V, R = ∞ 3.5 7 mA GND O L −40°C ≤ T ≤ +85°C 7 mA A V− Supply Current2 I− 2.2 4 mA −40°C ≤ T ≤ +85°C 5 mA A 1 Guaranteed by design. 2 Per comparator. Rev. B | Page 3 of 20

AD8611/AD8612 Data Sheet V+ = 3.0 V, V− = VGND = 0 V, T = 25°C, unless otherwise noted. A Table 2. Parameter Symbol Test Conditions/Comments Min Typ Max Unit INPUT CHARACTERISTICS Offset Voltage VOS 1 7 mV Input Bias Current IB VCM = 0 V −6 −4.0 μA IB −40°C ≤ TA ≤ +85°C −7 −4.5 μA Input Common-Mode Voltage Range VCM 0 1.0 V Common-Mode Rejection Ratio CMRR 0 V ≤ VCM ≤ 1.0 V 55 dB OUTPUT CHARACTERISTICS Output High Voltage VOH IOH = −3.2 mA, VIN > 250 mV 1.21 V Output Low Voltage VOL IOL = +3.2 mA, VIN > 250 mV 0.3 V LATCH ENABLE INPUT Not functional if VCC < 4.3 V POWER SUPPLY Power Supply Rejection Ratio PSRR 2.7 V ≤ V+ ≤ 6 V 46 dB Supply Currents VO = 0 V, RL = ∞ V+ Supply Current2 I+ −40°C ≤ TA ≤ +85°C 4.5 6.5 mA 10 mA Ground Supply Current2 IGND −40°C ≤ TA ≤ +85°C 2.5 3.5 mA 5.5 mA V– Supply Current2 I− 2 3.5 mA −40°C ≤ TA ≤ +85°C 4.8 mA DYNAMIC PERFORMANCE Propagation Delay tP 100 mV step with 20 mV overdrive3 4.5 6.5 ns 1 Output high voltage without pull-up resistor. It can be useful to have a pull-up resistor to V+ for 3 V operation. 2 Per comparator. 3 Guaranteed by design. Rev. B | Page 4 of 20

Data Sheet AD8611/AD8612 ABSOLUTE MAXIMUM RATINGS Stresses at or above those listed under Absolute Maximum Table 3. Ratings may cause permanent damage to the product. This is a Parameter Rating stress rating only; functional operation of the product at these Total Analog Supply Voltage 7.0 V or any other conditions above those indicated in the operational Digital Supply Voltage 7.0 V section of this specification is not implied. Operation beyond Input Voltage VCC +0.3 V to the maximum operating conditions for extended periods may VEE −0.3 V affect product reliability. Differential Input Voltage ±5 V THERMAL RESISTANCE Output Short-Circuit Duration to GND Indefinite Input Current ±5 mA Table 4. Storage Temperature Range Package Type θ 1 θ Unit JA JC R, RU, RM Packages −65°C to +150°C 8-Lead SOIC (R) 158 43 °C/W Operating Temperature Range −40°C to +85°C 8-Lead MSOP (RM) 240 43 °C/W Junction Temperature Range 14-Lead TSSOP (RU) 240 43 °C/W R, RU, RM Packages −65°C to +150°C Lead Temperature Range (Soldering, 10 sec) 300°C 1θJA is specified for the worst-case conditions, that is, a device in socket for P-DIP and a device soldered in circuit board for SOIC and TSSOP. ESD CAUTION Rev. B | Page 5 of 20

AD8611/AD8612 Data Sheet PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS V+ 1 8 QA IN+ 2 AD8611 7 QA INV–– 34 (NToOt Pto V SIEcWale) 65 GLANTDCH 06010-001 Figure 4. 8-Lead Narrow Body SOIC Pin Configuration V+ 1 8 QA AD8611 IN+ 2 7 QA TOP VIEW INV–– 34 (Not to Scale) 65 GLANTDCH 06010-002 Figure 5. 8-Lead MSOP Pin Configuration QA 1 14 QB QA 2 13 QB GND 3 AD8612 12 GND TOP VIEW LEA 4 (Not to Scale) 11 LEB V– 5 10 V+ INA– 6 9 INB– INA+ 7 8 INB+ 06010-003 Figure 6. 14-Lead TSSOP Pin Configuration Table 5. Pin Function Descriptions Pin No. SOIC and MSOP TSSOP Mnemonic Description 1 10 V+ Positive Supply Terminal. 2 IN+ Noninverting Analog Input of the Differential Input Stage. 3 IN− Inverting Analog Input of the Differential Input Stage. 4 5 V− Negative Supply Terminal. 5 LATCH Latch Enable Input. 6 3, 12 GND Negative Logic Supply 7 1 QA One of Two Complementary Output for Channel A. 8 2 QA One of Two Complementary Output for Channel A. 14 QB One of Two Complementary Output for Channel B. 13 QB One of Two Complementary Output for Channel B. 4 LEA Channel A Latch Enable. 11 LEB Channel B Latch Enable. 7 INA+ Noninverting Analog Input of the Differential Input Stage for Channel A. 6 INA− Inverting Analog Input of the Differential Input Stage for Channel A. 8 INB+ Noninverting Analog Input of the Differential Input Stage for Channel B. 9 INB− Inverting Analog Input of the Differential Input Stage for Channel B. Rev. B | Page 6 of 20

Data Sheet AD8611/AD8612 TYPICAL PERFORMANCE CHARACTERISTICS 8 18 V+ = 5V V+ = 5V 7 OVERDRIVE > 10mV TOAV E= R2D5°RCIVE = 5mV 14 AY (ns) 6 AY (ns)12 PD– DEL 5 PD– DEL PD+ ON 4 ON 8 ATI PD+ ATI PAG 3 PAG 6 O O PR 2 PR 2 1 0–50 –25 0TEMPERA25TURE (°C)50 75 100 06010-004 00 0.5 SOURC1.E0 RESISTAN1.C5E (kΩ) 2.0 2.5 06010-007 Figure 7. Propagation Delay vs. Temperature Figure 10. Propagation Delay vs. Source Resistance 18 8 16 VTA+ == 255V°C 7 TSOATV EE=P R2 D=5° R1CI0V0Em >V 10mV PD– PD+ AY (ns)1142 AY (ns) 6 N DEL10 N DEL 5 PD– O PD+ O 4 ATI 8 ATI G G A A 3 P 6 P O O R R P 4 P 2 2 1 00 5 O1V0ERDRIVE (m15V) 20 25 06010-005 02 3 SUPPLY VO4LTAGE (V) 5 6 06010-008 Figure 8. Propagation Delay vs. Overdrive Figure 11. Propagation Delay vs. Supply Voltage 8 35 V+ = 5V TA = 25°C 7 TOAV E= R2D5°RCIVE > 10mV 30 SOTVEEPR D= R1I0V0Em =V 50mV PD– PROPAGATION DELAY (ns) 65423 PD+ PROPAGATION DELAY (ns)11225050 PD+ 1 5 PD– 00 20 CAPACIT4A0NCE (pF) 60 80 06010-006 02 3COMMON-MOD4E VOLTAGE (V)5 6 06010-009 Figure 9. Propagation Delay vs. Load Capacitance Figure 12. Propagation Delay vs. Common-Mode Voltage Rev. B | Page 7 of 20

AD8611/AD8612 Data Sheet 1.2 0.40 VS = 3V +25°C 0.35 1.0 +85°C –40°C 0.30 V) 0.8 VS = 5V ENT (V)0.25 –40°C m R (OS 0.6 CUR0.20 +85°C V D A0.15 0.4 LO +25°C 0.10 0.2 0.05 0–60 –40 –20 TE0MPERA20TURE (4°C0) 60 80 100 06010-010 00 2 4SINK CURR6ENT (mA)8 10 12 06010-013 Figure 13. Offset Voltage vs. Temperature Figure 16. Output Low Voltage vs. Load Current (Sinking) Over Temperature 40 4.0 V+=5V 35 TA=25°C 3.8 30 GE (V)3.6 +85°C A 25 T3.4 A) OL +25°C m V I (SY+2105 UT HIGH 33..20 –40°C P T 10 OU2.8 5 2.6 01 INPUTFREQ1U0ENCY(MHz) 100 06010-011 2.40 2 L4OAD CUR6RENT (mA8) 10 12 06010-014 Figure 14. Supply Current vs. Input Frequency Figure 17. Output High Voltage vs. Load Current (Sourcing) Over Temperature 2.0 8 V+ = 5V 1.8 7 1.6 6 1.4 VS = 5V s)1.2 5 MING (n1.0 (mA)SY4 TI0.8 SETUP TIME I 3 VS = 3V 0.6 2 0.4 HOLD TIME 1 0.2 0–50 –25 0TEMPERA25TURE (°C)50 75 100 06010-012 0–60 –40 –20 TE0MPERA20TURE (4°0C) 60 80 100 06010-015 Figure 15. Latch Setup and Hold Time vs. Temperature Figure 18. Supply Current vs. Temperature Rev. B | Page 8 of 20

AD8611/AD8612 0 V+ = 5V TA = 25°C –0.5 –1.0 –1.5 VIN E (mA)GND––22..05 VS = 3V VOLTAG 0V VOUT I –3.0 VS = 5V –3.5 –4.0 –VIN TRACE @ 10mV/DIV VOUTTRACE @ 1V/DIV –4.550 0TEMPERATURE (°C5)0 100 06010-016 TIME (2ns/DIV) 06010-019 Figure 19. IGND vs. Temperature Figure 22. Falling Edge Response 0 V+ = 5V TA = 25°C VOUT –0.5 –1.0 E (mA)Y –1.5 VS = 3V OLTAG 0V IS V –2.0 VS = 5V VIN –2.5 –VIN TRACE @ 10mV/DIV VOUTTRACE @ 1V/DIV –3.0–60 –40 –20 TE0MPERA20TURE (4°C0) 60 80 100 06010-017 TIME (4ns/DIV) 06010-020 Figure 20. ISY− vs. Temperature Figure 23. Response to a 50 MHz, 100 mV Input Sine Wave V+ = 5V TA = 25°C VOUT E G A OLT 0V VIN V –VIN TRACE @ 10mV/DIV VOUTTRACE @ 1V/DIV TIME (2ns/DIV) 06010-018 Figure 21. Rising Edge Response Rev. A | Page 9 of 20

AD8611/AD8612 Data Sheet APPLICATIONS INFORMATION OPTIMIZING HIGH SPEED PERFORMANCE The LT1016 has an input voltage range from 1.25 V above the negative supply to 1.5 V below the positive supply. The AD8611 As with any high speed comparator or amplifier, proper design input voltage range extends down to the negative supply voltage and layout of the AD8611/AD8612 must ensure optimal to within 2 V of V+. If the input common-mode voltage is performance. Excess stray capacitance or improper grounding exceeded, input signals must be shifted or attenuated to bring can limit the maximum performance of high speed circuitry. them into range, keeping in mind the note about source resistance Minimizing resistance from the source to the comparator input in the Optimizing High Speed Performance section. is necessary to minimize the propagation delay of the circuit. For example, an AD8611 powered from a 5 V single supply has Source resistance in combination with the equivalent input its noninverting input connected to a 1 V peak-to-peak, high capacitance of the AD8611/AD8612 creates an R-C filter that frequency signal centered around 2.3 V and its inverting input could cause a lagged voltage rise at the input to the comparator. connected to a fixed 2.5 V reference voltage. The worst-case The input capacitance of the AD8611/AD8612 in combination input common-mode voltage to the AD8611 is 2.65 V. This is with stray capacitance from an input pin to ground results in well below the 3.0 V input common-mode voltage range to the several picofarads of equivalent capacitance. Using a surface-mount comparator. Note that signals much greater than 3.0 V result in package and a minimum of input trace length, this capacitance increased input currents and can cause the comparator to is typically around 3 pF to 5 pF. A combination of 3 kΩ source operate more slowly. resistance and 3 pF of input capacitance yields a time constant The input bias current to the AD8611 is 7 μA maximum over of 9 ns, which is slower than the 4 ns propagation delay of the temperature (−40°C to +85°C). This is identical to the maximum AD8611/AD8612. Source impedances must be less than 1 kΩ input bias current for the LT1394, and half of the maximum I for best performance. B for the LT1016. Input bias currents to the AD8611 and LT1394 Another important consideration is the proper use of power- flow out from the comparator inputs, as opposed to the LT1016 supply-bypass capacitors around the comparator. A 1 μF bypass whose input bias current flows into its inputs. Using low value capacitor must be placed within 0.5 inches of the device between resistors around the comparator and low impedance sources each power supply pin and ground. Another 10 nF ceramic will minimize any potential voltage shifts due to bias currents. capacitor must be placed as close as possible to the device in The AD8611 is able to swing within 200 mV of ground and parallel with the 1 μF bypass capacitor. The 1 μF capacitor reduces within 1.5 V of positive supply voltage. This is slightly more any potential voltage ripples from the power supply, and the 10 nF output voltage swing than the LT1016. The AD8611 also uses capacitor acts as a charge reservoir for the comparator during less current than the LT1016—5 mA as compared to 25 mA of high frequency switching. typical supply current. A continuous ground plane on the PC board is also recommended The AD8611 has a typical propagation delay of 4 ns, compared to maximize circuit performance. A ground plane can be created with the LT1394 and LT1016, whose propagation delays are by using a continuous conductive plane over the surface of the typically 7 ns and 10 ns, respectively. circuit board, only allowing breaks in the plane for necessary traces and vias. The ground plane provides a low inductive current MAXIMUM INPUT FREQUENCY AND OVERDRIVE return path for the power supply, thus eliminating any potential The AD8611 can accurately compare input signals up to 100 MHz differences at various ground points throughout the circuit board with less than 10 mV of overdrive. The level of overdrive required caused from ground bounce. A proper ground plane can also increases with ambient temperature, with up to 50 mV of minimize the effects of stray capacitance on the circuit board. overdrive recommended for a 100 MHz input signal and an UPGRADING THE LT1394 AND LT1016 ambient temperature of +85°C. The AD8611 single comparator is pin-for-pin compatible with It is not recommend to use an input signal with a fundamental the LT1394 and LT1016 and offers an improvement in propagation frequency above 100 MHz because the AD8611 could draw up delay over both comparators. These devices can easily be replaced to 20 mA of supply current and the outputs may not settle to a with the higher performance AD8611; however, there are differ- definite state. The device returns to its specified performance ences, so it is useful to ensure that the system still operates properly. once the fundamental input frequency returns to below 100 MHz. The five major differences between the AD8611 and the LT1016 OUTPUT LOADING CONSIDERATIONS include input voltage range, input bias currents, propagation delay, The AD8611 can deliver up to 10 mA of output current without output voltage swing, and power consumption. Input common- increasing its propagation delay. The outputs of the device must mode voltage is found by taking the average of the two voltages not be connected to more than 40 TTL input logic gates or drive at the inputs to the comparator. less than 400 Ω of load resistance. Rev. B | Page 10 of 20

Data Sheet AD8611/AD8612 The AD8611 output has a typical output swing between ground At or below approximately 4.1 V, the latch pin becomes and 1 V below the positive supply voltage. Decreasing the output unresponsive and must normally be tied low for low V CC load resistance to ground lowers the maximum output voltage operation. due to the increase in output current. Table 6 shows the typical INPUT STAGE AND BIAS CURRENTS output high voltage vs. load resistance to ground. The AD8611 and AD8612 each use a bipolar PNP differential input Table 6. Maximum Output Voltage vs. Resistive Load stage. This enables the input common-mode voltage range to Output Load to Ground V+ − VOUT, HI (typ) extend from within 2.0 V of the positive supply voltage to 200 mV 300 Ω 1.5 V below the negative supply voltage. Therefore, using a single 5 V 500 Ω 1.3 V supply, the input common-mode voltage range is −200 mV to 1 kΩ 1.2 V +3.0 V. Input common-mode voltage is the average of the voltages 10 kΩ 1.1 V at the two inputs. For proper operation, the input common-mode >20 kΩ 1.0 V voltage must be kept within the common-mode voltage range. The input bias current for the AD8611/AD8612 is 4 μA, Connecting a 500 Ω to 2 kΩ pull-up resistor to V+ on the which is the amount of current that flows from each input of output helps increase the output voltage so that it is closer to the the comparator. This bias current goes to zero on an input that positive rail; in this configuration, however, the output voltage is high and doubles on an input that is low, which is a characteristic will not reach its maximum until 20 ns to 50 ns after the output common to any bipolar comparator. Care must be taken in voltage switches. This is due to the R-C time constant between choosing resistances to be connected around the comparator the pull-up resistor and the output and load capacitances. The because large resistors could significantly decrease the voltage output pull-up resistor cannot improve propagation delay. due to the input bias current. The AD8611 is stable with all values of capacitive load; however, The input capacitance for the AD8611/AD8612 is typically 3 pF. loading an output with greater than 30 pF increases the This is measured by inserting a 5 kΩ source resistance in series propagation delay of that channel. Capacitive loads greater than with the input and measuring the change in propagation delay. 500 pF also create some ringing on the output wave. Table 7 shows USING HYSTERESIS propagation delay vs. several values of load capacitance. The loading on one output of the AD8611 does not affect the Hysteresis can easily be added to a comparator through the propagation delay of the other output. addition of positive feedback. Adding hysteresis to a comparator offers an advantage in noisy environments where it is undesirable Table 7. Propagation Delay vs. Capacitive Load for the output to toggle between states when the input signal is CL (pF) tPD Rising (ns) tPD Falling (ns) close to the switching threshold. Figure 24 shows a simple method <10 3.5 3.5 for configuring the AD8611 or AD8612 with hysteresis. 33 5 5 COMPARATOR SIGNAL 100 8 7 390 14.5 10 680 26 15 VREF R1 R2 USING THE LATCH CF 06010-021 TO MAINTAIN A CONSTANT OUTPUT Figure 24. Configuring the AD8611/AD8612 with Hysteresis In Figure 24, the input signal is connected directly to the inverting With the V supply at a nominal 5 V, the latch input to the CC input of the comparator. The output is fed back to the noninverting AD8611/AD8612 can retain data at the output of the comparator. input through R1 and R2. The ratio of R1 to R1 + R2 establishes When the latch voltage goes high, the output voltage remains in the width of the hysteresis window, with V setting the center its previous state, independent of changes in the input voltage. REF of the window, or the average switching voltage. The QA or QB The setup time for the AD8611/AD8612 is 0.5 ns and the hold output switches low when the input voltage is greater than V , HI time is 0.5 ns. Setup time is defined as the minimum amount of and does not switch high again until the input voltage is less time the input voltage must remain in a valid state before the than V , as given in Equation 1: LO latch is activated for the latch to function properly. Hold time is defined as the amount of time the input must remain constant V =(V+−1.5V ) R1 +V after the latch voltage goes high for the output to remain latched HI REF R1+R2 REF (1) to its voltage. R2 The latch input is TTL and CMOS compatible, so a logic high is VLO =VREF × R1+R2 a minimum of 2.0 V and a logic low is a maximum of 0.8 V. The latch circuitry in the AD8611/AD8612 has no built-in where V+ is the positive supply voltage. hysteresis. Rev. B | Page 11 of 20

AD8611/AD8612 Data Sheet The capacitor C is optional and can be added to introduce a A 5 V, HIGH SPEED WINDOW COMPARATOR F pole into the feedback network. This has the effect of increasing A window comparator circuit detects when a signal is between the amount of hysteresis at high frequencies, which is useful two fixed voltages. The AD8612 can create a high speed window when comparing relatively slow signals in high frequency noise comparator, as shown in Figure 26. In this example, the environments. At frequencies greater than f , the hysteresis P reference window voltages are set as: window approaches V = V+ − 1.5 V and V = 0 V. For HI LO R2 R4 frequencies less than fP, the threshold voltages remain as in V = V = Equation 1. HI R1+R2 LO R3+R4 CLOCK TIMING RECOVERY The output of the A1 comparator goes high when the input signal exceeds V , and the output of A2 goes high only when Comparators are often used in digital systems to recover clock HI V drops below V . When the input voltage is between V timing signals. High speed square waves transmitted over any IN LO HI and V , both comparator outputs are low, turning off both Q1 distance, even tens of centimeters, can become distorted due to LO and Q2, thus driving V to a high state. If the input signal stray capacitance and inductance. Poor layout or improper OUT goes outside of the reference voltage window, V goes low. termination can also cause reflections on the transmission line, OUT further distorting the signal waveform. A high speed comparator To ensure a minimum of switching delay, the use of high speed can recover the distorted waveform while maintaining a transistors is recommended for Q1 and Q2. Using the AD8612 minimum of delay. with 2N3960 transistors provides a total propagation delay from V to V of less than 10 ns. Figure 25 shows V vs. V as the AD8611 recovers a 65 MHz, IN OUT OUT IN 100 mV peak-to-peak distorted clock signal into a 4 V peak-to- Table 8. Window Comparator Output States peak square wave. The lower trace is the input to the AD8611, V Input Voltage OUT and the upper trace is the QA or QB output from the comparator. ≈ 200 mV V < V IN LO The AD8611 is powered from a 5 V single supply. +5 V V < V < V LO IN HI ≈ 200 mV V > V IN HI VOUT 5V 2V/DIV 5V 5V 1kΩ R1 VHI 6 10 VOUT 1 1kΩ R2 7 A1 Q1 Q2 20mV/DIV 3 VIN 4 AD8612 500Ω VIN 5V AD8612 TIME (10ns/DIV) 06010-022 R3 VLO 89 A2 1214 1kΩ Figure 25. Using the AD8611 to Recover a Noisy Clock Signal 11 500Ω R4 5 N12..O QPTI1NE, SSQ 22 A= N2DN 31936 A0.RE NO CONNECTS. 06010-023 Figure 26. A High Speed Window Comparator Rev. B | Page 12 of 20

Data Sheet AD8611/AD8612 SPICE Model * AD8611 SPICE Macro-Model Typical Values * 1/2000, Ver. 1.0 * TAM/ADSC * * Node assignments * non-inverting input * | inverting input * | | positive supply * | | | negative supply * | | | | Latch * | | | | | DGND * | | | | | | Q * | | | | | | | QNOT * | | | | | | | | .SUBCKT AD8611 1 2 99 50 80 51 45 65 * * INPUT STAGE * * Q1 4 3 5 PIX Q2 6 2 5 PIX IBIAS 99 5 800E-6 RC1 4 50 1E3 RC2 6 50 1E3 CL1 4 6 3E-13 CIN 1 2 3E-12 VCM1 99 7 DC 1.9 D1 5 7 DX EOS 3 1 POLY(1) (31,98) 1E-3 1 * * Reference Voltages * EREF 98 0 POLY(2) (99,0) (50,0) 0 0.5 0.5 RREF 98 0 100E3 * * CMRR = 66dB, ZERO AT 1 kHz Rev. B | Page 13 of 20

AD8611/AD8612 Data Sheet * ECM1 30 98 POLY(2) (1,98) (2,98) 0 0.5 0.5 RCM1 30 31 10E3 RCM2 31 98 5 CCM1 30 31 15.9E-9 * * Latch Section * RX 80 51 100E3 E1 10 98 (4,6) 1 S1 10 11 (80,51) SLATCH1 R2 11 12 1 C3 12 98 5 4E-12 E2 13 98 (12,98) 1 R3 12 13 500 * * Power Supply Section * GSY1 99 52 POLY(1) (99,50) 4E-3 -2 6E-4 GSY2 52 50 POLY(1) (99,50) 3 7E-3 -.6E-3 RSY 52 51 10 * * Gain Stage Av = 250 fp=100 MHz * G2 98 20 (12,98) 0.25 R1 20 98 1000 C1 20 98 10E-13 E3 97 0 (99,0) 1 E4 52 0 (51,0) 1 V1 97 21 DC 0.8 V2 22 52 DC 0.8 D2 20 21 DX D3 22 20 DX * * Q Output * Q3 99 41 46 NOX Rev. B | Page 14 of 20

Data Sheet AD8611/AD8612 Q4 47 42 51 NOX RB1 43 41 2000 RB2 40 42 2000 CB1 99 41 0.5E-12 CB2 42 51 1E-12 RO1 46 44 1 D4 44 45 DX RO2 47 45 500 EO1 97 43 (20,51) 1 EO2 40 51 (20,51) 1 * * Q NOT Output * Q5 99 61 66 NOX Q6 67 62 51 NOX RB3 63 61 2000 RB4 60 62 2000 CB3 99 61 0 5E-12 CB4 62 51 1E-12 RO3 66 64 1 D5 64 65 DX RO4 67 65 500 EO3 63 51 (20,51) 1 EO4 97 60 (20,51) 1 * * MODELS * .MODEL PIX PNP(BF=100,IS=1E-16) .MODEL NOX NPN(BF=100,VAF=130,IS=1E-14) .MODEL DX D(IS=1E-14) .MODEL SLATCH1 VSWITCH(ROFF=1E6,RON=500, +VOFF=2.1,VON=1.4) .ENDS AD8611 Rev. B | Page 15 of 20

AD8611/AD8612 Data Sheet OUTLINE DIMENSIONS 3.20 3.00 2.80 8 5 5.15 3.20 4.90 3.00 4.65 2.80 1 4 PIN 1 IDENTIFIER 0.65 BSC 0.95 15° MAX 0.85 1.10 MAX 0.75 0.80 0.15 0.40 6° 0.23 0.55 CO0P.0L50A.1N0ARICTOYMPLIANT0. 2T5O JEDEC STA0°NDARDS 0M.0O9-187-AA 0.40 10-07-2009-B Figure 27. 8-Lead Mini Small Outline Package [MSOP] (RM-8) Dimensions shown in millimeters 5.00 (0.1968) 4.80 (0.1890) 8 5 4.00 (0.1574) 6.20 (0.2440) 3.80 (0.1497) 1 4 5.80 (0.2284) 1.27B (0S.C0500) 1.75 (0.0688) 00..5205 ((00..00109969))× 45° 0.25 (0.0098) 1.35 (0.0532) 0.10 (0.0040) 0.51 (0.0201) 8° COPL0A.1N0ARITY SEPALTAINNGE 0.31 (0.0122) 00..2157 ((00..00009687)) 0° 10..2470 ((00..00510507)) COMPLIANT TO JEDEC STANDARDS MS-012-AA CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. Figure 28. 8-Lead Standard Small Outline Package [SOIC_N] Narrow Body (R-8) Dimensions shown in millimeters and (inches) 5.10 5.00 4.90 14 8 4.50 4.40 6.40 BSC 4.30 1 7 PIN 1 1.05 0.65 1.00 BSC 0.20 0.80 1M.A20X 0.09 0.75 00..1055 00..3109 SPELAANTIENG COPLANARITY80°° 00..6405 0.10 COMPLIANT TO JEDEC STANDARDS MO-153-AB-1 Figure 29. 14-Lead Thin Shrink Small Outline Package [TSSOP] (RU-14) Dimensions shown in millimeters Rev. B | Page 16 of 20

Data Sheet AD8611/AD8612 ORDERING GUIDE Model1 Temperature Range Package Description Package Option Branding AD8611ARMZ-REEL –40°C to +85°C 8-Lead Mini Small Outline Package [MSOP] RM-8 G1A AD8611ARMZ-R2 –40°C to +85°C 8-Lead Mini Small Outline Package [MSOP] RM-8 G1A AD8611AR –40°C to +85°C 8-Lead Standard Small Outline Package [SOIC_N] R-8 AD8611ARZ –40°C to +85°C 8-Lead Standard Small Outline Package [SOIC_N] R-8 AD8611ARZ-REEL –40°C to +85°C 8-Lead Standard Small Outline Package [SOIC_N] R-8 AD8611ARZ-REEL7 –40°C to +85°C 8-Lead Standard Small Outline Package [SOIC_N] R-8 AD8612ARUZ –40°C to +85°C 14-Lead Thin Shrink Small Outline Package [TSSOP] RU-14 AD8612ARUZ-REEL –40°C to +85°C 14-Lead Thin Shrink Small Outline Package [TSSOP] RU-14 1 Z = RoHS Compliant Part. Rev. B | Page 17 of 20

AD8611/AD8612 Data Sheet NOTES Rev. B | Page 18 of 20

Data Sheet AD8611/AD8612 NOTES Rev. B | Page 19 of 20

AD8611/AD8612 Data Sheet NOTES ©2000–2016 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D06010-0-12/16(B) Rev. B | Page 20 of 20

Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: A nalog Devices Inc.: AD8611ARMZ-R2 AD8611ARZ AD8612ARUZ AD8611AR AD8611ARMZ-REEL AD8611AR-REEL AD8611ARZ- REEL AD8611ARZ-REEL7 AD8612ARU AD8612ARU-REEL AD8612ARUZ-REEL