a High Speed, Low Power Monolithic Op Amp AD848/AD849 FEATURES CONNECTION DIAGRAMS 725MHz Gain Bandwidth – AD849 Plastic (N), 175MHz Gain Bandwidth – AD848 Small Outline (R) and 4.8mA Supply Current Cerdip (Q) Packages 300V/(cid:109)s Slew Rate 80ns Settling Time to 0.1% for a 10V Step – AD849 AD848/49 Differential Gain: AD848 = 0.07%, AD849 = 0.08% NULL 1 8 NULL Differential Phase: AD848 = 0.08(cid:56), AD849 = 0.04(cid:56) –IN 2 7 +VS Drives Capacitive Loads +IN 3 6 OUTPUT DC PERFORMANCE –VS 4 (NToOt Pto V SIEcaWle) 5 NC 3nV/(cid:214) Hz Input Voltage Noise – AD849 NC = NO CONNECT 85V/mV Open Loop Gain into a 1k(cid:86) Load – AD849 1mV max Input Offset Voltage 20-Terminal LCC Pinout Performance Specified for (cid:54)5V and (cid:54)15V Operation Available in Plastic, Hermetic Cerdip and Small Outline T U Packages. Chips and MIL-STD-883B Parts Available. TP Available in Tape and Reel in Accordance with NC V+ NC OU NC EIA-481A Standard 18 17 16 15 14 APPLICATIONS NC 19 13 NC Cable Drivers OFNFUSELLT 20 AD848SE/883B 12 NC 8- and 10-Bit Data Acquisition Systems NC 1 TOP VIEW 11 NC Video and R Amplification OFFSET 2 (Not to Scale) 10 V– F NULL Signal Generators NC 3 9 NC 4 5 6 7 8 PRODUCT DESCRIPTION NC –IN NC +IN NC The AD848 and AD849 are high speed, low power monolithic NC = NO CONNECT operational amplifiers. The AD848 is internally compensated so APPLICATIONS HIGHLIGHTS that it is stable for closed loop gains of 5 or greater. The AD849 1. The high slew rate and fast settling time of the AD848 and is fully decompensated and is stable at gains greater than 24. AD849 make them ideal for video instrumentation circuitry, The AD848 and AD849 achieve their combination of fast ac low noise pre-amps and line drivers. and good dc performance by utilizing Analog Devices’ junction isolated complementary bipolar (CB) process. This process 2. In order to meet the needs of both video and data acquisition enables these op amps to achieve their high speed while only applications, the AD848 and AD849 are optimized and requiring 4.8mA of current from the power supplies. tested for – 5V and – 15V power supply operation. The AD848 and AD849 are members of Analog Devices’ family 3. Both amplifiers offer full power bandwidth greater than of high speed op amps. This family includes, among others, the 20MHz (for 2V p-p with – 5V supplies). AD847 which is unity gain stable, with a gain bandwidth of 4. The AD848 and AD849 remain stable when driving any 50MHz. For more demanding applications, the AD840, capacitive load. AD841 and AD842 offer even greater precision and greater 5. Laser wafer trimming reduces the input offset voltage to output current drive. 1mV maximum on all grades, thus eliminating the need for The AD848 and AD849 have good dc performance. When external offset nulling in many applications. operating with – 5V supplies, they offer open loop gains of 13V/mV (AD848 with a 500W load) and low input offset 6. The AD848 is an enhanced replacement for the LM6164 series and can function as a pin-for-pin replacement for voltage of 1mV maximum. Common-mode rejection is a minimum of 92dB. Output voltage swing is – 3V even into many high speed amplifiers such as the HA2520/2/5 and loads as low as 150W . EL2020 in applications where the gain is 5 or greater. REV.B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. otherwise under any patent or patent rights of Analog Devices. Tel: 617/329-4700 Fax: 617/326-8703

AD848/AD849–SPECIFICATIONS (@ T = +25(cid:56)C, unless otherwise noted) A AD848J AD848A/S Model Conditions V Min Typ Max Min Typ Max Units S INPUT OFFSET VOLTAGE1 – 5V 0.2 1 0.2 1 mV – 15V 0.5 2.3 0.5 2.3 mV T to T – 5V 1.5 2 mV MIN MAX – 15V 3.0 3.5 mV Offset Drift – 5V, – 15V 7 7 m V/(cid:176) C INPUT BIAS CURRENT – 5V, – 15V 3.3 6.6 3.3 6.6/5 m A T to T – 5V, – 15V 7.2 7.5 m A MIN MAX INPUT OFFSET CURRENT – 5V, – 15V 50 300 50 300 nA T to T – 5V, – 15V 400 400 nA MIN MAX Offset Current Drift – 5V, – 15V 0.3 0.3 nA/(cid:176) C OPEN LOOP GAIN V = – 2.5V – 5V O R = 500W 9 13 9 13 V/mV LOAD T to T 7 7/5 V/mV MIN MAX R = 150W 8 8 V/mV LOAD V = – 10V – 15V OUT R = 1kW 12 20 12 20 V/mV LOAD T to T 8 8/6 V/mV MIN MAX DYNAMIC PERFORMANCE Gain Bandwidth A ‡ 5 – 5 V 125 125 MHz VCL – 15 V 175 175 MHz Full Power Bandwidth2 V = 2 V p-p, O R = 500W – 5V 24 24 MHz L V = 20 V p-p, O R = 1kW – 15V 4.7 4.7 MHz L Slew Rate – 5V 200 200 V/m s R = 1kW – 15V 225 300 225 300 V/m s LOAD Settling Time to 0.1% –2.5 V to +2.5 V – 5 V 65 65 ns 10 V Step, A = –4 – 15V 100 100 ns V Phase Margin C = 10 pF – 15V LOAD R = 1kW 60 60 Degrees LOAD DIFFERENTIAL GAIN f = 4.4 MHz – 15 V 0.07 0.07 % DIFFERENTIAL PHASE f = 4.4 MHz – 15 V 0.08 0.08 Degree COMMON-MODE REJECTION V = – 2.5 V – 5 V 92 105 92 105 dB CM V = – 12 V – 15 V 92 105 92 105 dB CM T to T 88 88 dB MIN MAX POWER SUPPLY REJECTION V = – 4.5 V to – 18 V 85 98 85 98 dB S T to T 80 80 dB MIN MAX INPUT VOLTAGE NOISE f = 10kHz – 15V 5 5 nV/(cid:214) Hz INPUT CURRENT NOISE f = 10kHz – 15V 1.5 1.5 pA/(cid:214) Hz INPUT COMMON-MODE VOLTAGE RANGE – 5V +4.3 +4.3 V –3.4 –3.4 V – 15 V +14.3 +14.3 V –13.4 –13.4 V OUTPUT VOLTAGE SWING R = 500W – 5 V 3.0 3.6 3.0 3.6 – V LOAD R = 150W – 5V 2.5 3 2.5 3 – V LOAD R = 50W – 5V 1.4 1.4 – V LOAD R = 1 kW – 15V 12 12 – V LOAD R = 500 W – 15 V 10 10 – V LOAD SHORT CIRCUIT CURRENT – 15 V 32 32 mA INPUT RESISTANCE 70 70 kW INPUT CAPACITANCE 1.5 1.5 pF OUTPUT RESISTANCE Open Loop 15 15 W POWER SUPPLY Operating Range (cid:54)4.5 (cid:54)18 (cid:54)4.5 (cid:54)18 V Quiescent Current – 5 V 4.8 6.0 4.8 6.0 mA T to T 7.4 7.4/8.3 mA MIN MAX – 15 V 5.1 6.8 5.1 6.8 mA T to T 8.0 8.0/9.0 mA MIN MAX NOTES 1Input offset voltage specifications are guaranteed after 5 minutes at T = +25(cid:176)C. A 2Full power bandwidth = slew rate/2 p V . Refer to Figure 1. PEAK All min and max specifications are guaranteed. Specifications in boldface are tested on all production units at final electrical test. All others are guaranteed but not necessarily tested. Specifications subject to change without notice. –2– REV. B

AD848/AD849 AD849J AD849A/S Model Conditions V Min Typ Max Min Typ Max Units S INPUT OFFSET VOLTAGE1 – 5V 0.3 1 0.1 0.75 mV – 15V 0.3 1 0.1 0.75 mV T to T – 5V 1.3 1.0 mV MIN MAX – 15V 1.3 1.0 mV Offset Drift – 5V, – 15V 2 2 m V/(cid:176) C INPUT BIAS CURRENT – 5V, – 15V 3.3 6.6 3.3 6.6/5 m A T to T – 5V, – 15V 7.2 7.5 m A MIN MAX INPUT OFFSET CURRENT – 5V, – 15V 50 300 50 300 nA T to T – 5V, – 15V 400 400 nA MIN MAX Offset Current Drift – 5V, – 15V 0.3 0.3 nA/(cid:176) C OPEN LOOP GAIN V = – 2.5V – 5V O R = 500W 30 50 30 50 V/mV LOAD T to T 20 20/15 V/mV MIN MAX R = 150W 32 32 V/mV LOAD V = – 10V – 15V OUT R = 1kW 45 85 45 85 V/mV LOAD T to T 30 30/25 V/mV MIN MAX DYNAMIC PERFORMANCE Gain Bandwidth A ‡ 25 – 5 V 520 520 MHz VCL – 15 V 725 725 MHz Full Power Bandwidth2 V = 2 V p-p, O R = 500W – 5V 20 20 MHz L V = 20 V p-p, O R = 1kW – 15V 4.7 4.7 MHz L Slew Rate – 5V 200 200 V/m s R = 1kW – 15V 225 300 225 300 V/m s LOAD Settling Time to 0.1% –2.5 V to +2.5 V – 5 V 65 65 ns 10 V Step, A = –24 – 15V 80 80 ns V Phase Margin C = 10 pF – 15V LOAD R = 1kW 60 60 Degrees LOAD DIFFERENTIAL GAIN f = 4.4 MHz – 15 V 0.08 0.08 % DIFFERENTIAL PHASE f = 4.4 MHz – 15 V 0.04 0.04 Degrees COMMON-MODE REJECTION V = – 2.5 V – 5 V 100 115 100 115 dB CM V = – 12 V – 15 V 100 115 100 115 dB CM T to T 96 96 dB MIN MAX POWER SUPPLY REJECTION V = – 4.5 V to – 18 V 98 120 98 120 dB S T to T 94 94 dB MIN MAX INPUT VOLTAGE NOISE f = 10kHz – 15V 3 3 nV/(cid:214) Hz INPUT CURRENT NOISE f = 10kHz – 15V 1.5 1.5 pA/(cid:214) Hz INPUT COMMON-MODE VOLTAGE RANGE – 5V +4.3 +4.3 V –3.4 –3.4 V – 15 V +14.3 +14.3 V –13.4 –13.4 V OUTPUT VOLTAGE SWING R = 500W – 5 V 3.0 3.6 3.0 3.6 – V LOAD R = 150W – 5V 2.5 3 2.5 3 – V LOAD R = 50W – 5V 1.4 1.4 – V LOAD R = 1 kW – 15V 12 12 – V LOAD R = 500 W – 15 V 10 10 – V LOAD SHORT CIRCUIT CURRENT – 15 V 32 32 mA INPUT RESISTANCE 25 25 kW INPUT CAPACITANCE 1.5 1.5 pF OUTPUT RESISTANCE Open Loop 15 15 W POWER SUPPLY Operating Range (cid:54)4.5 (cid:54)18 (cid:54)4.5 (cid:54)18 V Quiescent Current – 5 V 4.8 6.0 4.8 6.0 mA T to T 7.4 7.4/8.3 mA MIN MAX – 15 V 5.1 6.8 5.1 6.8 mA T to T 8.0 8.0/9.0 mA MIN MAX NOTES 1Input offset voltage specifications are guaranteed after 5 minutes at T = +25(cid:176)C. A 2Full power bandwidth = slew rate/2 p V . Refer to Figure 1. PEAK All min and max specifications are guaranteed. Specifications in boldface are tested on all production units at final electrical test. All others are guaranteed but not necessarily tested. Specifications subject to change without notice. REV. B –3–

AD848/AD849 ABSOLUTE MAXIMUM RATINGS1 METALIZATION PHOTOGRAPH Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 18 V Contact factory for latest dimensions. (AD848 and AD849 are identical Internal Power Dissipation2 except for the part number in the upper right.) Plastic (N) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.1 Watts Dimensions shown in inches and (mm). Small Outline (R) . . . . . . . . . . . . . . . . . . . . . . . . . 0.9 Watts Cerdip (Q) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.1 Watts LCC (E) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.8 Watts Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – V S Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . – 6 V Storage Temperature Range (Q) . . . . . . . . –65(cid:176) C to +150(cid:176) C (N, R) . . . . . . . . . . . . . . . . . . . . . . . . . . –65(cid:176) C to +125(cid:176) C Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . +175(cid:176) C Lead Temperature Range (Soldering 60 sec) . . . . . . . +300(cid:176) C NOTES 1Stresses above those listed under “Absolute Maximum Ratings” may cause per- manent damage to the device. This is a stress rating only, and functional opera- tion of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2LCC: q = 150(cid:176) C/Watt JA Mini-DIP Package: q = 110(cid:176) C/Watt JA Cerdip Package: q = 110(cid:176)C/Watt JA Small Outline Package: q = 155(cid:176)C/Watt. JA ORDERING GUIDE Gain Min Max Bandwidth Stable Offset Voltage Temperature Package Model MHz Gain mV Range – (cid:56)C Option1 AD848JN 175 5 1 0 to +70 N-8 AD848JR2 175 5 1 0 to +70 R-8 AD848JCHIPS 175 5 1 0 to +70 Die Form AD848AQ 175 5 1 –40 to +85 Q-8 AD848SQ 175 5 1 –55 to +125 Q-8 AD848SQ/883B 175 5 1 –55 to +125 Q-8 AD848SE/883B 175 5 1 –55 to +125 E-20A AD849JN 725 25 1 0 to +70 N-8 AD849JR2 725 25 1 0 to +70 R-8 AD849AQ 725 25 0.75 –40 to +85 Q-8 AD849SQ 725 25 0.75 –55 to +125 Q-8 AD849SQ/883B 725 25 0.75 –55 to +125 Q-8 AD847J/A/S 50 1 1 See AD847 Data Sheet NOTES 1E = LCC; N = Plastic DIP; Q = Cerdip; R = Small Outline IC (SOIC). 2Plastic SOIC (R) available in tape and reel. AD848 available in S grade chips. AD849 available in J and S grade chips. –4– REV. B

AD848/AD849 Figure 1.AD848 Inverting Amplifier Configuration Figure 2.AD849 Inverting Amplifier Configuration Figure 1a.AD848 Large Signal Pulse Response Figure 2a.AD849 Large Signal Pulse Response Figure 1b.AD848 Small Signal Pulse Response Figure 2b.AD849 Small Signal Pulse Response OFFSET NULLING The input voltage of the AD848 and AD849 are very low for high speed op amps, but if additional nulling is required, the circuit shown in Figure 3 can be used. For high performance circuits it is recommended that a resistor (R in Figures 1 and 2) be used to reduce bias current errors by B matching the impedance at each input. The offset voltage error caused by the input currents is decreased by more than an order of magnitude. Figure 3.Offset Nulling REV. B –5–

AD848/AD849–Typical Characteristics (@ T = +25(cid:56)C and V = (cid:54)15V, unless otherwise noted) A S Figure 4.Quiescent Current vs. Figure 5.Large Signal Frequency Figure 6.Output Voltage Swing vs. Supply Voltage (AD848 and AD849) Response (AD848 and AD849) Load Resistance (AD848 and AD849) Figure 7. Open Loop Gain vs. Figure 8. Open Loop Gain vs. Figure 9.Output Swing and Load Resistance (AD848) Load Resistance (AD849) Error vs. Settling Time (AD848) Figure 10. Quiescent Current vs. Figure 11. Short Circuit Current Figure 12.Input Bias Current vs. Temperature (AD848 and AD849) Limit vs. Temperature (AD848 Temperature (AD848 and AD849) and AD849) –6– REV. B

AD848/AD849 Figure 13.Open Loop Gain and Figure 14. Open Loop Gain and Figure 15. Normalized Gain Band- Phase Margin vs. Frequency (AD848) Phase Margin vs. Frequency (AD849) width Product vs. Temperature (AD848 and AD849) Figure 16.Harmonic Distortion vs. Figure 17. Harmonic Distortion vs. Figure 18. Slew Rate vs. Temperature Frequency (AD848) Frequency (AD849) (AD848 and AD849) Figure 19. Power Supply Rejection vs. Figure 20. Power Supply Rejection vs. Figure 21. Common-Mode Frequency (AD848) Frequency (AD849) Rejection vs. Frequency REV. B –7–

AADD884488//AADD884499–Applications GROUNDING AND BYPASSING Often termination is not used, either because signal integrity In designing practical circuits with the AD848 or AD849, the requirements are low or because too many high frequency user must remember that whenever high frequencies are signals returned to ground contaminate the ground plane. involved, some special precautions are in order. Circuits must Unterminated cables appear as capacitive loads. Since the be built with short interconnect leads. A large ground plane AD848 and AD849 are stable into any capacitive load, the op should be used whenever possible to provide a low resistance, amp will not oscillate if the cable is not terminated; however low inductance circuit path, as well as minimizing the effects of pulse integrity will be degraded. Figure 23 shows the AD848 0 high frequency coupling. Sockets should be avoided because the driving both 100pF and 1000pF loads. 9 9/ increased interlead capacitance can degrade bandwidth. – 5 – LOW NOISE PRE-AMP b Feedback resistors should be of low enough value to assure that 1 the time constant formed with the capacitances at the amplifier The input voltage noise spectral densities of the AD848 and the 126 AD849 are shown in Figure 24. The low wideband noise and C summing junction will not limit the amplifier performance. Resistor values of less than 5kW are recommended. If a larger high gain bandwidths of these devices makes them well suited as pre-amps for high frequency systems. resistor must be used, a small (< 10pF) feedback capacitor in parallel with the feedback resistor, R , may be used to compen- F sate for the input capacitances and optimize the dynamic per- formance of the amplifier. Power supply leads should be bypassed to ground as close as possible to the amplifier pins. 0.1m F ceramic disc capacitors are recommended. VIDEO LINE DRIVER The AD848 functions very well as a low cost, high speed line driver of either terminated or unterminated cables. Figure 22 shows the AD848 driving a doubly terminated cable. The termination resistor, R , (when equal to the characteristic T impedance of the cable) minimizes reflections from the far end of the cable. While operating off – 5V supplies, the AD848 maintains a typical slew rate of 200V/m s, which means it can Figure 24.Input Voltage Noise Spectral Density drive a – 1V, 24MHz signal on the terminated cable. Input voltage noise will be the dominant source of noise at the A back-termination resistor (R , also equal to the characteristic BT output in most applications. Other noise sources can be impedance of the cable) may be placed between the AD848 minimized by keeping resistor values as small as possible. output and the cable in order to damp any reflected signals caused by a mismatch between R and the cable’s characteristic T impedance. This will result in a “cleaner” signal, although it OUTLINE DIMENSIONS requires that the op amp supply – 2V to the output in order to Dimensions shown in inches and (mm). achieve a – 1V swing at the line. Mini-DIP (N) Package Cerdip (Q) Package A. S. U. N D I Figure 22.Video Line Driver E T N RI P 100pF LOAD Small Outline (R) Package 1000pF LOAD Figure 23.AD848 Driving a Capacitive Load –8– REV. B

Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: A nalog Devices Inc.: AD848JRZ-REEL AD848JRZ AD848AQ AD848SQ/883B AD848JRZ-REEL7 AD848JNZ