60 MHz, 2000 V/μs, Monolithic Op Amp with Quad Low Noise Data Sheet AD844 FEATURES FUNCTIONAL BLOCK DIAGRAMS Wide bandwidth NULL 1 AD844 8 NULL 60 MHz at gain of −1 –IN 2 7 +VS 33 MHz at gain of −10 +IN 3 6 OUTPUT Slew rate: 2000 V/μs –VS 4 5 TZ F2a0s Mt sHezt tfluinllg p: o1w00e rn bs aton d0w.1i%dt h(1, 02 0V Vst pe-pp), RL = 500 Ω (NToOt Pto V SIEcaWle) 00897-001 Differential gain error: 0.03% at 4.4 MHz Figure 1. 8-Lead PDIP (N) and 8-Lead CERDIP (Q) Packages Differential phase error: 0.16° at 4.4 MHz NC 1 16 NC Low offset voltage: 150 μV maximum (B Grade) OFFSETNULL 2 15 OFFSETNULL Low quiescent current: 6.5 mA –IN 3 14 V+ Available in tape and reel in accordance with NC 4 13 NC EIA-481-A standard +IN 5 12 OUTPUT NC 6 AD844 11 TZ APPLICATIONS V– 7 TOP VIEW 10 NC FHliagshh s ApDeeCd in cpuurrte anmt DplAifCie irnst erfaces NC 8NC( N= oNt Oto C SOcNalNeE)CT9 NC 00897-002 Figure 2. 16-Lead SOIC (R) Package Video buffers and cable drivers Pulse amplifiers GENERAL DESCRIPTION The AD844A and AD844B are specified for the industrial temperature range of −40°C to +85°C and are available in the The AD844 is a high speed monolithic operational amplifier CERDIP (Q) package. The AD844A is also available in an 8-lead fabricated using the Analog Devices, Inc., junction isolated PDIP (N). The AD844S is specified over the military temperature complementary bipolar (CB) process. It combines high band- range of −55°C to +125°C. It is available in the 8-lead CERDIP width and very fast large signal response with excellent dc (Q) package. A and S grade chips and devices processed to performance. Although optimized for use in current-to-voltage MIL-STD-883B, Rev. C are also available. applications and as an inverting mode amplifier, it is also suitable for use in many noninverting applications. PRODUCT HIGHLIGHTS The AD844 can be used in place of traditional op amps, but its 1. The AD844 is a versatile, low cost component providing an current feedback architecture results in much better ac perfor- excellent combination of ac and dc performance. mance, high linearity, and an exceptionally clean pulse response. 2. It is essentially free from slew rate limitations. Rise and fall times are essentially independent of output level. This type of op amp provides a closed-loop bandwidth that is 3. The AD844 can be operated from ±4.5 V to ±18 V power determined primarily by the feedback resistor and is almost supplies and is capable of driving loads down to 50 Ω, as independent of the closed-loop gain. The AD844 is free from well as driving very large capacitive loads using an external the slew rate limitations inherent in traditional op amps and network. other current-feedback op amps. Peak output rate of change can 4. The offset voltage and input bias currents of the AD844 are be over 2000 V/μs for a full 20 V output step. Settling time is laser trimmed to minimize dc errors; V drift is typically 1 typically 100 ns to 0.1%, and essentially independent of gain. OS μV/°C and bias current drift is typically 9 nA/°C. The AD844 can drive 50 Ω loads to ±2.5 V with low distortion 5. The AD844 exhibits excellent differential gain and and is short-circuit protected to 80 mA. differential phase characteristics, making it suitable for a The AD844 is available in four performance grades and three variety of video applications with bandwidths up to 60 MHz. package options. In the 16-lead SOIC (RW) package, the AD844J 6. The AD844 combines low distortion, low noise, and low is specified for the commercial temperature range of 0°C to 70°C. drift with wide bandwidth, making it outstanding as an input amplifier for flash analog-to-digital converters (ADCs). Rev. G Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rliicgehntsse o ifs t hgirradn pteadrt bieys itmhaptl micaatyio rne sourl to ftrhoemrw itiss ue suen. Sdpeer caifnicya ptiaotnesn st uobr jpecatt eton tc hriagnhgtse owf iAthnoaulot gn oDteicvei.c Neso. Tel: 781.329.4700 ©1989-2017 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of thei r respective owners. Technical Support www.analog.com

AD844 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1  Response as an Inverting Amplifier ......................................... 12  Applications ....................................................................................... 1  Response as an I-V Converter .................................................. 13  Functional Block Diagrams ............................................................. 1  Circuit Description of the AD844 ............................................ 13  General Description ......................................................................... 1  Response as a Noninverting Amplifier .................................... 14  Product Highlights ........................................................................... 1  Noninverting Gain of 100 ......................................................... 14  Revision History ............................................................................... 2  Using the AD844 ............................................................................ 15  Specifications ..................................................................................... 3  Board Layout ............................................................................... 15  Absolute Maximum Ratings ............................................................ 5  Input Impedance ........................................................................ 15  Metallization Photograph ............................................................ 5  Driving Large Capacitive Loads ............................................... 15  ESD Caution .................................................................................. 5  Settling Time ............................................................................... 15  Typical Performance Characteristics ............................................. 6  DC Error Calculation ................................................................ 16  Inverting Gain-of-1 AC Characteristics .................................... 8  Noise ............................................................................................ 16  Inverting Gain-of-10 AC Characteristics .................................. 9  Video Cable Driver Using ±5 V Supplies ................................ 16  Inverting Gain-of-10 Pulse Response ...................................... 10  High Speed DAC Buffer ............................................................ 17  Noninverting Gain-of-10 AC Characteristics ........................ 11  20 MHz Variable Gain Amplifier ............................................. 17  Understanding the AD844 ............................................................ 12  Outline Dimensions ....................................................................... 19  Open-Loop Behavior ................................................................. 12  Ordering Guide .......................................................................... 20  REVISION HISTORY 5/2017—Rev. F to Rev. G 1/2003—Rev. D to Rev. E Change to Figure 32 ....................................................................... 14 Updated Features ............................................................................... 1 Edit to TPC 18 ................................................................................... 7 2/2009—Rev. E to Rev F Edits to Figure 13 and Figure 14 ................................................... 13 Updated Format .................................................................. Universal Updated Outline Dimensions ....................................................... 15 Changes to Features Section............................................................ 1 Changes to Differential Phase Error Parameter, Table 1 ............. 3 11/2001—Rev. C to Rev. D Changes to Figure 13 ........................................................................ 8 Edits to Specifications ...................................................................... 2 Changes to Figure 18 ........................................................................ 9 Edits to Absolute Maximum Ratings .............................................. 3 Changes to Figure 23 and Figure 24 ............................................. 11 Edits to Ordering Guide ................................................................... 3 Changes to Figure 42 and High Speed DAC Buffer Section ..... 17 Updated Outline Dimensions ....................................................... 19 Changes to Ordering Guide .......................................................... 20 Rev. G | Page 2 of 20

Data Sheet AD844 SPECIFICATIONS T = 25°C and V = ±15 V dc, unless otherwise noted. A S Table 1. AD844J/AD844A AD844B AD844S Parameter Conditions Min Typ Max Min Typ Max Min Typ Max Unit INPUT OFFSET VOLTAGE1 50 300 50 150 50 300 μV TMIN to TMAX 75 500 75 200 125 500 μV vs. Temperature 1 1 5 1 5 μV/°C vs. Supply 5 V to 18 V Initial 4 20 4 10 4 20 μV/V TMIN to TMAX 4 4 10 4 20 μV/V vs. Common Mode V = ±10 V CM Initial 10 35 10 20 10 35 μV/V TMIN to TMAX 10 10 20 10 35 μV/V INPUT BIAS CURRENT Negative Input Bias Current1 200 450 150 250 200 450 nA TMIN to TMAX 800 1500 750 1100 1900 2500 nA vs. Temperature 9 9 15 20 30 nA/°C vs. Supply 5 V to 18 V Initial 175 250 175 200 175 250 nA/V TMIN to TMAX 220 220 240 220 300 nA/V vs. Common Mode V = ±10 V CM Initial 90 160 90 110 90 160 nA/V TMIN to TMAX 110 110 150 120 200 nA/V Positive Input Bias Current1 150 400 100 200 100 400 nA TMIN to TMAX 350 700 300 500 800 1300 nA vs. Temperature 3 3 7 7 15 nA/°C vs. Supply 5 V to 18 V Initial 80 150 80 100 80 150 nA/V TMIN to TMAX 100 100 120 120 200 nA/V vs. Common Mode V = ±10 V CM Initial 90 150 90 120 90 150 nA/V TMIN to TMAX 130 130 190 140 200 nA/V INPUT CHARACTERISTICS Input Resistance Negative Input 50 65 50 65 50 65 Ω Positive Input 7 10 7 10 7 10 MΩ Input Capacitance Negative Input 2 2 2 pF Positive Input 2 2 2 pF Input Common-Mode Voltage ±10 ±10 ±10 V Range INPUT VOLTAGE NOISE f ≥ 1 kHz 2 2 2 nV/√Hz INPUT CURRENT NOISE Negative Input f ≥ 1 kHz 10 10 10 pV/√Hz Positive Input f ≥ 1 kHz 12 12 12 pV/√Hz OPEN-LOOP TRANSRESISTANCE V = ±10 V OUT RL = 500 Ω 2.2 3.0 2.8 3.0 2.2 3.0 MΩ TMIN to TMAX 1.3 2.0 1.6 2.0 1.3 1.6 MΩ Transcapacitance 4.5 4.5 4.5 pF DIFFERENTIAL GAIN ERROR2 f = 4.4 MHz 0.03 0.03 0.03 % DIFFERENTIAL PHASE ERROR2 f = 4.4 MHz 0.16 0.16 0.16 Degree Rev. G | Page 3 of 20

AD844 Data Sheet AD844J/AD844A AD844B AD844S Parameter Conditions Min Typ Max Min Typ Max Min Typ Max Unit FREQUENCY RESPONSE Small Signal Bandwidth3, 4 Gain = −1 60 60 60 MHz Gain = −10 33 33 33 MHz TOTAL HARMONIC DISTORTION f = 100 kHz, 0.005 0.005 0.005 % 2 V rms5 SETTLING TIME 10 V Output Step ±15 V supplies Gain = −1, to 0.1%5 100 100 100 ns Gain = −10, to 0.1%6 100 100 100 ns 2 V Output Step ±5 V supplies Gain = −1, to 0.1%5 110 110 110 ns Gain = −10, to 0.1%6 100 100 100 ns OUTPUT SLEW RATE Overdriven 1200 2000 1200 2000 1200 2000 V/μs input FULL POWER BANDWIDTH THD = 3% VOUT = 20 V p-p5 VS = ±15 V 20 20 20 MHz VOUT = 2 V p-p5 VS = ±5 V 20 20 20 MHz OUTPUT CHARACTERISTICS Voltage RL = 500 Ω ±10 ±11 ±10 ±11 ±10 ±11 V Short-Circuit Current 80 80 80 mA TMIN to T MAX 60 60 60 mA Output Resistance Open loop 15 15 15 Ω POWER SUPPLY Operating Range ±4.5 ±18 ±4.5 ±18 ±4.5 ±18 V Quiescent Current 6.5 7.5 6.5 7.5 6.5 7.5 mA TMIN to TMAX 7.5 8.5 7.5 8.5 7.5 8.5 mA 1 Rated performance after a 5 minute warm-up at TA = 25°C. 2 Input signal 285 mV p-p carrier (40 IRE) riding on 0 mV to 642 mV (90 IRE) ramp. RL = 100 Ω; R1, R2 = 300 Ω. 3 For gain = −1, input signal = 0 dBm, CL = 10 pF, RL = 500 Ω, R1 = 500 Ω, and R2 = 500 Ω in Figure 29. 4 For gain = −10, input signal = 0 dBm, CL =10 pF, RL = 500 Ω, R1 = 500 Ω, and R2 = 50 Ω in Figure 29. 5 CL = 10 pF, RL = 500 Ω, R1 = 1 kΩ, R2 = 1 kΩ in Figure 29. 6 CL = 10 pF, RL = 500 Ω, R1 = 500 Ω, R2 = 50 Ω in Figure 29. Rev. G | Page 4 of 20

Data Sheet AD844 ABSOLUTE MAXIMUM RATINGS METALLIZATION PHOTOGRAPH Table 2. Parameter Ratings Contact factory for latest dimensions. Supply Voltage ±18 V Dimensions shown in inches and (millimeters). Power Dissipation1 1.1 W –IN NULL NULL +VS Output Short-Circuit Duration Indefinite Input Common-Mode Voltage ±VS Differential Input Voltage 6 V Inverting Input Current Continuous 5 mA Transient 10 mA 0.076 Storage Temperature Range (Q) −65°C to +150°C (1.9) Storage Temperature Range (N, RW) −65°C to +125°C Lead Temperature (Soldering, 60 sec) 300°C ESD Rating 1000 V 1 28-lead PDIP package: θJA = 90°C/W. 8-lead CERDIP package: θJA = 110°C/W. 16-lead SOIC package: θJA = 100°C/W. +IN –VS TZ OUTPUT Stresses at or above those listed under Absolute Maximum 0.095 Rstaretisnsg rsa tminagy ocnaulys;e f upnercmtioannaenl ot pdearmataigoen toof tthhee pprroodduucctt. aTth tihse isse a SUBSTRATE CO(2N.4N)ECTED TO +VS 00897-003 Figure 3. Die Photograph or any other conditions above those indicated in the operational ESD CAUTION section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. Rev. G | Page 5 of 20

AD844 Data Sheet TYPICAL PERFORMANCE CHARACTERISTICS T = 25°C and V = ±15 V, unless otherwise noted. A S 70 20 TA = 25°C 60 15 WIDTH (MHz) 50 LTAGE (V) 10 D O N V A T B U 3dB INP – 40 5 30 0 0 5 SUPPLY VO10LTAGE (±V) 15 20 00897-004 0 5 SUPPLY VO10LTAGE (±V) 15 20 00897-007 Figure 4. −3 dB Bandwidth vs. Supply Voltage, R1 = R2 = 500 Ω Figure 7. Noninverting Input Voltage Swing vs. Supply Voltage –60 20 1V rms RL = 500Ω TA = 25°C –70 B) 15 ON (d –80 E (V) TI G OR –90 TA ST OL 10 C DI –100 UT V NI P ARMO –110 SECOND HARMONIC OUT 5 H –120 THIRD HARMONIC –130 0 100 IN1kPUT FREQUENCY (1H0zk) 100k 00897-005 0 5 SUPPLY VO10LTAGE (±V) 15 20 00897-008 Figure 5. Harmonic Distortion vs. Input Frequency, R1 = R2 = 1 kΩ Figure 8. Output Voltage Swing vs. Supply Voltage 5 10 RL =∞ 9 4 CE (MΩ) 3 RL = 500Ω NT (mA) 8 N E A R T R 7 S U SI C NSRE 2 PPLY 6 VS = ±15V A U TR 1 RL = 50Ω S VS = ±5V 5 0 4 –50 0 TEMPERA50TURE (°C) 100 150 00897-006 –60 –40 –20 0 TEM20PERA40TURE6 0(-°C)80 100 120 140 00897-009 Figure 6. Transresistance vs. Temperature Figure 9. Quiescent Supply Current vs. Temperature and Supply Voltage Rev. G | Page 6 of 20

Data Sheet AD844 2 40 35 VS = ±15V T (µA) 1 IBP MHz) 30 EN H ( R T R D BIAS CU 0 BANDWI 25 VS = ±5V T B 20 U d P 3 N –1 – I IBN 15 –2 10 –50 0 TEMPERA50TURE (°C) 100 150 00897-010 –60 –40 –20 0 TEM20PERA40TURE6 0(-°C)80 100 120 140 00897-012 Figure 10. Inverting Input Bias Current (IBN) and Noninverting Input Bias Figure 12. –3 dB Bandwidth vs. Temperature, Gain = −1, R1 = R2 = 1 kΩ Current (IBP) vs. Temperature 100 Ω) 10 E ( C N A ±5V SUPPLIES D PE 1 M T I U P T U O 0.1 0.01 10k 100k FREQU1EMNCY (Hz) 10M 100M 00897-011 Figure 11. Output Impedance vs. Frequency, Gain = −1, R1 = R2 = 1 kΩ Rev. G | Page 7 of 20

AD844 Data Sheet INVERTING GAIN-OF-1 AC CHARACTERISTICS +VS 5V 4.7Ω 0.22µF 100 R1 90 R2 –IN – AD844 OUTPUT + RL CL 10 0.22µF 0 –VS 4.7Ω 00897-013 20ns 00897-016 Figure 13. Inverting Amplifier, Gain of −1 (R1 = R2) Figure 16. Large Signal Pulse Response, Gain = −1, R1 = R2 = 1 kΩ 6 500nV R1 = R2 = 500Ω 100 0 90 R1 = R2 = 1kΩ –6 B) d N ( AI G –12 10 –18 0 –24 20ns 00897-017 100k 1MFREQUENCY (Hz)10M 100M 00897-014 Figure 17. Small Signal Pulse Response, Gain = −1, R1 = R2 = 1 kΩ Figure 14. Gain vs. Frequency for Gain = −1, RL = 500 Ω, CL = 0 pF –180 –210 s) R1 = R2 = 500Ω ee –240 gr e D E ( AS –270 PH R1 = R2 = 1kΩ –300 –330 0 FREQUE2N5CY (MHz) 50 00897-015 Figure 15. Phase vs. Frequency for Gain = −1, RL = 500 Ω, CL = 0 pF Rev. G | Page 8 of 20

Data Sheet AD844 INVERTING GAIN-OF-10 AC CHARACTERISTICS +VS 26 4.7Ω 0.22µF RL = 500Ω 500Ω 20 50Ω 14 RL = 50Ω –IN – B) AD844 OUTPUT N (d + AI G 8 RL CL 0.22µF 2 –VS 4.7Ω 00897-018 –4 100k 1MFREQUENCY (Hz)10M 100M 00897-019 Figure 18. Gain of −10 Amplifier Figure 19. Gain vs. Frequency, Gain = −10 –180 –210 RL = 50Ω RL = 500Ω s) ee–240 gr e D E ( AS–270 H P –300 –330 0 FREQUE2N5CY (MHz) 50 00897-020 Figure 20. Phase vs. Frequency, Gain = −10 Rev. G | Page 9 of 20

AD844 Data Sheet INVERTING GAIN-OF-10 PULSE RESPONSE 5V 500nV 100 100 90 90 10 10 0 0 20ns 00897-021 20ns 00897-022 Figure 21. Large Signal Pulse Response, Gain = –10, RL = 500 Ω Figure 22. Small Signal Pulse Response, Gain = −10, RL = 500 Ω Rev. G | Page 10 of 20

Data Sheet AD844 NONINVERTING GAIN-OF-10 AC CHARACTERISTICS 4.7Ω +VS 0.22µF 2V 100ns 100 450Ω 90 50Ω – OUTPUT AD844 –IN + 0.22µF RL CL –VS 4.7Ω 00897-023 100 00897-026 Figure 23. Noninverting Gain of +10 Amplifier Figure 26. Noninverting Amplifier Large Signal Pulse Response, Gain = +10, RL = 500 Ω 26 200nV 50ns 20 100 RL = 50Ω RL = 500Ω 90 14 B) d N ( AI G 8 2 10 0 –4100k 1MFREQUENCY (Hz)10M 100M 00897-024 00897-027 Figure 24. Gain vs. Frequency, Gain = +10 Figure 27. Small Signal Pulse Response, Gain = +10, RL = 500 Ω –180 –210 RL = 50Ω RL = 500Ω s) ee–240 gr e D E ( AS–270 H P –300 –330 0 FREQUE2N5CY (MHz) 50 00897-025 Figure 25. Phase vs. Frequency, Gain = +10 Rev. G | Page 11 of 20

AD844 Data Sheet UNDERSTANDING THE AD844 The AD844 can be used in ways similar to a conventional op RESPONSE AS AN INVERTING AMPLIFIER amp while providing performance advantages in wideband Figure 29 shows the connections for an inverting amplifier. applications. However, there are important differences in the Unlike a conventional amplifier, the transient response and the internal structure that need to be understood to optimize the small signal bandwidth are determined primarily by the value of performance of the AD844 op amp. the external feedback resistor, R1, rather than by the ratio of OPEN-LOOP BEHAVIOR R1/R2 as is customarily the case in an op amp application. This is a direct result of the low impedance at the inverting input. As Figure 28 shows a current feedback amplifier reduced to essen- with conventional op amps, the closed-loop gain is −R1/R2. tials. Sources of fixed dc errors, such as the inverting node bias current and the offset voltage, are excluded from this model. The closed-loop transresistance is the parallel sum of R1 and R. t The most important parameter limiting the dc gain is the Because R1 is generally in the range of 500 Ω to 2 kΩ and R is t transresistance, R, which is ideally infinite. A finite value of R about 3 MΩ, the closed-loop transresistance is only 0.02% to t t is analogous to the finite open-loop voltage gain in a conventional 0.07% lower than R1. This small error is often less than the op amp. resistor tolerance. The current applied to the inverting input node is replicated by When R1 is fairly large (above 5 kΩ) but still much less than R, t the current conveyor to flow in Resistor R. The voltage developed the closed-loop HF response is dominated by the time constant t across R is buffered by the unity gain voltage follower. Voltage R1 C. Under such conditions, the AD844 is overdamped and t t gain is the ratio R/R . With typical values of R = 3 MΩ and provides only a fraction of its bandwidth potential. Because of t IN t R = 50 Ω, the voltage gain is about 60,000. The open-loop the absence of slew rate limitations under these conditions, the IN current gain, another measure of gain that is determined by the circuit exhibits a simple single-pole response even under large beta product of the transistors in the voltage follower stage (see signal conditions. Figure 31), is typically 40,000. In Figure 29, R3 is used to properly terminate the input if desired. R3 in parallel with R2 gives the terminated resistance. As R1 is +1 lowered, the signal bandwidth increases, but the time constant R1 C becomes comparable to higher order poles in the closed- t IIN Rt Ct +1 loop response. Therefore, the closed-loop response becomes RIN IIN 00897-028 ciso mmupclehx l, aarngder t hthea pnu tlhsee rinesppuotn rsees isshtaonwcse ,o RveINr,s ahto Poitn. W2, hmenos Rt 2o f Figure 28. Equivalent Schematic the feedback current in R1 is delivered to this input, but as R2 becomes comparable to R , less of the feedback is absorbed at IN The important parameters defining ac behavior are the Pin 2, resulting in a more heavily damped response. Consequently, transcapacitance, C, and the external feedback resistor (not t for low values of R2, it is possible to lower R1 without causing shown). The time constant formed by these components is instability in the closed-loop response. Table 3 lists combinations analogous to the dominant pole of a conventional op amp and of R1 and R2 and the resulting frequency response for the circuit thus cannot be reduced below a critical value if the closed-loop of Figure 29. Figure 16 shows the very clean and fast ±10 V system is to be stable. In practice, C is held to as low a value as t pulse response of the AD844. possible (typically 4.5 pF) so that the feedback resistor can be R1 maximized while maintaining a fast response. The finite R IN also affects the closed-loop response in some applications. The open-loop ac gain is also best understood in terms of the R2 VIN transimpedance rather than as an open-loop voltage gain. The R3 AD844 VOUT open-loop pole is formed by R in parallel with C. Because C is OPTIONAL t t t typically 4.5 pF, the open-loop corner frequency occurs at about RL CL 1th2e k cHlozs.e Hd-olwooepve rre, stphoisn psea.r ameter is of little value in determining 00897-029 Figure 29. Inverting Amplifier Rev. G | Page 12 of 20

Data Sheet AD844 R1 Table 3. Gain vs. Bandwidth Gain R1 R2 BW (MHz) GBW (MHz) ISIG −1 1 kΩ 1 kΩ 35 35 −1 500 Ω 500 Ω 60 60 CS AD844 VOUT −2 2 kΩ 1 kΩ 15 30 −2 1 kΩ 500 Ω 30 60 RL CL −−55 55 0k0Ω Ω 110 k0Ω Ω 459.2 22465 00897-030 Figure 30. Current-to-Voltage Converter −10 1 kΩ 100 Ω 23 230 CIRCUIT DESCRIPTION OF THE AD844 −10 500 Ω 50 Ω 33 330 −20 1 kΩ 50 Ω 21 420 A simplified schematic is shown in Figure 31. The AD844 differs −100 5 kΩ 50 Ω 3.2 320 from a conventional op amp in that the signal inputs have RESPONSE AS AN I-V CONVERTER radically different impedance. The noninverting input (Pin 3) presents the usual high impedance. The voltage on this input is The AD844 works well as the active element in an operational transferred to the inverting input (Pin 2) with a low offset voltage, current-to-voltage converter, used in conjunction with an ensured by the close matching of like polarity transistors operating external scaling resistor, R1, in Figure 30. This analysis includes under essentially identical bias conditions. Laser trimming nulls the stray capacitance, C, of the current source, which may be a S the residual offset voltage, down to a few tens of microvolts. The high speed DAC. Using a conventional op amp, this capacitance inverting input is the common emitter node of a complementary forms a nuisance pole with R1 that destabilizes the closed-loop pair of grounded base stages and behaves as a current summing response of the system. Most op amps are internally compensated node. In an ideal current feedback op amp, the input resistance for the fastest response at unity gain, so the pole due to R1 and is zero. In the AD844, it is about 50 Ω. C reduces the already narrow phase margin of the system. For S example, if R1 is 2.5 kΩ, a C of 15 pF places this pole at a A current applied to the inverting input is transferred to a S frequency of about 4 MHz, well within the response range of even complementary pair of unity-gain current mirrors that deliver a medium speed operational amplifier. In a current feedback amp, the same current to an internal node (Pin 5) at which the full this nuisance pole is no longer determined by R1 but by the output voltage is generated. The unity-gain complementary input resistance, R . Because this is about 50 Ω for the AD844, voltage follower then buffers this voltage and provides the load IN the same 15 pF forms a pole at 212 MHz and causes little driving power. This buffer is designed to drive low impedance trouble. It can be shown that the response of this system is: loads, such as terminated cables, and can deliver ±50 mA into a 50 Ω load while maintaining low distortion, even when operating KR1 V I at supply voltages of only ±6 V. Current limiting (not shown) OUT sig 1sTd1sTn ensures safe operation under short-circuited conditions. where: 7 +VS K is a factor very close to unity and represents the finite dc gain of the amplifier. IB Td is the dominant pole. Tn is the nuisance pole. R +IN 3 2 –IN TZ 5 6 OUTPUT K  t R R1 t Td = KR1C t Tn = R C (assuming R << R1) IB IN S IN Uotshinerg wtyopridcsa,l tvhael ugeasin o fe rRr1o r= i s1 oknΩly a 0n.d03 R%t .= T 3h Mis Ωis ,m Ku =ch 0 l.9es9s9 t7h; ainn 4 –VS 00897-031 Figure 31. Simplified Schematic the scaling error of virtually all DACs and can be absorbed, if necessary, by the trim needed in a precise system. In the AD844, R is fairly stable with temperature and supply t voltages, and consequently the effect of finite gain is negligible unless high value feedback resistors are used. Because that results in slower response times than are possible, the relatively low value of R in the AD844 is rarely a significant source of error. t Rev. G | Page 13 of 20

AD844 Data Sheet It is important to understand that the low input impedance at NONINVERTING GAIN OF 100 the inverting input is locally generated and does not depend on The AD844 provides very clean pulse response at high feedback. This is very different from the virtual ground of a noninverting gains. Figure 32 shows a typical configuration conventional operational amplifier used in the current summing providing a gain of 100 with high input resistance. The feedback mode, which is essentially an open circuit until the loop settles. resistor is kept as low as practicable to maximize bandwidth, In the AD844, transient current at the input does not cause and a peaking capacitor (C ) can optionally be added to PK voltage spikes at the summing node while the amplifier is further extend the bandwidth. Figure 33 shows the small signal settling. Furthermore, all of the transient current is delivered response with C = 3 nF, R = 500 Ω, and supply voltages of PK L to the slewing (TZ) node (Pin 5) via a short signal path (the either ±5 V or ±15 V. Gain bandwidth products of up to grounded base stages and the wideband current mirrors). 900 MHz can be achieved in this way. The current available to charge the capacitance (about 4.5 pF) at The offset voltage of the AD844 is laser trimmed to the 50 μV the TZ node is always proportional to the input error current, level and exhibits very low drift. In practice, there is an and the slew rate limitations associated with the large signal additional offset term due to the bias current at the inverting response of the op amps do not occur. For this reason, the rise input (I ), which flows in the feedback resistor (R1). This can BN and fall times are almost independent of signal level. In practice, optionally be nulled by the trimming potentiometer shown in the input current eventually causes the mirrors to saturate. Figure 32. When using ±15 V supplies, this occurs at about 10 mA (or ±2200 V/μs). Because signal currents are rarely this large, +VS classical slew rate limitations are absent. 4.7Ω OFFSET This inherent advantage is lost if the voltage follower used to TRIM bduesfifgern ethde t oo uatvpouidt hthasis s plerwob rlaetme l, iamnidta atsio an rse. sTuhlte, AthDe 8o4u4tp ius t C3nPKF 20kΩ 49R91Ω buffer exhibits a clean large signal transient response, free from 1 anomalous effects arising from internal saturation. 8 0.22µF RESPONSE AS A NONINVERTING AMPLIFIER 2 R2 7 4.99Ω Because current feedback amplifiers are asymmetrical with AD844 6 regard to their two inputs, performance differs markedly in VIN 3 RL noninverting and inverting modes. In noninverting modes, the 4 0.22µF large signal high speed behavior of the AD844 deteriorates at 4.7Ω low gains because the biasing circuitry for the input system (not svhooltwagne isnl eFwig ruartee s3. 1) is not designed to provide high input –VS 00897-032 Figure 32. Noninverting Amplifier Gain = 100, Optional Offset Trim Is Shown However, good results can be obtained with some care. The 46 noninverting input does not tolerate a large transient input; it must be kept below ±1 V for best results. Consequently, this VS = ±15V 40 mode is better suited to high gain applications (greater than ×10). Figure 23 shows a noninverting amplifier with a gain of 10 VS = ±5V and a bandwidth of 30 MHz. The transient response is shown in B) 34 d Figure 26 and Figure 27. To increase the bandwidth at higher N ( gains, a capacitor can be added across R2 whose value is GAI 28 approximately (R1/R2) × C. t 22 16 100k FRE1QMUENCY (Hz) 10M 20M 00897-040 Figure 33. AC Response for Gain = 100, Configuration Shown in Figure 32 Rev. G | Page 14 of 20

Data Sheet AD844 USING THE AD844 BOARD LAYOUT As with all high frequency circuits considerable care must be used in the layout of the components surrounding the AD844. AD844 6 VOUT 5 A ground plane, to which the power supply decoupling capaci- taeoxcrhhsii ebavirteisn cfgoi ncnilnteeae ncvto peldtua lbgseye rdtherseop psohsn obsreett.e wEstev epenno spas oicbionlent stli eonanud ost,hu iess gperlsaosneunen,td iaa npl dltao n e 750Ω 22pF CL 00897-034 Figure 34. Feedforward Network for Large Capacitive Loads this must be kept in mind when selecting the grounding points. In general, decoupling capacitors should be taken to a point 5V close to the load (or output connector) because the load 100 currents flow in these capacitors at high frequencies. The +IN 90 and −IN circuits (for example, a termination resistor and Pin 3) must be taken to a common point on the ground plane close to the amplifier package. Use low impedance 0.22 μF capacitors (AVX SR305C224KAA or equivalent) wherever ac coupling is required. Include either ferrite beads and/or a small series resistance (approximately 10 4.7 Ω) in each supply line. 0 INPUT IMPEDANCE 500ns 00897-035 At low frequencies, negative feedback keeps the resistance at the Figure 35. Driving 1000 pF CL with Feedforward Network of Figure 34 inverting input close to zero. As the frequency increases, the SETTLING TIME impedance looking into this input increases from near zero to Settling time is measured with the circuit of Figure 36. This the open-loop input resistance, due to bandwidth limitations, circuit employs a false summing node, clamped by the two making the input seem inductive. If it is desired to keep the Schottky diodes, to create the error signal and limit the input input impedance flatter, a series RC network can be inserted signal to the oscilloscope. For measuring settling time, the ratio across the input. The resistor is chosen so that the parallel sum of R6/R5 is equal to R1/R2. For unity gain, R6 = R5 = 1 kΩ, and of it and R2 equals the desired termination resistance. The capacit- R = 500 Ω. For the gain of −10, R5 = 50 Ω, R6 = 500 Ω, and R ance is set so that the pole determined by this RC network is L L was not used because the summing network loads the output about half the bandwidth of the op amp. This network is not with approximately 275 Ω. Using this network in a unity-gain important if the input resistor is much larger than the termination configuration, settling time is 100 ns to 0.1% for a –5 V to +5 V used, or if frequencies are relatively low. In some cases, the step with C = 10 pF. small peaking that occurs without the network can be of use in L extending the −3 dB bandwidth. TO SCOPE (TEK 7A11 FET PROBE) DRIVING LARGE CAPACITIVE LOADS R5 R6 Capacitive drive capability is 100 pF without an external net- work. With the addition of the network shown in Figure 34, D1 D2 the capacitive drive can be extended to over 10,000 pF, limited R1 by internal power dissipation. With capacitive loads, the output speed becomes a function of the overdriven output current limit. VIN Because this is roughly ±100 mA, under these conditions, the R2 AD844 VOUT maximum slew rate into a 1000 pF load is ±100 V/μs. Figure 35 R3 shows the transient response of an inverting amplifier (R1 = RL CL R2 = 1 kΩ) using the feedforward network shown in Figure 34, driving a load of 1000 pF. N1.O DT1E, SD2 IN6263 OR EQUIVALENT SCHOTTKY DIODE. 00897-036 Figure 36. Settling Time Test Fixture Rev. G | Page 15 of 20

AD844 Data Sheet DC ERROR CALCULATION +5V 2.2µF Figure 37 shows a model of the dc error and noise sources for the AD844. The inverting input bias current, IBN, flows in the VIN50Ω 32 7 6 50Ω ZO = 50Ω VOUT feedback resistor. I , the noninverting input bias current, flows 4 RL BP 2.2µF 50Ω in the resistance at Pin 3 (R ), and the resulting voltage (plus 300Ω P –5V any offset voltage) appears at the inverting input. The total error,V VO, atI theR outpVut is: I R 1 R1I R1 Figure 38. The AD844 3a0s0 aΩ Cable Driver 00897-038 O BP P OS BN IN  R2 BN Because I and I are unrelated both in sign and magnitude, BN BP RF OUT IN OUT VIN innoste nrteicnegs saa rreilsyis rteodr uince s derci eesr rwoirt han tdh em naoyn ainctvuearltliyn gin icnrpeuast ed iote. s ANHNEPAT8LW7Y5OZ3REAKR RF IN OUT HSPPL11IT8T5E0CR VIN CUITNREDCSEUTRIT VOUT R1 EXT 50Ω OUT TRIG (TERMINATOR) 470Ω SYNC OUT R2 VN RIN GSETHNAPEI3RR3C1AA4TASOER OUT 00897-039 Figure 39. Differential Gain/Phase Test Setup INN IBN VOS 0.3 IRE = 7.14mV INP IBP 0.2 s) e e RP AD844 Degr 0.1 00897-037 PHASE ( 0 Figure 37. Offset Voltage and Noise Model for the AD844 L A TI NOISE EN –0.1 R E F Noise sources can be modeled in a manner similar to the dc bias F DI –0.2 currents, but the noise sources are I , I , V , and the amplifier NN NP N induced noise at the output, V , is: ON –0.3 V  I R 2 V 21 R12 I R12 0 18 36VOUT (IRE)54 72 90 00897-040 ON NP P N  R2 NN Figure 40. Differential Phase for the Circuit of Figure 38 0.06 Overall noise can be reduced by keeping all resistor values to a IRE = 7.14mV minimum. With typical numbers, R1 = R2 = 1 kΩ, R = 0 Ω, P 0.04 V = 2 nV/√Hz, I = 10 pA/√Hz, I = 12 pA/√Hz, and V N NP NN ON calculates to 12 nV/√Hz. The current noise is dominant in this %) case, because it is in most low gain applications. N ( 0.02 AI G VIDEO CABLE DRIVER USING ±5 V SUPPLIES L A 0 TI N The AD844 can be used to drive low impedance cables. Using E R ±5 V supplies, a 100 Ω load can be driven to ±2.5 V with low FE–0.02 F distortion. Figure 38 shows an illustrative application that DI provides a noninverting gain of +2, allowing the cable to be –0.04 reverse-terminated while delivering an overall gain of +1 to the load. The −3 dB bandwidth of this circuit is typically 30 MHz. –0.06 Figure 39 shows a differential gain and phase test setup. In video 0 18 36VOUT (IRE)54 72 90 00897-041 applications, differential-phase and differential-gain characteris- Figure 41. Differential Gain for the Circuit of Figure 38 tics are often important. Figure 40 shows the variation in phase as the load voltage varies. Figure 41 shows the gain variation. Rev. G | Page 16 of 20

Data Sheet AD844 1 MSB +15V(VCC) 24 0.22µF* 0.22µF* +15V 2 REFCOM 23 0.22µF* 0.22µF* 3 –15V(VEE) 22 –15V 4 IBPO 21 2 7 5 IOUT 20 AD844 6 VOUT DINIGPIUTTASL 6 AD568 RL 19 3 4 RI 7 ACOM 18 ANALOG 8 LCOM 17 SUPPLY GROUND 9 SPAN 16 10 SPAN 15 GROUND 11 THCOM 14 DIGITAL 12 LSB VTH 13 100pF SUPPLY –5V TOP VIEW *POWER SUPPLY(N BoYt PtoA SSSca CleA)PACITORS. 00897-042 Figure 42. High Speed DAC Amplifier HIGH SPEED DAC BUFFER 20 MHZ VARIABLE GAIN AMPLIFIER The AD844 performs very well in applications requiring current- The AD844 is an excellent choice as an output amplifier for the to-voltage conversion. Figure 42 shows connections for use with AD539 multiplier, in all of its connection modes. (See the the AD568 current output DAC. In this application, the bipolar AD539 data sheet for full details.) Figure 44 shows a simple offset is used so that the full-scale current is ±5.12 mA, which multiplier providing the output: generates an output of ±5.12 V using the 1 kΩ application resistor V V on the AD568. Figure 43 shows the full-scale transient response. V  X Y (1) W 2V Care is needed in power supply decoupling and grounding techniques to achieve the full 12-bit accuracy and realize the where VX is the gain control input, a positive voltage from 0 V fast settling capabilities of the system. The AD568 data sheet to 3.2 V (maximum), and VY is the signal voltage, nominally should be consulted for more complete details about its use. ±2 V full scale but capable of operation up to ±4.2 V. The peak output in this configuration is thus ±6.7 V. Using all 2V four of the internal application resistors provided on the AD539 100 in parallel results in a feedback resistance of 1.5 kΩ, at which 90 value the bandwidth of the AD844 is about 22 MHz, and is essentially independent of V . The gain at V = 3.16 V is 4 dB. X X +VS TYP +6V 10Ω 10Ω AT 15µA 0.22µF 0.22µF INPUTS 100 0V TOV 3XV* 1 16 50ns 00897-043 ±2VV FYS* 23 1154 2 7 Figure 43. DAC Amplifier Full-Scale Transient Response 4 AD539 13 AD844 6 3nF 5 (NToOt Pto V SIEcaWle)12 3 4 OVWUTPUT 6 11 –VXVY INPUT 7 10 0.22µF VW= 2V GND 8 9 10Ω –VS 0.22µF TYP –6V 10Ω AT 15µA * TVYXP AICNADL VLYY I NBPYU UTSSIN MGA AY 5O0PΩT IOORN A75LΩL YR EBSEI STTEORRM ITNOA TGERDO;UND. 00897-044 Figure 44. 20 MHz VGA Using the AD539 Rev. G | Page 17 of 20

AD844 Data Sheet Figure 45 shows the small signal response for a 50 dB gain control 4 VX = 3.15V range (V = 10 mV to 3.16 V). At small values of V , capacitive X X feedthrough on the PC board becomes troublesome and very –6 VX = 1.0V careful layout techniques are needed to minimize this problem. A ground strip between the pins of the AD539 is helpful in this –16 VX = 0.316V regard. Figure 46 shows the response to a 2 V pulse on V for B) Y d V = 1 V, 2 V, and 3 V. For these results, a load resistor of 500 Ω N ( –26 X AI VX = 0.10V was used and the supplies were ±9 V. The multiplier operates G from supplies between ±4.5 V and ±16.5 V. –36 VX = 0.032V Disconnecting Pin 9 and Pin 16 on the AD539 alters the –46 denominator in Equation 1 to 1 V, and the bandwidth is approximately 10 MHz, with a maximum gain of 10 dB. –56 Ua bsianngd ownildyt hP ionf 95 oMr HPizn, a1n6d r eas multasx iinm au mde ngaoimn ionfa 1to6r d oBf. 0 .5 V, 100k 1MFREQUENCY (Hz) 10M 60M 00897-045 Figure 45. VGA AC Response 1V 1V 50ns 100 90 10 0 00897-046 Figure 46. VGA Transient Response with VX = 1 V, 2 V, and 3 V Rev. G | Page 18 of 20

Data Sheet AD844 OUTLINE DIMENSIONS 0.400 (10.16) 0.365 (9.27) 0.355 (9.02) 8 5 0.280 (7.11) 0.250 (6.35) 1 4 0.240 (6.10) 0.325 (8.26) 0.310 (7.87) 0.100 (2.54) 0.300 (7.62) BSC 0.060 (1.52) 0.195 (4.95) 0.210 (5.33) MAX 0.130 (3.30) MAX 0.115 (2.92) 0.015 0.150 (3.81) (0.38) 0.015 (0.38) 0.130 (3.30) MIN GAUGE 0.115 (2.92) SEATING PLANE 0.014 (0.36) PLANE 0.010 (0.25) 0.022 (0.56) 0.008 (0.20) 0.005 (0.13) 0.430 (10.92) 0.018 (0.46) MIN MAX 0.014 (0.36) 0.070 (1.78) 0.060 (1.52) 0.045 (1.14) COMPLIANTTO JEDEC STANDARDS MS-001 CONTROLLING DIMENSIONSARE IN INCHES; MILLIMETER DIMENSIONS (RCINEOFRPEANRREERENN LCTEEHA EODSNSEL MSY)AAAYNR BDEE AR CROOEU NNNFODIGETUDAR-POEPFDRFOA INSPC RWHIAH ETOEQL UFEIO VORAR LU EHSNAETL ISFN FLDOEEARSDIGSN.. 070606-A Figure 47. 8-Lead Plastic Dual-in-Line Package [PDIP] (N-8) Dimensions shown in inches and (millimeters) 0.005 (0.13) 0.055 (1.40) MIN MAX 8 5 0.310 (7.87) 0.220 (5.59) 1 4 0.100 (2.54) BSC 0.405 (10.29) MAX 0.320 (8.13) 0.290 (7.37) 0.200 (5.08) 0.060 (1.52) MAX 0.015 (0.38) 0.200 (5.08) 0.150 (3.81) MIN 0.125 (3.18) 0.015 (0.38) 00..002134 ((00..5386)) 0.070 (1.78) SPELAANTIENG 1 05°° 0.008 (0.20) 0.030 (0.76) CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. Figure 48. 8-Lead Ceramic Dual In-Line Package [CERDIP] (Q-8) Dimensions shown in inches and (millimeters) Rev. G | Page 19 of 20

AD844 Data Sheet 10.50 (0.4134) 10.10 (0.3976) 16 9 7.60 (0.2992) 7.40 (0.2913) 1 10.65 (0.4193) 8 10.00 (0.3937) 1.27 (0.0500) 0.75 (0.0295) BSC 2.65 (0.1043) 0.25 (0.0098) 45° 0.30 (0.0118) 2.35 (0.0925) 8° 0.10 (0.0039) 0° COPLANARITY 0.10 0.51 (0.0201) SPELAATNIENG 0.33 (0.0130) 1.27 (0.0500) 0.31 (0.0122) 0.20 (0.0079) 0.40 (0.0157) COMPLIANTTO JEDEC STANDARDS MS-013-AA C(RINOEFNPEATRRREOENNLCLTEIHN EOGSN EDLSIYM)AEANNRDSEI AORRNOESU NANORDEET DAIN-PO MPFRIFLO LMPIIMRLELIATIMTEEER TFSEO; RIRN ECUQHSU EDI VIINMA LEDENENSSTIIOGSN NFS.OR 032707-B Figure 49. 16-Lead Standard Small Outline Package [SOIC_W] Wide Body (RW-16) Dimensions shown in millimeters and (inches) ORDERING GUIDE Model Temperature Range Package Description Package Option AD844AN −40°C to +85°C 8-Lead Plastic Dual In-Line Package [PDIP] N-8 AD844ANZ1 −40°C to +85°C 8-Lead Plastic Dual In-Line Package [PDIP] N-8 AD844ACHIPS −40°C to +85°C Die AD844AQ −40°C to +85°C 8-Lead Ceramic Dual In-Line Package [CERDIP] Q-8 AD844BQ −40°C to +85°C 8-Lead Ceramic Dual In-Line Package [CERDIP] Q-8 AD844JRZ-161 0°C to 70°C 16-Lead Standard Small Outline Package [SOIC_W] RW-16 AD844JRZ-16-REEL71 0°C to 70°C 16-Lead SOIC_W, 7” Tape and Reel RW-16 AD844SCHIPS −55°C to +125°C Die AD844SQ −55°C to +125°C 8-Lead Ceramic Dual In-Line Package [CERDIP] Q-8 AD844SQ/883B −55°C to +125°C 8-Lead Ceramic Dual In-Line Package [CERDIP] Q-8 5962-8964401PA2 −55°C to +125°C 8-Lead Ceramic Dual In-Line Package [CERDIP] Q-8 1 Z = RoHS Compliant Part. 2 Refer to the DESC drawing for tested specifications. ©1989–2017 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D00897-0-5/17(G) Rev. G | Page 20 of 20

Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: A nalog Devices Inc.: AD844AN AD844BQ AD844SQ 5962-8964401PA AD844SQ/883B AD844AQ AD844JRZ-16 AD844JRZ-16- REEL7 AD844ANZ