a 34 MHz, CBFET Fast Settling Op Amp AD843 FEATURES CONNECTION DIAGRAMS AC PERFORMANCE 16-Pin SOIC (R-16) Package Plastic (N-8) and Unity Gain Bandwidth: 34 MHz Cerdip (Q-8) Package Fast Settling: 135 ns to 0.01% Slew Rate: 250 V/(cid:109)s Stable at Gains of 1 or Greater Full Power Bandwidth: 3.9 MHz DC PERFORMANCE Input Offset Voltage: 1 mV max (AD843K/B} Input Bias Current: 0.6 nA typ Input Voltage Noise: 19 nV/(cid:214) Hz Open Loop Gain: 30 V/mV into a 500 (cid:86) Load Output Current: 50 mA min Supply Current: 13 mA max Available in 8-Pin Plastic Mini-DIP & Cerdip, 16-Pin SOIC, TO-8 (H-12A) Package LCC (E-20A) Package 20-Pin LCC and 12-Pin Hermetic Metal Can Packages Available in Tape and Reel in Accordance with EIA-481A Standard Chips and MIL-STD-883B Parts Also Available APPLICATIONS High Speed Sample-and-Hold Amplifiers High Bandwidth Active Filters High Speed Integrators High Frequency Signal Conditioning PRODUCT DESCRIPTION The AD843 is a fast settling, 34 MHz, CBFET input op amp. The AD843 combines the low (0.6 nA) input bias currents characteristic of a FET input amplifier while still providing a 34 MHz bandwidth and a 135 ns settling time (to within 0.01% The AD843 is offered in either 8-pin plastic DIP or hermetic of final value for a 10 volt step). The AD843 is a member of the cerdip packages, in 16-pin SOIC, 20-Pin LCC, or in a 12-pin Analog Devices’ family of wide bandwidth operational amplifi- metal can. Chips are also available. ers. These devices are fabricated using Analog Devices’ junction isolated complementary bipolar (CB) process. This process per- PRODUCT HIGHLIGHTS mits a combination of dc precision and wideband ac perform- 1. The high slew rate, fast settling time and low input bias cur- ance previously unobtainable in a monolithic op amp. rent of the AD843 make it the ideal amplifier for 12-bit D/A The 250 V/m s slew rate and 0.6 nA input bias current of the and A/D buffers, for high speed sample-and-hold amplifiers AD843 ensure excellent performance in high speed sample-and- and for high speed integrator circuits. The AD843 can re- hold applications and in high speed integrators. This amplifier is place many FET input hybrid amplifiers such as the also ideally suited for high bandwidth active filters and high fre- LH0032, LH4104 and OPA600. quency signal conditioning circuits. 2. Fully differential inputs provide outstanding performance in Unlike many high frequency amplifiers, the AD843 requires no all standard high frequency op amp applications such as sig- external compensation and it remains stable over its full operat- nal conditioning and active filters. ing temperature range. It is available in five performance grades: 3. Laser wafer trimming reduces the input offset voltage to the AD843J and AD843K are rated over the commercial 1mV max (AD843K and AD843B). temperature range of 0(cid:176) C to +70(cid:176) C. The AD843A and AD843B 4. Although external offset nulling is unnecessary in many ap- are rated over the industrial temperature range of –40(cid:176) C to +85(cid:176) C. plications, offset null pins are provided. The AD843S is rated over the military temperature range of –55(cid:176) C to +125(cid:176) C and is available processed to MIL-STD-883B, Rev. C. 5. The AD843 does not require external compensation at closed loop gains of 1 or greater. REV.D Information furnished by Analog Devices is believed to be accurate and © Analog Devices, Inc., 1995 reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or One Technology Way, P.O. Box 9106, Norwood. MA 02062-9106, U.S.A. otherwise under any patent or patent rights of Analog Devices. Tel: 617/329-4700 Fax: 617/326-8703

AD843–SPECIFICATIONS (@ T = +25(cid:176) C and – 15 V dc, unless otherwise noted) A AD843J/A AD843K/B AD843S1 Model Conditions Min Typ Max Min Typ Max Min Typ Max Units INPUT OFFSET VOLTAGE1 1.0 2.0 0.5 1.0 1.0 2.0 mV T -T 1.7 4.0 1.2 2.0 3.0 4.5 mV MIN MAX Offset Drift 12 12 35 12 m V/(cid:176) C INPUT BIAS CURRENT Initial (T = +25(cid:176) C) 50 40 50 pA J Warmed-Up2 0.8 2.5 0.6 1.0 0.8 2.5 nA T -T 60/160 23/65 2600 nA MIN MAX INPUT OFFSET CURRENT Initial (T = +25(cid:176) C) 30 20 30 pA J Warmed-Up2 0.25 1.0 0.2 0.4 0.25 1.0 nA T -T 23/64 9/26 1025 nA MIN MAX INPUT CHARACTERISTICS Input Resistance 1010 1010 1010 W Input Capacitance 6 6 6 pF INPUT VOLTAGE RANGE Common Mode (cid:54)10 +12, (cid:54)10 +12, (cid:54)10 +12, V –13 –13 –13 COMMON-MODE REJECTION V = – 10 V 60 72 70 76 60 72 dB CM T -T 60 72 68 76 60 72 dB MIN MAX INPUT VOLTAGE NOISE f = 10 kHz 19 19 19 nV/(cid:214) Hz Wideband Noise 10 Hz to 10 MHz 60 60 60 m V rms OPEN LOOP GAIN V = – 10 V O R ‡ 500 W 15 25 20 30 15 30 V/mV LOAD T -T 10 20 10 25 10 25 V/mV MIN MAX OUTPUT CHARACTERISTICS Voltage R ‡ 500 W (cid:54)10 +11.5, (cid:54)10 +11.5, (cid:54)10 +11.5, V LOAD –12.6 –12.6 –12.6 Current V = – 10 V 50 50 50 mA OUT Output Resistance Open Loop 12 12 12 W FREQUENCY RESPONSE Unity Gain Bandwidth V = 90 mV p-p 34 34 34 MHz OUT Full Power Bandwidth3 V = 20 V p-p O R1 ‡ 500 W 2.5 3.9 2.5 3.9 2.5 3.9 MHz Rise Time A = –1 10 10 10 ns VCL Overshoot A = –1 15 15 15 % VCL Slew Rate A = –1 160 250 160 250 160 250 V/m s VCL Settling Time 10 V Step A = –1 VCL to 0.1% 95 95 95 ns to 0.01% 135 135 135 ns Overdrive Recovery –Overdrive 200 200 200 ns +Overdrive 700 700 700 ns Differential Gain f = 4.4 MHz 0.025 0.025 0.025 % Differential Phase f = 4.4 MHz 0.025 0.025 0.025 Degree POWER SUPPLY Rated Performance – 15 – 15 – 15 V Operating Range (cid:54)4.5 (cid:54)18 (cid:54)4.5 (cid:54)18 (cid:54)4.5 (cid:54)18 V Quiescent Current 12 13 12 13 12 13 mA T -T 12.3 14 12.3 14 12.5 16 mA MIN MAX Rejection Ratio – 5 V to – 18 V 65 76 70 80 65 76 dB Rejection Ratio T -T 62 76 68 80 62 76 dB MIN MAX TEMPERATURE RANGE Operating, Rated Performance Commercial (0(cid:176) C to +70(cid:176) C) AD843J AD843K Industrial (–40(cid:176) C to +85(cid:176) C) AD843A AD843B Military (–55(cid:176) C to +125(cid:176) C)4 AD843S PACKAGE OPTIONS Plastic (N-8) AD843JN AD843KN Cerdip (Q-8) AD843AQ AD843BQ AD843SQ, AD843SQ/883B Metal Can (H-12A) AD843BH AD843SH, AD843SH/883B LCC (E-20A) AD843SE/883B SOIC (R-16) AD843JR–16 Tape & Reel AD843JR-16–REEL AD843JR-16–REEL7 Chips AD843JCHIPS AD843SCHIPS –2– REV. D

AD843 NOTES 1Standard Military Drawings Available: 5962-9098001M2A (SE/883B), 5962-9098001MXA (SH/883B), 5962-9098001MPA (SQ/883B). 2Specifications are guaranteed after 5 minutes at T = +25(cid:176)C. A 3Full power bandwidth = Slew Rate/2 p V peak. 4All “S” grade T -T specifications are tested with automatic test equipment at T = –55(cid:176)C and T = +125(cid:176)C. MIN MAX A A Specifications subject to change without notice. Specifications in boldface are tested on all production units at final electrical test. Results from those tests are used to calculate outgoing quality levels. All min and max specifications are guaranteed although only those shown in boldface are tested on all production units. ABSOLUTE MAXIMUM RATINGS1 METALIZATION PHOTOGRAPH Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .– 18 V Contact factory for latest dimensions. Internal Power Dissipation2 Dimensions shown in inches and (mm). Plastic Package . . . . . . . . . . . . . . . . . . . . . . . . . . 1.50 Watts Cerdip Package . . . . . . . . . . . . . . . . . . . . . . . . . 1.35 Watts 12-Pin Header Package . . . . . . . . . . . . . . . . . . . 1.80 Watts 16-Pin SOIC Package . . . . . . . . . . . . . . . . . . . . 1.50 Watts 20-Pin LCC Package . . . . . . . . . . . . . . . . . . . . . . 1.00 Watt Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – V S Output Short Circuit Duration . . . . . . . . . . . . . . . . Indefinite Differential Input Voltage . . . . . . . . . . . . . . . . . . +V and –V S S Storage Temperature Range (N, R) . . . . . . . –65(cid:176) C to +125(cid:176) C Storage Temperature Range (Q, H, E) . . . . –65(cid:176) C to +150(cid:176) C Operating Temperature Range AD843J/R . . . . . . . . . . . . . . . . . . . . . . . . . . . 0(cid:176) C to +70(cid:176) C AD843A/B . . . . . . . . . . . . . . . . . . . . . . . . . –40(cid:176) C to +85(cid:176) C AD843S . . . . . . . . . . . . . . . . . . . . . . . . . . –55(cid:176) C to +125(cid:176) C Lead Temperature Range (Soldering 60 sec) . . . . . . . . +300(cid:176) C ESD Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500 V NOTES 1Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 28-Pin Plastic Package: q = 100(cid:176)C/Watt JA 8-Pin Cerdip Package: q = 110(cid:176)C/Watt JA 12-Pin Header Package: q = 80(cid:176)C/Watt JA 16-Pin SOIC Package: q = 100(cid:176) C/Watt JA 20-Pin LCC Package: q = 150(cid:176)C/Watt JA REV. D –3–

AD843–Typical Characteristics Figure 1.Input Voltage Range vs. Figure 2.Output Voltage Swing vs. Figure 3.Output Voltage Swing vs. Supply Voltage Supply Voltage Load Resistance Figure 4.Quiescent Current vs. Figure 5.Input Bias Current vs. Figure 6.Output Impedance vs. Supply Voltage Junction Temperature Frequency Figure 7.Input Bias Current vs. Figure 8.Short Circuit Current Figure 9.Gain Bandwidth Product Common Mode Voltage Limit vs. Junction Temperature (T) vs. Temperature J –4– REV. D

AD843 Figure 10.Open Loop Gain and Phase Figure 11.Open Loop Gain vs. Figure 12.Power Supply Rejection vs. Margin vs. Frequency Supply Voltage Frequency Figure 13.Common Mode Figure 14.Large Signal Frequency Figure 15.Output Swing and Error Rejection vs. Frequency Response vs. Settling Time Figure 16.Harmonic Distortion Figure 17.Input Noise Voltage Figure 18.Slew Rate vs. vs. Frequency Spectral Density Temperature REV. D –5–

AD843–Typical Characteristics Figure 19.Open Loop Gain vs. Figure 20a.Inverting Amplifier Figure 20b.Inverter Large Signal Resistive Load Connection Pulse Response. C = 0, C = 10 pF F L Figure 20c.Inverter Small Signal Figure 20d.Inverter Large Signal Figure 20e.Inverter Small Signal Pulse Response. CF = 0, CL = 10 pF Pulse Response. CF = 5 pF, CL = 110 pF Pulse Response. CF = 5 pF, CL = 110 pF Figure 21a.Unity Gain Inverter Figure 21b.Inserter Cap Load Figure 21c.Inverter Cap Load Circuit for Driving Capacitive Large Signal Pulse Response. Small Signal Pulse Response. Loads C = 15 pF, C = 410 pF C = 15 pF, C = 410 pF F L F L –6– REV. D

AD843 Figure 22a.Unity Gain Buffer Figure 22b.Buffer Large Figure 22c.Buffer Small Amplifier Signal Pulse Response. Signal Pulse Response. C = 10 pF C = 10 pF L L Figure 23a.Unity Gain Buffer Circuit Figure 23b.Buffer Cap Load Figure 23c.Buffer Cap Load Small for Driving Capacitive Loads Large Signal Pulse Response. Signal Pulse Response. C = 33 pF, F C = 33 pF, C = 10 pF C = 10 pF F L L Figure 23d.Buffer Cap Load Figure 23e.Buffer Cap Load Large Signal Pulse Response. Small Signal Pulse Response. C = 33 pF, C = 110 pF C = 33 pF, C = 110 pF F L F L REV. D –7–

AD843 GROUNDING AND BYPASSING GROUNDING AND BYPASSING Like most high bandwidth amplifiers, the AD843 is sensitive to In designing practical circuits using the AD843, the user must capacitive loading. Although it will drive capacitive loads up to keep in mind that some special precautions are needed when 20pF without degradation of its rated performance, both an dealing with high frequency signals. Circuits must be wired us- increased capacitive load drive capability and a “cleaner” ing short interconnect leads. Ground planes should be used (nonringing) pulse response can be obtained from the AD843 whenever possible to provide both a low resistance, low induc- by using the circuits illustrated in Figures 20 to 23. The addi- tance circuit path and to minimize the effects of high frequency tion of a 5 pF feedback capacitor to the unity gain inverter con- coupling. IC sockets should be avoided, since their increased nection (Figure 20a) substantially reduces the circuit’s interlead capacitance can degrade the bandwidth of the device. overshoot, even when it is driving a 110 pF load. This can be Power supply leads should be bypassed to ground as close as seen by comparing the waveforms of Figures 20b through 20e. possible to the pins of the amplifier. Again, the component leads To drive capacitive loads greater than 100 pF, the load should should be kept very short. As shown in Figure 24, a parallel be decoupled from the amplifier’s output by a 10 W resistor and combination of a 2.2 m F tantalum and a 0.1 m F ceramic disc ca- the feedback capacitor, C , should be connected directly be- F pacitor is recommended. tween the amplifier’s output and its inverting input (Figure 21a). When using a 15 pF feedback capacitor, this circuit can drive 400 pF with less than 20% overshoot, as illustrated in Fig- ures 21b and 21c. Increasing capacitor C to 47 pF also in- F creases the capacitance drive capability to 1000 pF, at the expense of a 10:1 reduction in bandwidth compared with the simple unity gain inverter circuit of Figure 20a. Unity gain voltage followers (buffers) are more sensitive to capacitive loads than are inverting amplifiers because there is no attenuation of the feedback signal. The AD843 can drive 10 pF to 20 pF when connected in the basic unity gain buffer circuit of Figure 22a. The 1 kW resistor in series with the AD843’s noninverting input serves two functions: first, together with the amplifier’s input capacitance, it forms a low-pass filter which slows down the actual signal seen by the AD843. This helps reduce ringing on Figure 24.Recommended Power Supply Bypassing for the amplifier’s output voltage. The resistor’s second function is the AD843 (DIP Pinout) to limit the current into the amplifier when the differential input voltage exceeds the total supply voltage. USING A HEAT SINK The AD843 will deliver a much “cleaner” pulse response when The AD843 consumes less quiescent power than most precision connected in the somewhat more elaborate follower circuit of high speed amplifiers and is specified to operate without using a Figure 23a. Note the reduced overshoot in Figure 23b and 23c heat sink. However, when driving low impedance loads, the cur- as compared to Figures 22b and 22c. rent applied to the load can be 4 to 5 times greater than the qui- For maximum bandwidth, in most applications, input and feed- escent current. This will produce a noticeable temperature rise, back resistors used with the AD843 should have resistance val- which will increase input bias currents. The use of a small heat ues equal to or less than 1.5 kW . Even with these low resistance sink, such as the Mouser Electronics #33HS008 is recommended. values, the resultant RC time constant formed between them and stray circuit capacitances is large enough to cause peaking in the amplifier’s response. Adding a small capacitor, C , as F shown in Figures 20a to 23a will reduce this peaking and flatten the overall frequency response. C will normally be less than F 10pF in value. The AD843 can drive resistive loads over the range of 500 W to ¥ with no change in dynamic response. While a 499 W load was used in the circuits of Figures 20-23, the performance of these circuits will be essentially the same even if this load is removed or changed to some other value, such as 2 kW . To obtain the “cleanest” possible transient response when driv- ing heavy capacitive loads, be sure to connect bypass capacitors directly between the power supply pins of the AD843 and ground as outlined in “grounding and bypassing.” Offset Null Configuration (DIP Pinout) –8– REV. D

AD843 SAMPLE-AND-HOLD AMPLIFIER CIRCUITS To make sure the circuit accommodates a wide – 10 V input range, the gates of the JFETs must be connected to a potential A Fast Switching Sample & Hold Circuit near the –15 V supply. The level-shift circuitry (diode D3, PNP A sample-and-hold circuit possessing short acquisition time and transistor Q7, and NPN transistor Q6) shifts the TTL level S/H low aperture delay can be built using an AD843 and discrete command to provide for an adequate pinch-off voltage for the JFET switches. The circuit of Figure 25 employs five n-channel JFET switches over the full input voltage range. JFETs (with turn-on times of 35 ns) and an AD843 op amp (which can settle to 0.01% in 135 ns). The circuit has an aper- The JFETs Q2, Q3, Q4 and Q5 across the two hold capacitors ture delay time of 50 ns and an acquisition time of 1m s or less. ensure signal acquisition for all conditions of V and V IN OUT when the circuit switches from the sample to the hold mode. This circuit is based on a noninverting open loop architecture, Transistor Q1 provides an extra stage of isolation between the using a differential hold capacitor to reduce the effects of pedes- output of amplifier A1 and the hold capacitor CH1. tal error. The charge that is removed from CH1 by Q2 and Q3 is offset by the charge removed from CH2 by Q4 and Q5. This When selecting capacitors for use in a sample-and-hold circuit, circuit can tolerate low hold capacitor values (approximately the designer should choose those types with low dielectric 100 pF), which improve acquisition time, due to the small gate- absorption and low temperature coefficients. Silvered-mica to-drain capacitance of the discrete JFETs. Although pedestal capacitors exhibit low (0 to 100 ppm/(cid:176) C) temperature coeffi- error will vary with input signal level, making trimming more cients and will still work in temperatures exceeding 200(cid:176) C. It is difficult, the circuit has the advantages of high bandwidth and also recommend that the user test the chosen capacitor to insure short acquisition times. In addition, it will exhibit some that its value closely matches that printed on it since not all nonlinearity because both amplifiers are operating with a com- capacitors are fully tested by their manufacturers for absolute mon-mode input. Amplifier A2, however, contributes less than tolerance. 0.025% linearity error, due to its 72 dB common-mode rejec- tion ratio. Figure 25. A Fast Switching Sample-and-Hold Amplifier A PING-PONG S/H AMPLIFIER A high speed CB amplifier, A1, follows the input signal. U1, a For improved throughput over the circuit of Figure 25, a “ping- dual wideband “T” switch, connects the input buffer amp to pong” architecture may be used. A ping-pong circuit overcomes one of the two output amplifiers while selecting the complemen- some of the problems associated with high speed S/H amplifiers tary amplifier to drive the A/D input. For example, when by allowing the use of a larger hold capacitor for a given sample “select” is at logic high, A1 drives CH1, A2 tracks the input sig- rate: this will reduce the associated feedthrough, droop and ped- nal and the output of A3 is connected to the input of the A/D estal errors. converter. At the same time, A3 holds an analog value and its output is connected to the input of the A/D converter. When the Figure 26 illustrates a simple, four-chip ping-pong sample-and- select command goes to logic LOW, the two output amplifiers hold amplifier circuit. This design increases throughput by using alternate functions. one channel to acquire a new sample while another channel holds the previous sample. Instead of having to reacquire the Since the input to the A/D converter is the alternated “held” signal when switching from hold to sample mode, it alternately outputs from A1 and A2, the offset voltage mismatch of the two connects the outputs from Channel 1 or from Channel 2 to the amplifiers will show up as nonlinearity and, therefore, distortion A/D converter. In this case, the throughput is the slew rate and in the output signal. To minimize this, potentiometers can be settling time of the output amplifiers, A2 and A3. used to adjust the offsets of the output amplifiers until they are REV. D –9–

AD843 equal. Alternatively, an autocalibration circuit using two D/A ther improves these specifications by using ground pins between converters can be employed. This can also be used to calibrate the signal pins. With an input frequency of 5 MHz, crosstalk out the effects of offset voltage drift over temperature. and isolation are –85 dB and –75 dB, respectively. A limitation of this switch is that it operates from a maximum –5 V negative The switch choice, for U1s, is critical in this type of design. The supply, making bipolar operation more difficult. It is recom- DG542 utilizes “T” switching techniques on each channel for mended that amplifiers A1, A2 and A3 operate from the same exceptionally low crosstalk and for high isolation. The part fur- –5 V supply to minimize any potential latch-up problems. Figure 26.A Ping-Pong Sample-and-Hold Amplifier Figure 27.Settling Time Test Circuit –10– REV. D

AD843 MEASURING AD843 SETTLING TIME detector’s output (top trace) loses slightly over a volt of the Figure 28 shows the dynamic response of the AD843 while op- 8volt peak input value (bottom trace) in 75 ms, or a rate of erating in the settling time test circuit of Figure 27. The input of approximately 16m V/m s. the settling time fixture is driven by a flat-top pulse generator. The error signal output from A1, the AD843 under test, is am- plified by op amp A2 and then clamped by two high speed Schottky diodes. Figure 30. Peak Detector Response to 125Hz Pulse Train Figure 28.Settling Characteristics: +10 V to 0 V Step. Upper Trace:Amplified Error Voltage (0.01%/Div) Lower Trace:Output of AD843 Under Test (5 V/Div) The error signal is clamped to prevent it from greatly overload- ing the oscilloscope preamp. A Tektronix oscilloscope preamp type 7A26 was chosen because it will recover from the approxi- mately 0.4 volt overload, quickly enough to allow accurate mea- surement of the AD843’s 135 ns settling time. Amplifier A2 is a very high speed op amp; it provides a voltage gain of 10, provid- ing a total gain of 5 from the error signal to the oscilloscope input. A FAST PEAK DETECTOR CIRCUIT The peak detector circuit of Figure 29, can accurately capture the amplitude of input pulses as narrow as 200 ns and can hold their value with a droop rate of less than 20 m V/m s. This circuit Figure 31.Peak Capture Time will capture the peak value of positive polarity waveforms; to Amplifier A1, an AD847, can drive 680 pF hold capacitor, C , detect negative peaks, simply reverse the polarity of the two P fast enough to “catch-up” with the next peak in 100 ns and still diodes. settle to the new value in 250 ns, as illustrated in Figure 31. The high bandwidth and 200 V/m s slew rate of amplifier A2, an Reducing the value of capacitor C to 100 pF will maximize the P AD843, allows the detector’s output to “keep up” with its input speed of this circuit at the expense of increased overshoot and thus minimizing overshoot. The low (<1 nA) input current of droop. Since the AD847 can drive an arbitrarily large value of the AD843 ensures that the droop rate is limited only by the capacitance, C can be increased to reduce droop, at the expense P reverse leakage of diode D2, which is typically <10 nA for the of response time. type shown. The low droop rate is apparent in Figure 30. The Figure 29. A Fast Peak Detector Circuit REV. D –11–

AD843 OUTLINE DIMENSIONS Dimensions shown in inches and (mm). Mini-DIP Package Cerdip Package (N-8) (Q-8) 5 9 6/ – 2 – b 4 1 3 1 C TO-8 Package 16-Pin SOIC Package (H-12A) (R-16) 0.4133 (10.50) 0.3977 (10.00) 16 9 1 8 0.2992 (7.60)0.2914 (7.40) 0.4193 (10.65)0.3937 (10.00) PIN 1 0.1043 (2.65) 0.0291 (0.74)x 45(cid:176) 0.0118 (0.30) 0.0926 (2.35) 0.0098 (0.25) 0.0040 (0.10) 8(cid:176) 0.0500 (1.27) 0(B1.0.S25C70)0 00..00119328 ((00..4395)) SPELAANTIENG 00..00102951 ((00..3223)) 0(cid:176) 0.0157 (0.40) LCC Package (E-20A) 0.082 – 0.018 (2.085 – 0.455) 0(8.3.8590 –– 00..2000)8 SSQQ 0.040 x 45(cid:176) (1.02 x 45(cid:176)) REF 3 PLCS 0.025 – 0.003 NO. 1 PIN (0.635 – 0.075) A. INDEX S. 0.050 U. (1.27) N 0.020 x 45(cid:176) D I (0.51 x 45(cid:176)) E REF T N RI P –12– REV. D