Wide Supply Range, Micropower, Rail-to-Rail Instrumentation Amplifier Data Sheet AD8420 FEATURES PIN CONFIGURATION Maximum supply current: 90 μA AD8420 Minimum CMRR: 100 dB NC 1 8 VOUT Drives heavy capacitive loads: ~700 pF +IN 2 + – 7 FB RInapilu-tto v-oraltial goeu trpauntg e goes below ground ––VINS 43 (N–ToOt Pto V SIEcaWl+e) 56 R+VESF 09945-001 Gain set with 2 external resistors Figure 1. Can achieve low gain drift at any gain Very wide power supply range Single supply: 2.7 V to 36 V Table 1. Instrumentation Amplifiers by Category1 Dual supply: ±2.7 V to ±18 V General Military Low Digital Bandwidth (G = 100): 2.5 kHz Purpose Zero Drift Grade Power Gain Input voltage noise: 55 nV/√Hz AD8221, AD8222 AD8231 AD620 AD8420 AD8250 High dc precision AD8220, AD8224 AD8290 AD621 AD8235 AD8251 Maximum offset voltage: 125 μV AD8236 Maximum offset drift: 1 μV/°C AD8226, AD8227 AD8293G80, AD524 AD627 AD8253 Maximum differential input voltage: ±1 V AD8293G160 8-lead MSOP package AD8228 AD8553 AD526 AD8226 AD8231 AD8227 APPLICATIONS AD8295, AD8224 AD8556 AD624 AD623 Bridge amplifiers AD8557 AD8223 Pressure measurement Medical instrumentation 1 See www.analog.com for the latest instrumentation amplifiers. Portable data acquisition Multichannel systems GENERAL DESCRIPTION The AD8420 is a low cost, micropower, wide supply range, Single-supply operation, micropower current consumption, and instrumentation amplifier with a rail-to-rail output and a novel rail-to-rail output swing make the AD8420 ideal for battery- architecture that allows for extremely flexible design. It is optimized powered applications. Its rail-to-rail output stage maximizes to amplify small differential voltages in the presence of large dynamic range when operating from low supply voltages. Dual- common-mode signals. supply operation (±15 V) and low power consumption make the AD8420 ideal for a wide variety of applications in medical The AD8420 is based on an indirect current feedback architecture or industrial instrumentation. that gives it an excellent input common-mode range. Unlike conventional instrumentation amplifiers, the AD8420 can easily The AD8420 is available in an 8-lead MSOP package. Performance amplify signals at or even slightly below ground without requiring is specified over the full temperature range of −40°C to +85°C, dual supplies. The AD8420 has rail-to-rail output, and the output and the device is operational from −40°C to +125°C. voltage swing is completely independent of the input common- mode voltage. Rev. A Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Tel: 781.329.4700 ©2012–2015 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com

AD8420 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Gain Accuracy ............................................................................ 20 Applications ....................................................................................... 1 Input Voltage Range ................................................................... 20 Pin Configuration ............................................................................. 1 Input Protection ......................................................................... 20 General Description ......................................................................... 1 Layout .......................................................................................... 21 Revision History ............................................................................... 2 Driving the Reference Pin ......................................................... 21 Specifications ..................................................................................... 3 Input Bias Current Return Path ............................................... 22 Absolute Maximum Ratings ............................................................ 7 Radio Frequency Interference (RFI) ........................................ 22 Thermal Resistance ...................................................................... 7 Output Buffering ........................................................................ 23 ESD Caution .................................................................................. 7 Applications Information .............................................................. 24 Pin Configuration and Function Descriptions ............................. 8 AD8420 in Electrocardiography (ECG) .................................. 24 Typical Performance Characteristics ............................................. 9 Classic Bridge Circuit ................................................................ 25 Theory of Operation ...................................................................... 19 4 mA to 20 mA Single-Supply Receiver .................................. 25 Architecture ................................................................................. 19 Outline Dimensions ....................................................................... 26 Setting the Gain .......................................................................... 19 Ordering Guide .......................................................................... 26 REVISION HISTORY 1/15—Rev. 0 to Rev. A Changes to Features Section............................................................ 1 Changes to Specifications Section .................................................. 3 Changes to Quiescent Current Parameter, Table 2 ...................... 4 Changes to Common-Mode Rejection Ratio (CMRR) Parameter, Table 3 and Quiescent Current Parameter, Table 3 ......... 5 Changes to ESD Parameter, Table 4 ............................................... 7 Changes to Figure 9, Figure 11, Figure 13, and Figure 14 ......... 10 Changes to Figure 15, Figure 16 Caption, Figure 18 Caption, and Figure 20 Caption .................................................................... 11 Changes to Figure 38 ...................................................................... 14 Change to Figure 40 Caption ........................................................ 15 Changes to Figure 56 Caption ....................................................... 17 Changes to Figure 57 Caption ....................................................... 18 Changes to Figure 58 and Architecture Section ......................... 19 Changes to Gain Accuracy Section .............................................. 20 Changes to Driving the Reference Pin Section ........................... 21 Changes to Output Buffering Section .......................................... 23 Changes to 4 mA to 20 mA Single-Supply Receiver Section .... 25 3/12—Revision 0: Initial Version Rev. A | Page 2 of 26

Data Sheet AD8420 SPECIFICATIONS +V = +5 V, −V = 0 V, V = 0.5 V, V = 0.5 V, V = 0.5 V, T = 25°C, G = 1 to 1000, R = 20 kΩ, specifications referred to input, S S REF +IN −IN A L unless otherwise noted. All Table 2 limits are valid from V = 3 V to V = ±5 V, unless otherwise specified. S S Table 2. Parameter Test Conditions/Comments Min Typ Max Unit COMMON-MODE REJECTION RATIO (CMRR) V = 0 V to 2.7 V CM CMRR DC to 60 Hz 100 dB CMRR at 1 kHz 100 dB NOISE Voltage Noise Spectral Density f = 1 kHz, V ≤ 100 mV 55 nV/√Hz DIFF Peak to Peak f = 0.1 Hz to 10 Hz, V ≤ 100 mV 1.5 μV p-p DIFF Current Noise Spectral Density f = 1 kHz 80 fA/√Hz Peak to Peak f = 0.1 Hz to 10 Hz 3 pA p-p VOLTAGE OFFSET Offset V = 3 V to V = 5 V 125 μV S S V = ±5 V 150 μV S Average Temperature Coefficient T = −40°C to +85°C 1 μV/°C A Offset RTI vs. Supply (PSR) V = 2.7 V to 5 V 86 dB S INPUTS Valid for REF and FB pair, as well as +IN and −IN Input Bias Current1 T = +25°C 20 27 nA A T = +85°C 24 nA A T = −40°C 30 nA A Average Temperature Coefficient T = −40°C to +85°C 30 pA/°C A Input Offset Current T = +25°C 1 nA A T = +85°C 1 nA A T = −40°C 1 nA A Average Temperature Coefficient T = −40°C to +85°C 0.5 pA/°C A Input Impedance Differential 130||2 MΩ||pF Common Mode 1000||2 MΩ||pF Differential Input Operating Voltage T = –40°C to +85°C −1 +1 V A Input Operating Voltage (+IN, −IN, REF, or FB) T = +25°C −V − 0.15 +V − 2.2 V A S S T = +85°C −V − 0.05 +V − 1.8 V A S S T = –40°C −V − 0.2 +V − 2.7 V A S S DYNAMIC RESPONSE Small Signal −3 dB Bandwidth G = 1 250 kHz G = 10 25 kHz G = 100 2.5 kHz G =1000 0.25 kHz Settling Time 0.01% V = ±5 V S G = 1 −1 V to +1 V output step 3 μs G = 10 −4.5 V to +4.5 V output step 130 μs G = 100 −4.5 V to +4.5 V output step 1 ms Slew Rate 1 V/μs Rev. A | Page 3 of 26

AD8420 Data Sheet Parameter Test Conditions/Comments Min Typ Max Unit GAIN2 G = 1 + (R2/R1) Gain Range 1 1000 V/V Gain Error G = 1 V = 0.1 V to 1.1 V, V = 0.1 V 0.02 % OUT REF G = 10 to 1000 V = 0.2 V to 4.8 V 0.05 0.1 % OUT Gain vs. Temperature T = −40°C to +85°C 10 ppm/°C A OUTPUT Output Swing V = 5 V, R = 10 kΩ to midsupply S L V = ±5 V, R = 20 kΩ to ground S L T = +25°C −V + 0.1 +V − 0.15 V A S S T = +85°C −V + 0.1 +V − 0.2 V A S S T = −40°C −V + 0.1 +V − 0.15 V A S S Short-Circuit Current 10 mA POWER SUPPLY Operating Range Single-supply operation3 2.7 36 V Quiescent Current V = 5 V S T = +25°C 55 70 90 μA A T = +85°C 110 μA A T = −40°C 75 μA A TEMPERATURE RANGE Specified −40 +85 °C Operational4 −40 +125 °C 1 The input stage uses PNP transistors; therefore, input bias current always flows out of the device. 2 For G > 1, errors from External Resistor R1 and External Resistor R2 should be considered in addition to these specifications, including error from FB pin bias current. 3 Minimum supply voltage indicated for V+IN, V−IN, and VREF = 0 V. 4 See the Typical Performance Characteristics section for operation between 85°C and 125°C. Rev. A | Page 4 of 26

Data Sheet AD8420 +V = +15 V, −V = −15 V, V = 0 V, T = 25°C, G = 1 to 1000, R = 20 kΩ, specifications referred to input, unless otherwise noted. S S REF A L Table 3. Parameter Test Conditions/Comments Min Typ Max Unit COMMON-MODE REJECTION RATIO (CMRR) V = −10 V to +10 V CM CMRR DC to 60 Hz 92 dB CMRR at 1 kHz 92 dB NOISE Voltage Noise Spectral Density f = 1 kHz, V ≤ 100 mV 55 nV/√Hz DIFF Peak to Peak f = 0.1 Hz to 10 Hz, V ≤ 100 mV 1.5 μV p-p DIFF Current Noise Spectral Density f = 1 kHz 80 fA/√Hz Peak to Peak f = 0.1 Hz to 10 Hz 3 pA p-p VOLTAGE OFFSET Offset V = ±15 V1 250 μV S Average Temperature Coefficient T = −40°C to +85°C 1 μV/°C A Offset RTI vs. Supply (PSR) V = ±15 V 100 dB S INPUTS Valid for REF and FB pair, as well as +IN and −IN Input Bias Current2 T = +25°C 20 27 nA A T = +85°C 24 nA A T = −40°C 30 nA A Average Temperature Coefficient T = −40°C to +85°C 30 pA/°C A Input Offset Current T = +25°C 1 nA A T = +85°C 1 nA A T = −40°C 1 nA A Average Temperature Coefficient T = −40°C to +85°C 0.5 pA/°C A Input Impedance Differential 130||3 MΩ||pF Common Mode 1000||3 MΩ||pF Differential Input Operating Voltage T = −40°C to +85°C −1 1 V A Input Operating Voltage (+IN, −IN, REF, or FB) T = +25°C −V − 0.15 +V − 2.2 V A S S T = +85°C −V − 0.05 +V − 1.8 V A S S T = −40°C −V − 0.2 +V − 2.7 V A S S DYNAMIC RESPONSE Small Signal −3 dB Bandwidth G = 1 250 kHz G = 10 25 kHz G = 100 2.5 kHz G =1000 0.25 kHz Settling Time 0.01% G = 1 −1 V to +1 V output step 3 μs G = 10 −5 V to +5 V output step 130 μs G = 100 −5 V to +5 V output step 1 ms Slew Rate 1 V/μs GAIN3 G = 1 + (R2/R1) Gain Range 1 1000 V/V Gain Error G = 1 V = ±1 V 0.02 % OUT G = 10 to 1000 V = ±10 V 0.05 0.1 % OUT Gain vs. Temperature T = −40°C to +85°C 10 ppm/°C A Rev. A | Page 5 of 26

AD8420 Data Sheet Parameter Test Conditions/Comments Min Typ Max Unit OUTPUT Output Swing R = 20 kΩ to Ground T = +25°C −V + 0.13 +V − 0.2 V L A S S T = +85°C −V + 0.15 +V − 0.23 V A S S T = –40°C −V + 0.11 +V − 0.16 V A S S Short-Circuit Current 10 mA POWER SUPPLY Operating Range Dual-supply operation4 ±2.7 ±18 V Quiescent Current V = ±15 V S T = +25°C 70 85 120 μA A T = +85°C 145 μA A T = −40°C 110 μA A TEMPERATURE RANGE Specified −40 +85 °C Operational5 −40 +125 °C 1 See the Typical Performance Characteristics section for the offset voltage vs. supply. 2 The input stage uses PNP transistors; therefore, input bias current always flows out of the device. 3 For G > 1, errors from External Resistor R1 and External Resistor R2 should be considered in addition to these specifications, including error from FB pin bias current. 4 Minimum positive supply voltage indicated for V+IN, V−IN, and VREF = 0 V. With V+IN, V−IN, and VREF = −VS, minimum supply is ±1.35 V. 5 See the Typical Performance Characteristics section for operation between 85°C and 125°C. Rev. A | Page 6 of 26

Data Sheet AD8420 ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE Table 4. Parameter Rating θ is specified for a device in free air. JA Supply Voltage ±18 V Table 5. Output Short-Circuit Current Indefinite Package θ Unit Maximum Voltage at −IN or +IN −V + 40 V JA S 8-Lead MSOP, 4-Layer JEDEC Board 135 °C/W Minimum Voltage at −IN or +IN −V − 0.5 V S Maximum Voltage at REF or FB +VS + 0.5 V Minimum Voltage at REF or FB −V − 0.5 V S ESD CAUTION Storage Temperature Range −65°C to +150°C ESD Human Body Model 4 kV Charge Device Model 1.25 kV Machine Model 0.2 kV Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. Rev. A | Page 7 of 26

AD8420 Data Sheet PIN CONFIGURATION AND FUNCTION DESCRIPTIONS AD8420 NC 1 8 VOUT +IN 2 + – 7 FB –IN 3 – + 6 REF –VS 4 (NToOt Pto V SIEcaWle) 5 +VS 09945-002 Figure 2. Pin Configuration Table 6. Pin Function Descriptions Pin No. Mnemonic Description 1 NC This pin is not connected internally. For best CMRR vs. frequency and leakage performance, connect this pin to negative supply. 2 +IN Positive Input. 3 −IN Negative Input. 4 −V Negative Supply. S 5 +V Positive Supply. S 6 REF Reference Input. 7 FB Feedback Input. 8 V Output. OUT Rev. A | Page 8 of 26

Data Sheet AD8420 TYPICAL PERFORMANCE CHARACTERISTICS T = 25°C, +V = 5 V, R = 20 kΩ, unless otherwise noted. S L MEAN: –34.8195 700 MEAN: 4.63764 700 SD: 31.3406 SD: 1.09498 600 600 TS 500 TS 500 HI HI OF 400 OF 400 R R E E MB 300 MB 300 U U N N 200 200 100 100 0 0 –150 –100 –50 VOS0 (µV) 50 100 150 09945-003 0 2 CMR4R, ±15V (µV6/V) 8 10 09945-008 Figure 3. Typical Distribution of Input Offset Voltage Figure 6. Typical Distribution of CMRR MEAN: 22.6643 700 MEAN: 22.706 700 SD: 0.6058 SD: 0.615728 600 600 500 TS 500 TS HI HI F F 400 O 400 O R R E E B B 300 M 300 M U U N N 200 200 100 100 0 0 20 21 POSITIV2E2 BIAS CUR2R3ENT (nA)24 25 09945-004 20 21gm2 POSIT2I2VE BIAS CU2R3RENT (nA2)4 25 09945-006 Figure 4. Typical Distribution of Input Bias Current Figure 7. Typical Distribution of REF, FB Bias Current 1200 MEAN: 0.000646761 1200 MEAN: 0.00144205 SD: 0.111551 SD: 0.112088 1000 1000 TS 800 TS 800 HI HI F F O O R 600 R 600 E E B B M M U U N 400 N 400 200 200 0 0 –0.9 –0.6 –O0F.3FSET CU0RRENT (0n.A3) 0.6 0.9 09945-005 –0.9 –0.6 gm–20 .O3FFSET C0URRENT0 .(3nA) 0.6 0.9 09945-007 Figure 5. Typical Distribution of Input Offset Current Figure 8. Typical Distribution of REF, FB Offset Current Rev. A | Page 9 of 26

AD8420 Data Sheet 3.0 0.5 15 0.6 VS = +5V VS = ±15V G = 1 G = 100 2.5 VV–RIENF = = 0 0VV VOUT 0.4 10 0.4 VOUT IIN T VOLTAGE (V) 21..05 IIN 00..32 CURRENT (mA) T VOLTAGE (V) 50 00.2 CURRENT (mA) OUTPU 1.0 0.1 INPUT OUTPU –5 –0.2 INPUT 0.5 0 –10 –0.4 0–5 0 5 10INPUT1 5VOLT2A0GE (V2)5 30 35 40–0.1 09945-309 –15–20 –15 –10 –5INPUT0 VOLTA5GE (V1)0 15 20 25–0.6 09945-312 Figure 9. Input Overvoltage Performance, G = 1 Figure 12. Input Overvoltage Performance, G = 100, VS = ±15 V 3 0.6 15 VS = ±15V G = 1 VOUT –1.0V, +12.3V 0.0V, +12.8V +1.0V, +12.3V 2 0.4 E (V) 10 G T VOLTAGE (V) 10 IIN 00.2 CURRENT (mA) N-MODE VOLTA –550 MAXIMUM VDIFF = ±1V OUTPU –1 –0.2 INPUT COMMO –10 T –2 –0.4 PU –1.0V, –14.6V +1.0V, –14.6V N –15 I 0.0V, –15.1V –3–20 –15 –10 –5INPUT0 VOLTA5GE (V1)0 15 20 25–0.6 09945-310 –20–1.2 –1.0 –0.8 –0.6 –0O.4UT–P0U.2T V0OLTA0.G2E (0V.4) 0.6 0.8 1.0 1.2 09945-313 Figure 10. Input Overvoltage Performance, G = 1, VS = ±15 V Figure 13. Input Common-Mode Voltage vs. Output Voltage, G = 1, VS = ±15 V 6 0.5 3.0 5 VOUT 0.4 E (V) 2.5 +4mV, +2.8V G +1.0V, +2.3V T VOLTAGE (V) 43 IIN 00..32 CURRENT (mA) N-MODE VOLTA 211...050 MAXIMUM VDIFF = ±1V OUTPU 2 VVGVS–R =I EN= F1 = 50= V00 0VV 0.1 INPUT T COMMO 0.5 +1.0V, +0.4V U +4mV, –0.1V 1 0 P N 0 I 0–5 0 5 10INPUT1 5VOLT2A0GE (V2)5 30 35 40–0.1 09945-311 –0.5–0.2 0 0.2OUTP0U.4T VOLT0A.6GE (V)0.8 1.0 1.2 09945-314 Figure 11. Input Overvoltage Performance, G = 100 Figure 14. Input Common-Mode Voltage vs. Output Voltage, G = 1, VS = 5 V, VREF = 0 V Rev. A | Page 10 of 26

Data Sheet AD8420 3.5 3.5 VREF = 2.5V RL = 10kΩ TO MIDSUPPLY V) 3.0 +2.5V, +2.8V V) 3.0 E ( E ( +44mV, +2.8V +4.8V, +2.78V AG 2.5 AG 2.5 T +3.03V, +2.46V T L +1.5V, +2.3V L O O V 2.0 V 2.0 E E D D MO 1.5 MO 1.5 ON- MAXIMUM VFB = +VS – 2.2V ON- M 1.0 M 1.0 M M O O T C 0.5 +1.5V, +0.4V T C 0.5 U +3.03V, +0.16V U P P IN 0 IN 0 +44mV, –0.1V +4.8V, –80mV +2.5V, –0.1V –0.5 –0.5 1.4 1.6 1.8 2O.0UTPU2T.2 VOL2T.A4GE (2V.6) 2.8 3.0 3.2 09945-315 –0.5 0 0.5 1.0 1O.5UTP2.U0T V2O.5LTA3.G0E (3V.5) 4.0 4.5 5.0 5.5 09945-318 Figure 15. Input Common-Mode Voltage vs. Output Voltage, Figure 18. Input Common-Mode Voltage vs. Output Voltage, G = 1, VS = 5 V, VREF = 2.5 V G = 100, VS = 5 V, VREF = 0 V 0.6 3.5 +4mV, +0.5V V) 0.5 V) 3.0 E ( E ( +86mV, +2.79V +2.5V, +2.8V +4.8V, +2.79V AG 0.4 AG 2.5 T T L L O O V 0.3 V 2.0 E E D D MO 0.2 +0.6V, +0.2V MO 1.5 N- N- O O M 0.1 M 1.0 M M O O T C 0 T C 0.5 U U P P IN –0.1 IN 0 +86mV, –90mV +2.5V, –0.1V +4.8V, –90mV +4mV, –0.1V –0.2 –0.5 –0.1 0 0.1 OU0.T2PUT V0O.3LTAG0E.4 (V) 0.5 0.6 0.7 09945-316 –0.5 0 0.5 1.0 1O.5UTP2.U0T V2O.5LTA3.G0E (3V.5) 4.0 4.5 5.0 5.5 09945-319 Figure 16. Input Common-Mode Voltage vs. Output Voltage, Figure 19. Input Common-Mode Voltage vs. Output Voltage, G = 1, VS = 2.7 V, VREF = 0 V G = 100, VS = 5 V, VREF = 2.5 V 20 0.6 +29mV, +0.5V +2.53V, +0.49V V) 15 –14.9V, +12.7V +14.8V, +12.7V V) 0.5 AGE ( 10 0.0V, +12.8V AGE ( 0.4 T T L L O O V 5 V 0.3 E E D D MO 0 MO 0.2 N- N- O O M –5 M 0.1 M M O O T C –10 T C 0 U U INP –15 0.0V, –15.1V INP –0.1 –14.9V, –15.0V +14.8V, –15.0V +29mV, –0.1V +2.53V, –90mV –20 –0.2 –20 –15 –10 OU–T5PUT V0OLTAGE5 (V) 10 15 20 09945-317 –0.5 0 0.5OUTP1U.0T VOLT1A.5GE (V)2.0 2.5 3.0 09945-320 Figure 17. Input Common-Mode Voltage vs. Output Voltage, Figure 20. Input Common-Mode Voltage vs. Output Voltage, G = 100, VS = ±15 V G = 100, VS = 2.7 V, VREF = 0 V Rev. A | Page 11 of 26

AD8420 Data Sheet 40 120 VS = ±15V 35 100 A) T BIAS CURRENT (n 322050 –0.2V +2.7V OSITIVE PSRR (dB) 468000 GGAAININ = =1 010000 PU 15 P N GAIN = 10 I BANDWIDTH 10 20 LIMIT IBIAS (+IN) IBIAS (–IN) GAIN = 1 5 0 –2.0 0 C0O.5MMON1-M.0ODE V1O.5LTAGE2 (.V0) 2.5 3.0 09945-019 0.1 1 10FREQU1E0N0CY (Hz)1k 10k 100k 09945-323 Figure 21. Input Bias Current vs. Common-Mode Voltage Figure 24. Positive PSRR vs. Frequency, RTI, VS = ±15 V 400 120 VS = ±15V SPECIFIED 300 PERFORMANCE RANGE GAIN = 1000 IBIAS (+IN) 100 GAIN = 100 A) 200 ENT (n 100 R (dB) 80 S CURR 0 VE PSR 60 BANLDIMWIITDTH BIA –100 ATI UT EG 40 GAIN = 10 P N N –200 I IBIAS (–IN) 20 GAIN = 1 –300 –400 0 –2.0 –1.5 D–1IF.0FERE–N0.T5IAL IN0PUT VO0.L5TAGE1 .(0V) 1.5 2.0 09945-020 0.1 1 10FREQU1E0N0CY (Hz)1k 10k 100k 09945-324 Figure 22. Input Bias Current vs. Differential Input Voltage, VS = ±15 Figure 25. Negative PSRR vs. Frequency, RTI, VS = ±15 V 100 70 GAIN = 1000 VS = ±15V 60 80 50 GAIN = 100 40 GAIN = 1000 B) 60 B) 30 R (d N (d 20 GAIN = 10 PSR 40 GAIN = 100 GAI 10 GAIN = 1 GAIN = 10 0 BANDWIDTH 20 LIMIT –10 –20 GAIN = 1 0 –30 0.1 1 10FREQU1E0N0CY (Hz)1k 10k 100k 09945-500 1 10 100FREQUE1kNCY (Hz)10k 100k 1M 09945-023 Figure 23. PSRR vs. Frequency on 5 V Supply Figure 26. Gain vs. Frequency Rev. A | Page 12 of 26

Data Sheet AD8420 70 120 GAIN = 1000 VS = 2.7V 60 100 50 GAIN = 100 40 80 B) 30 B) AIN (d 20 GAIN = 10 MRR (d 60 G 10 C GAIN = 1 40 0 –10 20 –20 VS = ±15V VCM = ±10V –30 0 1 10 100FREQUE1kNCY (Hz)10k 100k 1M 09945-024 0 0.1 0.2DIFF0E.3REN0T.I4AL IN0.P5UT V0.O6LTA0G.7E (V0).8 0.9 1.0 09945-329 Figure 27. Gain vs. Frequency, 2.7 V Single Supply Figure 30. CMRR vs. Differential Input Voltage 140 120 VS = ±15V BANDWIDTH GAIN = 1000 VS = 5V LIMIT 110 120 100 100 A) 90 GAIN = 100 T (µ B) 80 EN 80 CMRR (d 60 GAIN = 10 LY CURR 6700 P P 40 GAIN = 1 SU 50 40 20 30 00.1 1 10FREQU1E0N0CY (Hz)1k 10k 100k 09945-327 20–40 –25 –10 5 T2E0MPE35RATU50RE (°6C5) 80 95 110 125 09945-027 Figure 28. CMRR vs. Frequency, RTI, VS = ±15 V Figure 31. Supply Current vs. Temperature, VS = +5 V 140 30 250 VS = ±15V 120 25 –IN BIAS CURRENT 200 GAIN = 1000 100 A) CMRR (dB) 468000 GAIN = G10AGINA =IN 1 =0 01 BIAS CURRENT (nA) 112050 +IN BIAS CURRENT 11550000 OFFSET CURRENT (p 20 5 OFFSET CURRENT 0 00.1 1 10FREQU1E0N0CY (Hz)1k 10k 100k 09945-328 0–40 –25 –10 5 T2E0MPE35RATU50RE (°6C5) 80 95 110 125–50 09945-331 Figure 29. CMRR vs. Frequency, RTI, 1 kΩ Source Imbalance, VS = ±15 V Figure 32. Input Bias Current and Input Offset Current vs. Temperature Rev. A | Page 13 of 26

AD8420 Data Sheet 30 200 400 NORMALIZED TO 25°C 300 25 –IN BIAS CURRENT 150 200 A) V) NT (nA) 20 +IN BIAS CURRENT 100 ENT (p AGE (µ 100 E R T RR 15 50 UR OL 0 U C V C T T BIAS 10 0 FFSE FFSE –100 OFFSET CURRENT O O –200 5 –50 –300 0 –100 –400 –40 –25 –10 5 T2E0MPE3R5ATU50RE (°6C5) 80 95 110 125 09945-332 –40 –25 –10 5 T2E0MPE35RATU50RE (°6C5) 80 95 110 125 09945-031 Figure 33. FB, REF Bias Current and FB, REF Offset Current vs. Temperature Figure 36. Offset Drift 1000 5 VIN = ±1V REPRESENTATIVE DATA VS = ±15V 800 VS = ±15V 4 NORMALIZED AT 25°C 600 3 PART A 400 V) 2 µV/ 200 V) R ( V/ 1 N ERRO –2000 PART B CMRR (µ 0 PART A: 0.024ppm/°C GAI –400 –1 –600 –2 PART B: 0.038ppm/°C –800 –3 REPRESENTATIVE DATA NORMALIZED TO 25ºC –1000 –4 –40 –25 –10 T5EMPER20ATURE3 5(°C) 50 65 80 09945-333 –40 –25 –10 5 T2E0MPE35RATU50RE (°6C5) 80 95 110 125 09945-032 Figure 34. Gain Error vs. Temperature, G = 1, VIN = ±1 V, VS = ±15 V Figure 37. CMRR vs. Temperature, G = 1, VS = ±15 V 1000 +VS VIN = ±0.1V RL = 20kΩ 800 VS = ±15V –0.1 S 600 G (V)TAGE –0.2 ERROR (µV/V) 2400000 PART A OLTAGE SWINO SUPPLY VOL –0.3 –+++42810552°°°5CCC°C GAIN ––420000 PART B UTPUT VERRED T ++00..32 –600 OEF R +0.1 –800 REPRESENTATIVE DATA NORMALIZED TO 25ºC –1000–40 –25 –10 T5EMPER20ATURE3 5(°C) 50 65 80 09945-334 –VS2 4 6 SUP8PLY VO1L0TAGE1 (2±VS) 14 16 18 09945-035 Figure 35. Gain Error vs. Temperature, G = 1, VIN = ±0.1 V, VS = ±15 V Figure 38. Output Voltage Swing vs. Supply Voltage, RL = 20 kΩ Rev. A | Page 14 of 26

Data Sheet AD8420 +VS +VS –0.2 –0.2 S S WING (V)VOLTAGE ––00..64 WING (V)VOLTAGE ––00..46 VOLTAGE STO SUPPLY +–00..88 –+++42810552°°°5CCC°C VOLTAGE STO SUPPLY +–00..88 –+++42810552°°°5CCC°C T D T D PURE +0.6 PURE +0.6 TR TR OUREFE +0.4 VVSR E=F 5=V 2.5V OUREFE +0.4 +0.2 +0.2 –VS1k 1L0OkAD RESISTANCE1 (0Ω0)k 1M 09945-338 –VS0.1 OUTPUT CURRENT 1(mA) 09945-340 Figure 39. Output Voltage Swing vs. Load Resistance, VS = 5 V Figure 42. Output Voltage Swing vs. Output Current, VS = ±15 +VS 2k –0.2 S 1k T VOLTAGE SWING (V)D TO SUPPLY VOLTAGE +–––0000....6848 –+++42810552°°°5CCC°C NOISE (nV/ Hz) 100 GAIN = 1 TPURRE +0.6 GAIN = 10 OUREFE +0.4 VVSR E=F 5=V 2.5V +0.2 GAIN = 100 –VS0.1 OUTPUT CURRENT (mA) 1 09945-501 200.1 1 10FREQU1E0N0CY (Hz)1k 10k 100k 09945-042 Figure 40. Output Voltage Swing vs. Output Current, VS = 5 V Figure 43. Voltage Noise Spectral Density vs. Frequency, RTI 15 10 V) G ( N WI 5 S E G A 0 T L O V UT –5 P T OU –40°C –10 +25°C –15 ++8152°5C°C 0.4µV/DIV 1s/DIV 09945-043 1k 1L0OkAD RESISTANCE1 (0Ω0)k 1M 09945-339 Figure 41. Output Voltage Swing vs. Load Resistance, VS = ±15 V Figure 44. 0.1 Hz to 10 Hz RTI Voltage Noise, G = 1 Rev. A | Page 15 of 26

AD8420 Data Sheet 1k VS = ±5V Hz) 1V/DIV A/ 1.78µs TO 0.1% E (f 100 3.31µs TO 0.01% S OI N 0.02%/DIV 10 20µs/DIV 09945-149 1 10 F1R0E0QUENCY (1Hkz) 10k 100k 09945-348 Figure 45. Current Noise Spectral Density vs. Frequency Figure 48. Large Signal Pulse Response and Settling Time, G = 1 VS = ±5V 4.5V/DIV 67µs TO 0.1% 138µs TO 0.01% 0.02%/DIV 1.5pA/DIV 1s/DIV 09945-147 200µs/DIV 09945-150 Figure 46. 0.1 Hz to 10 Hz Current Noise Figure 49. Large Signal Pulse Response and Settling Time, G = 10 30 VS = ±15V, G = 15V/V VS = ±5V 27 24 p) p- 21 V E ( 18 4.5V/DIV G A 600ms TO 0.1% LT 15 1.04ms TO 0.01% O V T 12 U P 0.02%/DIV T 9 U O 6 03 VS = +5V, G = 5V/V 20ms/DIV 09945-151 1 10 100FREQUE1kNCY (Hz)10k 100k 1M 09945-148 Figure 47. Large Signal Frequency Response Figure 50. Large Signal Pulse Response and Settling Time, G = 100 Rev. A | Page 16 of 26

Data Sheet AD8420 20mV/DIV 4µs/DIV 09945-051 20mV/DIV 2ms/DIV 09945-054 Figure 51. Small Signal Pulse Response, G = 1, RL = 20 kΩ, CL = 100 pF Figure 54. Small Signal Pulse Response, G = 1000, RL = 20 kΩ, CL = 100 pF NO LOAD 220pF 470pF 780pF 20mV/DIV 20µs/DIV 09945-052 20mV/DIV 5µs/DIV 09945-055 Figure 52. Small Signal Pulse Response, G = 10, RL = 20 kΩ, CL = 100 pF Figure 55. Small Signal Response with Various Capacitive Loads, G = 1, RL = ∞ 90 85 80 A) µ T ( 75 N E R UR 70 C Y PL 65 P U S 60 20mV/DIV 200µs/DIV 09945-053 5505 0 5 10 SU1P5PLY V2O0LTAGE25 (V) 30 35 40 09945-057 Figure 53. Small Signal Pulse Response, G = 100, RL = 20 kΩ, CL = 100 pF Figure 56. Supply Current vs. Total Supply Voltage Rev. A | Page 17 of 26

AD8420 Data Sheet 90 TESTED WITH DUAL SUPPLIES CENTERED AT 0V –20 –40 V) –60 µ E ( G –80 A T OL –100 V ET –120 S F F –140 O –160 –180 –200 0 4 8 1S2UPPL1Y6 VOLT2A0GE (V24) 28 32 36 09945-502 Figure 57. Offset Voltage vs. Total Supply Voltage Rev. A | Page 18 of 26

Data Sheet AD8420 THEORY OF OPERATION AD8420 +VS – A VOUT + I3 –VS Vb +VS R2 ESD – +IN PROTECTION FB gm1 gm2 +–VVSS R1 ESD I1 I2 + –IN PROTECTION –VS REF 09945-058 Figure 58. Simplified Schematic ARCHITECTURE Table 7. Suggested Resistors for Various Gains, 1% Resistors The AD8420 is based on an indirect current feedback topology R1 (kΩ) R2 (kΩ) Gain consisting of three amplifiers: two matched transconductance None Short 1.00 amplifiers that convert voltage to current and one integrator 49.9 49.9 2.00 amplifier that converts current to voltage. 20 80.6 5.03 10 90.9 10.09 For the AD8420, assume that all initial voltages and currents are 5 95.3 20.06 zero until a positive differential voltage is applied between the 2 97.6 49.8 inputs, +IN and −IN. Transconductance Amplifier g converts this m1 input voltage into a current, I1. Because the voltage across g is 1 100 101 m2 initially zero, I2 is zero and I3 equals I1. 1 200 201 1 499 500 I3 is integrated to the output, making the output voltage, V , OUT 1 1000 1001 increase. This voltage continues to increase until the same differ- ential input voltage across the inputs of g is replicated across While the ratio of R2 to R1 sets the gain, the designer determines m1 the inputs of g , generating a current (I2) equal to I1. This reduces the absolute value of the resistors. Larger values reduce power m2 the Difference Current I3 to zero so that the output remains at a consumption and output loading; smaller values limit the FB input stable voltage. The gain in the configuration shown in Figure 58 is bias current and offset current error. For best output swing and set by R2 and R1. distortion performance, keep (R1 + R2) || RL ≥ 20 kΩ. In traditional instrumentation amplifiers, the input common- A method that allows large value feedback resistors while limiting mode voltage can limit the available output swing, typically FB bias current error is to place a resistor of value R1 || R2 in depicted in a hexagon plot. Because the AD8420 converts the series with the REF terminal, as shown in Figure 59. At higher input differential signals to current, this limit does not apply. This gains, this resistor can simply be the same value as R1. is particularly important when amplifying a signal with a common- +IN mode voltage near one of the supply rails. IB+ VOUT To improve robustness and ease of use, the AD8420 includes AD8420 differential voltage protection to limit the current into its inputs IB– FB to a safe level. This protection scheme allows wide differential –IN REF IBF input voltages without damaging the device. IBR + SETTING THE GAIN R1||R2 R2 – R1 R2 G = 1 + The transfer function of the AD8420 is R1 VOUT = G(V+IN − V−IN) + VREF VREF 09945-059 Figure 59. Cancelling Out Error from FB Input Bias Current R2 where G1 . R1 Rev. A | Page 19 of 26

AD8420 Data Sheet GAIN ACCURACY INPUT PROTECTION Unlike most instrumentation amplifiers, the relative match of The current into the AD8420 inputs is limited internally. This the two gain setting resistors determines the gain accuracy of ensures that the diodes that limit the differential voltage seen by the AD8420 rather than a single resistor. For example, if two the internal amplifier do not draw excessive current when they resistors have exactly the same absolute error, there is no error turn on. The device can handle large differential input voltages, in gain. Conversely, two 1% resistors can cause approximately 2% regardless of the amount of gain applied, without damage. As a maximum gain error at high gains. Temperature coefficient result, the AD8420 inputs are protected from voltages beyond mismatch of the gain setting resistors increases the gain drift of the positive rail. If voltages beyond the negative rail are expected, the instrumentation amplifier circuit, according to the gain external protection must be used. equation. Because these external resistors do not have to match Keep all of the AD8420 terminals within the voltage range specified any on-chip resistors, resistors with good TC tracking can in the Absolute Maximum Ratings section. All terminals of the achieve excellent gain drift. Even with standard thin film AD8420 are protected against ESD. resistors, the AD8420 can still achieve better gain drift than Input Voltages Beyond the Rails most instrumentation amplifiers. For applications that require protection beyond the negative rail, When the differential voltage at the inputs approaches the one option is to use an external resistor in series with each input differential input limit, the diodes start to conduct, limiting the to limit current during overload conditions. In this case, size the voltage seen by the inputs of amplifier g . This can look like m1 resistors to limit the current into the AD8420 to 6 mA. increased gain error at large differential inputs. Performance of the AD8420 is specified for ±1 V differential from −40°C to +85°C. RPROTECT ≥ (Negative Supply − VIN)/6 mA However, at higher temperatures, the reduced forward voltage of Although the AD8420 inputs must still be kept within the −V + S the diodes limits the differential input to a smaller voltage. 40 V limitation, the I × R drop across the protection resistor Figure 60 tracks 1% error across the operating temperature increases the protection on the positive side to approximately range to show the effect of temperature on the input limit. (40 V + Negative Supply) + 300 μA × R PROTECT 2.0 NEGATIVE VOLTAGE VS = ±15V An alternate protection method is to place diodes at the AD8420 OR) 1.8 inputs to limit voltage and resistors in series with the inputs to 1% ERR 11..64 POSITIVE VOLTAGE lai mmiitn tihmeu cmur rfoenr tn ionrtmo athl eospee draiotidoens,. uTsoe kloewep l einapkuagt eb idaiso cduer crleanmt apts , E ( G 1.2 such as the BAV199. The AD8420 also combines well with TVS A OLT 1.0 diodes, such as the PTVSxS1UR. V NPUT 0.8 RPROTECT +VS RPROTECT +VS +VS M I 0.6 + + I XIMU 0.4 VI–N+ AD8420 V–IN+ –VS AD8420 MA 0.2 +VS RPROTECT RPROTECT 0–40Fig–u25re 6–010. Diff5erenT2tEi0aMl PInE3p5RuAtT LU5i0RmEi t( °v6Cs5). Te8m0per9a5ture1 1 0 125 09945-503 VI+–N– SIMPLE MET–HVOSD V+–IN– ALTERN–AVTSE METH–OVDS 09945-160 INPUT VOLTAGE RANGE Figure 61. Protection for Voltages Beyond the Rails The allowed input range of the AD8420 is much simpler than Large Differential Input Voltage traditional architectures. For the transfer function of the AD8420 The AD8420 is able to handle large differential input voltage to be valid, the input voltage should follow two rules: without damage to the device. Refer to Figure 9, Figure 10,  Keep the differential input voltage within ±1 V. Figure 11, and Figure 12 for overvoltage performance. The  Keep the voltage on the +IN, −IN, REF, and FB pins in the AD8420 differential voltage is internally limited with diodes to ±1 V. If this limit is exceeded, the diodes start to conduct and specified input voltage range. draw current, as shown in Figure 22. This current is limited Because the output swing is completely independent of the internally to a value that is safe for the AD8420, but if the input input common-mode voltage, there are no hexagonal figures current cannot be tolerated in the system, place resistors in or complicated formulas to follow, and no limitation for the series with each input with the following value: output swing the amplifier has for input signals with changing common mode. 1V 1V R   DIFF  PROTECT 2 I   MAX  Rev. A | Page 20 of 26

Data Sheet AD8420 LAYOUT Reference Common-Mode Rejection Ratio over Frequency The output voltage of the AD8420 is developed with respect to the potential on the reference terminal. Take care to tie REF to the Poor layout can cause some of the common-mode signal to be appropriate local ground. The differential voltage at the inputs is converted to a differential signal before reaching the in-amp. This reproduced between the REF and FB pins; therefore, it is important conversion can occur when the path to the positive input pin to set V so that the voltage at FB does not exceed the input range. has a different frequency response than the path to the negative REF input pin. For best CMRR vs. frequency performance, the input DRIVING THE REFERENCE PIN source impedance and capacitance of each path should be closely Traditional instrumentation amplifier architectures require the matched. This includes connecting Pin 1 to −V, which matches the S reference pin to be driven with a low impedance source. In these parasitic capacitance and the leakage between the inputs and architectures, impedance at the reference pin degrades both CMRR adjacent pins. Place additional source resistance in the input and gain accuracy. With the AD8420 architecture, resistance at path (for example, for input protection) close to the in-amp inputs the reference pin has no effect on CMRR. to minimize their interaction with the parasitic capacitance from the printed circuit board (PCB) traces. +IN Power Supplies VOUT AD8420 Use a stable dc voltage to power the instrumentation amplifier. FB Noise on the supply pins can adversely affect performance. For –IN REF more information, see the PSRR performance curves in Figure 24 R1 R2 and Figure 25. G = 1 +R2 + RREF RREF PAlsa cshe oaw 0n.1 i nμF F cigaupraec i6t2o,r aa s1 0cl μoFse t aasn tpaolussmib clea ptoa ceiatochr csaunp pbley upsiend. R1 VREF 09945-062 Figure 63. Calculating Gain with Reference Resistance farther away from the device. This capacitor, which is intended to be effective at low frequencies, can usually be shared by other Resistance at the reference pin does affect the gain of the AD8420, precision integrated circuits. Keep the traces between these but if this resistance is constant, the gain setting resistors can be integrated circuits short to minimize interaction of the trace adjusted to compensate. For example, the AD8420 can be driven parasitic inductance with the shared capacitor. with a voltage divider to level shift the output as shown in Figure 64. +VS +IN 0.1µF 10µF VOUT AD8420 +IN FB VOUT –IN REF AD8420 VS R1 R2 R1 R2 R3 –IN R2 + R3||R4 G = 1 + R1 R4 09945-063 0.1µF 10µF Figure 64. Using Resistor Divider to Set Reference Voltage –VS 09945-060 Figure 62. Supply Decoupling, REF, and Output Referred to Local Ground Rev. A | Page 21 of 26

AD8420 Data Sheet INCORRECT CORRECT +VS +VS VOUT VOUT AD8420 AD8420 –VS –VS TRANSFORMER TRANSFORMER +VS +VS VOUT VOUT AD8420 AD8420 10MΩ –VS –VS THERMOCOUPLE THERMOCOUPLE +VS +VS C C AD8420 VOUT fHIGH-PASS =2π1RCR AD8420 VOUT C C R CAPACITIVE–LVYS COUPLED CAPACITIVELY COUP–LVESD 09945-061 Figure 65. Creating an IBIAS Path INPUT BIAS CURRENT RETURN PATH +VS 0.1µF 10µF The input bias current of the AD8420 must have a return path R CC to ground. When the source, such as a thermocouple, cannot 20kΩ 330pF 1% 5% provide a return current path, create one, as shown in Figure 65. +IN VOUT RADIO FREQUENCY INTERFERENCE (RFI) 20RkΩ 3300CpFD AD8420 1% All instrumentation amplifiers can rectify high frequency out-of- –IN CC R1 R2 band signals. Once rectified, these signals appear as dc offset errors 330pF 5% at the output. High frequency signals can be filtered with a low-pass 0.1µF 10µF RshCo wnent wino rFki gpularcee 6d6 a. tT thhee ifnilpteurt loimf tihtse tihnes tirnupmute nsitgantiaoln b aanmdpwliifdietrh, as –VS 09945-064 according to the following relationship: Figure 66. Suggested RFI Suppression Filter 1 CD affects the differential signal and CC affects the common-mode FilterFrequency  DIFF 2πR(2C C ) signal. Values of R and CC are chosen to minimize out of band D C RFI at the expense of reduced signal bandwidth. Mismatch 1 between the R × C at the positive input and the R × C at the FilterFrequency  C C CM 2πRC negative input degrades the CMRR of the AD8420. By using a C value of C that is at least one magnitude larger than C , the where C  10 C . D C D C effect of the mismatch is reduced and performance is improved. Rev. A | Page 22 of 26

Data Sheet AD8420 OUTPUT BUFFERING Because the ADA4692-2 is a dual op amp, another op amp is now free for use as an active filter stage or to buffer another AD8420 The AD8420 is designed to drive loads of 20 kΩ or greater but output on the same PCB. Figure 68 shows another suggestion can deliver up to 10 mA to heavier loads at lower output voltage for how to use this second op amp. In this circuit, the voltage swings (see Figure 42). If more output current is required, buffer from the wiper of a potentiometer is buffered by the ADA4692-2, the AD8420 output with a precision op amp. Figure 67 shows allowing a variable level shift of the output. Resistors above and the recommended configuration using the ADA4692-2 with a below the potentiometer reduce the total range of the level shift single supply. This low power op amp can swing its output from but increase the precision. If the potentiometer were connected 1 V to 4 V on a single 5 V supply while sourcing or sinking directly to the REF pin of the AD8420, gain error would be intro- more than 30 mA of current. When using this configuration, duced from the variable resistance. The potentiometer can be tuned the load seen by the AD8420 is approximately R1 + R2. in hardware or software, depending on the type of potentiometer +5V chosen. For a list of digital potentiometers made by Analog +VS 0.1µF Devices, Inc., visit www.analog.com/digitalpotentiometers. +VS 0.1µF +5V VIN AD8420 0.1µF ADA4692-2 VOUT R1 R2 0.1µF –VS VREF VIN AD8420 VOUT –VS 09945-065 R1 R2 WCW R Figure 67. Output Buffering REF ADA4692-2 CCW R SUGGESTION FOR SECOND AALEMFVFPEELLCIF TSIIEHNRIGF: TVG AWARIINTIAHBOLUET 09945-066 Figure 68. Variable Level Shift Rev. A | Page 23 of 26

AD8420 Data Sheet APPLICATIONS INFORMATION AD8420 IN ELECTROCARDIOGRAPHY (ECG) by unbalancing the transconductance amplifier at the REF and FB pins. In the steady state, the offset at the input is not gained A high-pass filter is commonly used in ECG signal conditioning to the output, and higher frequency signals can be gained and circuitry to remove electrode offset and motion artifacts. To avoid passed through. Using the AD8420 in this way, the offset tolerance degrading the input impedance and CMRR of the system, this is nearly the differential input range of the device (±1 V). filtering is typically implemented after the instrumentation amplifier, which limits the gain that can be applied with the Figure 69 shows an ECG front end that applies a gain of 100 to instrumentation amplifier. the signal while rejecting dc and high frequencies. This circuit combines the AD8420 with the AD8657, which is a low power, With a 3-op-amp instrumentation amplifier, gain is applied in the low cost, dual, precision CMOS op amp. first stage. Because of this, the electrode offset is gained and then must be removed afterward with a high-pass filter. In the AD8420 architecture, the offset can be accounted for in the input stage INSTRUMENTATION THREE-POLE LPF, AMPLIFIER BESSEL RESPONSE 200pF G = +100 FC = 50Hz +5V 402kΩ A B 100kΩ 110kΩ 200kΩ 0.015μF 2000pF AD8420 FB 100kΩ 500kΩ 100kΩ 0.022μF 200kΩ +5V REF 1kΩ 200pF –5V 3.3μF 8200pF C 10MΩ +5V –5V AD8657-1 AD8657-2 –5V HIINGTHE-GPARSAST OPRO LPER OATV I0D.E5HSz 09945-072 Figure 69. AD8420 in an ECG Front End Rev. A | Page 24 of 26

Data Sheet AD8420 CLASSIC BRIDGE CIRCUIT 4 mA TO 20 mA SINGLE-SUPPLY RECEIVER Figure 70 shows the AD8420 configured to amplify the signal from The 90 μA maximum supply current, input range that goes a classic resistive bridge. This circuit works in dual-supply mode or below ground, and low drift characteristics make the AD8420 a single-supply mode. Typically, the same voltage that powers the very good candidate for use in a 4 mA to 20 mA loop. Figure 71 instrumentation amplifier excites the bridge. Connecting the shows how a signal from a 4 mA to 20 mA transducer can be bottom of the bridge to the negative supply of the instrumentation interfaced to the AD8420. The signal from a 4 mA to 20 mA amplifier sets up an input common-mode voltage that is located transducer is single-ended, which initially suggests the need for midway between the supply voltages. The voltage on the REF pin a simple shunt resistor to ground to convert the current to a voltage. can be varied to suit the application. For example, the REF pin However, any line resistance in the return path (to the transducer) is tied to the V pin of an analog-to-digital converter (ADC) adds a current-dependent offset error; therefore, the current must REF whose input range is (V ± V ). With an available output swing be sensed differentially. REF IN on the AD8420 of (−V + 100 mV) to (+V − 150 mV), the S S In this example, a 5 Ω shunt resistor generates a differential voltage maximum programmable gain is simply this output range divided at the inputs of the AD8420 between 20 mV (for 4 mA in) and by the input range. 100 mV (for 20 mA in) with a very low common-mode value. +VS With the gain resistors shown, the AD8420 amplifies the 100 mV 0.1µF input voltage by a factor of 40 to 4.0 V. VDIFF AD8420 VOUT VREF 0.1µF –VS 09945-069 Figure 70. Classic Bridge Circuit 5V 0.1µF – 4mA TO 20mA LINE 4mA TO 20mA 5Ω AD8A4D20627 0.8V TO 4.0V TRANSDUCER IMPEDANCE G = 40 + + – PSOUPWPELRY RR12 == 29.74.96kkΩΩ R1 R2 09945-073 Figure 71. 4 mA to 20 mA Receiver Circuit Rev. A | Page 25 of 26

AD8420 Data Sheet OUTLINE DIMENSIONS 3.20 3.00 2.80 8 5 5.15 3.20 4.90 3.00 4.65 2.80 1 4 PIN 1 IDENTIFIER 0.65 BSC 0.95 15° MAX 0.85 1.10 MAX 0.75 0.80 0.15 0.40 6° 0.23 0.55 CO0P.0L50A.1N0ARICTOYMPLIANT0. 2T5O JEDEC STA0°NDARDS 0M.0O9-187-AA 0.40 10-07-2009-B Figure 72. 8-Lead Mini Small Outline Package [MSOP] (RM-8) Dimensions shown in millimeters ORDERING GUIDE Package Model1 Temperature Range Package Description Option Branding AD8420ARMZ −40°C to +85°C 8-Lead Mini Small Outline Package [MSOP], Tube RM-8 Y3Y AD8420ARMZ-R7 −40°C to +85°C 8-Lead Mini Small Outline Package [MSOP], 7-Inch Tape and Reel RM-8 Y3Y AD8420ARMZ-RL −40°C to +85°C 8-Lead Mini Small Outline Package [MSOP], 13-Inch Tape and Reel RM-8 Y3Y 1 Z = RoHS Compliant Part. ©2012–2015 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D09945-0-1/15(A) Rev. A | Page 26 of 26

Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: A nalog Devices Inc.: AD8420ARMZ AD8420ARMZ-R7 AD8420ARMZ-RL