LF to 2.7 GHz Dual 60 dB TruPwr™ Detector Data Sheet AD8364 FEATURES FUNCTIONAL BLOCK DIAGRAM RMS measurement of high crest-factor signals PA CA MA SR OM MP OM PA H E O P C E C L Dual-channel and channel difference outputs ports C D C V A T A C 24 23 22 21 20 19 18 17 Integrated accurately scaled temperature sensor Wide dynamic range ±1 dB over 60 dB TEMP VGA ±0.5 dB temperature-stable linear-in-dB response VPSA 25 CONTROL 16 VSTA Low log conformance ripple INHA 26 CHANNEL A ISIG2 15 OUTA +Sm5 Val ol fpoeortaptiroinnt ,a 5t 7m0m m ×A ,5 – m40m°C, L tFoC +S8P5 °C INLA 27 TruPwr™ ITGT2 14 FBKA APPLICATIONS PWDN 28 OUTA 13 OUTP OUTB COMR 29 12 OUTN Wireless infrastructure power amplifier linearization/control Antenna VSWR monitor INLB 30 11 FBKB CHANNEL B ISIG2 Gain and power control and measurement INHB 31 TruPwr™ 10 OUTB Transmitter signal strength indication (TSSI) ITGT2 VPSB 32 9 VSTB Dual-channel wireless infrastructure radios VGA CONTROL BIAS 1 2 3 4 5 6 7 8 CHPB DECB COMB ADJB ADJA VREF VLVL CLPB 05334-001 Figure 1. Functional Block Diagram GENERAL DESCRIPTION The AD8364 is a true rms, responding, dual-channel RF power Integrated in the AD8364 are two matched AD8362 channels measurement subsystem for the precise measurement and control (see the AD8362 data sheet for more information) with improved of signal power. The flexibility of the AD8364 allows communi- temperature performance and reduced log conformance ripple. cations systems, such as RF power amplifiers and radio transceiver Enhancements include improved temperature performance and AGC circuits, to be monitored and controlled with ease. Operating reduced log-conformance ripple compared to the AD8362. On- on a single 5 V supply, each channel is fully specified for operation chip wide bandwidth output operational amplifiers are connected up to 2.7 GHz over a dynamic range of 60 dB. The AD8364 to accom-modate flexible configurations that support many provides accurately scaled, independent, rms outputs of both RF system solutions. measurement channels. Difference output ports, which measure The device can easily be configured to provide four rms the difference between the two channels, are also available. The measurements simultaneously. Linear-in-dB rms measurements on-chip channel matching makes the rms channel difference are supplied at OUTA and OUTB, with conveniently scaled outputs extremely stable with temperature and process variations. slopes of 50 mV/dB. The rms difference between OUTA and The device also includes a useful temperature sensor with an OUTB is available as differential or single-ended signals at accurately scaled voltage proportional to temperature, specified OUTP and OUTN. An optional voltage applied to VLVL over the device operating temperature range. The AD8364 can provides a common mode reference level to offset OUTP and be used with input signals having rms values from −55 dBm to OUTN above ground. +5 dBm referred to 50 Ω and large crest factors with no The AD8364 is supplied in a 32-lead, 5 mm × 5 mm LFCSP, for accuracy degradation. the operating temperature of –40°C to +85°C. Rev. C Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Tel: 781.329.4700 ©2005–2016 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com

AD8364 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Controller Mode ......................................................................... 22 Applications ....................................................................................... 1 RF Measurement Mode Basic Connections ........................... 23 Functional Block Diagram .............................................................. 1 Controller Mode Basic Connections ....................................... 24 General Description ......................................................................... 1 Constant Output Power Operation .......................................... 27 Revision History ............................................................................... 2 Gain-Stable Transmitter/Receiver ............................................ 29 Specifications ..................................................................................... 3 Temperature Compensation Adjustment................................ 31 Absolute Maximum Ratings ............................................................ 7 Device Calibration and Error Calculation .............................. 31 ESD Caution .................................................................................. 7 Selecting Calibration Points to Improve Accuracy over a Pin Configuration and Function Descriptions ............................. 8 Reduced Range ........................................................................... 32 Typical Performance Characteristics ............................................. 9 Channel Isolation ....................................................................... 34 Theory of Operation ...................................................................... 18 Altering the Slope ....................................................................... 35 Square Law Detector and Amplitude Target........................... 19 Choosing the Right Value for CHP[A, B] and CLP[A, B] .... 36 RF Input Interface ...................................................................... 19 RF Burst Response Time ........................................................... 36 Offset Compensation ................................................................. 19 Single-Ended Input Operation ................................................. 36 Temperature Sensor Interface ................................................... 20 Printed Circuit Board Considerations ..................................... 37 VREF Interface ........................................................................... 20 Package Considerations ............................................................. 37 Power-Down Interface ............................................................... 20 Description of Characterization ............................................... 38 VST[A, B] Interface .................................................................... 20 Basis for Error Calculations ...................................................... 38 OUT[A, B, P, N] Outputs .......................................................... 21 Evaluation Board ........................................................................ 40 Outline Dimensions ....................................................................... 41 Measurement Channel Difference Output Using OUT[P, N] ....................................................................................................... 22 Ordering Guide .......................................................................... 41 REVISION HISTORY 8/2016—Rev. B to Rev. C Deleted Figure 85 and Figure 86; Renumbered Sequentially ... 41 Updated Outline Dimensions ....................................................... 41 Updated Outline Dimensions ....................................................... 41 Changes to Ordering Guide .......................................................... 41 Changes to Ordering Guide .......................................................... 41 Deleted Table 7, AD8364-EVAL-500 Evaluation Board 1/2012—Rev. A to Rev. B Configuration Options and AD8364-EVAL-2140 Evaluation Change to Figure 84 ....................................................................... 40 Board Configuration Options; Renumbered Sequentially ....... 42 Deleted Evaluation Boards Section and Figure 87 ..................... 44 11/2011—Rev. 0 to Rev. A Deleted Figure 88 ............................................................................ 45 Changes to Figure 2 .......................................................................... 8 Deleted Assembly Drawings Section, Figure 89, and Changes to Automatic Power Control Section ........................... 24 Figure 90 .......................................................................................... 46 Replaced Evaluation and Characterization Circuit Board Layouts Section with Evaluation Board Section ......................... 40 4/2005—Revision 0: Initial Version Changes to Figure 84 ...................................................................... 40 Rev. C | Page 2 of 44

Data Sheet AD8364 SPECIFICATIONS V = VPSA = VPSB = VPSR = 5 V, T = 25°C, Channel A frequency = Channel B frequency, VLVL = VREF, VST[A, B] = OUT[A, S A B], OUT[P, N] = FBK[A, B], differential input via Balun, CW input f ≤ 2.7 GHz, unless otherwise noted. Table 1. Parameter Test Conditions/Comments Min Typ Max Unit OVERALL FUNCTION Channel A and Channel B, CW sine wave input Signal Input Interface INH[A, B] (Pins 26, 31) INL[A, B] (Pins 27, 30) Specified Frequency Range LF 2.7 GHz DC Common-Mode Voltage 2.5 V Signal Output Interface OUT[A, B] (Pins 15, 10) Wideband Noise CLP[A, B] = 0.1µF, f = 100 kHz, 40 nV/√Hz SPOT RF input = 2140 MHz, ≥−40 dBm MEASUREMENT MODE, ADJA = ADJB = 0 V, error referred to best fit line using 450 MHz OPERATION linear regression @ PINH[A, B] = −40 dBm and −20 dBm, T = 25°C, balun = M/A-Com ETK4-2T A ±1 dB Dynamic Range1 Pins OUT[A, B] 69 dB −40°C < T < +85°C 65 dB A ±0.5 dB Dynamic Range1 Pins OUT[A, B], (Channel A/Channel B) 62/59 dB −40°C < T < +85°C, (Channel A/Channel B) 50/52 dB A Maximum Input Level ±1 dB error 12 dBm Minimum Input Level ±1 dB error −58 dBm Slope 51.6 mV/dB Intercept −59 dBm Output Voltage—High Power In Pins OUT[A, B] @ P = −10 dBm 2.53 V INH[A, B] Output Voltage—Low Power In Pins OUT[A, B] @ P = −40 dBm 0.99 V INH[A, B] Temperature Sensitivity Deviation from OUT[A, B] @ 25°C −40°C < T < 85°C; P = −10 dBm −0.1, +0.2 dB A INH[A, B] −40°C < T < 85°C; P = −25 dBm −0.2, +0.3 dB A INH[A, B] −40°C < T < 85°C; P = −40 dBm −0.3, +0.4 dB A INH[A, B] Deviation from OUTP to OUTN @ 25°C −40°C < T < 85°C; P = −10 dBm, −25 dBm ±0.25 dB A INH[A, B] −40°C < T < 85°C; P = −25 dBm, −25 dBm ±0.2 dB A INH[A, B] −40°C < T < 85°C; P = −40 dBm, −25 dBm ±0.2 dB A INH[A, B] Input A to Input B Isolation Baluns = Macom ETC1.6-4-2-3 (both channels) 71 dB Input A to OUTB Isolation Freq separation = 1 kHz Input B to OUTA Isolation2 P = −50 dBm, OUTB = OUTB ± 1 dB 54 dB INHB PINHB P = −50 dBm, OUTA = OUTA ± 1 dB 54 dB INHA PINHA Input Impedance INHA/INLA, INHB/INLB differential drive 210||0.1 Ω||pF Input Return Loss With recommended balun −12 dB MEASUREMENT MODE, ADJA = ADJB = 0 V, error referred to best fit line using 880 MHz OPERATION linear regression @ PINH[A, B] = −40 dBm and −20 dBm, T = 25°C, balun = Mini-Circuits® JTX-4-10T A ±1 dB Dynamic Range1 Pins OUT[A, B], (Channel A/Channel B) 66/57 dB −40°C < T < +85°C 58/40 dB A ±0.5 dB Dynamic Range1 Pins OUT[A, B], (Channel A/Channel B) 62/54 dB −40°C < T < +85°C 20/20 dB A Maximum Input Level ±1 dB error, (Channel A/Channel B) 8/0 dBm Minimum Input Level ±1 dB error, (Channel A/Channel B) −58/−57 dBm Slope 51.6 mV/dB Intercept −59.2 dBm Output Voltage—High Power In Pins OUT[A, B] @ P = −10 dBm 2.54 V INH[A, B] Output Voltage—Low Power In Pins OUT[A, B] @ P = −40 dBm 0.99 V INH[A, B] Rev. C | Page 3 of 44

AD8364 Data Sheet Parameter Test Conditions/Comments Min Typ Max Unit Temperature Sensitivity Deviation from OUT[A, B] @ 25°C −40°C < T < 85°C; P = −10 dBm +0.5 dB A INH[A, B] −40°C < T < 85°C; P = −25 dBm +0.5 dB A INH[A, B] −40°C < T < 85°C; P = −40 dBm +0.5 dB A INH[A, B] Deviation from OUTP to OUTN @ 25°C −40°C < T < 85°C; P = −10 dBm, −25 dBm +0.1, −0.2 dB A INH[A, B] −40°C < T < 85°C; P = −25 dBm, −25 dBm +0.1, −0.2 dB A INH[A, B] −40°C < T < 85°C; P = −40 dBm, −25 dBm +0.1, −0.2 dB A INH[A, B] Input A to Input B Isolation Baluns = Macom ETC1.6-4-2-3 (both channels) 64 dB Input A to OUTB Isolation P = −50 dBm, OUTB = OUTB ± 1 dB 35 dB INHB PINHB Input B to OUTA Isolation2 P = −50 dBm, OUTA = OUTA ± 1 dB 35 dB INHA PINHA Input Impedance INHA/INLA, INHB/INLB differential drive 200||0.3 Ω||pF Input Return Loss With recommended balun −9 dB MEASUREMENT MODE, ADJA = ADJB = 0.75 V, error referred to best fit line using 1880 MHz OPERATION linear regression @ PINH[A, B] = −40 dBm and −20 dBm, T = 25°C, balun = Murata LDB181G8820C-110 A ±1 dB Dynamic Range1 Pins OUT[A, B], (Channel A/Channel B) 69/61 dB −40°C < T < +85°C 60/50 dB A ±0.5 dB Dynamic Range1 Pins OUT[A, B], (Channel A/Channel B) 62/51 dB −40°C < T < +85°C 58/51 dB A Maximum Input Level ±1 dB error, (Channel A/Channel B) 11/3 dBm Minimum Input Level ±1 dB error −58 dBm Slope 50 mV/dB Intercept −62 dBm Output Voltage—High Power In Pins OUT[A, B] @ P = −10 dBm 2.49 V INH[A,B] Output Voltage—Low Power In Pins OUT[A, B] @ P = −40 dBm 0.98 V INH[A,B] Temperature Sensitivity Deviation from OUT[A, B] @ 25°C −40°C < T < 85°C; P = −10 dBm +0.5, −0.2 dB A INH[A, B] −40°C < T < 85°C; P = −25 dBm +0.5, −0.2 dB A INH[A, B] −40°C < T < 85°C; P = −40 dBm +0.5, −0.2 dB A INH[A, B] Deviation from OUTP to OUTN @ 25°C −40°C < T < 85°C; P = −10 dBm, −25 dBm ±0.3 dB A INH[A, B] −40°C < T < 85°C; P = −25 dBm, −25 dBm ±0.3 dB A INH[A, B] −40°C < T < 85°C; P = −40 dBm, −25 dBm ±0.3 dB A INH[A, B] Input A to Input B Isolation Baluns = Macom ETC1.6-4-2-3 (both channels) 61 dB Input A to OUTB Isolation P = −50 dBm, OUTB = OUTB ± 1 dB 33 dB INHB PINHB Input B to OUTA Isolation2 P = −50 dBm, OUTA = OUTA ± 1 dB 33 dB INHA PINHA Input Impedance INHA/INLA, INHB/INLB differential drive 167||0.14 Ω||pF Input Return Loss With recommended balun −8 dB MEASUREMENT MODE, ADJA = ADJB = 1.02 V, error referred to best fit line using 2.14 GHz OPERATION linear regression @ PINH[A, B] = −40 dBm and −20 dBm, T = 25°C, balun = Murata LDB212G1020C-001 A ±1 dB Dynamic Range1 Pins OUT[A, B], (Channel A/Channel B) 66/57 dB −40°C < T < +85°C 58/40 dB A ±0.5 dB Dynamic Range1 Pins OUT[A, B], (Channel A/Channel B) 62/54 dB −40°C < T < +85°C 30/30 dB A Maximum Input Level ±1 dB Error, (Channel A/Channel B) −2/−4 dBm Minimum Input Level ±1 dB Error, (Channel A/Channel B) −57−51 dBm Slope Channel A/Channel B 49.5/52.1 mV/dB Intercept Channel A/Channel B −58.3/−57.1 dBm Output Voltage—High Power In Pins OUT[A, B] @ P = −10 dBm 2.42 V INH[A, B] Output Voltage—Low Power In Pins OUT[A, B] @ P = −40 dBm 0.90 V INH[A, B] Rev. C | Page 4 of 44

Data Sheet AD8364 Parameter Test Conditions/Comments Min Typ Max Unit Temperature Sensitivity Deviation from OUT[A, B] @ 25°C −40°C < T < 85°C; P = −10 dBm +0.1, −0.4 dB A INH[A, B] −40°C < T < 85°C; P = −25 dBm +0.1, −0.4 dB A INH[A, B] −40°C < T < 85°C; P = −40 dBm +0.1, −0.4 dB A INH[A, B] Deviation from OUTP to OUTN @ 25°C −40°C < T < 85°C; P = −10 dBm, −25 dBm +0.1, −0.4 dB A INH[A, B] −40°C < T < 85°C; P = −25 dBm, −25 dBm +0.2, −0.2 dB A INH[A, B] −40°C < T < 85°C; P = −40 dBm, −25 dBm +0.1, −0.2 dB A INH[A, B] Deviation from CW Response 5.5 dB peak-to-rms ratio (WCDMA one channel) 0.2 dB 12 dB peak-to-rms ratio (WCDMA three channels) 0.3 dB 18 dB peak-to-rms ratio (WCDMA four channels) 0.3 dB Input A to Input B Isolation Baluns = Macom ETC1.6-4-2-3 (both channels) 58 dB Input A to OUTB Isolation P = −50 dBm, OUTB = OUTB ± 1 dB 33 dB INHB PINHB Input B to OUTA Isolation2 P = −50 dBm, OUTA = OUTA ± 1 dB 33 dB INHA PINHA Input Impedance INHA/INLA, INHB/INLB differential drive 150||1.9 Ω||pF Input Return Loss With recommended balun −10 dB MEASUREMENT MODE, ADJA = ADJB = 1.14 V, error referred to best fit line using 2.5 GHz OPERATION linear regression @ PINH[A, B] = −40 dBm and −20 dBm, T = 25°C, balun = Murata LDB182G4520C-110 A ± 1 dB Dynamic Range1 Pins OUT[A, B], (Channel A/Channel B) 69/63 dB −40°C < T < +85°C 58 dB A ±0.5 dB Dynamic Range1 Pins OUT[A, B], (Channel A/Channel B) 55/50 dB −40°C < T < +85°C 25 dB A Maximum Input Level ±1 dB error, (Channel A/Channel B) 17/11 dBm Minimum Input Level ±1 dB error −52 dBm Slope 50 mV/dB Intercept −52.7 dBm Output Voltage—High Power In Pins OUT[A, B] @ P = −10 dBm 2.14 V INH[A, B] Output Voltage—Low Power In Pins OUT[A, B] @ P = −40 dBm 0.65 V INH[A, B] Temperature Sensitivity Deviation from OUT[A, B] @ 25°C −40°C < T < 85°C; P = −10 dBm ±0.5 dB A INH[A, B] −40°C < T < 85°C; P = −25 dBm ±0.5 dB A INH[A, B] −40°C < T < 85°C; P = −40 dBm ±0.5 dB A INH[A, B] Deviation from OUTP to OUTN @ 25°C −40°C < T < 85°C; P = −10 dBm, −25 dBm ±0.3 dB A INH[A, B] −40°C < T < 85°C; P = −25 dBm, −25 dBm ±0.3 dB A INH[A, B] −40°C < T < 85°C; P = −40 dBm, −25 dBm ±0.3 dB A INH[A, B] Input A to Input B Isolation Baluns = Macom ETC1.6-4-2-3 (both channels) 54 dB Input A to OUTB Isolation P = −50 dBm, OUTB = OUTB ± 1 dB 31 dB INHB PINHB Input B to OUTA Isolation2 P = −50 dBm, OUTA = OUTA ± 1 dB 31 INHA PINHA Input Impedance INHA/INLA, INHB/INLB differential drive 150||1.7 Ω||pF Input Return Loss With recommended balun −11.5 dB OUTPUT INTERFACE Pin OUTA and OUTB Voltage Range Min R ≥ 200 Ω to ground 0.09 V L Voltage Range Max R ≥ 200 Ω to ground V − 0.15 V L S Source/Sink Current OUTA and OUTB held at V/2, to 1% change 70 mA S Rev. C | Page 5 of 44

AD8364 Data Sheet Parameter Test Conditions/Comments Min Typ Max Unit SETPOINT INPUT Pin VSTA and VSTB Voltage Range Law conformance error ≤1 dB 0.5 3.75 V Input Resistance 68 kΩ Logarithmic Scale Factor f = 450 MHz, −40°C ≤ T ≤ +85°C 50 mV/dB A Logarithmic Intercept f = 450 MHz, −40°C ≤ T ≤ +85°C, referred to 50 Ω −55 dBm A CHANNEL DIFFERENCE OUTPUT Pin OUTP and OUTN Voltage Range Min R ≥ 200 Ω to ground 0.1 V L Voltage Range Max R ≥ 200 Ω to ground V − 0.15 V L S Source/Sink Current OUTP and OUTN held at V/2, to 1% change 70 mA S DIFFERENCE LEVEL ADJUST Pin VLVL Voltage Range3 OUT[P, N] = FBK[A, B] 0 5 V OUT[P,N] Voltage Range OUT[P, N] = FBK[A, B] 0 V − V S 0.15 Input Resistance 1 kΩ TEMPERATURE COMPENSATION Pin ADJA and ADJB Input Voltage Range 0 2.5 V Input Resistance >1 MΩ VOLTAGE REFERENCE Pin VREF Output Voltage RF in = −55 dBm 2.5 V Temperature Sensitivity −40°C ≤ T ≤ +85°C 0.4 mV/°C A Current Limit Source/Sink 1% change 10/3 mA TEMPERATURE REFERENCE Pin TEMP Output Voltage T = 25°C, R ≥ 10 kΩ 0.62 V A L Temperature Coefficient −40°C ≤ T ≤ +85°C, R ≥ 10 kΩ 2 mV/°C A L Current Source/Sink T = 25°C to 1% change 1.6/2 mA A POWER-DOWN INTERFACE Pin PWDN Logic Level to Enable Logic LO enables 1 V Logic Level to Disable Logic HI disables 3 V Input Current Logic HI PWDN = 5 V 95 µA Logic LO PWDN = 0 V <100 µA Enable Time PWDN LO to OUTA/OUTB at 100% final value, 2 µs C = Open, C = 10 nF, RF in = 0 dBm LPA/B HPA/B Disable Time PWDN HI to OUTA/OUTB at 10% final value, 1.6 µs C = Open, C = 10nF, RF in = 0 dBm LPA/B HPA/B POWER INTERFACE Pin VPS[A, B], VPSR Supply Voltage 4.5 5.5 V Quiescent Current RF in = −55 dBm, V = 5 V 70 mA S −40°C ≤ T ≤ +85°C 90 mA A Supply Current PWDN enabled, V = 5 V 500 µA S −40°C ≤ T ≤ +85°C 900 µA A 1 Best fit line, linear regression. 2 See Figure 73 for a plot of isolation vs. frequency for a ±1 dB error. 3 VLVL + OUTA/2 should not exceed VPSA − 1.31 V. Likewise, VLVL + OUTB/2 should not exceed VPSB − 1.31 V. Rev. C | Page 6 of 44

Data Sheet AD8364 ABSOLUTE MAXIMUM RATINGS Table 2. Stresses at or above those listed under Absolute Maximum Parameter Rating Ratings may cause permanent damage to the product. This is a Supply Voltage VPSA, VPSB, VPSR 5.5 V stress rating only; functional operation of the product at these PWDN, VSTA, VSTB, ADJA, ADJB, 0 V, 5.5 V or any other conditions above those indicated in the operational FBKA, FBKB section of this specification is not implied. Operation beyond Input Power (Referred to 50 Ω) 23 dBm the maximum operating conditions for extended periods may Internal Power Dissipation 600 mW affect product reliability. θ 39.8°C/W1, 2 JA ESD CAUTION θ 3.9°C/W2 JC θ 22.8°C/W2 JB Ψ 0.4°C/W1, 2 JT Maximum Junction Temperature 125°C Operating Temperature Range −40°C to +85°C Storage Temperature Range −65°C to +150°C 1 Still air. 2 All values are modeled using a standard 4-layer JEDEC test board with the pad soldered to the board and thermal vias in the board. Rev. C | Page 7 of 44

AD8364 Data Sheet PIN CONFIGURATION AND FUNCTION DESCRIPTIONS PACAMASROMMPOMPA HEOPCECL CDCVATAC 43210987 22222111 VPSA 25 16 VSTA INHA 26 15 OUTA INLA 27 14 FBKA AD8364 PWDN 28 13 OUTP COMR 29 TOP VIEW 12 OUTN (Not to Scale) INLB 30 11 FBKB INHB 31 10 OUTB VPSB 32 9 VSTB 12345678 BBBBAFLB PCMJJEVP CHDECOADADVRVLCL NOTES 1. THE EXPOSED PADDLE ON THE UNDERSIDE OAEL FGE TRCHOTEUR INPCADAC LPK LCAAHGNAEER SWAHCITOTHUE LRLDIOS WBTIE CT SSHO.ELRDMEARLE ADN TDO 05334-002 Figure 2. Pin Configuration Table 3. Pin Function Descriptions Pin No. Mnemonic Description Equiv. Circuit 1 CHPB Connect to common via a capacitor to determine 3 dB point of Channel B input signal high-pass filter. 2, 23 DECB, DECA Decoupling Terminals for INHA/INLA and INHB/INLB. Connect to common via a large capacitance Figure 52 to complete input circuit. 3, 22, 29 COMB, COMA, COMR Input System Common Connection. Connect via low impedance to system common. 4, 5 ADJB, ADJA Temperature Compensation for Channel B and Channel A. An external voltage is connected to Figure 68 these pins to improve temperature drift. This voltage can be derived from VREF, that is, connect a resistor from VREF to ADJ[A, B] and another resistor from ADJ[A, B] to ground. The value of these resistors change as the frequency changes. 6 VREF General-Purpose Reference Voltage Output of 2.5 V. Figure 54 7 VLVL Reference Level Input for OUTP and OUTN. (Usually connected to VREF through a voltage divider Figure 58 or left open). 8, 17 CLPB, CLPA Channel B and Channel A Connection for Loop Filter Integration (Averaging) Capacitor. Connect a ground-referenced capacitor to this pin. A resistor can be connected in series with this capacitor to improve loop stability and response time. 9 VSTB The voltage applied to this pin sets the decibel value of the required RF input voltage to Channel Figure 56 B, which results in zero current flow in the loop integrating capacitor pin, CLPB. 10 OUTB Channel B Output of Error Amplifier. In measurement mode, normally connected directly to VSTB. Figure 57 11 FBKB Feedback Through 1 kΩ to the Negative Terminal of the Integrated Op Amp Driving OUTN. 12 OUTN Channel Differencing Op Amp Output. In measurement mode, normally connected directly to FBKB Figure 58 and follows the equation OUTN = OUTA − OUTB + VLVL. 13 OUTP Channel Differencing Op Amp Output. In measurement mode, normally connected directly to FBKA Figure 58 and follows the equation OUTP = OUTA − OUTB + VLVL. 14 FBKA Feedback Through 1kΩ to the Negative Terminal of the Integrated Op Amp Driving OUTP. 15 OUTA Channel A Output of Error Amplifier. In measurement mode, normally connected directly to VSTA. Figure 57 16 VSTA The voltage applied to this pin sets the decibel value of the required RF input voltage to Channel Figure 56 A that results in zero current flow in the loop integrating capacitor pin, CLPA. 18, 20 ACOM Analog Common for Channels A and B. Connect via low impedance to common. 21, 25, 32 VPSR, VPSA, VPSB Supply for the Input System of Channels A and B. Supply for the internal references. Connect to +5 V power supply. 19 TEMP Temperature Sensor Output. Figure 53 24 CHPA Connect to common via a capacitor to determine 3 dB point of Channel A input signal high-pass filter. 26, 27 INHA, INLA Channel A High and Low RF Signal Input Terminal. Figure 52 28 PWDN Disable/Enable Control Input. Apply logic high voltage to shut down the AD8364. Figure 55 30, 31 INLB, INHB Channel B Low and High RF Signal Input Terminal. Figure 52 Under Exposed Paddle The exposed paddle on the underside of the package must be soldered to a ground plane with Package low thermal and electrical characteristics. Rev. C | Page 8 of 44

Data Sheet AD8364 TYPICAL PERFORMANCE CHARACTERISTICS V = 5 V; T = +25°C, –40°C, +85°C; CLPA/B = OPEN. Colors: +25°C black, –40°C blue, +85°C red. P A 5 2.5 5 2.5 2.0 2.0 4 1.5 4 1.5 A OUTN OUTP 1.0 1.0 OUT[A, B] (V) 32 B 00–.05.5 ERROR (dB) OUT [P, N] (V) 23 00–.05.5 ERROR (dB) –1.0 –1.0 1 –1.5 1 –1.5 –2.0 –2.0 0–60 –50 –40INP–U3T0 AMP–L2IT0UDE –(1d0Bm) 0 10 20–2.5 05334-060 0–60 –50 –40INP–U3T0 AMP–L2IT0UDE –(1d0Bm) 0 10 20–2.5 05334-065 Figure 3. OUT[A, B] Voltage and Log Conformance vs. Input Amplitude at Figure 6. OUT[P, N] Voltage and Log Conformance vs. Input Amplitude at 450 MHz, Typical Device, ADJ[A, B] = 0 V, Sine Wave, Differential Drive, 450 MHz, with B Input Held at −25 dBm and A Input Swept, Typical Device, Balun = Macom ETK4-2T ADJ[A, B] = 0 V, Sine Wave, Differential Drive, Balun = Macom ETK4-2T (Note that the OUTP and OUTN Error Curves Overlap) 5 2.5 5 2.5 2.0 4 2.0 4 1.5 3 1.5 1.0 2 1.0 A, B] (V) 3 00.5 OR (dB) OUTN (V) 10 00.5 OR (dB) OUT[ 2 –0.5 ERR UTP– –1 –0.5 ERR O –1.0 –2 –1.0 1 –1.5 –3 –1.5 –2.0 –4 –2.0 0–60 –50 –40INP–U3T0 AMP–L2IT0UDE –(1d0Bm) 0 10 20–2.5 05334-075 –5–60 –50 –40INP–U3T0 AMP–L2IT0UDE –(1d0Bm) 0 10 20–2.5 05334-079 Figure 4. Distribution of OUT[A, B] Voltage and Error over Temperature After Figure 7. Distribution of [OUTP − OUTN] Voltage and Error over Temperature Ambient Normalization vs. Input Amplitude for at Least 30 Devices from After Ambient Normalization vs. Input Amplitude for at Least 30 Devices Multiple Lots, Frequency = 450 MHz, ADJ[A, B] = 0 V, Sine Wave, Differential from Multiple Lots, Frequency = 450 MHz, ADJ[A, B] = 0 V, Sine Wave, Drive, Balun = Macom ETK4-2T Differential Drive, PIN Ch. B = −25 dBm, Channel A Swept 0.20 0.15 4 +2DB 0.10 2 +1DB +15DEG B (V) 0.05 0 T OUTA–OU–0.050 ROR (dB) ––24 R+E1F0DEG–15DEG R E –0.10 –6 –10DEG –1DB ––00..2105 05334-070 –8 SPDIANEOESPRV LURIAIEATER,STF IRIE TONERYANL EAM AANNETPCDI PVEIN MLEDDI AETTICGDOOA N TTTTIOHTHEU EESTD HIRTNEEHEL OEFIAN F SHI NITAGPHNUEATL,. –2DB –60 –50 –40INP–U3T0 AMP–L2IT0UDE –(1d0Bm) 0 10 20 –10–40 –35 –30 –2R5F IN–P20UT A–T15 INL–A1 (0dBm–)5 0 5 10 05334-003 Figure 5. Distribution of [OUTA – OUTB] Voltage vs. Input Amplitude over Figure 8. Log Conformance vs. Input Amplitude at various Amplitude and Temperature for at Least 30 Devices from Multiple Lots, Frequency = 450 MHz, Phase Balance points, 450 MHz, Typical Device, ADJ[A, B] = 0 V, Sine Wave, ADJ[A, B] = 0 V, Sine Wave, Differential Drive, Balun = Macom ETK4-2T Differential Drive Rev. C | Page 9 of 44

AD8364 Data Sheet 5 2.5 2.0 5 2.5 4 B 1.5 2.0 1.0 4 1.5 A OUTN OUTP OUT[A, B] (V) 32 00–.05.5 ERROR (dB) OUT[P, N] (V) 32 100–..005.5 ERROR (dB) –1.0 –1.0 1 –1.5 1 –1.5 –2.0 –2.0 0–60 –50 –40INP–U3T0 AMP–L2IT0UDE –(1d0Bm) 0 10 20–2.5 05334-061 0–60 –50 –40INP–U3T0 AMP–L2IT0UDE –(1d0Bm) 0 10 20–2.5 05334-066 Figure 9. OUT[A, B] Voltage and Log Conformance vs. Input Amplitude at Figure 12. OUT[P, N] Voltage and Log Conformance vs. Input Amplitude at 880 MHz, Typical Device, ADJ[A, B] = 0.5 V, Sine Wave, Differential Drive, 880 MHz, with B Input Held at −25 dBm and A Input Swept, Typical Device, Balun = Mini-Circuits JTX-4-10T ADJ[A, B] = 0.5 V, Sine Wave, Differential Drive, Balun = JTX-4-10T (Note that the OUTP and OUTN Error Curves Overlap) 5 2.5 2.0 5 2.5 4 1.5 4 2.0 B 1.0 3 1.5 A OUT[A, B] (V) 32 00–.05.5 ERROR (dB) UTP–OUTN (V)–2011 100–..005.5 ERROR (dB) –1.0 O –2 –1.0 1 –1.5 –3 –1.5 –2.0 –4 –2.0 0–60 –50 –40INP–U3T0 AMP–L2IT0UDE –(1d0Bm) 0 10 20–2.5 05334-076 –5–60 –50 –40INPU–T3 0AMPL–I2T0UDE (–d1B0m) 0 10 20–2.5 05334-084 Figure 10. Distribution of OUT[A, B] Voltage and Error over Temperature Figure 13. Distribution of [OUTP − OUTN] Voltage and Error over After Ambient Normalization vs. Input Amplitude for at Least 15 Devices Temperature After Ambient Normalization vs. Input Amplitude for at Least from Multiple Lots, Frequency = 880 MHz, ADJ[A, B] = 0.5 V, Sine Wave, 15 Devices from Multiple Lots, Frequency = 880 MHz, ADJ[A, B] =0.5 V, Sine Differential Drive, Balun =JTX-4-10T Wave, Differential Drive, PIN Ch. B = −25 dBm, Channel A Swept 0.20 0.15 4 +20DEG 2 +30DEG 0.10 0 TB (V) 0.05 ––24 -15DEG REF U +1dB TA–O 0 R (dB) ––68 +10DEG OU–0.05 ERRO –10 +2dB –12 –0.10 –14 SERIES NAME INDICATES THE POLARITY -2dB ––00..2105 05334-071 ––1168 AATTOHNPEP DT L HRMIEEEAD FIGN STNLOIIGAT TNUINHADPELEU . IONTF,H A ATS HI NERP EDUFETEV,R IRAEETNLICOAENTDIV TEO -10DE-G1dB –60 –50 –40INP–U3T0 AMP–L2IT0UDE –(1d0Bm) 0 10 20 –20–40 –35 –30 –2R5F IN–P20UT A–T15 INL–A1 (0dBm–)5 0 5 10 05334-004 Figure 11. Distribution of [OUTA – OUTB] Voltage vs. Input Amplitude over Figure 14. Log Conformance vs. Input Amplitude at Various Amplitude and Temperature for at Least 15 Devices from Multiple Lots, Frequency = Phase Balance points, 880 MHz, Typical Device, ADJ[A, B] = 0.5 V, Sine Wave, 880 MHz, ADJ[A, B] = 0.5 V, Sine Wave, Differential Drive, Balun =JTX-4-10T Differential Drive Rev. C | Page 10 of 44

Data Sheet AD8364 5 2.5 5 2.5 2.0 2.0 4 1.5 4 1.5 A OUTN OUTP 1.0 1.0 A, B] (V) 3 00.5 OR (dB) P, N] (V) 3 00.5 OR (dB) OUT[ 2 –0.5 ERR OUT[ 2 –0.5 ERR –1.0 –1.0 1 B –1.5 1 –1.5 –2.0 –2.0 0–60 –50 –40INP–U3T0 AMP–L2IT0UDE –(1d0Bm) 0 10 20–2.5 05334-062 0–60 –50 –40INP–U3T0 AMP–L2IT0UDE –(1d0Bm) 0 10 20–2.5 05334-067 Figure 15. OUT[A, B] Voltage and Log Conformance vs. Input Amplitude at Figure 18. OUT[P, N] Voltage and Log Conformance vs. Input Amplitude at 1.88 GHz, Typical Device, TADJ[A, B]= 0.65 V, Sine Wave, Differential Drive, 1.88 GHz, with B Input Held at −25 dBm and A Input Swept, Typical Device, Balun = Murata LDB181G8820C-110 ADJ[A, B] = 0.65 V, Sine Wave, Differential Drive, Balun = Murata LDB181G8820C-110 (Note that the OUTP and OUTN Error Curves Overlap) 5 2.5 5 2.5 2.0 4 2.0 4 1.5 3 1.5 1.0 2 1.0 OUT[A ,B] (V) 23 00–.05.5 ERROR (dB) OUTP–OUTN (V)–110 00–.05.5 ERROR (dB) –1.0 –2 –1.0 1 –1.5 –3 –1.5 –2.0 –4 –2.0 0–60 –50 –40INPU–T3 0AMPL–I2T0UDE (–d1B0m) 0 10 20–2.5 05334-083 –5–60 –50 –40INPU–T3 0AMPL–I2T0UDE (–d1B0m) 0 10 20–2.5 05334-080 Figure 16. Distribution of OUT[A, B] Voltage and Error over Temperature Figure 19. Distribution of [OUTP − OUTN] Voltage and Error over After Ambient Normalization vs. Input Amplitude for at Least 20 Devices Temperature After Ambient Normalization vs. Input Amplitude for at Least from Multiple Lots, Frequency = 1.88 GHz, ADJ[A, B] = 0.65 V, Sine Wave, 20 Devices from Multiple Lots, Frequency = 1.88 GHz, ADJ[A, B] =0.65 V, Differential Drive, Balun = Murata LDB181G8820C-110 Sine Wave, Differential Drive, PIN Ch. B = −25 dBm, Channel A Swept 0.20 2 –2dB +20DEG 0 0.15 –2 REF 0.10 –1dB +30deg –4 OUTA–OUTB (V)–00..00055 ERROR (dB) ––1–608 –––3+120010dd0ded+eegg1egdgB +2dB –12 –0.10 –14 SERIES NAME INDICATES THE POLARITY AND MAGNITUDE OF THE DEVIATION ––00..1205–60 –50 –40INP–U3T0 AMP–L2IT0UDE –(1d0Bm) 0 10 2005334-072 ––1168–40ATTOHPEP T L–HRI3EEE5D FIN STLOIGA– TN3INHA0PELU .INT–,H 2AAR5S IF NR PIEN–UFP2TE0,UR RETEN LA–CAT1ET5 DIIVN TELO–A1 (0dBm–)5 0 5 10 05334-005 Figure 17. Distribution of [OUTA – OUTB] Voltage vs. Input Amplitude over Figure 20. Log Conformance vs. Input Amplitude at Various Amplitude and Temperature for at Least 20 Devices from Multiple Lots, Frequency = Phase Balance Points, 1.880 GHz, Typical Device, ADJ[A, B] = 0.65 V, 1.88 GHz, ADJ[A, B] = 0.65 V, Sine Wave, Differential Drive, Balun = Murata Sine Wave, Differential Drive LDB181G8820C-110 Rev. C | Page 11 of 44

AD8364 Data Sheet 5 2.5 2.0 5 2.5 4 1.5 2.0 B 1.0 4 1.5 OUTN OUTP OUT[A, B] (V) 32 00–.05.5 ERROR (dB) OUT[P, N] (V) 32 100–..005.5 ERROR (dB) –1.0 A –1.0 1 –1.5 1 –1.5 –2.0 –2.0 0–60 –50 –40INP–U3T0 AMP–L2IT0UDE –(1d0Bm) 0 10 20–2.5 05334-063 0–60 –50 –40INP–U3T0 AMP–L2IT0UDE –(1d0Bm) 0 10 20–2.5 05334-068 Figure 21. OUT[A, B] Voltage and Log Conformance vs. Input Amplitude at Figure 24. OUT[P, N] Voltage and Log Conformance vs. Input Amplitude at 2.14 GHz, Typical Device, ADJ[A, B] = 0.85 V, Sine Wave, Differential Drive, 2.14 GHz, with B Input Held at −25 dBm and A Input Swept, Typical Device, Balun = Murata LDB212G1020C-001 ADJ[A, B] = 0.85 V, Sine Wave, Differential Drive, Balun = Murata LDB212G1020C-001 (Note that the OUTP and OUTN Error Curves Overlap) 5 2.5 5 2.5 2.0 4 2.0 4 1.5 3 1.5 B 1.0 2 1.0 OUT[A, B] (V) 32 00–.05.5 ERROR (dB) UTP–OUTN (V)–110 00–.05.5 ERROR (dB) O –1.0 –2 –1.0 A 1 –1.5 –3 –1.5 –2.0 –4 –2.0 0–60 –50 –40INP–U3T0 AMP–L2IT0UDE –(1d0Bm) 0 10 20–2.5 05334-077 –5–60 –50 –40INP–U3T0 AMP–L2IT0UDE –(1d0Bm) 0 10 20–2.5 05334-081 Figure 22. Distribution of OUT[A, B] Voltage and Error over Temperature Figure 25. Distribution of [OUTP − OUTN] Voltage and Error over After Ambient Normalization vs. Input Amplitude for at Least 3 Devices from Temperature After Ambient Normalization vs. Input Amplitude for at Least Multiple Lots, Frequency = 2.14 GHz, ADJ[A, B] = 0.85 V, Sine Wave, 3 Devices from Multiple Lots, Frequency = 2.14 GHz, ADJ[A, B] = 0.85 V, Differential Drive, Balun = Murata LDB212G1020C-001 Sine Wave, Differential Drive, PIN Ch. B = −25 dBm, Channel A Swept 0.20 4 –2dB +30DEG 2 0.15 0 0.10 –2 +2dB –4 –1dB OUTA–OUTB (V)–00..00550 ERROR (dB) –––––11168024 R–1E+0+F2D10EdDGBEG +10DEG –16 –0.10 –18 SERIES NAME INDICATES THE POLARITY ––00..2105–60 –50 –40INP–U3T0 AMP–L2IT0UDE –(1d0Bm) 0 10 2005334-073 –––222024–40AATTOHNPEP DT L– HRMI3EEEA5D FIGN STNLOIIGA–T TNU3INHA0DPELEU . IONT–F,H 2A ATR5S HIF NER PI ENDU–FEP2TEV,0UR IRAETETN LAIC–OAT1ENT5 DIIVN TELO–A1 (0dBm–)5 0 ––23500DDEEGG10 05334-006 Figure 23. Distribution of [OUTA – OUTB] Voltage vs. Input Amplitude over Figure 26. Log Conformance vs. Input Amplitude at Various Amplitude and Temperature for 3 Devices from Multiple Lots, Frequency = 2.14 GHz, Phase Balance Points, 2.140 GHz, Typical Device, ADJ[A, B] = 0.85 V, Sine ADJ[A, B] = 0.85 V, Sine Wave, Differential Drive, Balun = Murata Wave, Differential Drive LDB212G1020C-001 Rev. C | Page 12 of 44

Data Sheet AD8364 5 2.5 5 2.5 2.0 2.0 4 1.5 4 1.5 OUTN OUTP 1.0 OUT[A, B] (V) 32 A 100–..005.5 ERROR (dB) OUT[P, N] (V) 32 00–.05.5 ERROR (dB) –1.0 –1.0 B 1 –1.5 1 –1.5 –2.0 –2.0 0–60 –50 –40INP–U3T0 AMP–L2IT0UDE –(1d0Bm) 0 10 20–2.5 05334-064 0–60 –50 –40INP–U3T0 AMP–L2IT0UDE –(1d0Bm) 0 10 20–2.5 05334-069 Figure 27. OUT[A, B] Voltage and Log Conformance vs. Input Amplitude at Figure 30. OUT[P, N] Voltage and Log Conformance vs. Input Amplitude at 2.5 GHz, Typical Device, ADJ[A, B] = 1.1 V, Sine Wave, Differential Drive, 2.5 GHz, with B Input Held at −25 dBm and A Input Swept, Typical Device, Balun = Murata LDB182G4520C-110 ADJ[A, B] = 1.1 V, Sine Wave, Differential Drive, Balun = Murata LDB182G4520C-110 (Note that the OUTP and OUTN Error Curves Overlap) 5 2.5 5 2.5 2.0 4 2.0 4 1.5 3 1.5 1.0 2 1.0 OUT[A, B] (V) 32 00–.05.5 ERROR (dB) UTP–OUTN (V)–110 00–.05.5 ERROR (dB) O –1.0 –2 –1.0 1 –1.5 –3 –1.5 –2.0 –4 –2.0 0–60 –50 –40INP–U3T0 AMP–L2IT0UDE –(1d0Bm) 0 10 20–2.5 05334-078 –5–60 –50 –40INP–U3T0 AMP–L2IT0UDE –(1d0Bm) 0 10 20–2.5 05334-082 Figure 28. Distribution of OUT[A, B] Voltage and Error over Temperature Figure 31. Distribution of [OUTP − OUTN] Voltage and Error over After Ambient Normalization vs. Input Amplitude for at Least 15 Devices Temperature After Ambient Normalization vs. Input Amplitude for at Least from Multiple Lots, Frequency = 2.5 GHz, ADJ[A, B] = 1.1 V, Sine Wave, 15 Devices from Multiple Lots, Frequency = 2.5 GHz, ADJ[A, B] =1.1 V, Sine Differential Drive, Balun = Murata LDB182G4520C-110 Wave, Differential Drive, PIN Ch. B = −25 dBm, Channel A Swept 0.20 4 –2dB 2 –1dB 0.15 0 –2 0.10 –4 OUTA–OUTB (V)–00..00055 ERROR (dB) ––––11–162084 +20DEG +30DEG –1R0ED+FE1G+0+1D2dEdBGB –20DEG –16 –0.10 –30DEG –18 ––00..2105–60 –50 –40INP–U3T0 AMP–L2IT0UDE –(1d0Bm) 0 10 2005334-074 –––222204–40SMTAHESAER GR I–INEEN3SIFHT5E UNARDA IENEM–NP EO3CU 0FEITN DT,D R HTICE–EOAL2 DRTAT5EHEFTVEIS VII ANRET–TH EP2TIEFO0UO NSP TT IO AGHA–LPENTA1P AI5 RNLILNIIL.TEALYD –A IATN1 NOP(0dDUBT,m–)5 0 5 10 05334-007 Figure 29. Distribution of [OUTA – OUTB] Voltage vs. Input Amplitude over Figure 32. Log Conformance vs. Input Amplitude at Various Amplitude and Temperature for at Least 15 Devices from Multiple Lots, Frequency = 2.5 GHz, Phase Balance Points, 2.500 GHz, Typical Device, ADJ[A, B] = 1.1 V, Sine ADJ[A, B] = 1.1 V, Sine Wave, Differential Drive, Balun = Murata Wave, Differential Drive LDB182G4520C-110 Rev. C | Page 13 of 44

AD8364 Data Sheet 2.0 2.0 1.5 1.5 ERROR CW ERROR QPSK 4dB CF 1.0 1.0 ERROR 256 QAM 8dB CF 0.5 0.5 B) B) d d R ( 0 R ( 0 RO RO ERROR CW R R E –0.5 E –0.5 ERROR 16C CDMA2K ERROR 3 CARRIER –1.0 9CH SR1 14dB CF –1.0 CDMA2K SR1 –1.5 ERROR 1C TM1-32 DPCH –1.5 ERROR 4 CARRIER 13dB CF WCDMA TM 1-64 –2.0–60–55–50–45–40–35–3P0IN– 2M5E–A2S0 (–d1B5m–1)0–5 0 5 10 15 20 05334-008 –2.0–60–55–50–45–40–35–3P0IN– 2M5E–A2S0 (–d1B5m–1)0–5 0 5 10 15 20 05334-010 Figure 33. Output Error from CW Linear Reference vs. Input Amplitude with Figure 35. Output Voltage and Error from CW Linear Reference vs. Input Different Waveforms, CW, QPSK, 256QAM, WCDMA 1-Carrier Test Model 1 Amplitude with Different Waveforms, CW, 3-Carrier CDMA2000 SR1, with 32 DPCH, CDMA2000, 16-Carrier, 9-Channel SR1 Frequency 2.140 GHz, 4-Carrier WCDMA, Test Model 1 with 64 DPCH, Frequency 2.140 GHz, CLP[A, B] = 1 µF, Balun = Murata LDB212G1020C-001 Balun = Murata LDB212G1020C-001 2 2.0 1.5 1.5 ECRDRMOAR2K F PWILDO 1T SCRA1RRIER 1.0 ERROR 2 1.0 ERROR CW CARRIER TM1-64 ERROR (dB) –00..055 ERREORRR O CRW 3 ECRARRORIRE R4 TM1-64 ERROR (dB) –00..505 EC9CRAHRR ORSIRRE 1RFW CDD M4A2K ECRDRMOAR2K F W 9CDH 1 SCRA1RRIER CARRIER TM1-64 ERROR FWD 16 –1.0 –1.0 ERROR FWD 4 CARR9ICEHR SCRD1MA2K CARRIER CDMA2K ERROR 1 9CH SR1 –1.5 CARRIER TM1-64 –1.5 ERROR FWD 3 CARRIER CDMA2K 9CH SR1 –2.0–60–55–50–45–40–35–3P0IN– 2M5E–A2S0 (–d1B5m–1)0–5 0 5 10 15 20 05334-009 –2.0–60–55–50–45–40–35–3P0IN– 2M5E–A2S0 (–d1B5m–1)0–5 0 5 10 15 20 05334-011 Figure 34. Error from CW Linear Reference vs. Input Amplitude with Different Figure 36. Error from CW Linear Reference vs. Input Amplitude with Different Waveforms, CW, WCDMA1, 2-, 3-, and 4-Carrier, Test Model 1 with 64 DPCH, Waveforms, CW, 1-Carrier CDMA2000 Pilot CH SR1, 1-Carrier CDMA2000 Frequency 2.14 GHz, Balun = Murata LDB212G1020C-001 9CH SR1, 3-Carrier CDMA2000 9CH SR1, 4-Carrier CDMA2000 9CH SR1 Frequency 16-Carrier CDMA2000 9CH SR1, Frequency 2.140 GHz, Balun = Murata LDB212G1020C-001 Rev. C | Page 14 of 44

Data Sheet AD8364 90 120 60 20 15 150 30 10 V) (mF 5 E 180 0 N VR 0 E I NG –5 A 210 330 H C –10 –15 240 300 270 05334-053 –20–40 –30 –20 –10 0 TE1M0PE2R0AT3U0RE 4(°0C)50 60 70 80 90 05334-014 Figure 37. Differential Input Impedance (S11) vs. Frequency; ZO = 50 Ω Figure 40. Change in VREF vs. Temperature for 11 Devices 14 TOTAL = 40 DEVICES RF INPUT =–60dBm 10000 450MHz, 0dB 450MHz,–40dB 12 450MHz,–20dB 10 T 8 V/Hz)1000 2140MHz, 0dB 2140MHz,–20dB 2140MHz,–40dB N n COU 6 OISE ( N T 4 TPU 100 U O 2 450MHz, RF OFF 20.486 2.488 2.490 2.492 2.494VR2E.4F9 (6V)2.498 2.500 2.502 2.504 2.506 05334-012 10100 1k450MHz F1R0EkQUENCY1 (0H0zk) 1M 10M 05334-057 Figure 38. Distribution of VREF for 40 Devices Figure 41. Noise Spectral Density of OUT[A, B]; CLP[A, B] = Open 14 TOTAL = 40 DEVICES RF INPUT =–60dBm 10000 12 0dB 10 Hz) 8 1000 NT nV/ –20dB COU 6 OISE ( –40dB N T 4 U TP 100 U O 2 RF OFF 0 0.617 0.619 0.62V1REF (V0).623 0.625 0.627 05334-013 10100 1k F1R0EkQUENCY1 (0H0zk) 1M 10M 05334-059 Figure 39. Distribution of TEMP Voltage for 40 Devices Figure 42. Noise Spectral Density of OUT[P, N]; CLP[A, B] = 0.1 µF, Frequency = 2140 MHz Rev. C | Page 15 of 44

AD8364 Data Sheet 10000 PWDN 0dB 2 Hz)1000 OUTA V/ CARRIER FREQUENCY 450MHz, SE (n –20dB CLPA =OPEN OI N 0dBm UTPUT 100 –40dB –20dBm VVVDABD == =50 VV5V O –40dBm B2 10100 1k F1R0EkRQFU OEFNFCY1 (0H0zk) 1M 10M 05334-058 REF2 1.0V 4.0µCCsHH24 51..00VV MA 4 C.0Hµ2s 6 225.1MVS/s 1.6ns/pt 05334-017 Figure 43. Noise Spectral Density of OUT[A, B]; CLP[A, B] = 0.1 µF, Figure 46. Output Response Using Power-Down Mode for Various RF Input Frequency = 2140 MHz Levels, Carrier Frequency 450 MHz, CLPA = Open PWDN RF BURST ENABLE 2 2 OUTA OUTA CARRIER FREQUENCY 450MHz, CARRIER FREQUENCY 450MHz, CLPA = OPEN CLPA =0.1µF 0dBm 0dBm –20dBm VVVDABD == =50 VV5V –20dBm VVVDABD == =50 VV5V –40dBm –40dBm B2 B2 REF2 1.0V 2.0µCCsHH24 51..00VV MA 2 C.0Hµ2s 1 .22.51GVS/s 800ps/pt 05334-015 REF2 1.0V 2.0µCCsHH24 51..00VV MA 2 C.0Hm2s 1 1.2.75VMS/s 800ns/pt 05334-018 Figure 44. Output Response to RF Burst Input for Various RF Input Levels, Figure 47. Output Response Using Power-Down Mode for Various RF Input Carrier Frequency 450 MHz, CLPA = Open Levels, Carrier Frequency 450 MHz, CLPA = 0.1 µF, CHPA = 10 nF RF BURST ENABLE 2 OUTA CARRIER FREQUENCY 450MHz, CLPA = 0.1µF 0dBm VDD = 5V –20dBm VA = 5V VB = 0V –40dBm B2 REF2 1.0V 2.0mCCsHH24 51..00VV MA 2 C.0Hµ2s 1 .22.51MVS/s 800ns/pt 05334-016 Figure 45. Output Response to RF Burst Input for Various RF Input Levels, Carrier Frequency 450 MHz, CLPA = 0.1 µF Rev. C | Page 16 of 44

Data Sheet AD8364 80 2.0 70 1.5 60 1.0 A) m T ( 50 ROR (dB) 0.50 Y CURREN 40 DECREVAPSWINDGN VINPCWRDENASING ER –0.5 PPL 30 U S 20 –1.0 10 –1.5 –2.0–60 –50 –40 –3R0F INP–U2T0 (dBm–1)0 0 10 20 05334-019 01.0 1.2 1.4 1.6VPWDN1 .(8V) 2.0 2.2 2.4 05334-020 Figure 48. Output Voltage Stability vs. VP (Supply Voltage) at 2.14 GHz, Figure 49. Supply Current vs. VPWDN When VP Varies by 10%,ADJ[A, B] =0.85 V, Sine Wave, Differential Drive, Murata LDB212G1020C-001 Rev. C | Page 17 of 44

AD8364 Data Sheet THEORY OF OPERATION The AD8364 is a dual-channel, 2.7 GHz, true rms responding HPA ECA OMA PSR COM EMP COM LPA detector with 60 dB measurement range. It incorporates two C D C V A T A C 24 23 22 21 20 19 18 17 AD8362 channels with shared reference circuitry (See the AD8362 datasheet for more information). Multiple enhancements have been TEMP VGA CONTROL made to the AD8362 cores to improve measurement accuracy. VPSA 25 16 VSTA Log-conformance peak-to-peak ripple has been reduced to <±0.2 INHA 26 CHANNEL A ISIG2 15 OUTA dB over the entire dynamic range. Temperature stability of the INLA 27 TruPwr™ ITGT2 14 FBKA rms output measurements provides <±0.5 dB error over the specified temperature range of −40°C to 85°C through proprietary PWDN 28 13 OUTP OUTA techniques. The use of well-matched channels offers extremely OUTB COMR 29 12 OUTN temperature-stable difference outputs, OUTP and OUTN. INLB 30 11 FBKB Given well-matched channels through IC integration, the rms CHANNEL B ISIG2 measurement outputs, OUTA and OUTB, drift in the same INHB 31 TruPwr™ 10 OUTB ITGT2 manner. With OUTP shorted to FBKA, the function at OUTP is VPSB 32 9 VSTB VGA OUTP = OUTA – OUTB + VLVL (1) CONTROL BIAS When OUTN is shorted to FBKB, the function at OUTN is 1 2 3 4 5 6 7 8 OUTN = OUTB – OUTA + VLVL (2) CHPB DECB COMB ADJB ADJA VREF VLVL CLPB 05334-001 OUTP and OUTN are insensitive to the common drift due to Figure 50. Block Diagram the difference cancellation of OUTA and OUTB. VIN INH[A, B] The AD8364 is a fully calibrated rms-to-dc converter capable of VGA x2 x2 operating on signals of a few hertz to 2.7 GHz or more. Unlike INL[A, B] VSIG CTOEMMPPEENRSAATUTIROEN ADJ[A, B] OFFSET logarithmic amplifiers, the AD8364 response is waveform CHP[A, B] NULLING GSET VREF×0.03 independent. The device accurately measures waveforms that OUTPUT have a high peak-to-rms ratio (crest factor). Figure 50 shows a VST[A, B] SINETTEPROFIANCTE BUFFER block diagram. VST[A, B] CF OUT[A, B] CLP [A, B] AAa Gw siiCnd gelol beo acpnh. daAwnsni dsehtlh oo wvf anthr iiena bA FlDeig g8ua3ri6en 45 a 1cmo, ntphslieifs iAtesrG o (CfV a Gl ohAoigp)h, cs poqemurafproreri mslaewas n ce VREF V2R.5EVF RBEAFNEDR EGNACPE EXTERCNLAPLF ACOM 05334-023 detectors, an amplitude target circuit, and an output driver. For Figure 51. Single-Channel Details a more detailed description of the functional blocks, see the AD8362 data sheet. Rev. C | Page 18 of 44

Data Sheet AD8364 SQUARE LAW DETECTOR AND AMPLITUDE RF INPUT INTERFACE TARGET The AD8364 RF inputs are connected as shown in Figure 52. The output of the VGA, called V , is applied to a wideband There are 100 Ω resistors connected between DEC[A, B] and SIG square law detector. The detector provides the true rms INH[A, B] and also between DEC[A, B] and INL[A, B]. The response of the RF input signal, independent of waveform, up DEC[A, B] pins have a dc level established as (7 × VPS[A, B] + to a crest factor of 6. The detector output, called ISQU, is a 55 × VBE)/30. With a 5 V supply, DEC[A, B] is approximately fluctuating current with positive mean value. The difference 2.5 V. between I and an internally generated current, I , is SQU TGT[A, B] Signal-coupling capacitors must be connected from the input integrated by C and a capacitor attached to CLP[A, B]. CF is F signal to the INH[A, B] and INL[A, B] pins. The high-pass the on-chip 25 pF filter capacitor. CLP[A, B] can be used to corner is arbitrarily increase the averaging time while trading off f = 1/(2 × π × 100 × C) (8) response time. When the AGC loop is at equilibrium, high-pass A decoupling capacitor must be connected from DEC[A, B] to MEAN(I ) = I (3) SQU TGT[A, B] ground to attenuate any signal at the midpoint. A 100 pF and This equilibrium occurs only when 0.1 µF cap from DEC[A, B] to ground are recommended, with a MEAN(V 2) = V 2 (4) 1 nF coupling capacitor such that signals greater than 1.6 MHz SIG TGT[A, B] can be measured. For coupling signals less than 1.6 MHz, where V is an attenuated version of the VREF voltage. TGT 100 × C for the DEC[A, B] capacitor generally can be used. coupling Because the square law detectors are electrically identical and DEC[A, B] VSP[A, B] well matched, process and temperature dependent variations are effectively cancelled. COM[A, B] INH[A, B] By forcing the above identity through varying the VGA setpoint, it is apparent that 100Ω RMS(V ) = √(MEAN(V 2)) = √(V 2) = V (5) VIN VGA SIG SIG TGT TGT 100Ω Substituting the value of V , we have SIG INL[A, B] RMS(G0 × RF exp(−VST[A, B]/V )) = V (6) IN GNS TGT VSP[A, B] VSP[A, B] When connected as a measurement device VST[A, B] = OUT[A, B]. Solving for OUT[A, B] as a function of RF , OUT[A, B] = VSLOPE × Log10(RMS(RFIN)/VZ) IN (7) COM[A, B] COM[A, B] 05334-024 Figure 52. AD8364 RF Inputs where V is laser trimmed to 1 V/decade (or 50 mV/dB) at SLOPE 100 MHz. V is the intercept voltage, since Log 10(1) = 0 when OFFSET COMPENSATION Z RMS(RF ) = V . If desired, the effective value of V may be IN Z SLOPE An offset-nulling loop is used to address small dc offsets in the altered by using a resistor divider from OUT[A, B] to drive VGA. The high-pass corner frequency of this loop is internally VST[A, B]. The intercept, V , is also laser trimmed to 180 µV Z preset to about 1 MHz using an on-chip capacitor of 25 pF (−62 dBm, referred to 50 Ω) with a CW signal at 100 MHz. This (1/(2 × 5K × 25 pF)), which is sufficiently low for most HF value is extrapolated, because OUT[A, B] do not respond to input applications. The high-pass corner can be reduced by a of less than approximately −55 dBm with differential drive. capacitor from CHP[A, B] to ground. The input offset voltage In most applications, the AGC loop is closed through the varies depending on the actual gain at which the VGA is setpoint interface, VST[A, B]. In measurement mode, OUT[A, B] operating and, thus, on the input signal amplitude. When an are tied to VST[A, B], respectively. In controller mode, a control excessively large value of CHP[A, B] is used, the offset voltage is applied to VST[A, B]. Pins OUT[A, B] drive the control correction process may lag the more rapid changes in the VGA input of a system. The RF feedback signal to the input pins is gain, which may increase the time required for the loop to fully forced to have an rms value determined by VSTA or VSTB. settle for a given steady input amplitude. Rev. C | Page 19 of 44

AD8364 Data Sheet TEMPERATURE SENSOR INTERFACE POWER-DOWN INTERFACE The AD8364 provides a temperature sensor output capable of The operating and stand-by currents for the AD8364 at 25°C are driving about 1.6 mA. A 330 Ω-equivalent internal resistance is approximately 70 mA and 500 µA, respectively. The PWDN pin connected from TEMP to COMR to provide current sink is connected to an internal resistor divider made with two 42 kΩ capability. The temperature scaling factor of the output voltage is resistors. The divider voltage is applied to the base of an NPN approximately 2 mV/°C. The typical absolute voltage at 25°C is transistor to force a power-down condition when the device is about 620 mV. active. Typically when PWDN is pulled greater than 2 V, the VPSR device is powered down. Figure 46 and Figure 47 show typical response times for various RF input levels. The output reaches INTERNAL to within 0.1 dB of the steady-state value in about 1.6 µs; the VPTAT TEMP reference voltage is available to full accuracy in a much shorter 4kΩ time. This wake-up response vary depending on the input 350Ω coupling means and the capacitances CDEC[A, B], CHP[A, B], 1kΩ and CLP[A, B]. COMR 05334-025 PWDN 42kΩ PSOIGWNEARL DOWN Figure 53. TEMP Interface Simplified Schematic 42kΩ VREF INTERFACE An internal voltage reference is provided to the user at Pin VREF. COMR 05334-027 The VREF voltage is a temperature stable 2.5 V reference that Figure 55. PWDN Interface Simplified Schematic can drive about 18 mA. An 830 Ω equivalent internal resistance VST[A, B] INTERFACE is connected from VREF to ACOM for 3 mA sink capability. VPSR The VST[A, B] interface has a high input impedance of 72 kΩ. The voltage at VST[A, B] is converted to an internal current INTERNAL VOLTAGE used to steer the VGA gain. The VGA attenuation control is VREF set to 20 dB/V. 9kΩ GAIN ADJUST 900Ω 1.35µA/dB 1.465kΩ VST[A, B] 36kΩ COMR 05334-026 36kΩ Figure 54. VREF Interface Simplified Schematic 18.5kΩ ACOM 05334-028 Figure 56. VST[A, B] Interface Simplified Schematic Rev. C | Page 20 of 44

Data Sheet AD8364 OUT[A, B, P, N] OUTPUTS VLVL VPSR The output drivers used in the AD8364 are different than the 1kΩ 1kΩ OUTA output stage on the AD8362. The AD8364 incorporates rail-to- 1kΩ OUTP rail output drivers with pull-up and pull-down capabilities. The OUTB output noise is approximately 40 nV/√Hz at 100 kHz. OUT[A, 1kΩ B, P, N] can source and sink up to 70 mA. There is also an internal FBKA COMR load from both OUTA and OUTB to ACOM of 2.5 kΩ. VLVL VPSR VPS[A, B] 1kΩ 1kΩ OUTB INTERNAL 1kΩ OUTN VOLTAGE OUTA OUT[A, B] 2kΩ FBK1BkΩCOMR 05334-030 COM[A, B] 500Ω Figure 58. OUT[P, N] Interface Simplified Schematic ACOM 05334-029 Figure 57. OUT[A, B] Interface Simplified Schematic Rev. C | Page 21 of 44

AD8364 Data Sheet MEASUREMENT CHANNEL DIFFERENCE OUTPUT CONTROLLER MODE USING OUT[P, N] The channel difference outputs can be used for controlling a The AD8364 incorporates two operational amplifiers with rail- feedback loop to the AD8364 RF inputs. A capacitor connected to-rail output capability to provide a channel difference output. between FBKA and OUTP forms an integrator, keeping in mind As in the case of the output drivers for OUT[A, B], the output that the on-chip 1 kΩ feedback resistor forms a zero. (The value stages have the capability of driving 70 mA. The output noise is of the on-chip resistors can vary as much as ±20% with manufac- approximately 40 nV/√Hz at 100 kHz. OUTA and OUTB are turing process variation.) If Channel A is driven and Channel B internally connected through 1 kΩ resistors to the inputs of each has a feedback loop from OUTP through a PA, then OUTP operational amplifier. The pin VLVL is connected to the positive integrates to a voltage value such that terminal of both operational amplifiers through 1 kΩ resistors to OUTB = (OUTA + VLVL)/2 (11) provide level shifting. The negative feedback terminal is also made The output value from OUTN may or may not be useful. It is available through a 1 kΩ resistor. The input impedance of VLVL given by is 1 kΩ and FBK[A, B] is 2 kΩ. See Figure 59 for the connections of these pins. OUTN = 0 V (12) HPA ECA OMA PSR COM EMP COM LPA For VLVL < OUTA/3, C D C V A T A C Otherwise, 24 23 22 21 20 19 18 17 TEMP OUTN = (3 × VLVL – OUTA)/2 (13) VGA VPSA 25 CONTROL 16 VSTA If VLVL is connected to OUTA, then OUTB is forced to equal INHA 26 CHANNEL A ISIG2 15 OUTA OUTA through the feedback loop. This flexibility provides the INLA 27 TruPwr™ ITGT2 14 FBKA ugisveern w pitohw tehre l ecvaepla abnildit yfr teoq umeenacsyu wreh oilnee f ochrcainnnge tlh oep oetrhaetirn cgh aatn an el PWDN 28 13 OUTP to a desired power level at another frequency. ADJA and ADJB OUTA OUTB must be set to different voltage levels to reduce the temperature COMR 29 12 OUTN drift of the output measurement. The temperature drift will be INLB 30 11 FBKB CHANNEL B ISIG2 statistical sum of the drift from Channel A and Channel B. As INHB 31 TruPwr™ 10 OUTB stated before, VLVL can be used to force the slaved channel to ITGT2 operate at a different power than the other channel. If the two VPSB 32 9 VSTB VGA channels are forced to operate at different power levels, then CONTROL BIAS some static offset occurs due to voltage drops across metal 1 2 3 4 5 6 7 8 wiring in the IC. CHPB DECB COMB ADJB ADJA VREF VLVL CLPB 05334-001 If an inversion is necessary in the feedback loop, OUTN can be Figure 59. Operational Amplifier Connections (All Resistors are 1 kΩ ± 20%) used as the integrator by placing a capacitor between OUTN and OUTP. This changes the output equation for OUTB and If OUTP is connected to FBKA, then OUTP is given as OUTP to OUTP = OUTA – OUTB + VLVL (9) OUTB = 2 × OUTA − VLVL (14) If OUTN is connected to FBKB, then OUTN is given as For VLVL < OUTA/2, OUTN = OUTB – OUTA + VLVL (10) OUTN = 0 V (15) In this configuration, all four measurements, OUT[A, B, P, N], Otherwise, are made available simultaneously. A differential output can be taken from OUTP − OUTN, and VLVL can be used to adjust OUTN = 2 × VLVL – OUTA (16) the common-mode level for an ADC connection. The previous equations are valid when Channel A is driven and Channel B is slaved through a feedback loop. When Channel B is driven and Channel A is slaved, the above equations can be altered by changing OUTB to OUTA and OUTN to OUTP. Rev. C | Page 22 of 44

Data Sheet AD8364 RF MEASUREMENT MODE BASIC CONNECTIONS The device is placed in measurement mode by connecting OUTA and/or OUTB to VSTA and/or VSTB, respectively. This closes the The AD8364 requires a single supply of nominally 5 V. The AGC loop within the device with OUT[A, B] representing the supply is connected to the three supply pins, VPSA, VPSB, and VGA control voltage, which is required to present the correct VPSR. Each pin must be decoupled using the two capacitors rms voltage at the input of the internal square law detector. with values equal or similar to those shown in Figure 60. These capacitors must provide a low impedance over the full frequency As the input signal to Channel A and Channel B are swept over range of the input, and they must be placed as close as possible to their nominal input dynamic range of +10 dBm to −50 dBm, the VPOS pins. Two different capacitors are used in parallel to the output swings from 0 V to 3.5 V. The voltages OUTA and provide a broadband ac short to ground. OUTB are also internally applied to a difference amplifier with a gain of two. So as the dB difference between INA and INB ranges The input signals are applied to the input differentially. The RF from approximately −30 dB to +30 dB, the difference voltage on inputs of the AD8364 have a differential input impedance of 200 Ω. OUTP and OUTN swings from −3.5 V to +3.5 V. Input differences When the AD8364 RF inputs are driven from a 50 Ω source, a larger than ±30 dB can be measured as long as the absolute input 4:1 balun transformer is recommended to provide the necessary level at INA and INB are within their nominal ranges of +10 dBm impedance transformation. The inputs can be driven single-ended, to −50 dBm. However, measurement of large differences between however, this reduces the measurement range of the rms detectors INA and INB are affected by on-chip signal leakage (see the (see the Single-Ended Input Operation section). Channel Isolation section). The common-mode level of OUTP Table 4. Baluns Used to Characterize the AD8364 and OUTN is set by the voltage applied to VLVL. These output Frequency Balun can be easily biased up to a common-mode voltage of 2.5 V by 450 MHz MIA-COM ETK4-2T connecting VREF to VLVL. As the gain range is swept, OUTP 880 MHz Mini-Circuits JTX-4-10T swings from approximately 1 V to 4.5 V and OUTN swings 1880 MHz Murata LDB181G8820C-110 from 4.5 V to 1 V. 2140 MHz Murata LDB212G1020C-001 2500 MHz Murata LDB182G4520C-110 Rev. C | Page 23 of 44

AD8364 Data Sheet VPOS R24 0Ω C23 C13 100pF R5 0.1µF 0Ω VPOS C8 C12 0.1µF 100pF C14 0.C1µ1F1 CC99 0.1µF 00..11µµFF 24 23 22 21 20 19 18 17 C10 100pF CHPADECACOMAVPSRACOMTEMPACOMCLPA 25 VPSA VSTA 16 C5 C7 0.1µF T2 0.1µF INPA 26 INHA OUTA 15 OUTA 1:4 27 INLA FBKA 14 C6 0.1µF AD8364ACPZ 28 PWDN OUTP 13 OUTP 29 COMR OUTN 12 OUTN C4 T1 0.1µF 30 INLB FBKB 11 1:4 INPB 31 INHB EXPOSED PADDLE OUTB 10 OUTB C2 C3 0.1µF 0.1µF 32 VPSB VSTB 9 CHPBDECBCOMBADJB ADJA VREF VLVL CLPB C20 1 2 3 4 5 6 7 8 100pF C22 C19 C16 0.1µF R201 R181 0.1µF 0.1µF C21 0.1µF C1 C24 0.1µF 100pF R191 R171 VPOS 1SEE TEXT. 05334-031 Figure 60. Basic Connections for Operation in Measurement Mode CONTROLLER MODE BASIC CONNECTIONS Some additional attenuation may be required to set the maximum input signal at the AD8364 to be equal to the recommended In addition to being a measurement device, the AD8364 can maximum input level for optimum linearity and temperature also be configured to measure and control rms signal levels. The stability at the frequency of operation. AD8364 has two controller modes. Each of the two rms log detectors can be separately configured to set and control the VSTA and OUTA are no longer shorted together. OUTA now output power level of a variable gain amplifier (VGA) or variable provides a bias or gain control voltage to the VGA. The gain voltage attenuator (VVA). Alternatively, the two rms log detectors control sense of the VGA must be negative and monotonic, that can be configured to measure and control the gain of an is, increasing voltage tends to decrease gain. However, the gain amplifier or signal chain. control transfer function of the device does not need to be well controlled or particularly linear. If the gain control sense of the Automatic Power Control VGA is positive, an inverting operational amplifier circuit with Figure 61 shows how the device must be reconfigured to control a dc offset shift can be used between the AD8364 and the VGA output power. to keep the gain control voltage in the 0 V to 5 V range. The RF input to the device is configured as before. A directional VSTA becomes the setpoint input to the system. This can be coupler taps off some of the power being generated by the VGA driven by a DAC, as shown in Figure 61, if the output power is (typically a 10 dB to 20 dB coupler is used). A power splitter can expected to vary, or it can simply be driven by a stable reference be used instead of a directional coupler if there are no concerns voltage if constant output power is required. This DAC must about reflected energy from the next stage in the signal chain. have an output swing that covers the 0 V to 3.5 V range. Rev. C | Page 24 of 44

Data Sheet AD8364 When VSTA is set to a particular value, the AD8364 compares Automatic Gain Control this value to the equivalent input power present at the RF input. Figure 62 shows how the AD8364 can be connected to provide If these two values do not match, OUTA increases or decreases automatic gain control to an amplifier or signal chain. in an effort to balance the system. The dominant pole of the Additional pins are omitted for clarity. In this configuration, error amplifier/integrator circuit that drives OUTA is set by the both rms detectors are connected in measurement mode with capacitance on Pin CLPA; some experimentation may be necessary appropriate filtering being used on CLP[A, B] to effect a valid to choose the right value for this capacitor. In general, CLPA must rms computation on both channels. OUTA, however, is also be chosen to provide stable loop operation for the complete output connected to the VLVL pin of the on-board difference amplifier. power control range. If the slope (in dB/V) of the gain control Also, the OUTP output of the difference amplifier drives a transfer function of the VGA is not constant, CLPA must be chosen variable gain element (either VVA or VGA) and is connected to guarantee a stable loop when the gain control slope is at the back to the FBKA input via a capacitor so that it is operating as maximum. On the other hand, CLPA must provide adequate an integrator. averaging to the internal low range squaring detector so that the Assume that OUTA is much bigger than OUTB. Because OUTA rms computation is valid. Larger values of CLPA tend to make also drives VLVL, this voltage is also present on the noninverting the loop less responsive. input of the operational amplifier driving OUTP. This results in The relationship between VSTA and the RF input follows from a net current flow from OUTP through the integrating the measurement mode behavior of the device. For example, capacitor into the FBKA input. This results in the voltage on from Figure 9, which shows the measurement mode transfer OUTP increasing. If the gain control transfer function of the function at 880 MHz, it can be seen that an input power of VVA/VGA is positive, this increases the gain, which in turn −10 dBm yields an output voltage of 2.5 V. Therefore, in increases the input signal to INHB. The output voltage on the controller mode, VSTA must be set to 2.5 V, which results in an integrator continues to increase until the power on the two input power of −10 dBm to the AD8364. input channels is equal, resulting in a signal chain gain of unity. If a gain other than 0 dB is required, an attenuator can be used VGA OR VVA in one of the RF paths, as shown in Figure 62. Alternatively, PIN (DOEUCTRPUEAT SPEOSW AESR POUT power splitters or directional couplers of different coupling VAPC INCREASES) factors can be used. Another convenient option is to apply a VAPC voltage on VLVL other than OUTA. Refer to Equation 11 and ATTENUATOR the Controller Mode section for more detail. (0V TO 4.9V AVAILABLE SWING) If the VGA/VVA has a negative gain control sense, the OUTN OUTA C7 C5 output of the difference amplifier can be used with the 0.1µF T2 0.1µF integrating capacitor tied back to FBKB. INHA AD8364 1:4 The choice of the integrating capacitor affects the response time INLA of the AGC loop. Small values give a faster response time but C6 VSTA INHA 0.1µF can result in instability, whereas larger values reduce the response time. Note that in this mode, the capacitors on CLPA and CLPB, DAC 0V TO 3.5V SEE TEXT 05334-032 wanhdic ahls poe arfffoercmt t thhee l ormops raevseproagnisneg t ifmunec. t ion, must still be used Figure 61. Operation in Controller Mode for Automatic Power Control Rev. C | Page 25 of 44

AD8364 Data Sheet DIRECTIONAL DIRECTIONAL OR OR POWER SPLITTER VGA/VVA POWER SPLITTER CLPF VGA IERR C5 T1 C7 CONTROL VSTA 0.1µF 1:4 0.1µF INHA CHANNEL A ISIG2 OUTA 1:4 INLA TruPwr™ ITGT2 FBKA CINT ATTENUATOR C6 0.1µF OUTP AD8364 OUTA DIFF OUT + OUTB OUTN T2 C4 1:4 0.1µF FBKB 1:4 INLB CHANNEL B ISIG2 OUTB INHB TruPwr™ C2 C3 ITGT2 0.1µF 0.1µF VGA VSTB CONTROL VLVL CLPF 05334-054 Figure 62. Operation in Controller Mode for Automatic Gain Control Rev. C | Page 26 of 44

Data Sheet AD8364 CONSTANT OUTPUT POWER OPERATION The AD8364 is able to maintain a fixed output power from the AD8367 even though the input power is changing. The input In controller mode, the AD8364 can be used to hold the output power can vary over a 36 dB range, while the output power power stable over a broad temperature/input power range. This remains constant and the drift over temperature is less than 0.2 dB can be very useful in systems, such as a transmit module driving a high power amplifier (HPA) in a base station, that connect Figure 64 shows a constant output power circuit using the multiple power sensitive modules together. In applications AD8364 and the AD8367 VGA. The input power was swept where stable output power is needed, the RF output is from +3 dBm to −35 dBm, the output power was measured at connected to Channel B using a coupler, VLVL is connected to multiple temperatures between −40°C and +85°C, and the VREF, VSTB is used to set the power to a particular level and power changed less than ±0.07 dB (Figure 63). can be controlled using a DAC or a dc voltage, OUTB is used to –15.0 drive the gain control of an amplifier that is capable of negative- –15.1 gain law conformance (such as the AD8367), and ADJB (set at POUT +25°C POUT +85°C –15.2 0 V in this example) is used to control the temperature drift. –15.3 Using this configuration, the RF input signal is down converted to 80 MHz using the AD8343 and amplified using the AD8367. m)–15.4 –20°C B The signal then splits and part of it is fed back to the AD8364 d–15.5 (T through Channel B, and a setpoint voltage is applied to VSTB. OU–15.6 P This voltage corresponds to a particular power level, which is POUT–40°C –15.7 determined by the slope of the AD8364. The power detected at –15.8 the input of the AD8364 is compared with this voltage, and the voltage present at OUTB is adjusted up or down to match the –15.9 sOeUtpToBin vt ovlotlatgaeg eis, wcoitnhn tehcete pdo twoe trh de egtaeicnte cdo nontr othl eo fi nthpeu tA. TDh8e3 67 –16.0–40 –35 –30 –25 –P2IN0 (dB–m15) –10 –5 0 5 05334-033 VGA and increases or decreases the gain of the AD8367, Figure 63. AD8364 Constant Power Performance resulting in the output power being held constant, regardless of variations in the input power. Rev. C | Page 27 of 44

AD8364 Data Sheet RFIN AD8343 IFOUT 1880MHz 0 0 80MHz AD8367 107 90MHz LPF 11dB COUPLING MODE SEL 0V TO 1.2V VPOS R24 0 R23 0 C23 C13 C14 100pF R5 0.1F 0.1F 0 C11 C8 C12 TEMP R6 0.1F 0.1F 100pF SENSOR 0 R4 0 J4 CC99 C15 00..11FF 0.1F C10 24 23 22 21 20 19 18 17 100pF CHPA DECA COMA VPSR ACOM TEMP ACOM CLPA T2 LDB181G8820C-110 25 VPSA VSTA 16 C5 C7 R9 INPA 0.1F 0.1F 0 J3 26 INHA OUTA 15 1:4 OPERN3 R010 27 INLA FBKA 14 C6 PWDN A 0.1F AD8364ACPZ J2 SW1 28 PWDN OUTP 13 B R2 10k VPOS 29 COMR OUTN 12 C4 EXPOSED PADDLE R11 0.1F 0 30 INLB FBKB 11 R1 INPB 1:4 OPEN J1 31 INHB OUTB 10 C3 0.C15F T1 0.1F R12 ETK4-2T 32 VPSB VSTB 9 0 R13 R14 VSTB CHPB DECB COMB ADJB ADJA VREF VLVL CLPB OPEN OPEN 0.4V TO R21 C10200pF 1 2 3 4 5 6 7 8 3.4V 0 C0.212F R020 R018 0C.119F C21 C18 C17 R15 C16 0.1F OPEN 0.1F 0 0.1F C1 C24 0.705V R16 0.1F 100pF OPEN VPOS TP1 COMM TP2 VREF 05334-055 Figure 64. Constant Output Power Circuit Rev. C | Page 28 of 44

Data Sheet AD8364 GAIN-STABLE TRANSMITTER/RECEIVER Because the difference in the coupler values is 8.32 dB, a fixed gain of −8.32 dB is expected. In practice, there is a gain of −13 dB. There are many applications for a transmitter or receiver with a This is caused by the intercept shift of the AD8364 due to the highly accurate temperature-stable gain. For example, a multi- frequency response, the insertion loss of the output coupler, and carrier base station high power amplifier (HPA) using digital the insertion loss differences of the baluns used on the input of predistortion has a power detector and an auxiliary receiver. The the AD8364. In this configuration, approximately 33 dB of power detector and all parts associated with it can be removed if control range with 0.5 dB drift over temperature is obtained. the auxiliary receiver has a highly accurate temperature-stable gain. With a set gain receiver, the ADC on the auxiliary receiver Figure 66 shows a gain-stable receiver amplifier circuit using can not only determine the overall power being transmitted but can the AD8364 to control an ADL5330 VGA and the AD8343 also determine the power in each carrier for a multicarrier HPA. mixer. The input power was swept from +3 dBm to −35 dBm, the output power was measured, and the gain was calculated at In controller mode, the AD8364 can be used to hold the multiple temperatures between −40°C and +85°C. Note that the receiver gain constant over a broad input power/temperature gain changed less than ±0.45 dB over this range (Figure 65). range. In this application, the difference outputs are used to Most of the gain change was caused by performance differences hold the receiver gain constant. at different frequencies. The RF input is connected to INPA, using a 19.1 dB coupler, –11.0 and the down converted output from our signal chain is connected to INPB, using a 10.78 dB coupler. A 0.1 µF capacitor is connected –11.5 between FBKA and OUTP, forming an integrator. OUTA is connected to VLVL, forcing OUTP to adjust the VGA so that –12.0 OUTB is equal to OUTA. The circuit gain is set by the difference in –40°C tOhUe TcoPu ipsl iunsge dv atlou desr iovfe tthhee ignapiunt caonndt rooul topfu tth ceo AupDleLr5s3. 3A0s bnyo ted, AIN (dB)–12.5 +25°C G adjusting the gain up or down as needed to force the power at –13.0 the AD8364 inputs to be equal in amplitude. Since operating at +85°C different frequencies, the appropriate voltages on the ADJ[A, B] –13.5 pins must be supplied. Because INPA is operating at 1880 MHz, ADJA is set to 0.75 V. Likewise, because INPB is operating at 80 MHz, ADJB is set to 0 V. –14.0–40 –35 –30 –25 –P2IN0 (dB–m15) –10 –5 0 5 05334-034 Figure 65. Performance of Gain-Stable Receiver Rev. C | Page 29 of 44

AD8364 Data Sheet 18R80FMINHz 0 0 AD8343 0 0 8IF0OMUHTz ADL5330 454 107 90MHz 19dB LPF 11dB COUPLING COUPLING MODE SEL 0V TO 1.2V VPOS R24 0 R23 0 C23 C13 C14 100pF R5 0.1F 0.1F 0 C11 C8 C12 TEMP R6 0.1F 0.1F 100pF SENSOR 0 R4 0 J4 CC99 C15 00..11FF 0.1F C10 24 23 22 21 20 19 18 17 100pF CHPA DECA COMA VPSR ACOM TEMP ACOM CLPA T2 LDB181G8820C-110 25 VPSA VSTA 16 C5 C7 R9 0.1F 0.1F 0 26 INHA OUTA 15 INJP3A 1:4 OPERN3 0.1F 27 INLA FBKA 14 C6 PWDN A 0.1F AD8364 J2 SW1 DIFF OUT + 28 PWDN OUTP 13 B R2 10k VPOS 29 COMR OUTN 12 C4 R11 0.1F 0 30 INLB FBKB 11 R1 INPB 1:4 OPEN J1 31 INHB OUTB 10 C3 0.C15F T1 0.1F R12 ETK4-2T 32 VPSB VSTB 9 0 R13 R14 CHPB DECB COMB ADJB ADJA VREF VLVL CLPB OPEN OPEN C20 R21 100pF 1 2 3 4 5 6 7 8 0 C0.212F R020 R018 0C.119F C21 C18 C17 R15 C16 0.1F OPEN 0.1F 0 0.1F 0.75V C1 C24 R16 0.1F 100pF OPEN VPOS TP1 COMM TP2 VREF 05334-056 Figure 66. Gain-Stable Receiver Circuit Rev. C | Page 30 of 44

Data Sheet AD8364 TEMPERATURE COMPENSATION ADJUSTMENT VPSR The AD8364 has a highly stable measurement output with INTERNAL CURRENT respect to temperature. However, when the RF inputs exceed a frequency of 600 MHz, the output temperature drift must be compensated for using ADJ[A, B] for optimal performance. Proprietary techniques are used to compensate for the temper- ADJ[A, B] VREF/2 afrteuqreu ednrcifyt,. bTahlue na bcshooliuctee, vaanldu ec iorfc ucoitm bpoeanrdsa mtioatne rviaarl.i eTsa wblieth 5 COMR IADJ[A, B] 05334-036 shows recommended voltages for ADJ[A, B] to maintain a Figure 68. ADJ[A, B] Interface Simplified Schematic temperature drift error of typically ±0.5 dB or better over the DEVICE CALIBRATION AND ERROR CALCULATION entire rated temperature range with the recommended baluns. The measured transfer function of the AD8364 at 2.14 GHz is Table 5. Recommended Voltages for ADJ[A, B] shown in Figure 69. The figure shows plots of both output Frequency (MHz) 450 880 1880 2140 2500 voltage vs. input power and calculated error vs. input power. As ADJ[A, B] (V) 0 0.5 0.65 0.85 1.10 the input power varies from −50 dBm to 0 dBm, the output voltage varies from 0.4 V to about 2.8 V. Compensating the device for temperature drift using ADJ[A, B] allows for great flexibility. If the user requires minimum temper- ature drift at a given input power or subset of the dynamic range, 3.50 2.0 BLUE =–40°C the ADJ[A, B] voltage can be swept while monitoring OUT[A, B] 3.15 GREEN = +25°C 1.6 RED = +85°C over temperature. Figure 67 shows the result of such an exercise ERROR CW–40°C 2.80 1.2 with a broadband balun, one that is not the recommended balun 2.45 0.8 at 1880 MHz. The value of ADJ[A, B] where the output has V) ERROR CW +25°C minimum movement (approximately 0.77 V for the example in (OUT 2.10 ERROR CW +85°C 0.4 dB) Figure 67) is the recommended voltage for ADJ[A, B] to achieve V 1.75 0 R ( VOUT2 RO minimum temperature drift at a given power and frequency. 1.40 –0.4 R E 1.70 1.05 –0.8 0.70 –1.2 +85°C VOUT1 1.65 0.35 –1.6 V) 1.60 ++6455°°CC I–0N6T0ER–C5E5PT–50P–IN415 –40–35–30P–IN225 –P2IN0 M–E15AS– 1(d0Bm–5) 0 5 10–2.0 04862-037 TA ( 1.55 +25°C Figure 69. Transfer Function at 2.14 GHz. U O Because slope and intercept vary from device to device, board- 1.50 +10°C level calibration must be performed to achieve high accuracy. –20°C The equation for output voltage can be written as 1.45 V = Slope × (P − Intercept) OUT IN –40°C 1.400 0.25 0.50 0.75 1.00AD1J.A25 (V)1.50 1.75 2.00 2.25 2.50 05334-035 Wchahnergee Sinlo ppeo wise trh (ed cBh)a, nagned iInn toeurctpeputt ivso tlhtaeg cea dlciuvildateedd bpyo twheer at Figure 67. OUTA vs. ADJA over Temp. Pin = −30 dBm, 1.9 GHz which the output voltage is 0 V. (Note that Intercept is a theoretical The ADJ[A, B] input has high input impedance. The input can value; the output voltage can never achieve 0 V). be conveniently driven from an attenuated value of VREF using In general, the calibration is performed by applying two known a resistor divider, if desired. signal levels to the AD8364 input and measuring the corresponding Figure 68 shows a simplified schematic representation of the output voltages. The calibration points are generally chosen to ADJ[A, B] interface. be within the linear-in-dB operating range of the device (see the Specifications section for more details). Calculation of the slope and intercept is done using the equations: Slope = (V − V )/(P − P ) OUT1 OUT2 IN1 IN2 Intercept = P − (V /Slope) IN1 OUT1 Rev. C | Page 31 of 44

AD8364 Data Sheet Once slope and intercept have been calculated, an equation can Calibration points must be chosen to suit the application at be written that will allow calculation of the input power based hand. In general, though, do not choose calibration points in on the output voltage of the detector. the nonlinear portion of the log amp transfer function (above 0 dBm or below −50 dBm in this case). P (unknown) = (V /Slope) + Intercept IN OUT1(MEASURED) Figure 71 shows how calibration points can be adjusted to The log conformance error of the calculated power is given by increase dynamic range, but at the expense of linearity. In this Error (dB) = (V − V )/Slope OUT(MEASURED) OUT(IDEAL) case, the calibration points for slope and intercept are set at −1 dBm Figure 69 includes a plot of the error at 25°C, the temperature at and −50 dBm. These points are at the end of the device linear which the log amp is calibrated. Note that the error is not zero. range. At 25°C, there is an error of 0 dB at the calibration points. This is because the log amp does not perfectly follow the ideal Note also that the range over which the AD8364 maintains an error V vs. P equation, even within the operating region. The of <±0.4 dB is extended to 57 dB at 25°C. The disadvantage of this OUT IN error at the calibration points (−43 dBm and −23 dBm in this approach is that linearity suffers, especially at the top end of the case) will, however, be equal to zero by definition. input range. Figure 69 also includes error plots for the output voltage at Another way of presenting the error function of a log amp −40°C and +85 °C. These error plots are calculated using the detector is shown in Figure 72. In this case, the dB error at hot slope and intercept at 25°C. This is consistent with calibration and cold temperatures is calculated with respect to the output in a mass-production environment, where calibration at voltage at ambient. This is a key difference in comparison to the temperature is not practical. previous plots, in which all errors have been calculated with respect to the ideal transfer function at ambient. SELECTING CALIBRATION POINTS TO IMPROVE ACCURACY OVER A REDUCED RANGE When the alternative technique, the error at ambient becomes by definition equal to 0 (see Figure 72). In some applications, very high accuracy is required at one power level or over a reduced input range. For example, in a This is valid if the device transfer function perfectly followed wireless transmitter, the accuracy of the high power amplifier the ideal VOUT = Slope × (PIN − Intercept) equation. However, (HPA) is most critical at or close to full power. since an rms amp, in practice, never perfectly follows this equation (especially outside of the linear operating range), this plot tends Figure 70 shows the same measured data as Figure 69. Notice to artificially improve linearity and extend the dynamic range, that accuracy is very high from −10 dBm to −25 dBm. At unless enough calibration points were taken to remove the error. approximately −45 dBm, the error increases to about −0.3 dB This plot is a useful tool for estimating temperature drift at a because the calibration points have been changed to −15 dBm particular power level with respect to the (nonideal) output and −25 dBm. voltage at ambient. Rev. C | Page 32 of 44

Data Sheet AD8364 3.50 2.0 3.50 2.0 BLUE =–40°C 3.15 GRERDE E=N + =85 +°2C5°C 1.6 3.15 ERROR CW–40°C 1.6 ERROR CW–40°C V) 2.80 1.2 2.80 1.2 (OUT 2.45 ERROR CW +25°C 0.8 2.45 0.8 VOUT2V 2.10 ERROR CW +85°C 0.4 dB) 2.10 ERROR CW +25°C 0.4 B) VOUT1 11..4705 0–0.4 RROR ( (V)OUT 1.75 0 ROR (d E V 1.40 –0.4 R E 1.05 –0.8 ERROR CW +85°C 1.05 –0.8 0.70 –1.2 0.70 –1.2 0.35 –1.6 0.35 –1.6 IN–T60E0RC–E5P5T–50–45P–I4N0 M–E3A5S– (3d0BP–mI2N1)5 –20P–I1N25 –10 –5 0 5 10 –2.0 04862-038 0–60–55–50–45–40–35PIN–3 M0E–A2S5 (–d2B0m–)15–10 –5 0 5 10–2.0 04862-040 Figure 70. Output Voltage and Error vs. PIN with 2-Point Calibration at Figure 72. Error vs. Temperature with Respect to Output Voltage at 25 °C, −15 dBm and −25 dBm, 2.14 GHz 2.14 GHz (Does Not Account for Transfer Function Nonlinearities at 25°C) PIN1 PIN2 3.50 2.0 3.15 1.6 ERROR CW–40°C 2.80 1.2 VOUT2 2.45 0.8 ERROR CW +25°C 2.10 0.4 B) (V)UT 1.75 0 OR (d VO 1.40 ERROR CW +85°C –0.4 RR E 1.05 –0.8 0.70 –1.2 VOUT1 0.35 –1.6 0 –2.0 –60–55–50–45–40–35–30–25–20–15–10 –5 0 5 10 57dBPI ND YMNEAAMSI C(d BRmAN)GE 04862-039 Figure 71. Dynamic Range Extension by Choosing Calibration Points that are Close to the End of the Linear Range, 2.14 GHz Rev. C | Page 33 of 44

AD8364 Data Sheet CHANNEL ISOLATION –40 –45 Isolation must be considered when using both channels of the AD8364 at the same time. The two isolation requirements that –50 must be considered are the isolation from one RF channel input –55 to the other RF channel input and the isolation from one RF B) –60 channel input to the other channel output. When using both N (d B->A O –65 channels of the AD8364, care must be taken in the layout to ATI L –70 isolate the RF inputs from each other. Coupling on the PC SO I –75 board affects both types of isolation. A->B –80 In most applications, the designer has the ability to adjust the –85 power going into the AD8364 through the use of different vstaalbuleed a ttetemnpueartaotrusr. eW-shtaebnl eis coolautpiolenr si sa an dc oanccceurrna,t eit t iesm upseefruatl utore - –9010 100FREQUENCY (MH1z,)000 10,000 05334-021 adjust the input power so the lowest expected detectable power Figure 73. RF Channel Input-to-Input Isolation is not far from the lowest detectable power of the AD8364 at the 16 PEAK INTERFERENCE (IN dB) TO A–45dBm INPUT SIGNAL frequency of operation. The AD8364 lowest detectable power DUE TO AN INTERFERING SIGNAL ON THE OTHER point has little variation from part to part and is not affected by B) 14 CCHHAANNNNEELL. AA -IN>BP U=T A B I-N>TAE =R FBE IRNITNEGR FWEITRHIN BG, WX-IATXHI SA ,I SX-AXIS d IS CHANNEL B INPUT FREQUENCY SEPARATION OF THE the balun. This equalizes the signals on both channels at their S ( 12 TWO CHANNELS = 1kHz. SEE CHARACTERIZATION lrtohewqe uedisertve pimcoees,n sritebsdl eau ncpdion wpg oetrhs selie bRvleyFl ,ac wdhdahnsi cnahett lre ienndupuaucttoe isrs sot hltaoet itoohvnee rrReaFqll u iinisropelumattsei onontfs . ATION FROMENT OUTPUT 108 DESCRAIP–BT>–IABO>– N1A> 8S B18E 80C88MT80I0HOMMNzH HFzzOR MORE IBN–F>OARM 8A8T0IMONH.z Misshooelawastnuio rinnin iFgsi gtshutrerae Ri g7Fh3 t.c Nfhoaorntwen atehrld ait,n aapdnuddti tntohg e ta hrnee asoutttlehtn eourf a RstouFrc chinh a asnne rneixeesle riwnciiptshue ti s PEAK DEVIdBm EQUIVAL 64 A–B>–BB> A–2>1 24A50 02M01H 4Mz0HMzHz A–>B 45B0– M>AHz the RF signal increases the channel input-to-input isolation by –45 2 A–>B 450 MHz the value of the attenuator. 2500MHZ Touhtep iusot liast iao lnit btleet wmeoerne ocnoem RpFli cchataendn. eDl ion pnuott aansdsu tmhee o tthhaetr wchoarnstn-el 0–20 –1I5NTERF–E10RING C–H5ANNEL 0AMPLITU5DE (dBm10) 15 05334-022 Figure 74. Apparent Measurement Error Due to Overall Channel-to-Channel case isolation happens when one RF channel has high power Cross-Coupling and the other RF channel is set at the lowest detectable power. 7 Worst-case isolation happens when the low power channel is at a NT PEAK INTERFERENCE (IN dB) TO A -45dBm INPUT nominally low power level, as chosen in Figure 74. If the inputs ALE 6 SOITGHNEARL CDHUAEN TNOE LA.N INTERFERING SIGNAL ON THE V to both RF channels are at the same frequency, the isola-tion UI Q A->B = A INTERFERING WITH B, X-AXIS IS CHANNEL A also depends on the phase shift between the RF signals put into m E 5 INPUT Freq chA = 2500 MHz Freq CHB = 1880MHz tohnee ARDF 8ch3a6n4n. Telh inisp cuatn a nbde asneeonth beyr spiglancailn (glo aw h pigohw pero)w sleirg hstiglyn oaflf soent OM -45dBPUT(dB)4 BCFr-He>AqAN C=NH BEA LI N =B T1 EI8NR8P0FU EMTRH FINzreGq W CIHTBH =A ,2 X50-A0X MISH zIS icnh afrnenqeul eins coyb stoer tvheed o wthitehr aRnF o cshcailnlonsecl.o Ipfe t,h iet hoaust pau rti popf lteh teh laotw lo pookws er ON FROUT3 FTRWEOQ CUHEANNCNYE SLESP =A R62A0T MIOHNz .OF THE TI SEE CHARCTERIZATION DESCRIPTION similar to a full-wave rectified sine wave with a frequency equal VIA 2 SECTION FOR MORE INFORMATION to the frequency difference between the two channels, that is, a DE beat tone. The magnitude of the ripple reflects the isolation at a AK 1 B->A E P A->B specific phase offset (note that two signals of slightly different fprheaqs-eu)e,n acnieds t ahcet flriekqeu tewnoc ysi ogfn tahlsa tw riitphp lae cios ndsirtaencttllyy rcehlaatnegdi ntog the 0–20 –15INTER–F1E0RING C–H5ANNEL0 AMPLITU5DE (dB1m0) 15 05334-085 Figure 75. Improved Measurement Error with Increased Frequency frequency offset. The data taken in Figure 74 assumes worst-case Separation amplitude and phase offset. If the RF signals on Channel A and Channel B are at significantly different frequencies, the input-to- output isolation increase, depending on the capacitors placed on CLP[A, B] and CHP[A, B] and the frequency offset of the two signals (Figure 75), due to the response roll-off within AD8364. Rev. C | Page 34 of 44

Data Sheet AD8364 ALTERING THE SLOPE HPA ECA OMA PSR COM EMP COM LPA C D C V A T A C None of the changes to operating conditions discussed so far 24 23 22 21 20 19 18 17 affect the logarithmic slope, V , in Equation 7. The slope can SLOPE TEMP readily be altered by controlling the fraction of OUT[A, B] that VGA CONTROL VPSA 25 16 VSTA is fed back to the setpoint interface at the VST[A, B] pin. When the full signal from OUT[A, B] is applied to VST[A, B], the slope INHA 26 CHANNEL A ISIG2 15 OUTA assumes the nominal value of 50 mV/dB. It can be increased by INLA 27 TruPwr™ ITGT2 14 FBKA including a voltage divider between these pins, as shown in PWDN 28 13 OUTP Figure 76. Moderately low resistance values must be used to OUTA OUTB minimize scaling errors due to the approximately 70 kΩ input COMR 29 12 OUTN rsetrsiinstga nalcseo alto tahdes VthSeT o[Aut,p Bu]t ,p ainnd. K ite eevpe innt umailnlyd r tehdautc tehsi sth ree sliosatodr- IINNHLBB 3301 CHTrAuNPNwEr™L B ISIG2 1101 FBKB VOUT driving capabilities if very low values are used. Equation 17 can ITGT2 OUTB R1 VPSB 32 9 be used to calculate the resistor values. VGA VSTB BIAS CONTROL R2 R1 = R2' (S /50 − 1) (17) D 1 2 3 4 5 6 7 8 wSDh iesr teh: e desired slope, expressed in mV/dB. CHPB DECB COMB ADJB ADJA VREF VLVL CLPB 05334-041 Figure 76. External Network to Raise Slope R2' is the value of R2 in parallel with 70 kΩ. For example, using R1 = 1.65 kΩ and R2 = 1.69 kΩ (R2' = HPA ECA OMA PSR COM EMP COM LPA C D C V A T A C 1.649 kΩ), the nominal slope is increased to 100 mV/dB. This 24 23 22 21 20 19 18 17 choice of scaling is useful when the output is applied to a digital TEMP voltmeter because the displayed number directly reads as a VGA CONTROL decibel quantity with only a decimal point shift. VPSA 25 16 VSTA Operating at a high slope is useful when it is desired to measure INHA 26 CHANNEL A ISIG2 15 OUTA a particular section of the input range in greater detail. A INLA 27 TruPwr™ ITGT2 14 FBKA measurement range of 60 dB corresponds to a 6 V change in PWDN 28 13 OUTP OUTA VOUT at this slope, exceeding the capacity of the AD8364 OUTB COMR 29 12 OUTN output stage when operating on a 5 V supply. This requires that tshecet iinotne rwcietphti nis ar ewpionsditoiwon ceodr rtoes pploancde itnhge tdoe asinr eodu itnppuut tr arnangeg eo f IINNHLBB 3301 CHTrAuNPNwEr™L B ISIG2 1101 OFBUKTBB VOUT ITGT2 R1 0.1 V ≤ VOUT ≤ 4.8 V, a 47 dB range. VPSB 32 9 VSTB 4.02k VGA Using the arrangement shown in Figure 77, an output of 0.4 V CONTROL R2 BIAS 4.32k corresponds to the lower end of the desired range, and an output of 1 2 3 4 5 6 7 8 3.5 V corresponds to the upper limit with 3 dB of margin at each B B B B A F L B end of the range, nominally −32 dBm to −1 dBm with the CHP DEC COM ADJ ADJ VRE VLV CLP irnattehrecre tphta ant g−r3o5u.6n dd.B Rm3. iNs noteee dtheadt tRo2 e niss cuoren ntheactt etdh et oA VDR8E36F4 R2k3 05334-042 reference buffer is correctly loaded. Figure 77. Scheme Providing 100 mV/dB Slope for Operation over a 3 mV to 300 mV Input Range When the slope is raised by some factor, the loop capacitor, CLP[A, B], must be raised by the same factor to ensure stability and to preserve a chosen averaging time. The slope can be lowered by placing a voltage divider after the output pin, following standard practice. Rev. C | Page 35 of 44

AD8364 Data Sheet CHOOSING THE RIGHT VALUE Once the response time is set so that the AD8364 is just able to FOR CHP[A, B] AND CLP[A, B] follow the RF burst requirements (within the tolerance of the capacitors), the output of the AD8364 must be evaluated with The AD8364 VGA includes an offset cancellation loop, which an oscilloscope. If there is ripple on the output (due to the introduces a high-pass filter effect in the transfer function. The modulated signal), averaging may need to be performed on corner frequency, f , of this filter must be below that of the lowest HP the DSP to achieve a true rms response. Figure 44 and Figure 45 input signal in the desired measurement bandwidth frequency may help in determining the proper CLP[A, B] values to use. to properly measure the amplitude of the input signal. The required value of the external capacitor is given by SINGLE-ENDED INPUT OPERATION CHP[A, B] = 200 μF/(2 × π × f )(f in Hz) (18) For optimum operation, the RF inputs to the AD8364 must be HP HP driven differentially. However, the AD8364 RF inputs can also Thus, for operation at frequencies down to 100 kHz, CHP[A, B] be driven in a single-ended configuration with reduced dynamic must be 318 pF. range. Figure 78 shows a recommended input configuration for In the standard connections for the measurement mode, the a single channel. VST[A, B] pin is tied to OUT[A, B]. For small changes in input Figure 79 shows the performance obtained with the configuration amplitude (a few decibels), the time-domain response of this shown in Figure 78. The user must note that the dynamic range loop is essentially linear with a 3 dB low-pass corner frequency performance suffers in single-ended configuration due to the of nominally f = 1/(2 × π × CLP[A, B] × 1.1 kΩ). Internal time LP inherent amplitude and phase imbalance at the RF inputs. delays around this local loop set the minimum recommended However, at low frequency the dynamic range is quite good and value of this capacitor to about 300 pF, making f = 482 kHz. LP users trying to detect low frequency or baseband signals may For operation at lower signal frequencies, or whenever the want to consider this as an option. At frequencies greater than averaging time needs to be longer, use 450 MHz, the dynamic range decreases to about 20 dB, reducing CLP[A, B] = 900 μF/2 × π × f (f in Hz) (19) the AD8364 usefulness for many applications. Performance in LP LP single-ended configuration is subject to circuit board layout When the input signal exhibits large crest factors, such as a (see the Printed Circuit Board Considerations section). WCDMA signal, CLP[A, B] must be much larger than might at first seem necessary. This is due to the presence of significant low INHx frequency components in the complex, pseudo random modu- 100 INLx lation, which generates fluctuations in the output of the AD8364. RF BURST RESPONSE TIME 100 05334-044 RF burst response time is important for modulated signals that Figure 78. Recommended Input Configuration for Single-Ended Input Drive have large steps in power, such as a single carrier EVDO that 5.0 has the potential for a greater than 20 dB burst of power (for 50MHz 4.5 approximately 200 μs out of every 800 μs). 4.0 Accurate power detection for signals with RF bursts is achieved 3.5 when the AD8364 is able to respond quickly to the change in RF 50MHz Error 450MHz ERROR 3.0 B) pploawceedr; ohno wPeinves rC, tLhPe[ rAes, pBo]n, sCeH tiPm[Ae i,s B li]m, aintedd DbyE Cth[eA c,a Bp]a.c itors A (V) 2.5 100MHz OR (d Capacitors placed on the DEC[A, B] pins affect the response time OUT 2.0 45 MHz ERR the least and must be chosen as stated in the RF Input Interface 1.5 section. Capacitors placed on CHP[A, B] and CLP[A, B] must be 1.0 chosen according to the equations in the Choosing the Right 0.5 100MHz ERROR Value for CHP[A, B] and CLP[A, B] section and the response time ffaosrt tehneo AugDh8 t3o6 4fo mllouwst t bhee bevuarlsut arteesdp.o Inf steh, et hree svpaolunesse ftoirm CeL isP [nAo,t B] 0–60 –50 –40 –3R0F INP–U2T0 (dBm–1)0 0 10 20 05334-045 must be decreased. The capacitor values placed on the CLP[A, B] Figure 79. Single-Ended Performance for have the largest effect on the rise and fall times. The capacitor the Configuration Shown in Figure 78 values placed on CHP[A, B] affect the rising and falling corner of the response (overshoot or under-shoot); however, the falling corner is most likely swamped out by the effect of CLP[A, B]. Rev. C | Page 36 of 44

Data Sheet AD8364 PRINTED CIRCUIT BOARD CONSIDERATIONS The accurate measurement range (that is, the dynamic range) of AD8364 detectors is sensitive to amplitude and phase matching Each RF input pin of the AD8364 presents 100 Ω impedance of the signals presented at the differential inputs. Care should be relative to their respective ac grounds. To ensure that signal taken to ensure matching of these parameters and to minimize integrity is not seriously impaired by the printed circuit board parasitic capacitance on the RF inputs when laying out the PC (PCB), the relevant connection traces must provide appropriate board. It is also suggested that the two traces associated with characteristic impedance to the ground plane. This can be each differential input be mirror images, or duplicates, of one achieved through proper layout. When laying out an RF trace another where possible. A high quality balun with known with controlled impedance, consider the following: output magnitude and phase characteristics is recommended to  When calculating the RF line impedance, take into account perform single-ended to balanced conversions. It is possible to the spacing between the RF trace and the ground on the improve the dynamic range by skewing the amplitude and same layer. phase matching at the input. See the Typical Performance  Ensure that the width of the microstrip line is constant and Characteristics section for more details. that there are as few discontinuities, such as component Stable, low ESR capacitors are mandatory in the RF circuitry of pads, as possible along the length of the line. Width variations the AD8364. This corresponds to capacitors connected to cause impedance discontinuities in the line and may result Pins INH[A, B], INL[A, B], DEC[A, B], and CHP[A, B]. High in unwanted reflections. ESR capacitors may result in amplitude and phase mismatch at  Do not use silkscreen over the signal line because it can the differential inputs, which in turn results in low dynamic range. alter the line impedance. Capacitors with poor aging characteristics under temperature cycling have been shown to accentuate the temperature drift  Keep the length of the RF input traces as short as possible. during operation of the AD8364. Use of Samsung CL10 series Figure 80 shows the cross section of a PC board, and Table 6 multilayer ceramic capacitors (or similar) in the RF area are shows two possible sets of dimensions that provide a 100 Ω line recommended. impedance for FR-4 board material with ε = 4.6 and Rodgers 4003 r High transient and noise levels on the power supply, ground, board material with ε = 3.38. r and inputs must be avoided. This reinforces the need for proper supply bypassing and decoupling. See the Evaluation Board Table 6. Possible Trace Dimensions for Z = 100 Ω O section for suggestions. Dimension FR-4 (mil) Rodgers 4003 (mil) W 22 6 A solder appropriate for either the lead-free or leaded version of H 53 11 the AD8364 must be chosen. After the circuit board has been T 2 0.7 soldered, it is important to thoroughly clean all excess solder flux and residues from the board. Any residual material may act 3W W 3W as stray parasitic capacitance, which could result in degraded T performance. PACKAGE CONSIDERATIONS H ER 05334-046 Tpahded AleD o8n3 6th4e u bsoestt ao mco omf pthacet d 3e2v-ilceea dp rLoFvCidSePs. bAo ltahr gae t hexerpmosaeld Figure 80. Cross-Section View of a PC Board benefit and a low inductance path to ground for the circuit. To It is possible to approximate a 100 Ω trace on a board designed make proper use of this packaging feature, the PCB RF/dc with the 50 Ω dimensions above by removing the ground plane common ground reference needs to make contact directly within three line widths of the area directly below the trace. under the device with as many vias as possible to lower the However, more predictable performance may be obtained with inductance and thermal impedance. precise ground plane spacing. It is possible to design a circuit board with two ground planes, one plane for areas with 50 Ω characteristic impedance and another for areas with 100 Ω characteristic impedance. If the 100 Ω plane is placed below the 50 Ω plane, then an opening can be made in the 50 Ω plane to allow the 100 Ω traces to work against the 100 Ω ground plane. The two ground planes must be connected together with as many vias as possible. Rev. C | Page 37 of 44

AD8364 Data Sheet DESCRIPTION OF CHARACTERIZATION BASIS FOR ERROR CALCULATIONS The general hardware configuration used for most of the The slope and intercept are derived using the coefficients of a AD8362 characterization is shown in Figure 81. The signal linear regression performed on data collected in the central sources used in this example are the Rohde & Schwarz SMIQ03B operating range. Error is stated in two forms: (1) error from and Agilent E4438C. Input-matching baluns are used to transform linear response to CW waveform and (2) output delta from the single-ended RF signal to the differential form. Due to the 25°C performance. differential input sensitivity to amplitude and phase mismatch, The error from linear response to CW waveform is the decibel specific baluns were used for each characterization frequency to difference in output from the ideal output defined by the achieve the best performance. conversions gain and output reference. This is a measure of the Other selected configurations are shown in Figure 82 and linearity of the device response to both CW and modulated Figure 83 as well. waveforms. The error in dB is calculated by ( ) SSOIGUNRACLE –3dB INA AD8364 OOUUTTBA AGILENT Error (dB) = VOUT −Slope× PIN −PZ OUTP 34970A Slope SSOIGUNRACLE –3dB ICNHBARABCOTAERRDIZATIONOTVEURMTENPF SWMIETTCEHRIN/G where PZ is the x-axis intercept expressed in dBm. This is analogous to the input amplitude that produces an output of 0 V, if such an output was possible. Error from the linear response to the CW waveform is not a CCOONMTRPOUTLELERR 05334-047 msloepaes uanred o inf taebrscoeplut toef aecaccuhr dacevy,i csei.n Hceo wit eisv ecra, lict uvleartiefide su tshien gli ntheaer ity Figure 81. General Characterization Configuration and the effect of modulation on the device response. Similarly, MINI-CIRCUITS error from 25°C performance uses the 25°C performance of a ZHL–42W given device and waveform type as the reference from which all –6dB SPLITTER ADA83D4813 4V0E OCTROR INHA/B other performance parameters shown alongside it are compared. It AGRIFL ESNOTU 8R6C4E8 50Ω –8dB MODULATOR –8dB –6dB is predominantly (and most often) used as a measurement of output variation with temperature. –9dB –8dB –6dB INLA/B 05334-052 Figure 82. Configuration for Amplitude and Phase Mismatch Characterization Rev. C | Page 38 of 44

Data Sheet AD8364 VPOS R24 0Ω VPOS C23 C13 100pF R5 0.1µF 0Ω C11 C8 C12 TEKTDS510 0.1µF 0.1µF 100pF SCOPE R4 0Ω C15 CLPA CC99 00..11µµFF C10 24 23 22 21 20 19 18 17 100pF CHPADECACOMAVPSRACOMTEMPACOMCLPA 25 VPSA VSTA 16 SMIQ06B 26 INHA OUTA 15 SIGNAL 3dB BALUN GENERATOR 27 INLA FBKA 14 AD8364ACPZ 28 PWDN OUTP 13 LECROY9213 PULSE GENERATOR 29 COMR OUTN 12 30 INLB FBKB 11 BALUN 31 INHB OUTB 10 32 VPSB VSTB 9 CHPBDECBCOMBADJB ADJA VREF VLVL CLPB C20 R21 100pF 1 2 3 4 5 6 7 8 HP6236B 0Ω C22 C16 POWER 0.1µF CLPB SUPPLY C21 0.1µF C1 C24 VPOS 0.1µF 100pF 05334-048 Figure 83. Configuration for RF Burst Measurement Rev. C | Page 39 of 44

AD8364 Data Sheet EVALUATION BOARD The two RF input signals are applied to two broadband baluns (Anaren BD0826J50200A00), which, in turn, drive the AD8364 AD8364-EVALZ is a 4-layer, FR4-based printed circuit board. RF inputs. This device is specified to operate from 800 MHz to For normal operation, it requires a 5 V/100 mA power supply. 2.6 GHz but is operational from 500 MHz to 2.7 GHz. To oper- The 5 V power supply should be connected to the clip leads ate below 500 MHz, these baluns can be removed so that the labeled VPS and COMM1. The two RF input signals are applied AD8364 is driven single-ended. to two edge-mounted SMA-type RF connectors. The output signals are accessible via the OUTA, OUTB, OUTN, OUTP, and TEMP clip leads. The circuit board can also accommodate 6-pin and 26-pin headers through which the power supply, ground, temperature adjust nodes, and output signal pins are accessible (the circuit board is shipped with these headers not installed). INB INA JOHNSON142-0701-851 1 1 JOHNSON142-0701-851 2345 5432 AGND AGND PWDN R2 AGND 1K C5 C2 0.1UF 0.1UF T1 DT2NI BD1086U2NN6CJB652A0GL210BB50AAGALL2021034 BD1086U2NN6CJB652A0GL210BB50AAGALL2021034 VPS L1 P1 AGND AGND C19 C21TBDD08N0I5 C11 C13 VOSUTTAA 12 DNI 0.1UFC3 0.1UFC4 0C.61UF 0C.71UF A0G.1NUDF A1G0N00DPF AD2G2NNUIDF AD2G2NNUIDF OUTN 3456 22-12-2064DNPI2 123456 AGND 11 BBAALLDDKKJJAB AADDJJBA 1V0P0CSPA2FG0ND AGND A1CG01N00PDFVPS R1D2KN5I VPS_SEOPOTVVNEWSRUUSMTETTDEBBPPFN 1111111178901234567 18 0.1UFC8 100PCF1 0.1UCF22 PAD 3231302928272625 DUT 0C.91UF 1C0203PF 0C.214UF VREF R1D4KN1I 12229012 AGND AGND AGND AGND AGND AGND 23 24 1 24 25 V1REFBLK 1R.51K9 R17 ADJA ADJB 2345 AD8364ACPZ 22220123 VPS AGND 26 3M3429-1302 VREF 1.5K 6 19 C12 7 18 100PF 8 17 AGND R20 R18 C16 C14 DNI AGND A1KGND 1K 0.1UAFGND AGND 910111213141516 AGND A0G.1NUDF 1 BTELMKPR24 TEMP COMM1 COMM2 VPS OUTB OUTA 1DKNI 1 BLK 1 BLK 1 1 BLK 1 BLK AGND AGND VPS OUTN OUTP R14 R9 DNI DNI 1K BLK1 1 BLK 1K COMM3 COMM4 DNI DNI OUTB OUTA AGND1 BLK AGND1 BLK DRN31I5KOUTN OUT1RPKD32NI 05334-086 Figure 84. AD8364 Evaluation Board Schematic Rev. C | Page 40 of 44

Data Sheet AD8364 OUTLINE DIMENSIONS 5.10 0.30 5.00 SQ 0.25 PIN 1 4.90 0.18 INDICATOR PIN 1 25 32 INDICATOR 24 1 0.50 BSC EXPOSED 3.25 PAD 3.10 SQ 2.95 17 8 0.50 16 9 0.25 MIN TOP VIEW 0.40 BOTTOM VIEW 0.30 FOR PROPER CONNECTION OF 0.80 THE EXPOSED PAD, REFER TO 0.75 THE PIN CONFIGURATION AND 0.05 MAX FUNCTION DESCRIPTIONS 0.70 0.02 NOM SECTION OF THIS DATA SHEET. COPLANARITY 0.08 SEATING 0.20 REF PLANE COMPLIANT TO JEDEC STANDARDS MO-220-WHHD. 112408-A Figure 85. 32-Lead Lead Frame Chip Scale Package [LFCSP] 5 mm × 5 mm Body and 0.75 mm Package Height (CP-32-7) Dimensions shown in millimeters ORDERING GUIDE Model1,2 Temperature Range Package Description Package Option Ordering Quantity AD8364ACPZ-WP −40°C to +85°C 32-Lead Lead Frame Chip Scale Package [LFCSP] CP-32-7 36 Units AD8364ACPZ-REEL7 −40°C to +85°C 32-Lead Lead Frame Chip Scale Package [LFCSP] CP-32-7 1,500 Units AD8364ACPZ-R2 −40°C to +85°C 32-Lead Lead Frame Chip Scale Package [LFCSP] CP-32-7 250 Units AD8364-EVALZ Evaluation Board 1 Z = RoHS Compliant Part. 2 WP = Waffle Pack. Rev. C | Page 41 of 44

AD8364 Data Sheet NOTES Rev. C | Page 42 of 44

Data Sheet AD8364 NOTES Rev. C | Page 43 of 44

AD8364 Data Sheet NOTES ©2005–2016 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D05334-0-8/16(C) Rev. C | Page 44 of 44

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