2 GHz, Ultralow Distortion, Differential RF/IF Amplifier Data Sheet AD8352 FEATURES FUNCTIONAL BLOCK DIAGRAM −3 dB bandwidth of 2.2 GHz (A = +10 dB) V VCM Single resistor gain adjust: 3 dB ≤ AV ≤ 25 dB ENB BIASCELL VCC Single resistor and capacitor distortion adjust RGP Input resistance: 3 kΩ, independent of gain (A ) V Differential or single-ended input to differential output RDP Low noise input stage: 2.7 nV/√Hz RTI at A = 10 dB V + Low broadband distortion VIP VOP CD 10 MHz: −86 dBc HD2, −82 dBc HD3 RG RD 70 MHz: −84 dBc HD2, −82 dBc HD3 VIN – VON 190 MHz: −81 dBc HD2, −87 dBc HD3 RDN OIP3 of 41 dBm at 150 MHz SFaleswt s reatttlein: 8g Van/nds o verdrive recovery of <2 ns RGN AD8352 GND 05728-001 Single-supply operation: 3 V to 5.5 V Figure 1. Low power dissipation: 37 mA typical at 5 V Power-down capability: 5 mA at 5 V Fabricated using the high speed XFCB3 SiGe process APPLICATIONS Differential ADC drivers Single-ended-to-differential conversion RF/IF gain blocks SAW filter interfacing GENERAL DESCRIPTION The AD8352 is a high performance differential amplifier 3 mm × 3 mm, 16-lead LFCSP and operates over a temperature optimized for RF and IF applications. It achieves better than range of −40°C to +85°C. 80 dB SFDR performance at frequencies up to 200 MHz, and –60 44 65 dB beyond 500 MHz, making it an ideal driver for high –65 42 speed 12-bit to 16-bit analog-to-digital converters (ADCs). Unlike other wideband differential amplifiers, the AD8352 has –70 40 buffers that isolate the gain setting resistor (R ) from the signal G –75 38 inputs. As a result, the AD8352 maintains a constant 3 kΩ input c) m) rdersiivset arnecqeu ifroerm geanintss. oTf h3e d ABD t8o3 2552 dhBas, ae ansoinmgi nmaal t1c0h0i nΩg dainffde riennptuiatl HD3 (dB –80 36 IP3 (dB –85 34 output resistance. –90 32 The device is optimized for wideband, low distortion performance at frequencies beyond 500 MHz. These attributes, together with –95 30 its wide gain adjust capability, make this device the amplifier of –100 28 cwhhoeircee lfoowr gdeinsteorratli-opnu,r npooissee ,I Fan adn pdo bwreora adrbea cnrdit iacpalp. lIitc iast iiodnesa lly 20 40 60 80 FR1E00QUE1N2C0Y(1M4H0z) 160 180 200 220 05728-002 Figure 2. Third Harmonic Distortion (HD3) and IP3 vs. suited for driving not only ADCs but also mixers, pin diode Frequency, Measured Differentially attenuators, surface acoustic wave (SAW) filters, and multi- element discrete devices. The device is available in a compact Rev. C Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Tel: 781.329.4700 ©2006–2018 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com

AD8352 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Gain and Distortion Adjustment (Differential Input) .......... 11 Applications ....................................................................................... 1 Single-Ended Input Operation ................................................. 12 Functional Block Diagram .............................................................. 1 Narrow-Band, Third-Order Intermodulation Cancellation . 13 General Description ......................................................................... 1 High Performance ADC Driving ............................................. 14 Revision History ............................................................................... 2 Layout and Transmission Line Effects ..................................... 15 Specifications ..................................................................................... 3 Evaluation Board ............................................................................ 16 Noise Distortion Specifications .................................................. 4 Evaluation Board Loading Schemes ........................................ 16 Absolute Maximum Ratings ............................................................ 6 Soldering Information ............................................................... 16 ESD Caution .................................................................................. 6 Evaluation Board Schematics ................................................... 17 Pin Configuration and Function Descriptions ............................. 7 Outline Dimensions ....................................................................... 19 Typical Performance Characteristics ............................................. 8 Ordering Guide .......................................................................... 19 Applications Information .............................................................. 11 REVISION HISTORY 4/2018—Rev. B to Rev. C 9/2006—Rev. 0 to Rev. A Changes to Figure 3 and Table 4 ..................................................... 7 Changes to Absolute Maximum Ratings ........................................ 6 Updated Outline Dimensions ....................................................... 19 Inserted Figure 10, Figure 11, and Figure 13 ................................. 9 Changes to Ordering Guide .......................................................... 19 Inserted Figure 17, Figure 18, and Figure 21 .............................. 10 Changes to Figure 34 ...................................................................... 14 7/2008—Rev. A to Rev. B Changes to Table 9 .......................................................................... 16 Changes to Features Section............................................................ 1 Changes to Figure 38 ...................................................................... 18 Changes to Figure 21 ...................................................................... 10 Changes to Ordering Guide .......................................................... 19 Changes to Table 9 .......................................................................... 16 Added Soldering Information Section ......................................... 16 1/2006—Revision 0: Initial Version Changes to Figure 38 ...................................................................... 17 Changes to Ordering Guide .......................................................... 19 Rev. C | Page 2 of 19

Data Sheet AD8352 SPECIFICATIONS V = 5 V, R = 200 Ω differential, R = 118 Ω (A = 10 dB), f = 100 MHz, T = 25°C; parameters specified differentially (in/out), unless S L G V otherwise noted. C and R are selected for differential broadband operation (see Table 5 and Table 6). D D Table 1. Parameter Conditions Min Typ Max Unit DYNAMIC PERFORMANCE −3 dB Bandwidth A = 6 dB, V ≤ 1.0 V p-p 2500 MHz V OUT A = 10 dB, V ≤ 1.0 V p-p 2200 MHz V OUT A = 14 dB, V ≤ 1.0 V p-p 1800 MHz V OUT Bandwidth for 0.1 dB Flatness 3 dB ≤ A ≤ 20 dB, V ≤ 1.0 V p-p 190 MHz V OUT Bandwidth for 0.2 dB Flatness 3 dB ≤ A ≤ 20 dB, V ≤ 1.0 V p-p 300 MHz V OUT Gain Accuracy Using 1% resistor for R , 0 dB ≤ A ≤ 20 dB ±1 dB G V Gain Supply Sensitivity V ± 5% 0.06 dB/V S Gain Temperature Sensitivity −40°C to +85°C 4 mdB/°C Slew Rate R = 1 kΩ, V = 2 V step 9 V/ns L OUT R = 200 Ω, V = 2 V step 8 V/ns L OUT Settling Time 2 V step to 1% <2 ns Overdrive Recovery Time V = 4 V to 0 V step, V ≤ ±10 mV <3 ns IN OUT Reverse Isolation (S12) −80 dB INPUT/OUTPUT CHARACTERISTICS Common-Mode Nominal VCC/2 V Voltage Adjustment Range 1.2 to 3.8 V Maximum Output Voltage Swing 1 dB compressed 6 V p-p Output Common-Mode Offset Referenced to VCC/2 −100 +20 mV Output Common-Mode Drift −40°C to +85°C 0.25 mV/°C Output Differential Offset Voltage −20 +20 mV Common-Mode Rejection Ratio (CMRR) 57 dB Output Differential Offset Drift −40°C to +85°C 0.15 mV/°C Input Bias Current ±5 µA Input Resistance 3 kΩ Input Capacitance (Single Ended) 0.9 pF Output Resistance 100 Ω Output Capacitance 3 pF POWER INTERFACE Supply Voltage 3 5 5.5 V ENB Threshold 1.5 V ENB Input Bias Current ENB at 3 V 75 nA ENB at 0.6 V −125 µA Quiescent Current ENB at 3 V 35 37 39 mA ENB at 0.6 V 5.3 mA Rev. C | Page 3 of 19

AD8352 Data Sheet NOISE DISTORTION SPECIFICATIONS V = 5 V, R = 200 Ω differential, R = 118 Ω (A = 10 dB), V = 2 V p-p composite, T = 25°C; parameters specified differentially, unless S L G V OUT otherwise noted. C and R are selected for differential broadband operation (see Table 5 and Table 6). See the Applications Information D D section for single-ended-to-differential performance characteristics. Table 2. Parameter Conditions Min Typ Max Unit 10 MHz Second/Third Harmonic Distortion1 R = 1 kΩ, V = 2 V p-p −88/−95 dBc L OUT R = 200 Ω, V = 2 V p-p −86/−82 dBc L OUT Output Third-Order Intercept R = 200 Ω, f = 9.5 MHz, f = 10.5 MHz 38 dBm L 1 2 Third-Order IMD R = 1 kΩ, f = 9.5 MHz, f = 10.5 MHz, −86 dBc L 1 2 V = 2 V p-p composite OUT R = 200 Ω, f = 9.5 MHz, f = 10.5 MHz, −81 dBc L 1 2 V = 2 V p-p composite OUT Noise Spectral Density (RTI) 2.7 nV/√Hz 1 dB Compression Point (RTO) 15.7 dBm 70 MHz Second/Third Harmonic Distortion R = 1 kΩ, R = 178 Ω, V = 2 V p-p −83/−84 dBc L G OUT R = 200 Ω, R = 115 Ω, V = 2 V p-p −84/−82 dBc L G OUT Output Third-Order Intercept R = 200 Ω, f = 69.5 MHz, f = 70.5 MHz 40 dBm L 1 2 Third-Order IMD R = 1 kΩ, f = 69.5 MHz, f = 70.5 MHz, −91 dBc L 1 2 V = 2 V p-p composite OUT R = 200 Ω, f = 69.5 MHz, f = 70.5 MHz, −83 dBc L 1 2 V = 2 V p-p composite OUT Noise Spectral Density (RTI) 2.7 nV/√Hz 1 dB Compression Point (RTO) 15.7 dBm 100 MHz Second/Third Harmonic Distortion R = 1 kΩ, V = 2 V p-p −83/−83 dBc L OUT R = 200 Ω, V = 2 V p-p −84/−82 dBc L OUT Output Third-Order Intercept R = 200 Ω, f = 99.5 MHz, f = 100.5 MHz 40 dBm L 1 2 Third-Order IMD R = 1 kΩ, f = 99.5 MHz, f = 100.5 MHz, −91 dBc L 1 2 V = 2 V p-p composite OUT R = 200 Ω, f = 99.5 MHz, f = 100.5 MHz, −84 dBc L 1 2 V = 2 V p-p composite OUT Noise Spectral Density (RTI) 2.7 nV/√Hz 1 dB Compression Point (RTO) 15.6 dBm 140 MHz Second/Third Harmonic Distortion R = 1 kΩ, V = 2 V p-p −83/−82 dBc L OUT R = 200 Ω, V = 2 V p-p −82/−84 dBc L OUT Output Third-Order Intercept R = 200 Ω, f = 139.5 MHz, f = 140.5 MHz 41 dBm L 1 2 Third-Order IMD R = 1 kΩ, f = 139.5 MHz, f = 140.5 MHz, −89 dBc L 1 2 V = 2 V p-p composite OUT R = 200 Ω, f = 139.5 MHz, f = 140.5 MHz, −85 dBc L 1 2 V = 2 V p-p composite OUT Noise Spectral Density (RTI) 2.7 nV/√Hz 1 dB Compression Point (RTO) 15.5 dBm Rev. C | Page 4 of 19

Data Sheet AD8352 Parameter Conditions Min Typ Max Unit 190 MHz Second/Third Harmonic Distortion R = 1 kΩ, V = 2 V p-p −82/−85 dBc L OUT R = 200 Ω, V = 2 V p-p −81/−87 dBc L OUT Output Third-Order Intercept R = 200 Ω, f = 180.5 MHz, f = 190.5 MHz 39 dBm L 1 2 Third-Order IMD R = 1 kΩ, f = 180.5 MHz, f = 190.5 MHz, −83 dBc L 1 2 V = 2 V p-p composite OUT R = 200 Ω, f = 180.5 MHz, f = 190.5 MHz, −81 dBc L 1 2 V = 2 V p-p composite OUT Noise Spectral Density (RTI) 2.7 nV/√Hz 1 dB Compression Point (RTO) 15.4 dBm 240 MHz Second/Third Harmonic Distortion R = 1 kΩ, V = 2 V p-p −82/−76 dBc L OUT R = 200 Ω, V = 2 V p-p −80/−73 dBc L OUT Output Third-Order Intercept R = 200 Ω, f = 239.5 MHz, f = 240.5 MHz 36 dBm L 1 2 Third-Order IMD R = 1 kΩ, f = 239.5 MHz, f = 240.5 MHz, −85 dBc L 1 2 V = 2 V p-p composite OUT R = 200 Ω, f = 239.5 MHz, f = 240.5 MHz, −77 dBc L 1 2 V = 2 V p-p composite OUT Noise Spectral Density (RTI) 2.7 nV/√Hz 1 dB Compression Point (RTO) 15.3 dBm 380 MHz Second/Third Harmonic Distortion2 R = 1 kΩ, V = 2 V p-p −72/−68 dBc L OUT R = 200 Ω, V = 2 V p-p −74/−69 dBc L OUT Output Third-Order Intercept R = 200 Ω, f = 379.5 MHz, f = 380.5 MHz 33 dBm L 1 2 Third-Order IMD R = 1 kΩ, f = 379.5 MHz, f = 380.5 MHz, −74 dBc L 1 2 V = 2 V p-p composite OUT R = 200 Ω, f = 379.5 MHz, f = 380.5 MHz, −70 dBc L 1 2 V = 2 V p-p composite OUT Noise Spectral Density (RTI) 2.7 nV/√Hz 1 dB Compression Point (RTO) 14.6 dBm 500 MHz Second/Third Harmonic Distortion2 R = 200 Ω, V = 2 V p-p −71/−64 dBc L OUT Output Third-Order Intercept R = 200 Ω, f = 499.5 MHz, f = 500.5 MHz 28 dBm L 1 2 Third-Order IMD R = 200 Ω, f = 499.5 MHz, f = 500.5 MHz, −61 dBc L 1 2 V = 2 V p-p composite OUT Noise Spectral Density (RTI) 2.7 nV/√Hz 1 dB Compression Point (RTO) 13.9 dBm 1 When using the evaluation board at frequencies below 50 MHz, replace the Output Balun T1 with a transformer, such as Mini-Circuits® ADT1-1WT to obtain the low frequency balance required for differential HD2 cancellation. 2 CD and RD can be optimized for broadband operation below 180 MHz. For operation above 300 MHz, CD and RD components are not required. Rev. C | Page 5 of 19

AD8352 Data Sheet ABSOLUTE MAXIMUM RATINGS ESD CAUTION Table 3. Parameter Rating Supply Voltage, VCC 5.5 V VIP, VIN VCC + 0.5 V Internal Power Dissipation 210 mW θJA 91.4°C/W Maximum Junction Temperature 125°C Operating Temperature Range −40°C to +85°C Storage Temperature Range −65°C to +150°C Lead Temperature (Soldering 60 sec) 300°C Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. Rev. C | Page 6 of 19

Data Sheet AD8352 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS VIP ENB VCM VCC 6 5 4 3 1 1 1 1 RDP 1 12 GND RGP 2 AD8352 11 VOP RGN 3 TOP VIEW 10 VON (Not to Scale) RDN 4 9 GND 5 6 7 8 N D D C VI GN GN VC NOTES 1.THE EXPOSED PAD MUST BE CLTOHOEWNRN IMEMACPLTELEDYDA ANTNOCDE G EPRLAOETUCHNT, DRB IOVCITAAHL ALY. 05728-003 Figure 3. Pin Configuration Table 4. Pin Function Descriptions Pin No. Mnemonic Description 1 RDP Positive Distortion Adjust. 2 RGP Positive Gain Adjust. 3 RGN Negative Gain Adjust. 4 RDN Negative Distortion Adjust. 5 VIN Balanced Differential Input. This pin is biased to VCM, typically ac-coupled. 6, 7, 9, 12 GND Ground. Connect this pin to low impedance GND. 8, 13 VCC Positive Supply. 10 VON Balanced Differential Output. This pin is biased to VCM, typically ac-coupled. 11 VOP Balanced Differential Output. This pin is biased to VCM, typically ac-coupled. 14 VCM Common-Mode Voltage. A voltage applied to this pin sets the common-mode voltage of the input and output. Typically decoupled to ground with a 0.1 µF capacitor. With no reference applied, input and output common mode floats to midsupply (VCC/2). 15 ENB Enable. Apply positive voltage (1.3 V < ENB < VCC) to activate device. 16 VIP Balanced Differential Input. This pin is biased to VCM, typically ac-coupled. EPAD Exposed Pad. The exposed pad must be connected to ground via a low impedance path, both thermally and electrically. Rev. C | Page 7 of 19

AD8352 Data Sheet TYPICAL PERFORMANCE CHARACTERISTICS 25 30 20 25 RG=20Ω RG=43Ω 20 15 B) RG=100Ω B) 15 RG=100Ω d d N ( 10 N ( AI AI RG=182Ω G RG=520Ω G 10 5 RG=383Ω 5 RG=715Ω 0 0 –5 –5 10 100FREQUENCY(MHz)1k 10k 05728-036 10 100FREQUENCY(MHz)1k 10k 05728-039 Figure 4. Gain vs. Frequency for a 200 Ω Differential Load with Baluns, Figure 7. Gain vs. Frequency for a 1 kΩ Differential Load Without Baluns, AV = 18 dB, 12 dB, and 6 dB RD/CD Open, AV = 25 dB, 14 dB, 10 dB, 6 dB, and 3 dB 25 13.0 11.0 RL = 1kΩ 12.5 –40°C RG = 182Ω 10.5 20 TC = 0.002dB/°C RG=62Ω 12.0 10.0 +85°C 11.5 +25°C 9.5 15 B) RG=190Ω B) 11.0 9.0 B) AIN (d 10 AIN (d 10.5 –40°C 8.5 AIN (d G RG=3kΩ G 10.0 8.0 G 5 9.5 +85°C 7.5 RL = 200Ω +25°C 0 9.0 RG = 118Ω 7.0 TC = 0.004dB/°C 8.5 6.5 –5 8.0 6.0 10 100FREQUENCY(MHz)1k 10k 05728-037 10 100FREQUENCY (MHz)1k 10k 05728-040 Figure 5. Gain vs. Frequency for a 1 kΩ Differential Load with Baluns, Figure 8. Gain vs. Frequency over Temperature (−40°C, +25°C, +85°C) AV = 18 dB, 12 dB, and 6 dB Without Baluns, AV = 10 dB, RL = 200 Ω and 1 kΩ 25 80 20 RG=19Ω 70 RL=200Ω 60 15 RG=64Ω N (dB) 10 RG=118Ω R (dB) 50 RL=1kΩ GAI RG=232Ω CMR 40 5 30 RG=392Ω 0 20 –510 100FREQUENCY(MHz)1k 10k 05728-038 1010 FREQUE1N0C0Y(MHz) 1000 05728-043 Figure 6. Gain vs. Frequency for a 200 Ω Differential Load Without Baluns, Figure 9. CMRR vs. Frequency, RL = 200 Ω and 1 kΩ, RD/CD Open, AV = 22 dB, 14 dB, 10 dB, 6 dB, and 3 dB Differential Source Resistance Rev. C | Page 8 of 19

Data Sheet AD8352 50 5.0 16.5 m) 45 OIP3 4.5 V/ Hz) 16.0 70MHz 100MHz 140MHz 3 (dB 40 AV= 10dB 4.0 RTI (n m) 15.5 NOISE FIGURE (dB), OIP 32320055 NAOVIS=E 1 F0IdGBURAEV= 6dABV= 10dB AV= 15dB 3232....0055 CTRAL NOISE DENSITY OUTPUT P1dB (dB 111544...005 3805M00HMzHz 240MH1z90MHz E 11500 50 100 150 FR20E0QUE2N50CY (3M0H0z)350 400 450 50011..50 SP05728-049 1133..500 50 100GA1I5N0 SET2T0I0NG R2E5S0ISTO30R0 (Ω)350 400 45005728-051 Figure 10. Noise Figure, OIP3, and Spectral Noise Density vs. Figure 13. Output 1 dB Compression Point (P1dB) vs. Frequency, 2 V p-p Composite, RL = 200 Ω RG for Multiple Frequencies, RL = 200 Ω 45 –60 70MHz 140MHz 100MHz –65 40 190MHz c) –70 HD3 B d 240MHz ON ( –75 m) 35 380MHz RTI –80 HD2 B O P3 (d DIST –85 OI 30 500MHz NIC –90 O M –95 R A 25 H –100 20 05728-050 ––110150 0 50 100GAIN 1S5E0TTIN2G0 0RESIS2T5O0R (Ω3)00 350 400 0 50 100 150 FR2E00QUE2N5C0Y(3M0H0z) 350 400 450 500 05728-005 Figure 11. Output IP3 (OIP3) vs. RG for Multiple Frequencies, RL = 200 Ω Figure 14. Harmonic Distortion vs. Frequency for 2 V p-p into RL = 1 kΩ, AV = 10 dB, 5 V Supply, RG = 180 Ω, RD = 6.8 kΩ, CD = 0.1 pF –60 –50 >300MHzNOCD ORRDUSED –65 –60 Bc) Bc) ON (d –70 2HVDp3-p ON (d –70 HD3 RTI RTI O O ST –75 HD2 ST –80 DI 2Vp-p DI HD2 C C NI NI O –80 O –90 M M R R HA HD3 HA –85 1Vp-p –100 –90 220 260 300FRE3Q4U0ENCY38(0MHz)420 460 500 05728-009 –1100 50 100 F15R0EQUE2N0C0Y(M2H5z0) 300 350 400 05728-007 Figure 12. Third-Order Harmonic Distortion (HD3) vs. Frequency, Figure 15. Harmonic Distortion vs. Frequency for 2 V p-p into RL = 200 Ω, AV = 10 dB, RL = 200 Ω AV = 10 dB, RG = 115 Ω, RD = 4.3 kΩ, CD = 0.2 pF Rev. C | Page 9 of 19

AD8352 Data Sheet 0.6 0 1.5 tRISE (10/90) = 215ps tFALL (10/90) = 210ps 0.5 –20 1.0 GROUP DELAY (ns) 000...432 –––468000 PHASE (Degrees) VOLTAGE (V) –00..550 0.1 –100 –1.0 00 100 200 300 FR4E00QUE5N0C0Y(6M0H0z) 700 800 900 100–0120 05728-042 –1.50 0.5 1.0 TIME1 .(5nsec) 2.0 2.5 3.0 05728-046 Figure 16. Group Delay and Phase vs. Frequency, AV = 10 dB, RL = 200 Ω Figure 19. Large Signal Output Transient Response, RL = 200 Ω, AV = 10 dB 3500 0 5 4 3000 –0.05 3 E (Ω) 2500 –0.10 E (pF) 2 SISTANC 2000 –0.15 ACITANC LING (%) 10 UT RE 1500 –0.20 T CAP SETT –1 P U IN 1000 –0.25 NP –2 I –3 500 –0.30 –4 00 100 200 300 FR40E0QUE5N00CY (6M0H0z)700 800 900 1000–0.35 05728-052 –50 0.5 1.0 1.5TIME2.(0nsec)2.5 3.0 3.5 4.0 05728-047 Figure 17. S11 Equivalent RC Parallel Network, RG = 115 Ω Figure 20. 1% Settling Time for a 2 V p-p Step Response, AV = 10 dB, RL = 200 Ω 160 0.7 6 25 140 0.6 Hz) V/ 5 OUTPUT RESISTANCE (Ω) 110268400000 00000.....54231OUTPUT CAPACITANCE (pF) TRAL NOISE DENSITY RTI (n 342 112050NOISE FIGURE (dB) C E 1 20 0 SP 00 100 200 300 FR40E0QUE5N00CY (6M0H0z)700 800 900 1000–1.0 05728-053 00 50 100GAIN1 S5E0TTIN2G0 0RESIS2T50OR (Ω3)00 350 4005 05728-054 Figure 18. S22 Equivalent RC Parallel Network, RG = 115 Ω Figure 21. Spectral Noise Density RTI and Noise Figure vs. RG, RL = 200 Ω Rev. C | Page 10 of 19

Data Sheet AD8352 APPLICATIONS INFORMATION GAIN AND DISTORTION ADJUSTMENT Table 6. Broadband Selection of R , C , and R , 1 kΩ Load (DIFFERENTIAL INPUT) G D D A (dB) R (Ω) C (pF) R (kΩ) V G D D Table 5 and Table 6 show the required value of R for the gains G 3 750 Open 6.8 specified at 200 Ω and 1 kΩ loads. Figure 22 and Figure 24 plot 6 360 Open 6.8 gain vs. R up to 18 dB for both load conditions. For other output G 9 210 Open 6.8 loads (R), use Equation 1 to compute gain vs. R . L G 10 180 0.05 6.8  R +500  12 130 0.1 6.8 AVDifferential= (R +5)(GR +53)+430RL (1) 15 82 0.3 6.8 G L 18 54 0.5 6.8 where R is the single-ended load. 20 L RG is the gain setting resistor. 18 The third-order harmonic distortion can be reduced by using 16 external components RD and CD. Table 5 and Table 6 show the 14 required values for R and C for the specified gains to achieve D D B) 12 (single tone) third-order distortion reduction at 180 MHz. d N ( 10 Figure 23 and Figure 25 show any gain (up to 18 dB) vs. CD for GAI 8 200 Ω and 1 kΩ loads, respectively. When these values are selected, they result in minimum single tone, third-order distortion at 6 180 MHz. This frequency point provides the best overall broad- 4 band distortion for the specified frequencies below and above 2 this value. For applications above ~300 MHz, C and R are D D 0 nhaort mreoqnuiicr epdlo. tSse feo trh me oSpree cdiefitcaailtsi o(nsese s Fecigtiuorne a1n2d, F tihgeu trhe i1rd4-, oarndde r 0 50 100 150 R2G0(0Ω) 250 300 350 400 05728-026 Figure 15). Figure 22. Gain vs. RG, RL = 200 Ω 20 C can be further optimized for narrow-band tuning requirements D below 180 MHz that result in relatively lower third-order (in- 18 band) intermodulation distortion terms. See the Narrow-Band, 16 Third-Order Intermodulation Cancellation section for more 14 information. Though not shown, single tone, third-order B) 12 optimization can also be improved for narrow-band frequency d N ( 10 applications below 180 MHz with the proper selection of CD, AI G and 3 dB to 6 dB of relative third-order improvement can be 8 realized at frequencies below approximately 140 MHz. 6 Using the information listed in Table 5 and Table 6, an extrapolated 4 value for RD can be determined for loads between 200 Ω and 1 kΩ. 2 For loads above 1 kΩ, use the 1 kΩ RD values listed in Table 6. 0 Table 5. Broadband Selection of RG, CD, and RD, 200 Ω Load 0 0.1 0.2 0.3 0.4 CD0.(5pF) 0.6 0.7 0.8 0.9 1.0 05728-027 AV (dB) RG (Ω) CD (pF) RD (kΩ) Figure 23. Gain vs. CD, RL = 200 Ω 3 390 Open 6.8 6 220 Open 4.3 9 140 0.1 4.3 10 115 0.2 4.3 12 86 0.3 4.3 15 56 0.6 4.3 18 35 1 4.3 Rev. C | Page 11 of 19

AD8352 Data Sheet 20 Figure 27 plots gain vs. RG for 200 Ω and 1 kΩ loads. Table 7 18 and Table 8 show the values of C and R required (for 180 MHz D D 16 broadband, third-order, single tone optimization) for 200 Ω and 1 kΩ loads, respectively. This single-ended configuration provides 14 −3 dB bandwidths similar to input differential drive. Figure 28 dB) 12 through Figure 31 show distortion levels at a gain of 12 dB for AIN ( 10 both 200 Ω and 1 kΩ loads. Gains from 3 dB to 18 dB, using G 8 optimized C and R values, obtain similar distortion levels. D D 6 4 0.1µF VIP 0.1µF 2 65Ω RGP 00 100 200 300 R4G0(0Ω) 500 600 700 800 05728-028 50Ω 0.1µF CD RD RG RGAND8352 AC 20 Figure 24. Gain vs. RG, RL = 1 kΩ 25Ω 20R0NΩ 0.1µF 05728-024 18 Figure 26. Single-Ended Schematic 16 40 14 B) 12 35 d AIN ( 10 30 G 8 25 6 B) 4 AIN (d 20 GAIN,RL=1kΩ G 2 15 GAIN,RL=200Ω 0 0 0.1 0.2 CD(pF) 0.3 0.4 0.5 05728-029 105 Figure 25. Gain vs. CD, RL = 1 kΩ 0 SINGLE-ENDED INPUT OPERATION 1 10 R1G0(0Ω) 1k 10k 05728-020 The AD8352 can be configured as a single-ended-to-differential Figure 27. Gain vs. RG amplifier, as shown in Figure 26. To balance the outputs when driving the VIP input, an external resistor (R ) of 200 Ω is added N –60 between VIP and RGN. See Equation 2 to determine the single- ended input gain (A ) for a given R or R. V Single-Ended G L –70 2V p-p OUT  R +500  R AVSingle−Ended=(RG+5)(GRL+53)+430 RL+RL+L30 (2) c) –80 1V p-p OUT B where 2 (d D RL is the single-ended load. H –90 R is the gain setting resistor. G –100 –110 10 70 FREQUE1N4C0Y (MHz) 190 240 05728-021 Figure 28. Single-Ended, Second-Order Harmonic Distortion (HD2) vs. Frequency, 200 Ω Load Rev. C | Page 12 of 19

Data Sheet AD8352 This broadband optimization was also performed at 180 MHz. Table 7. Distortion Cancellation Selection Components As with differential input drive, the resulting distortion levels (R and C ) for Required Gain, 200 Ω Load D D at lower frequencies are based on the CD and RD specified in AV (dB) RG (Ω) CD (pF) RD (kΩ) Table 7 and Table 8. As with differential input drive, relative 3 4.3 k Open 4.3 third-order reduction improvement at frequencies below 6 540 Open 4.3 140 MHz is realized with proper selection of CD and RD. 9 220 0.1 4.3 –60 12 120 0.3 4.3 15 68 0.6 4.3 18 43 0.9 4.3 –70 2V p-p OUT Table 8. Distortion Cancellation Selection Components c) –80 dB (RD and CD) for Required Gain, 1 kΩ Load HD3 ( –90 1V p-p OUT AV (dB) RG (Ω) CD (pF) RD (kΩ) 6 3 k Open 4.3 9 470 Open 4.3 –100 12 210 0.2 4.3 15 120 0.3 4.3 18 68 0.5 4.3 –110 10 70 FREQUE1N4C0Y (MHz) 190 240 05728-022 NARROW-BAND, THIRD-O RDER Figure 29. Single-Ended, Third-Order Harmonic Distortion (HD3) vs. INTERMODULATION CANCELLATION Frequency, 200 Ω Load –60 Broadband single tone, third-order harmonic optimization does not necessarily result in optimum (minimum) two tone, third- order intermodulation levels. The specified values for C and –70 D R in Table 5 and Table 6 were determined for minimizing D broadband, single tone third-order levels. Bc) –80 Due to phase-related distortion coefficients, optimizing single d 2V p-p OUT 2 ( tone third-order distortion does not result in optimum in-band D H –90 (2f − f and 2f − f), third-order distortion levels. By proper 1 2 2 1 selection of C (using a fixed 4.3 kΩ R ), IP3s of better than D D 1V p-p OUT –100 45 dBm are achieved. This results in degraded out-of-band, third-order frequencies (f + 2f, f + 2f, 3f and 3f). Thus, careful 2 1 1 2 1 2 frequency planning is required to determine the trade-offs. –110 10 70 FREQUE1N4C0Y (MHz) 190 240 05728-023 oFpigtuimrei z3e2d s ahto 3w2s MnaHrrzo, w70-b ManHdz (, 21 0M0H MzH spza, cainndg )1 8O0I PM3H lezv uelssi ng Figure 30. Single-Ended, Second-Order Harmonic Distortion (HD2) vs. the C values specified in Figure 33. These four data points (the Frequency, 1 kΩ Load D C value and associated OIP3 levels) are extrapolated to provide –60 D close estimates of OIP3 levels for any specific frequency between 30 MHz and 180 MHz. For frequencies below ~140 MHz, narrow- –70 band tuning of OIP3 results in relatively higher OIP3s (vs. the broadband results shown in Table 2 of the specifications). Though Bc) –80 2V p-p OUT not shown, frequencies below 30 MHz also result in improved 3 (d OIP3s when using proper values for CD. D H –90 1V p-p OUT –100 –110 10 70 FREQUE1N4C0Y (MHz) 190 240 05728-025 Figure 31. Single-Ended, Third-Order Harmonic Distortion (HD3) vs. Frequency, 1 kΩ Load Rev. C | Page 13 of 19

AD8352 Data Sheet 48 Refer to the Layout and Transmission Line Effects section for RL = 200Ω 47 RD = 4.3kΩ more information. The circuit in Figure 35 represents a single- CD = 0.3pF 46 ended input to differential output configuration for driving the AD9445. In this case, the input 50 Ω resistor with R (typically 45 N 200 Ω) provide the input impedance match for a 50 Ω system. m) 44 B Again, if input reflections are minimal, this impedance match is OIP3 (d 4432 AV = 16110d58dddBBBB nthoet oreuqtpuuirte vdo. lAta gfiexse tdh 2at0 0a rΩe rreeqsuisitroerd ( fRoNr) s iesc roenqdu-iorerdde tro d biastloanrtcieo n 41 cancellation. RG is the gain setting resistor for the AD8352 with the R and C components providing distortion cancellation. 40 D D The AD9445 presents approximately 2 kΩ in parallel with 39 5 pF/differential load to the AD8352 and requires a 2.0 V p-p 38 0 50 FREQUE1N0C0Y (MHz) 150 200 05728-030 fduifllf-esrceanltei aolu stipgunta lo (pVerRaEFt i=on 1. V) between VIN+ and VIN− for a Figure 32. Third-Order Intermodulation Distortion, OIP3 vs. These AD8352 simplified circuits provide the gain, isolation, Frequency for Various Gain Settings and distortion performance necessary for efficiently driving 6.0 5.5 RRLD == 240.30kΩΩ hprigohvi dliense baariltayn cceodn voeurttpeurtss, wsuhcehth aesr tdhrei vAenD d9i4f4fe5r.e nTthiaisll yd eovr iscien galles-o 5.0 ended, thereby maintaining excellent second-order distortion 4.5 levels. However, at frequencies above ~100 MHz, due to phase- 4.0 related errors, single-ended, second-order distortion is relatively C (pF)D 332...505 AV = 1610d5ddBBB ohpigthimeru. mTh ceo omumtpount -omf tohdee a smetptilnifgie art i tsh aec -AcDouCp liendp utot. aIlnlopwut faocr an 18dB coupling can be required if the source also requires a common- 2.0 mode voltage that is outside the optimum range of the AD8352. 1.5 A VCM common-mode pin is provided on the AD8352 that 1.0 equally shifts both input and output common-mode levels. 0.5 Increasing the gain of the AD8352 increases the system noise and, 0 30 50 70 F9R0EQUE1N1C0Y (M1H3z0) 150 170 190 05728-031 tohf uths,e d AecDre9a4s4e5s wthhee SnN nRo (f3il.t5e rdinBg a its 1 u0s0e dM. HNoz tien tphuatt faomr Aplvi f=ie r1 0g adiBn)s Figure 33. Narrow-Band CD vs. Frequency for Various Gain Settings from 3 dB to 18 dB, with proper selection of C and R , do not D D HIGH PERFORMANCE ADC DRIVING appreciably affect distortion levels. These circuits, when configured properly, can result in SFDR performance of better than 87 dBc The AD8352 provides the gain, isolation, and balanced low at 70 MHz and 82 dBc at 180 MHz input. Single-ended drive, with distortion output levels for efficiently driving wideband ADCs appropriate C and R , give similar results for SFDR and third- such as the AD9445. D D order intermodulation levels shown in these figures. Figure 34 and Figure 35 (single and differential input drive) Placing antialiasing filters between the ADC and the amplifier illustrate the typical front-end circuit interface for the AD8352 is a common approach for improving overall noise and broad- differentially driving the AD9445 14-bit ADC at 105 MSPS. The band distortion performance for both band-pass and low-pass AD8352, when used in the single-ended configuration, shows little applications. For high frequency filtering, matching to the filter or no degradation in overall third-order harmonic performance is required. The AD8352 maintains a 100 Ω output impedance (vs. differential drive). See the Single-Ended Input Operation well beyond most applications and is well-suited to drive most section. The 100 MHz FFT plots shown in Figure 36 and Figure 37 filter configurations with little or no degradation in distortion. display the results for the differential configuration. Though not shown, the single-ended, third-order levels are similar. The 50 Ω resistor shown in Figure 34 provides a 50 Ω differential input impedance to the source for matching considerations. When the driver is less than one eighth of the wavelength from the AD8352, impedance matching is not required thereby negating the need for this termination resistor. The output 24 Ω resistors provide isolation from the analog-to-digital input. Rev. C | Page 14 of 19

Data Sheet AD8352 VCC 0 SNR = 61.98dBc –10 NOISE FLOOR = –111.2dB 0.1µF –20 FFUUNNDD12 == ––77..007423ddBBFFSS 0.1µF –30 IMD (2F2-F1) = –89dBc 0Ω16 IMD (2F1-F2) = –88dBc 8, 13 –40 1 11 0.1µF 24Ω S) –50 IF/RF INPUT 2 dBF –60 ADT1-1WT 50Ω CD RD RG3 AD8352 AD9445 LITUDE ( –––789000 45 10 0.1µF 24Ω AMP –100 14 –110 0.1µF 0Ω 0.1µF 05728-012 ––112300 Figure 34. Differential Input to the AD8352 Driving the AD9445 –140 –150 0.1µF VIP VOP 0.1µF 33Ω 0 5.25 10.50 15.75F2R1E.0Q0U2E6N.2C5Y 3(M1.H50z)36.75 42.00 47.25 52.50 05728-035 Figure 37. Two Tone Distortion AD8352 Driving AD9445, 50Ω 50Ω VIN+ Encode Clock at 105 MHz with fC at 100 MHz (AV = 10 dB), Analog In = 98 MHz and 101 MHz, See Figure 34 AC CD RD RG AD8352 AD9445 VIN VIN– LAYOUT AND TRANSMISSION LINE EFFECTS 33Ω VON High Q inductive drives and loads, as well as stray transmission 0.1µF 0.1µF 25Ω 20R0NΩ 05728-033 lpinotee cnatpiaalclyit faonrcme ian r ceosomnbainnta ctiiorcnu witi atht hpiagchk afrgeeq puaernacsiietisc rse, scualnti ng Figure 35. Single-Ended Input to the AD8352 Driving the AD9445 in excessive gain peaking or possible oscillation. If RF transmission 0 SNR = 67.26dBc lines connecting the input or output are used, they should be –10 SFDR = 83.18dBc –20 NOISE FLOOR = –110.5dB designed such that stray capacitance at the input/output pins is FUND = –1.074dBFS –30 SECOND = –83.14dBc minimized. In many board designs, the signal trace widths should –40 THIRD = –85.39dBc be minimal where the driver/ receiver is more than one-eighth S) –50 F of the wavelength from the AD8352. This nontransmission line dB –60 E ( –70 configuration requires that underlying and adjacent ground and D U –80 low impedance planes be dropped from the signal lines. In a T PLI –90 similar fashion, stray capacitance should be minimized near the AM –100 R , C , and R components and associated traces. This also –110 G D D –120 requires not placing low impedance planes near these components. –130 Refer to the evaluation board layout (Figure 39 and Figure 40) –140 for more information. Excessive stray capacitance at these nodes –150 0 5.25 10.50 15.75F2R1E.0Q0U2E6N.2C5Y 3(M1.H50z)36.75 42.00 47.25 52.50 05728-034 rdeescuoltusp inlin ugn wcaapnatceidt ohrisg hn efreedq utoe nbcey c dloissteo rtoti otnh.e T ahmep 0l.i1f iμeFr. sTuhpipsl y Figure 36. Single Tone Distortion AD8352 Driving AD9445, includes Signal Capacitor C2 through Signal Capacitor C5. Encode Clock at 105 MHz with fC at 100 MHz (AV = 10 dB), See Figure 34 Parasitic suppressing resistors (R5, R6, R7, and R11) can be used at the device input/output pins. Use 25 Ω series resistors (Size 0402) to adequately de-Q the input and output system from most parasitics without a significant decrease in gain. In general, if proper board layout techniques are used, the suppression resistors are not necessarily required. Output Parasitic Suppression Resistor R7 and Output Parasitic Suppression Resistor R11 can be required for driving some switch capacitor ADCs. These suppressors, with Input C of the converter (and possibly added External Shunt C), help provide charge kickback isolation and improve overall distortion at high encode rates. Rev. C | Page 15 of 19

AD8352 Data Sheet EVALUATION BOARD An evaluation board is available for experimentation of various parameters such as gain, common-mode level, and distortion. The output network can be configured for different loads via minor output component changes. The schematic and evaluation board artwork are shown in Figure 38, Figure 39, and Figure 40. All discrete capacitors and resistors are Size 0402, except for C1 (3528-B). Table 9. Evaluation Board Circuit Components and Functions Additional Component Name Function Information C8, C9, C10 Capacitors C8, C9, and C10 are bypass capacitors. C8 = C9 = C10 = 0.1 µF R , C Distortion Distortion Adjustment Components. Allows for third-order distortion Typically, both are open D D tuning adjustment HD3. above 300 MHz components C = 0.2 pF, R = 4.32 kΩ D D C is Panasonic High-Q D (microwave) multilayer chip 402 capacitor R1, R2, R3, Resistors, Input Interface. R1 and R4 ground one side of the differential drive interface R1 = open, R2 = 25 Ω, R4, R5, R6, transformer, for single-ended applications. T2 is a 1-to-1 impedance ratio balun to transform a R3 = 25 Ω, R4 = 0 Ω, T2, C2, C3 capacitors single-ended input into a balanced differential signal. R2 and R3 provide R5 = 0 Ω, R6 = 0 Ω, a differential 50 Ω input termination. R5 and R6 can be increased to reduce T2 = M/A-COM ETC1-1-13, gain peaking when driving from a high source impedance. The 50 Ω C2 = 0.1 μF, C3 = 0.1 μF termination provides an insertion loss of 6 dB. C2 and C3 provide ac-coupling. R7, R8, R9, Resistors, Output Interface. R13 and R14 ground one side of the differential output R7 = 0 Ω, R8 = 86.6 Ω, R11, R12, transformer, interface for single-ended applications. T1 is a 1-to-1 impedance ratio balun to R9 = 57.6 Ω, R11 = 0 Ω, R13, R14, capacitors transform a balanced differential signal to a single-ended signal. R8, R9, and R12 = 86.6 Ω, R13 = 0 Ω, T1, C4, C5 R12 are provided for generic placement of matching components. R7 and R14 = open, R11 allow additional output series resistance when driving capacitive loads. T1 = M/A-COM ETC1-1-13, The evaluation board is configured to provide a 200 Ω to 50 Ω impedance C4 = 0.1 µF, C5 = 0.1 µF transformation with an insertion loss of 11.6 dB. C4 and C5 provide ac-coupling. R7 and R11 provide additional series resistance when driving capacitive loads. R Resistor Gain Setting Resistor. Resistor R is used to set the gain of the device. Refer R = 115 Ω (Size 0402) for G G G to Table 5 and Table 6 when selecting the gain resistor. a gain of 10 dB SW1, R18, Switch, Enable Interface. R10 connects the enable pin, ENB, to the supply for constant SW1 = installed R19, R20 resistors enable operation. The enable function can be toggled by removing R10 and R18 = R19 = R20 = 0 Ω using SW1 to switch between enable and disable modes. C1, C6, C7 Capacitors Power Supply Decoupling. The supply decoupling consists of a 10 µF capacitor C1 = 10 µF, C6 = 0.1 µF, (C1) to ground. C6 and C7 are bypass capacitors. C7 = 0.1 µF T3, T4, Transformer, Calibration Circuit. T3 and T4 are dummy baluns, which can be used to T3 = T4 = M/A-COM ETC1-1-13 C11, C12 capacitors calibrate the insertion loss across the transformers in the AD8352 signal chain. C11 = C12 = 0.1 µF EVALUATION BOARD LOADING SCHEMES Table 10. Values Used for 200 Ω and 1000 Ω Loads The AD8352 evaluation board is characterized with two load Component 200 Ω Load (Ω) 1000 Ω Load (Ω) configurations representing the most common ADC input R8 86.6 487 resistance. The loads chosen are 200 Ω and 1000 Ω using a R9 57.6 51.1 broadband resistive match. The loading can be changed via R8, R12 86.6 487 R9, and R12 giving the flexibility to characterize the AD8352 evaluation board for the load in any given application. These SOLDERING INFORMATION loads are inherently lossy and must be accounted for in overall On the underside of the chip scale package, there is an exposed gain/loss for the entire evaluation board. Measure the gain of compressed paddle. This paddle is internally connected to the the AD8352 with an oscilloscope using the following procedure ground of the chip. Solder the paddle to the low impedance to determine the actual gain: ground plane on the PCB to ensure the specified electrical 1. Measure the peak-to-peak voltage at the input node (C2 or C3). performance and to provide thermal relief. To further reduce 2. Measure the peak-to-peak voltage at the output node (C4 or C5). thermal impedance, it is recommended that the ground planes 3. Compute gain using the following formula: on all layers under the paddle be stitched together with vias. Gain = 20log(VOUT/VIN) Rev. C | Page 16 of 19

Data Sheet AD8352 EVALUATION BOARD SCHEMATICS P N 710-82750 T T U U O O V V R14OPEN 1 T1 3 M/A_COMETC1-1-13 R130Ω Ω TRACES 0 5 2 5 4 9Ω R6 CK R886.6Ω 57. R1286.6Ω VPOS A L GND B C40.1µF C50.1µF CUIT C70.1µF DUT R R VPOS R70Ω R110Ω PASS CI C60.1µF APS NEA Y C VCM YELLOW C10CM0.1µF C90.1µFR200Ω MBCNCCEVV 151413GND12 VOP11 Z1VON10AD8352GND9678DDCNNCVGG VPOS DANCE TRACESS UNDER TRACES) BVPOS RED +C110µF LOCATE VSPDT ENB VIP 16RDP1 RGP2 RGN3 RDN4 5 VIN HIGH IMPEPEN PLANE SWITCH_ SW1 C80.1µF RG115Ω (O J2 5Ω 6Ω 1 T43 R0 R0 W O L 2 ENBL R19YEL0Ω R180Ω C20.1µF RCDDpF4.32kΩ C30.1µF ATION CIRCUIT C110.1µF5 C1240.1µF 0.2 BR S R225Ω R325Ω CALI 1 T33 O VP 2 4 5 5 4 2 R1OPEN 3 T2 1 M/A_COMETC1-1-13 R40Ω 0Ω TRACES J1 5 P N N N VI VI Figure 38. AD8352 Evaluation Board, Version A01212A Rev. C | Page 17 of 19

AD8352 Data Sheet 05728-018 Figure 39. Component Side Silkscreen 05728-019 Figure 40. Far Side Showing Ground Plane Pull Back Around Critical Features Rev. C | Page 18 of 19

Data Sheet AD8352 OUTLINE DIMENSIONS DETAIL A 3.10 0.30 (JEDEC 95) 3.00 SQ 0.23 PIN 1 2.90 0.18 INDICATOR B0.S5C0 1213 16 1 (PISNIENDE ID1CAETTAOILR A A)REA OPTIONS 1.75 EXPPAODSED 1.60 SQ 1.45 9 4 0.50 8 5 0.20 MIN TOP VIEW 0.40 BOTTOM VIEW 0.30 0.80 FOR PROPER CONNECTION OF 0.75 SIDE VIEW THE EXPOSED PAD, REFER TO 0.05 MAX THE PIN CONFIGURATION AND 0.70 0.02 NOM FUNCTION DESCRIPTIONS COPLANARITY SECTION OF THIS DATA SHEET. SEATING 0.08 PLANE 0.20 REF PKG-005138 COMPLIANTTOJEDEC STANDARDS MO-220-WEED-6. 02-23-2017-E Figure 41. 16-Lead Lead Frame Chip Scale Package [LFCSP] 3 mm × 3 mm Body and 0.75 mm Package Height (CP-16-22) Dimensions shown in millimeters ORDERING GUIDE Model1 Temperature Range Package Description Ordering Quantity Package Option Marking Code AD8352ACPZ-WP −40°C to +85°C 16-Lead LFCSP, Waffle Pack 50 CP-16-22 Q0R AD8352ACPZ-R7 −40°C to +85°C 16-Lead LFCSP, 7” Tape and Reel 3,000 CP-16-22 Q0R AD8352ACPZ-R2 −40°C to +85°C 16-LeadLFCSP, 7” Tape and Reel 250 CP-16-22 Q0R AD8352-EVALZ Evaluation Board 1 Z = RoHS Compliant Part. ©2006–2018 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D05728-0-4/18(C) Rev. C | Page 19 of 19