50 MHz to 1000 MHz Quadrature Demodulator AD8348 FEATURES FUNCTIONAL BLOCK DIAGRAM Integrated I/Q demodulator with IF VGA amplifier VREF IMXO IOFS IAIN IOPP IOPN 14 8 13 6 4 3 Operating IF frequency 50 MHz to 1000 MHz (3 dB IF BW of 500 MHz driven from RS = 200 Ω) ENBL15 CBEIALSL VREF 5 VCMO Demodulation bandwidth 75 MHz VCMO Linear-in-decibel AGC range 44 dB DIVIDE 1 LOIP IFIP11 BY 2 Third-order intercept IFIN10 SPPLHIATSTEER IIP3 +28 dBm @ minimum gain (F = 380 MHz) 28LOIN IF AD8348 IIP3 −8 dBm @ maximum gain (F = 380 MHz) IF Quadrature demodulation accuracy VGIN17 COGNATIRNOL VCMO PAhmapslei taucdceu rbaaclya n0c.5e° 0 .25 dB M1X8IP M1X9IN EN2V4G QX2M1O QO16FS QA23IN QO25PP QO26PN 03678-001 Figure 1. Noise figure 11 dB @ maximum gain (F = 380 MHz) IF LO input −10 dBm Single supply 2.7 V to 5.5 V Power-down mode Compact, 28-lead TSSOP package APPLICATIONS QAM/QPSK demodulator W-CDMA/CDMA/GSM/NADC Wireless local loop LMDS GENERAL DESCRIPTION The AD8348 is a broadband quadrature demodulator with an Separate I- and Q-channel baseband amplifiers follow the baseband integrated intermediate frequency (IF), variable gain amplifier outputs of the mixers. The voltage applied to the VCMO pin sets (VGA), and integrated baseband amplifiers. It is suitable for use in the dc common-mode voltage level at the baseband outputs. communications receivers, performing quadrature demodulation Typically, VCMO is connected to the internal VREF voltage, but from IF directly to baseband frequencies. The baseband amplifiers it can also be connected to an external voltage. This flexibility are designed to interface directly with dual-channel ADCs, such allows the user to maximize the input dynamic range to the ADC. as the AD9201, AD9283, and AD9218, for digitizing and post- Connecting a bypass capacitor at each offset compensation input processing. (IOFS and QOFS) nulls dc offsets produced in the mixer. Offset compensation can be overridden by applying an external voltage The IF input signal is fed into two Gilbert cell mixers through at the offset compensation inputs. an X-AMP® VGA. The IF VGA provides 44 dB of gain control. A precision gain control circuit sets a linear-in-decibel gain char- The mixers’ outputs are brought off-chip for optional filtering acteristic for the VGA and provides temperature compensation. before final amplification. Inserting a channel selection filter The LO quadrature phase splitter employs a divide-by-2 frequency before each baseband amplifier increases the baseband amplifiers’ divider to achieve high quadrature accuracy and amplitude balance signal handling range by reducing the amplitude of high level, over the entire operating frequency range. out-of-channel interferers before the baseband signal is fed into the I/Q baseband amplifiers. The single-ended mixer output is Optionally, the IF VGA can be disabled and bypassed. In this amplified and converted to a differential signal for driving ADCs. mode, the IF signal is applied directly to the quadrature mixer inputs via the MXIP and MXIN pins. Rev. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Tel: 781.329.4700 www.analog.com Trademarks and registered trademarks are the property of their respective owners. Fax: 781.461.3113 ©2006 Analog Devices, Inc. All rights reserved.

AD8348 TABLE OF CONTENTS Features..............................................................................................1 Enable...........................................................................................18 Applications.......................................................................................1 Baseband Offset Cancellation...................................................18 Functional Block Diagram..............................................................1 Applications.....................................................................................20 General Description.........................................................................1 Basic Connections......................................................................20 Revision History...............................................................................2 Power Supply...............................................................................20 Specifications.....................................................................................3 Device Enable.............................................................................20 Absolute Maximum Ratings............................................................6 VGA Enable................................................................................20 ESD Caution..................................................................................6 Gain Control...............................................................................20 Pin Configuration and Function Descriptions.............................7 LO Inputs.....................................................................................20 Equivalent Circuits...........................................................................9 IF Inputs......................................................................................20 Typical Performance Characteristics...........................................11 MX Inputs...................................................................................20 VGA and Demodulator.............................................................11 Baseband Outputs......................................................................21 Demodulator Using MXIP and MXIN....................................14 Output DC Bias Level................................................................21 Final Baseband Amplifiers........................................................15 Interfacing to Detector for AGC Operation...............................21 VGA/Demodulator and Baseband Amplifier.........................16 Baseband Filters..........................................................................22 Theory of Operation......................................................................18 LO Generation............................................................................23 VGA..............................................................................................18 Evaluation Board........................................................................23 Downconversion Mixers...........................................................18 Outline Dimensions.......................................................................28 Phase Splitter...............................................................................18 Ordering Guide..........................................................................28 I/Q Baseband Amplifiers...........................................................18 REVISION HISTORY 4/06—Rev. 0 to Rev. A Updated Format..................................................................Universal Changes to Specifications................................................................3 Changes to IF Inputs Section........................................................20 Changes to Evaluation Board Section..........................................23 Changes to Table 6..........................................................................27 Changes to Ordering Guide..........................................................28 8/03—Revision 0: Initial Version Rev. A | Page 2 of 28

AD8348 SPECIFICATIONS V = 5 V, T = 25oC, F = 380 MHz, F = 381 MHz, P = −10 dBm, R (LO) = 50 Ω, R (IFIP and MXIP/MXIN) = 200 Ω, unless S A LO IF LO S S otherwise noted. Table 1. Parameter Conditions Min Typ Max Unit OPERATING CONDITIONS LO Frequency Range External input = 2 × LO frequency 100 2000 MHz IF Frequency Range 50 1000 MHz Baseband Bandwidth 75 MHz LO Input Level 50 Ω source −12 −10 0 dBm V (V) 2.7 5.5 V SUPPLY S Temperature Range −40 +85 °C IF FRONT END WITH VGA IFIP to IMXO (QMXO), ENVG = 5 V, IMXO/QMXO load = 1.5 kΩ Input Impedance Measured differentially across MXIP/MXIN 200||1.1 Ω||pF Gain Control Range 44 dB Maximum Conversion Voltage Gain VGIN = 0.2 V (maximum voltage gain) 25.5 dB Minimum Conversion Voltage Gain VGIN = 1.2 V (minimum voltage gain) −18.5 dB 3 dB Bandwidth 500 MHz Gain Control Linearity VGIN = 0.4 V (+21 dB) to 1.1 V (−14 dB) ±0.5 dB IF Gain Flatness F = 380 MHz ± 5% (VGIN = 1.2 V) 0.1 dB p-p IF FIF = 900 MHz ± 5% (VGIN = 1.2 V) 1.3 dB p-p Input 1 dB Compression Point (P1dB) VGIN = 0.2 V (maximum gain) −22 dBm VGIN = 1.2 V (maximum gain) +13 dBm Second-Order Input Intercept (IIP2) IF1 = 385 MHz, IF2 = 386 MHz +3 dBm each tone from 200 Ω source, 65 dBm VGIN = 1.2 V (minimum gain) −42 dBm each tone from 200 Ω source, 18 dBm VGIN = 0.2 V (maximum gain) Third-Order Input Intercept (IIP3) IF1 = 381 MHz, IF2 = 381.02 MHz Each tone 10 dB below P1dB from 28 dBm 200 Ω source, VGIN = 1.2 V (minimum gain) Each tone 10 dB below P1dB from −8 dBm 200 Ω source, VGIN = 0.2 V (maximum gain) LO Leakage Measured at IFIP, IFIN −80 dBm Measured at IMXO/QMXO (LO = 50 MHz) −60 dBm Demodulation Bandwidth Small signal 3 dB bandwidth 75 MHz Quadrature Phase Error1 LO = 380 MHz (LOIP/LOIN 760 MHz) −0.7 ±0.1 +0.7 Degrees vs. temperature −0.0032 °/°C vs. baseband frequency (dc to 30 MHz) +0.01 °/MHz I/Q Amplitude Imbalance1 −0.3 ±0.05 +0.3 dB vs. temperature 0 dB/°C vs. baseband frequency (dc to 30 MHz) ±0.0125 dB Noise Figure (Double Sideband) Maximum gain, from 200 Ω source, 10.75 dB F = 380 MHz IF Mixer Output Impedance 40 Ω Capacitive Load Shunt from IMXO, QMXO to VCMO 0 10 pF Resistive Load Shunt from IMXO, QMXO to VCMO 200 1.5 kΩ Mixer Peak Output Current 2.5 mA Rev. A | Page 3 of 28

AD8348 Parameter Conditions Min Typ Max Unit IF FRONT END WITHOUT VGA From MXIP, MXIN to IMXO (QMXO), ENVG = 0 V, IMXO/QMXO load = 1.5 kΩ Input Impedance Measured differentially across MXIP/MXIN 200||1.5 Ω||pF Conversion voltage Gain 10.5 dB 3 dB Output Bandwidth 75 MHz IF Gain Flatness F = 380 MHZ ± 5% 0.1 dB p-p IF F = 900 MHZ ± 5% 0.15 dB p-p IF Input 1 dB Compression Point (P1dB) −4 dBm Third-Order Input Intercept (IIP3) IF1 = 381 MHz, IF2 = 381.02 MHz 14 dBm Each tone 10 dB below P1dB from 200 Ω source LO Leakage Measured at MXIP/MXIN −70 dBm Measured at IMXO, QMXO −60 dBm Demodulation Bandwidth Small signal 3 dB bandwidth 75 MHz Quadrature Phase Error LO = 380 MHz (LOIP/LOIN 760 MHz, −2 ±0.5 +2 Degrees single-ended) I/Q Amplitude Imbalance 0.25 dB Noise Figure (Double Sideband) From 200 Ω source, F = 380 MHz 21 dB IF I/Q BASEBAND AMPLIFIER From IAIN to IOPP/IOPN and QAIN to QOPP/ QOPN, R = 2 kΩ, single-ended to ground LOAD Gain 20 dB Bandwidth 10 pF differential load 125 MHz Output DC Offset (Differential) LO leakage offset corrected using 500 pF −50 ±12 +50 mV capacitor on IOFS, QOFS (V − V ) IOPP IOPN Output Common-Mode Offset (V + V )/2 − VCMO −75 ±35 +75 mV IOPP IOPN Group Delay Flatness 0 MHz to 50 MHz 3 ns p-p Input-Referred Noise Voltage Frequency = 1 MHz 8 nV/√Hz Output Swing Limit (Upper) V −1 V S Output Swing Limit (Lower) 0.5 V Peak Output Current 1 mA Input Impedance 50||1 kΩ||pF Input Bias Current 2 μA RESPONSE FROM IF AND MX INPUTS TO IMXO and QMXO connected directly to BASEBAND AMPLIFIER OUTPUT IAIN and QAIN, respectively Gain From MXIP/MXIN 30.5 dB From IFIP/IFIN, VGIN = 0.2 V 45.5 dB From IFIP/IFIN, VGIN = 1.2 V 1.5 dB CONTROL INPUT/OUTPUTS VCMO Input Range V = 5 V 0.5 1 4 V S V = 2.7 V 0.5 1 1.7 V S VREF Output Voltage 0.95 1 1.05 V Gain Control Voltage Range VGIN 0.2 1.2 V Gain Slope −55 −50 −45 dB/V Gain Intercept Linear extrapolation back to theoretical 55 61 67 dB gain at VGIN = 0 V Gain Control Input Bias Current 1 μA LO INPUTS LOIP Input Return Loss LOIN ac-coupled to ground −6 dB (760 MHz applied to LOIP) Rev. A | Page 4 of 28

AD8348 Parameter Conditions Min Typ Max Unit POWER-UP CONTROL ENBL Threshold Low Low = standby 0 V/2 1 V S ENBL Threshold High High = enable V − 1 V/2 V V S S S Input Bias Current 2 μA Power-Up Time Time for final baseband amplifiers to be 45 μs within 90% of final amplitude Power-Down Time Time for supply current to be <10% of 700 ns enabled value POWER SUPPLIES VPOS1, VPOS2, VPOS3 Voltage 2.7 5.5 V Current (Enabled) V = 5 V, V = 5 V 38 48 58 mA S ENBL Current (Standby) V = 5 V, V = 0 V 75 μA S ENBL 1 These parameters are guaranteed but not tested in production. Limits are ±6 Σ from the mean. Rev. A | Page 5 of 28

AD8348 ABSOLUTE MAXIMUM RATINGS Table 2. Stresses above those listed under Absolute Maximum Ratings Parameter Rating may cause permanent damage to the device. This is a stress Supply Voltage on VPOS1, VPOS2, VPOS3 Pins 5.5 V rating only; functional operation of the device at these or any LO Input Power 10 dBm (re: 50 Ω) other conditions above those indicated in the operational IF Input Power 18 dBm (re: 200 Ω) section of this specification is not implied. Exposure to absolute Internal Power Dissipation 450 mW maximum rating conditions for extended periods may affect θ 68°C/W JA device reliability. Maximum Junction Temperature 150°C Operating Temperature Range −40°C to +85°C Storage Temperature Range −65°C to +125°C Lead Temperature (Soldering, 60 sec) 300°C ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. Rev. A | Page 6 of 28

AD8348 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS LOIP 1 28 LOIN VPOS1 2 AD8348 27 COM1 IOPN 3 TOP VIEW 26 QOPN IOPP 4 (Not to Scale) 25 QOPP VCMO 5 24 ENVG IAIN 6 23 QAIN COM3 7 22 COM3 IMXO 8 21 QMXO COM2 9 20 VPOS3 IFIN 10 19 MXIN IFIP 11 18 MXIP VPOS2 12 17 VGIN VIOREFSF 1134 1165 QENOBFLS 03678-002 Figure 2. 28-Lead TSSOP Pin Configuration Table 3. Pin Function Descriptions—28-Lead TSSOP Equivalent Pin No. Mnemonic Description Circuit 1, 28 LOIP, LOIN LO Inputs. For optimum performance, these inputs should be ac-coupled and driven A differentially. Differential drive from single-ended sources can be achieved via a balun. To obtain a broadband 50 Ω input impedance, connect a 60.4 Ω shunt resistor between LOIP and LOIN. Typical input drive level is equal to −10 dBm. 2, 12, 20 VPOS1, VPOS2, Positive Supply for LO, IF, and Biasing and Baseband Sections, Respectively. These pins VPOS3 should be decoupled with 0.1 μF and 100 pF capacitors. 3, 4, 25, 26 IOPN, IOPP, I- and Q-Channel Differential Baseband Outputs. Typical output swing is equal to 2 V p-p B QOPP, QOPN differential. The dc common-mode voltage level on these pins is set by the voltage on VCMO. 5 VCMO Baseband DC Common-Mode Voltage. The voltage applied to this pin sets the dc C common-mode levels for all the baseband outputs and inputs (IMXO, QMXO, IOPP, IOPN, QOPP, QOPN, IAIN, and QAIN). This pin can be connected either to VREF or to a reference voltage from another device (typically an ADC). 6, 23 IAIN, QAIN I- and Q-Channel Baseband Amplifier Inputs. The single-ended signals on these pins are D referenced to VCMO and must have a dc bias equal to the dc voltage on the VCMO pin. If IMXO (QMXO) is dc-coupled to IAIN (QAIN), biasing will be provided by IMXO (QMXO). If an ac-coupled filter is placed between IMXO and IAIN, these pins can be biased from the source driving VCMO through a 1 kΩ resistor. The gain from IAIN/QAIN to the differential outputs (IOPP/IOPN and QOPP/QOPN) is 20 dB. 7, 22 COM3 Ground for Biasing and Baseband Sections. 8, 21 IMXO, QMXO I- and Q-Channel Mixer Baseband Outputs. These are low impedance (40 Ω) outputs whose H bias levels are set by the voltage applied to the VCMO pin. These pins are typically connected to IAIN and QAIN, respectively, either directly or through a filter. Each output can drive a maximum current of 2.5 mA. 9 COM2 IF Section Ground. 10, 11 IFIN, IFIP IF Inputs. IFIN should be ac-coupled to ground. The single-ended IF input signal should E be ac-coupled into IFIP. The nominal differential input impedance of these pins is 200 Ω. For a broadband 50 Ω input impedance, a minimum-loss L pad should be used; R = 174 Ω, SERIES R = 57.6 Ω. This provides a 200 Ω source impedance to the IF input. However, the AD8348 SHUNT does not necessarily require a 200 Ω source impedance, and a single shunt 66.7 Ω resistor can be placed between IFIP and IFIN. 13, 16 IOFS, QOFS I- and Q-Channel Offset Nulling Inputs. DC offsets on the I-channel mixer output (IMXO) F can be nulled by connecting a 0.1 μF capacitor from IOFS to ground. Driving IOFS with a fixed voltage (typically a DAC calibrated such that the offset at IOPP/IOPN is nulled) can extend the operating frequency range to include dc. The QOFS pin can likewise be used to null offsets on the Q-channel mixer output (QMXO). 14 VREF Reference Voltage Output. This output voltage (1 V) is the main bias level for the device G and can be used to externally bias the inputs and outputs of the baseband amplifiers. The typical maximum drive current for this output is 2 mA. Rev. A | Page 7 of 28

AD8348 Equivalent Pin No. Mnemonic Description Circuit 15 ENBL Chip Enable Input. Active high. Threshold is equal to V/2. D S 17 VGIN Gain Control Input. The voltage on this pin controls the gain on the IF VGA. The gain D control voltage range is from 0.2 V to 1.2 V and corresponds to a conversion gain range from +25.5 dB to −18.5 dB. This is the gain to the output of the mixers (that is, IMXO and QMXO). There is an additional 20 dB of fixed gain in the final baseband amplifiers (IAIN to IOPP/IOPN and QAIN to QOPP/QOPN). Note that the gain control function has a negative sense (that is, increasing voltage decreases gain). 18, 19 MXIP, MXIN Auxiliary Mixer Inputs. If ENVG is low, the IFIP and IFIN inputs are disabled and MXIP and I MXIN are enabled, allowing the VGA to be bypassed. The auxiliary mixer inputs are fully differential inputs that should be ac-coupled to the signal source. 24 ENVG Active High VGA Enable. When ENVG is high, IFIP and IFIN inputs are enabled and MXIP D and MXIN inputs are disabled. When ENVG is low, MXIP and MXIN inputs are enabled and IFIP and IFIN inputs are disabled. 27 COM1 LO Section Ground. Rev. A | Page 8 of 28

AD8348 EQUIVALENT CIRCUITS VPOS1 LOIN VPOS3 LOIP IAIN, QAIN, VGIN, ENBL, ENVG COM1 03678-003 COM3 03678-006 Figure 3. Circuit A Figure 6. Circuit D VPOS3 VPOS2 IFIP IOPP, IOPN, QOPP, QOPN IFIN VCMO COM3 03678-004 COM3 03678-007 Figure 4. Circuit B Figure 7. Circuit E VPOS3 50µA VPOS3 MAX IOFS, VCMO QOFS COM3 03678-005 COM3 03678-008 Figure 5. Circuit C Figure 8. Circuit F Rev. A | Page 9 of 28

AD8348 VPOS3 VPOS2 MXIP VREF MXIN COM2 03678-009 COM3 03678-011 Figure 9. Circuit G Figure 11. Circuit I VPOS3 IMXO, QMXO COM3 03678-010 Figure 10. Circuit H Rev. A | Page 10 of 28

AD8348 TYPICAL PERFORMANCE CHARACTERISTICS VGA AND DEMODULATOR 30 4 25 4 LINERR T = +85°C, VPOS = 5V, FREQ = 380MHz LINERR T = +85°C, VPOS = 2.7V, FREQ =900MHz 25 LINERR T = +25°C, VPOS = 5V, FREQ = 380MHz 3 20 LINERR T = +25°C, VPOS = 2.7V, FREQ =900MHz 3 20 LINERR T = –40°C, VPOS = 5V, FREQ = 380MHz 2 15 LINERR T = –40F°RCE, VQP =O S9 0=0 2M.7HVz, 2 dB) 15 1 B) dB) 10 1 B) AIN ( 10 0 R (d AIN ( 5 0 R (d G O G O GAAND MIXER –550 T = +85°C, VPOS = 5V, FREQ = 380MHz –––312 LINEARITY ERR GAAND MIXER –1–050 T = +85F°RCE, QVP =O S9 0=0 2M.7HVz, –––312 LINEARITY ERR V –10 T = +25°C, VPOS = 5V, FREQ = 380MHz –4 V –15 T = +25°C, VPOS = 2.7V, FREQ =900MHz –4 –15 T = –40°C, VPOS = 5V, FREQ = 380MHz –5 –20 T = –40°C, VPOS = 2.7V, FREQ = 900MHz –5 –200.2 0.3 0.4 0.5 0.6VGI0N.7 (V)0.8 0.9 1.0 1.1 1.2–6 03678-012 –250.2 0.3 0.4 0.5 0.6VGI0N.7 (V)0.8 0.9 1.0 1.1 1.2–6 03678-015 Figure 12. Mixer Gain and Linearity Error vs. VGIN, VPOS = 5 V, FIF = 380 MHz, Figure 15. Mixer Gain and Linearity Error vs. VGIN, VPOS = 2.7 V, FIF = 900 MHz, FBB = 1 MHz, Temperature = −40°C, +25°C, +85°C FBB = 1 MHz, Temperature = −40°C, +25°C, +85°C 25 4 28 LINERR T = +85°C, VPOS = 5V, FREQ = 900MHz 20 LINERR T = +25°C, VPOS = 5V, FREQ = 900MHz 3 15 LINERR T = –40°C, VPOS = 5V, 2 26 FREQ = 900MHz dB) 10 1 B) dB) AIN ( 5 0 R (d AIN ( 24 ND MIXER G –50 T = +F85R°ECQ, V=P 9O0S0 =M 5HVz, ––12 ARITY ERRO ND MIXER G 22 2.7V, 0.2V, +25°C 5V, 0.2V5,V +, 205.2°VC, +85°C GAA –10 –3 LINE GAA 2.7V, 0.2V, +85°C V –15 T = +25°C, VPOS = 5V, FREQ = 900MHz –4 V 20 5V, 0.2V, –40°C –20 T = –40°C, VPOS = 5V, FREQ = 900MHz –5 2.7V, 0.2V, –40°C –250.2 0.3 0.4 0.5 0.6VGI0N.7 (V)0.8 0.9 1.0 1.1 1.2–6 03678-013 18 100 200 300 IF4 0F0REQ5U0E0NCY60 (0MHz7)00 800 900 1000 03678-016 Figure 13. Mixer Gain and Linearity Error vs. VGIN, VPOS = 5 V, FIF = 900 MHz, Figure 16. Gain vs. FIF, VGIN = 0.2 V, FBB = 1 MHz, FBB = 1 MHz, Temperature = −40°C, +25°C, +85°C Temperature = −40°C, +25°C, +85°C 30 4 –15 LINERR T = +85°C, VPOS = 2.7V, FREQ = 380MHz 5V, 1.2V, +85°C 25 LINERR T = +25°C, VPOS = 2.7V, FREQ = 380MHz 3 20 LINERR T = –40°C, VPOS = 2.7V, 2 FREQ = 380MHz AIN (dB) 1105 01 R (dB) AIN (dB) –20 2.7V, 1.2V, +85°C G O G 5V, 1.2V, –40°C GAAND MIXER –550 T = +85F°RCE, QVP =O S3 8=0 2M.7HVz, –––312 LINEARITY ERR GAAND MIXER –25 2.7V, 1.22.V7,V 5+,V 21,5. 21°V.C2,V –,4 +02°5C°C V –10 T = +25°C, VPOS = 2.7V, FREQ = 380MHz –4 V –15 T = –40°C, VPOS = 2.7V, FREQ = 380MHz –5 –200.2 0.3 0.4 0.5 0.6VGI0N.7 (V)0.8 0.9 1.0 1.1 1.2–6 03678-014 –30 100 200 300 IF4 0F0REQ5U0E0NCY60 (0MHz7)00 800 900 1000 03678-017 Figure 14. Mixer Gain and Linearity Error vs. VGIN, VPOS = 2.7 V, FIF = 380 MHz, Figure 17. Gain vs. FIF, VGIN = 1.2 V, FBB = 1 MHz, FBB = 1 MHz, Temperature = −40°C, +25°C, +85°C Temperature = −40°C, +25°C, +85°C Rev. A | Page 11 of 28

AD8348 27 20 26 5V, 0.2V,+25°C 200Ω) 15 –40°C, 5V, 900MHz e +25°C, 2.7V, 900MHz GAIN (dB) 222354 22..77VV,, 00..22VV,,++2855°°CC 5V, 0.2V, –40°C OINT (dBm) (r 105 ++852°5C°C, 2, .57VV,, 990000MMHHzz ER 22 2.7V, 0.2V, –40°C N P 0 X O D MI 21 5V, 0.2V,+85°C ESSI –5 +85°C, 5V, 900MHz N R AA 20 MP G O –10 V 19 B C 18 T 1d –15 U 170 10 20 BA3S0EBAN40D FR5E0QUEN60CY (M7H0z) 80 90 100 03678-018 INP –200.2 0.3 0.4 –400.5°C, 20.7.6V,V 9G00I0N.M7 (HVz)0.8 0.9 1.0 1.1 1.2 03678-021 Figure 18. Gain vs. FBB, VGIN = 0.2 V, FIF = 380 MHz, VPOS = 2.7 V, 5 V, Figure 21. Input 1 dB Compression Point (IP1dB) vs. VGIN, FIF = 900 MHz, Temperature = −40°C, +25°C, +85°C FBB = 1 MHz, VPOS = 2.7 V, 5 V, Temperature = −40°C, +25°C, +85°C –17 30 29 5V, 1.2V,+85°C 2.7V, 1.2V, +85°C B) Ω) N (d –20 200 28 5V, 1.2V,+25°C XER GAI 2.7V, 1.2V, +25°C 5V, 1.2V, +85°C dBm) (re 27 2.7V, 1.2V,+85°C D MI 5V, 1.2V, +25°C P3 ( VGAAN –23 INPUT II 26 2.7V, 1.2V,+52V5, °1C.2V, –40°C 5V, 1.2V, –40°C 25 2.7V, 1.2V, –40°C 2.7V, 1.2V, –40°C –260 10 20 BA3S0EBAN40D FR5E0QUEN60CY (M7H0z) 80 90 100 03678-019 24 100 200 300 IF4 0F0REQ5U0E0NCY6 0(0MHz7)00 800 900 1000 03678-022 Figure 19. Gain vs. FBB, VGIN = 1.2 V, FIF = 380 MHz, VPOS = 2.7 V, 5 V, Figure 22. IIP3 vs. FIF, VGIN = 1.2 V, FBB = 1 MHz, VPOS = 2.7 V, 5 V, Temperature = −40°C, +25°C, +85°C Temperature = −40°C, +25°C, +85°C, Tone Spacing = 20 kHz 15 0 Ω) +25°C, 5V, 380MHz 0 5V, 0.2V,+85°C e 20 10 –40°C, 5V, 380MHz m) (r 5 2.7V, 0.2V,+85°C B Ω) 2.7V, 0.2V,+25°C MPRESSION POINT (d –1–050 +85°C, 5V, 380MHz +25°+C8, 52°.C7V, ,2 3.78V0,M 3H80zMHz UT IIP3 (dBm) (re 200 –1–05 5V, 0.2V, –40°C B CO –15 INP 5V, 0.2V,+25°C 2.7V, 0.2V, –40°C 1d –20 UT –40°C, 2.7V, 380MHz INP –250.2 0.3 0.4 0.5 0.6VG0IN.7 (V)0.8 0.9 1.0 1.1 1.2 03678-020 –15 100 200 300 IF4 0F0REQ5U0E0NCY60 (0MHz7)00 800 900 1000 03678-023 Figure 20. Input 1 dB Compression Point (IP1dB) vs. VGIN, FIF = 380 MHz, Figure 23. IIP3 vs. FIF, VGIN = 0.2 V, FBB = 1 MHz, VPOS = 2.7 V, 5 V, FBB = 1 MHz, VPOS = 2.7 V, 5 V, Temperature = −40°C, +25°C, +85°C Temperature = −40°C, +25°C, +85°C Rev. A | Page 12 of 28

AD8348 32 45 35 2.7V, 1.2V, –40°C 0Ω) 5V, 1.2V, –40°C 40 NF 30 e 20 30 2.7V, 1.2V,+25°C 35 25 ER INPUT IIP3 (dBm) (r 2268 52V.,7 V1,. 21V.,2V+,2+58°C5°C OISE FIGURE (dB) 13225050 IIP3 5112500 T IIP3 (dBm) (re 200Ω) X N U D MI 24 5V, 1.2V,+85°C 10 0 INP N A A 5 –5 G V 220 10 20 BA3S0EBAN40D FR5E0QUEN60CY (M7H0z) 80 90 100 03678-024 00.2 0.3 0.4 0.5 0.6VGI0N.7 (V)0.8 0.9 1.0 1.1 1.2–10 03678-027 Figure 24. IIP3 vs. FBB, VGIN = 1.2 V, FIF = 380 MHz, VPOS = 2.7 V, 5 V, Figure 27. Noise Figure and IIP3 vs. VGIN, Temperature = 25°C, Temperature = −40°C, +25°C, +85°C FIF = 380 MHz, FBB = 1 MHz, VPOS = 2.7 V 0 40 35 Ω) 2.7V, 0.2V,+85°C 35 NF 30 0 0 2 5V, 0.2V,+85°C XER INPUT IIP3 (dBm) (re –1–05 2.7V, 0.2V, –40°C 5V, 0.2V, –40°C5V, 0.2V,+25°C NOISE FIGURE (dB) 13225050 IIP3 511225050 UT IIP3 (dBm) (re 200Ω) ND MI –15 2.7V, 0.2V,+25°C 10 0 INP AA 5 –5 G V –200 10 20 BA3S0EBAN40D FR5E0QUEN60CY (M7H0z) 80 90 100 03678-025 00.2 0.3 0.4 0.5 0.6VGI0N.7 (V)0.8 0.9 1.0 1.1 1.2–10 03678-028 Figure 25. IIP3 vs. FBB, VGIN = 0.2 V, FIF = 380 MHz, VPOS = 2.7 V, 5 V, Figure 28. Noise Figure and IIP3 vs. VGIN, Temperature = 25°C, Temperature = −40°C, +25°C, +85°C FIF = 380 MHz, FBB = 1 MHz, VPOS = 5 V 16 16 2.0 15 15 1.5 NF @ LO = 900MHz 14 14 1.0 dB) 13 NF VGIN = 0.2V dB) 13 PHASE ERROR 50MHz PHASE ERROR 380MHz 0.5 grees) E ( E ( De UR 12 UR 12 0 R ( G G O OISE FI 11 OISE FI 11 PHASE ERNRFO @R 9L0O0M =H 3z80MHz –0.5 SE ERR N N A 10 10 –1.0 H P 9 9 –1.5 NF @ LO = 50MHz 850 150 250 35I0F FR4E50QUE5N5C0Y (M6H50z) 750 850 950 03678-026 8–12 –10 –8LO INPUT– 6LEVEL (V–)4 –2 0–2.0 03678-029 Figure 26. Noise Figure vs. FIF, T = 25°C, VGIN = 0.2 V, FBB = 1 MHz Figure 29. Noise Figure and Quadrature Phase Error IMXO/QMXO vs. LO Input Level, Temperature = 25°C, VGIN = 0.2 V, VPOS = 5 V for FIF = 50 MHz, 380 MHz, and 900 MHz Rev. A | Page 13 of 28

AD8348 DEMODULATOR USING MXIP AND MXIN 11.0 18 23.0 NF 5V 17 22.5 10.5 TEMP = –40°C, VPOS = 2.7V 16 22.0 Ω) MIXER GAIN (dB) 1099...050 TEVMPPO S= =+ 255V°C, TEMP = –40°C, VTPEVOMPSOP S= = =5 + V28.57°VC, UT IIP3 (dBm) (re 200 111435 IIP3 5V NF 2.7V 222101...055 NOISE FIGURE (dB) TEMP = +25°C, NP 12 20.0 8.5 VPOS = 2.7V I 11 19.5 IIP3 2.7V TEMP = +85°C, VPOS = 5V 8.0 100 200 300 IF4 0F0REQ5U0E0NCY60 (0MHz7)00 800 900 1000 03678-030 1050 150 250 35I0F FR4E50QUE5N5C0Y (M6H50z) 750 850 950 19.0 03670-032 Figure 30. Mixer Gain vs. FIF, VPOS = 2.7 V, 5 V, FBB = 1 MHz, Figure 32. IIP3 and Noise Figure vs. FIF, VPOS = 2.7 V, 5 V, Temperature = 25°C Temperature = −40°C, +25°C, +85°C –1.5 –2.0 TEMP = +85°C, VPOS = 5V –2.5 Ω) TEMP = +25°C, VPOS = 5V 0 –3.0 0 e 2 –3.5 TEMP = –40°C, VPOS = 5V m) (r –4.0 B d –4.5 B ( d –5.0 P1 TEMP = +85°C, VPOS = 2.7V UT –5.5 TEMP = –40°C, VPOS = 2.7V NP –6.0 ER I –6.5 TEMP = +25°C, VPOS = 2.7V X MI –7.0 –7.5 –8.0 100 200 300 IF4 0F0REQ5U0E0NCY60 (0MHz7)00 800 900 1000 03678-031 Figure 31. Input 1 dB Compression Point vs. FIF, FBB = 1 MHz, VPOS = 2.7 V, 5 V, Temperature = −40°C, +25°C, +85°C Rev. A | Page 14 of 28

AD8348 FINAL BASEBAND AMPLIFIERS 21 35 –40°C, 5V –40°C, 5V –40°C, 2.7V 30 20 +25°C, 5V +85°C, 5V 25 +85°C, 5V 19 +25°C, 2.7V +25°C, 5V 20 18 15 +85°C, 2.7V GAIN (dB) 1176 +85°C, 2.7V OIP3 (dBV) 105 +25°C, 2.7V 0 15 –40°C, 2.7V –5 14 –10 130.1 1BASEBAND FR1E0QUENCY (MH1z0)0 1000 03678-033 –1510 30 50BAS7E0BAN9D0 FRE1Q1U0ENC13Y0 (MH1z5)0 170 190 03678-035 Figure 33. Gain vs. FBB, VVCMO = VREF = 1 V, VPOS = 2.7 V, 5 V, Figure 35. OIP3 vs. FBB, VVCMO = VREF = 1 V, VPOS = 2.7 V, 5 V, Temperature = −40°C, +25°C, +85°C Temperature = −40°C, +25°C, +85°C 5 10 +25°C, 5V –40°C, 5V +85°C, 5V 9 E 0 S 8 –40°C,+ 22.57°VC, 2.7V PUT NOInV/Hz) 7 BV) –5 R INTY ( 6 P1dB (d –10 +85°C, 2.7V MPLIFIEL DENSI 54 O AA NDCTR 3 AE –15 EBSP 2 S A B 1 –200.1 1BASEBAND FR1E0QUENCY (MH1z0)0 1000 03678-034 01 10 FR10E0QUENCY 1(k0H00z) 10000 100000 03678-036 Figure 34. OP1dB Compression vs. FBB, VVCMO = VREF = 1 V, VPOS = 2.7 V, 5 V, Figure 36. Noise Spectral Density Temperature = −40°C, +25°C, +85°C Rev. A | Page 15 of 28

AD8348 VGA/DEMODULATOR AND BASEBAND AMPLIFIER 2.0 2.0 s) 1.5 1.5 e e R (Degr 1.0 2.7V, 0.2V, –40°C 5V, 0.2V,+85°C CH (dB) 1.0 O 0.5 T 0.5 R A R M E S E 0 MI 0 HAS 5V, 0.2V, –40°C DE ATURE P ––10..05 5V, 0.2V,+25°C2.7V, 0.2V,+85°C 2.7V, 0.2V,+25°C AMPLITU ––10..05 R Q UAD –1.5 I/ –1.5 Q –2.0 100 200 300 IF4 0F0REQ5U0E0NCY60 (0MHz7)00 800 900 1000 03678-037 –2.0 100 200 300 IF4 0F0REQ5U0E0NCY60 (0MHz7)00 800 900 1000 03678-040 Figure 37. Quadrature Phase Error vs. FIF, VGIN = 0.7 V, VPOS = 2.7 V, 5 V, Figure 40. I/Q Amplitude Imbalance vs. FIF, Temperature = 25°C, VPOS = 5 V Temperature = −40°C, +25°C, +85°C 2.0 300 2.2 s) 1.5 2.7V, 0.7V,+25°C 280 2.0 e RATURE PHASE ERROR (Degre ––1001....05050 2.7V, 05.7VV, ,0+.7825V.5V7,°,V +C0,2 .075.V°7,CV –, 4–04°0C°C 5V, 0.7V,+85°C SHUNT RESISTANCE (Ω) 112212264208640000000 SSHHUUNNTT R CEASPISATCAITNACNECE 0011111.......8642086 SHUNT CAPACITANCE (pF) D QUA –1.5 120 0.4 –2.00 5 1B0ASEB1A5ND FR2E0QUENC25Y (MHz3)0 35 40 03678-038 10050 150 250 35I0F FR4E50QUE5N5C0Y (M6H50z) 750 850 950 0.2 03678-041 Figure 38. Quadrature Phase Error vs. FBB, VGIN = 0.7 V, VPOS = 2.7 V, 5 V, Figure 41. Input Impedance of IF Input vs. FIF, VGIN = 0.7 V, VPOS = 5 V Temperature = −40°C, +25°C, +85°C, FIF = 380 MHz 90 120 60 0.4 150 30 dB) 0.2 H ( C T MA 180 0 S 5V, 0.7V, 25°C IFIP WITHLPAD MI 0 E D U T PLI 210 IFIP WITHOUTLPAD 330 AM –0.2 Q I/ IMPEDANCE CIRCLE 240 300 –0.40 5 1B0ASEB1A5ND FR2E0QUENC25Y (MHz3)0 35 40 03678-039 270 03678-042 Figure 39. I/Q Amplitude Imbalance vs. FBB, Temperature = 25°C, VPOS = 5 V Figure 42. S11 of IF Input vs. FIF, FIF = 50 MHz to 1 GHz, VGIN = 0.7 V, VPOS = 5 V (with L Pad, with No Pad, Normalized to 50 Ω) Rev. A | Page 16 of 28

AD8348 300 2.5 0 280 –5 260 2.0 Ω) 240 (SHUNT CAPACITANCE) pF) –10 NT RESISTANCE ( 221208000 11..50 T CAPACITANCE ( ETURN LOSS (dB) ––2105 RWEITTUHR 6N0. 4LΩO SINS SLHOU INNTP UBTE, TTWHREEONU GLOH IBPA/LLOUINN U 160 (SHUNT RESISTANCE) N R –25 H U S H 140 0.5 S –30 120 100 0 –35 50 100 150 200 250 300 350IF400 FR450EQU500EN550CY600 (M650Hz)700 750 800 850 900 950 1000 03678-043 100 200 300 400FRE500QU600EN700CY800AP900PLI1000ED1100TO1200 LO1300IP/L1400OI1500N (M1600Hz1700) 1800 1900 2000 03678-046 Figure 43. Input Impedance of Mixer Input vs. FIF, VGIN = 0.7 V, VPOS = 5 V Figure 46. Return Loss of LO Input vs. External LO Frequency Through Balun, with Termination Resistor 90 120 60 65 150 30 60 MX INPUTS WITH 4:1 BALUN mA) 55 180 0 T ( N E R 50 R CU VS = 5V 210 MXIP INPUT PIN 330 PPLY 45 VS = 2.7V U S 40 IMPEDANCE CIRCLE 240 300 270 03678-044 35–40 –30 –20 –10 0TE1M0PER20ATU3R0E (°4C0) 50 60 70 80 03678-047 Figure 44. S11 of Mixer Input vs. FIF, FIF = 50 MHz to 1 GHz, Figure 47. Supply Current vs. Temperature VGIN = 0.7 V, VPOS = 5 V (With and Without Balun) 0 –5 RETURN LOSS LOIP PIN SINGLE-ENDED, –10 LOINAC-COUPLEDTO GROUND. B) d S ( –15 S O L N –20 R U T E R –25 –30 –35 100 200 300 400 500EX600TE700RN800AL 900LO 1000FRE1100QU1200EN1300CY1400 (M1500Hz)1600 1700 1800 1900 2000 03678-045 Figure 45. Return Loss of LOIP Input vs. External LO Frequency Rev. A | Page 17 of 28

AD8348 THEORY OF OPERATION VREF IMXO IOFS IAIN IOPP IOPN PHASE SPLITTER 14 8 13 6 4 3 Quadrature generation is achieved using a divide-by-2 frequency ENBL15 CBEIALSL VREF 5 VCMO divider. Unlike a polyphase filter that achieves quadrature over VCMO a limited frequency range, the divide-by-2 approach maintains DIVIDE 1 LOIP IFIP11 BY 2 quadrature over a broad frequency range and does not attenuate IFIN10 PHASE the LO. The user, however, must provide an external signal XLO SPLITTER 28LOIN AD8348 that is twice the frequency of the desired LO frequency. XLO drives VGIN17 COGNATIRNOL the clock inputs of two flip-flops that divide down the frequency VCMO by a factor of 2. The outputs of the two flip-flops are one-half M1X8IP M1X9IN EN2V4G QX2M1O QO16FS Q2A3IN QO25PP QO26PN 03678-049 period of XLO out of phase. Equivalently, the outputs are one- quarter period (90°) of the desired LO frequency out of phase. Figure 48. Functional Block Diagram Because the transitions on XLO define the phase difference at VGA the outputs, deviation from 50% duty cycle translates directly to The VGA is implemented using the patented X-AMP architecture. quadrature phase errors. The single-ended IF signal is attenuated in eight discrete 6 dB If the user generates XLO from a 1× frequency (f ) and a REF steps by a passive R-2R ladder. Each discrete attenuated version frequency-doubling circuit (XLO = 2 × f ), fundamentally of the IF signal is applied to the input of a transconductance REF there is a 180° phase uncertainty between f and the AD8348 stage. The current outputs of all transconductance stages are REF internal quadrature LO. The phase relationship between I and Q summed together and drive a resistive load at the output of the LO, however, is always 90°. VGA. Gain control is achieved by smoothly turning on and off the relevant transconductance stages with a temperature- I/Q BASEBAND AMPLIFIERS compensated interpolation circuit. This scheme allows the gain Two (I and Q) fixed gain (20 dB), single-ended-to-differential to continuously vary over a 44 dB range with linear-in-decibel amplifiers are provided to amplify the demodulated signal gain control. This configuration also keeps the relative dynamic after off-chip filtering. The amplifiers use voltage feedback to range constant (for example, IIP3 − NF in dB) over the gain linearize the gain over the demodulation bandwidth. These setting; however, the absolute intermodulation intercepts and amplifiers can be used to maximize the dynamic range at the noise figure vary directly with gain. The analog voltage VGIN input of an ADC following the AD8348. sets the gain. VGIN = 0.2 V is the maximum gain setting, and VGIN = 1.2 V is the minimum voltage gain setting. The input to the baseband amplifiers, IAIN (QAIN), feeds into the base of a bipolar transistor with an input impedance of DOWNCONVERSION MIXERS roughly 50 kΩ. The baseband amplifiers sense the single-ended The output of the VGA drives two (I and Q) double-balanced difference between IAIN (QAIN) and VCMO. IAIN (QAIN) Gilbert cell downconversion mixers. Alternatively, driving the can be dc biased by terminating it with a shunt resistor to ENVG pin low can disable the VGA, and the mixers can be VCMO, such as when an external filter is inserted between externally driven directly via the MXIP and MXIN ports. At IMXO (QMXO) and IAIN (QAIN). Alternatively, any dc the input of the mixer, a degenerated differential pair performs connection to IMXO (QXMO) can provide appropriate bias via linear voltage-to-current conversions. The differential output the offset-nulling loop. current feeds into the mixer core where it is downconverted by ENABLE the mixing action of the Gilbert cell. The phase splitter provides quadrature LO signals that drive the LO ports of the in-phase A master biasing cell that can be disabled using the ENBL pin and quadrature mixers. controls the biasing for the chip. If the ENBL pin is held low, the entire chip powers down to a low power sleep mode, Buffers at the output of each mixer drive the IMXO and QMXO typically consuming 75 μA at 5 V. pins. These linear, low output impedance buffers drive 40 Ω, temperature-stable, passive resistors in series with each output BASEBAND OFFSET CANCELLATION pin (IMXO and QMXO). This 40 Ω should be considered when A low output current integrator senses the output voltage offset calculating the reverse termination if an external filter is inserted at IOPP and IOPN (QOPP and QOPN) and injects a nulling between IMXO (QMXO) and IAIN (QAIN). The VCMO pin sets current into the signal path. The integration time constant of the the dc output level of the buffer. This can be set externally or offset-nulling loop is set by Capacitor COFS from IOFS (QOFS) to connected to the on-chip 1.0 V reference, VREF. Rev. A | Page 18 of 28

AD8348 VCMO. This forms a high-pass response for the baseband The IOFS (QOFS) pin must be connected to either a bypass signal path with a lower 3 dB frequency of capacitor (>0.1 μF) or an external voltage source to prevent the feedback loop from oscillating. 1 f = PASS 2π×2650Ω ×COFS The feedback loop will be broken at dc if an ac-coupled baseband filter is placed between the mixer outputs and the baseband Alternatively, the user can externally adjust the dc offset by driving amplifier inputs. If an ac-coupled filter is implemented, the user IOFS (QOFS) with a digital-to-analog converter or other voltage must handle the offset compensation via some external means. source. In this case, the baseband circuit operates all the way down to dc (f = 0 Hz). The integrator output current is only 50 μA PASS and can be easily overridden with an external voltage source. The nominal voltage level applied to IOFS (QOFS) to produce a 0 V differential offset at the baseband outputs is 900 mV. Rev. A | Page 19 of 28

AD8348 APPLICATIONS BASIC CONNECTIONS LO 4 5 Figure 49 shows the basic connections schematic for the AD8348. ETC1-1-13 J21 4 5 3 1 LO 1000pF 1000pF T21 60.4Ω ETC1-1-13 3 1 100C0p21F1LOAIPD6R08.2431Ω4L8OINC12028020pF 1 LOIP LOIN28 03678-050 Figure 50. Differential LO Drive with Balun +VS C52 C51 2VPOS1COM127 IOJ3PIN 0.1µF 100pF 3IOPN QOPN26 QJO3PQN Alternatively, the LO port can be driven from a single-ended source IOJ2PIP 4IOPP QOPP25 IF +VS QJO2QPP without a balun (Figure 51). The LO signal is ac-coupled directly VREF 5VCMO ENVG24 SW12 into the LOIP pin via an ac-coupling capacitor, and the LOIN pin MX 6IAIN QAIN23 is ac-coupled to ground. Driving the LO port from a single- 7COM3 COM322 ended source results in an increase in both quadrature phase 8IMXO QMXO21 C55 C56 error and LO leakage. C32 9COM2VPOS320 100pF 0.1µF +VS C43 R42 R31 R321000pF 10IFIN MXIN19 C41 T411000pF 0Ω LO 57.6Ω 174Ω 1µF ETK4-2T IFIP 11IFIP MXIP18 MXIP C31 C42 1000pF 1000pF +VS C54 100C05p3F 12VPOS2 VGIN17 VGIN 1000pF 60.4Ω 0.1µF 100pF 0C.10µlF 13IOFS QOFS16 0C.10µQF ENBL +VS Figur4Ce.71µ 14F9. Ba14sViRcE FCoEnNnBLe1c5tions SchematSiDcWE 1N1BL 03678-064 1 LOIP LOIN28 03678-051 Figure 51. Single-Ended LO Drive POWER SUPPLY The recommended LO drive level is between −12 dBm and The voltage supply for the AD8348, between 2.7 V and 5 V, should 0 dBm. The LO frequency at the input to the device should be be provided to the +VPOSx pins, and ground should be connected twice that of the desired LO frequency at the mixer core. The to the COMx pins. Each supply pin should be decoupled separately applied LO frequency range is between 100 MHz and 2 GHz. using two capacitors whose recommended values are 100 pF and 0.1 μF (values close to these can also be used). IF INPUTS DEVICE ENABLE The IF inputs have an input impedance of 200 Ω. A broadband To enable the device, the ENBL pin should be driven to V. 50 Ω match can be presented to the driving source through the use S Grounding the ENBL pin disables the device. of a minimum-loss L pad. This minimum-loss pad introduces an 11.46 dB loss in the input path and must be taken into account VGA ENABLE when calculating metrics such as gain and noise figure. Figure 42 Driving the voltage on the ENVG pin to VS enables the VGA. In shows the S11 of the IF input with and without the L pad. this mode, the MX inputs are disabled and the IF inputs are 1000pF used. Grounding the ENVG pin disables the VGA and the IF 10 IFIN inputs. When the VGA is disabled, the MX inputs should be used. 57.6Ω 174Ω GAIN CONTROL IFIP 1000pF11 IFIP 03678-052 When the VGA is enabled, the voltage applied to the VGIN pin sets Figure 52. Minimum-Loss L Pad for 50 Ω IF Input the gain. The gain control voltage range is between 0.2 V and 1.2 V. MX INPUTS This corresponds to a gain range between +25.5 dB and −18.5 dB. The mixer inputs, MXIP and MXIN, have a nominal impedance LO INPUTS of 200 Ω and should be driven differentially. When driven from For optimum performance, the local oscillator port should be a differential source, the input should be ac-coupled to the driven differentially through a balun. The recommended balun source via capacitors, as shown in Figure 53. is M/A-COM ETC1-1-13. The LO inputs to the device should be ac-coupled, unless an ac-coupled transformer is being used. For a broadband match to a 50 Ω source, a 60.4 Ω resistor should be placed between the LOIP and LION pins. Rev. A | Page 20 of 28

AD8348 LO 4 5 1000pF MXIN 19 MXIN 1:1 3 1 MXIP 18 1000pF MXIP 03678-053 1000pF AD608.43Ω48 1000pF Figure 53. Driving the MX Inputs from a Differential Source 1 LOIP LOIN28 +VS 0.1µF 100pF 2 VPOS1COM127 If the MX inputs are to be driven from a single-ended 50 Ω source, 3 IOPN QOPN26 a 4:1 balun can be used to transform the 200 Ω impedance of TO BASEBAND TO BASEBAND IADC QADC the inputs to 50 Ω while performing the required single-ended- 4 IOPP QOPP25 to-differential conversion. The recommended transformer is the VREF 5 VCMO ENVG24 +VS M/A-COM ETK4-2T. 6 IAIN QAIN23 7 COM3 COM322 1000pF 1.02kΩ 1.24kΩ MXIN19 8 IMXO QMXO21 VCMO 1µF ETK4-2T 9 COM2VPOS320 100pF 0.1µF +VS MFXigIPur1e8 54. Driving the MX Inputs from a Si1n0g0l0ep-FEnded 50 Ω MSoXuIPrce03678-066 ZIOF I=N 2P0U0TΩ 11000000ppFF 1110IIFFIIPN MMXXIINP1189 11000000ppFF +VS 0.1µF 100pF 12VPOS2 VGIN17 BASEBAND OUTPUTS 13IOFS QOFS16 100pF 100pF The baseband amplifier outputs, IOPP, IOPN, QOPP, and QOPN, VREF 1000pF 14VREF ENBL15 100pF +VS should be presented with loads of at least 2 kΩ (single-ended to ground). They are not designed to drive 50 Ω loads directly. The AD8362 typical swing for these outputs is 2 V p-p differential (1 V p-p 1 COMM ACOM16 single-ended), but larger swings are possible as long as care is taken 1µF 2 CHPF VREF15 to ensure that the signals remain within the lower limit of 0.5 V 1µF 3 DECL VTGT14 and the upper limit of VS − 1 V of the output swing. To achieve 1µF a larger swing, it is necessary to adjust the common-mode bias of 4 INHI VPOS13 100pF 0.1µF +VS 1µF the baseband output signals. Increasing the swing can have the 5 INLO VOUT12 benefit of improving the signal-to-noise ratio of the baseband 6 DECL VSET11 VSET amplifier output. 7 PWDN ACOM10 1µF Wshohuenld c boen tnaekcetnin tgo tehnes buarese tbhaant dth oeu otpuutptsu ttos aorteh nero td ceavpicaecsi,t icvaerley 8 COMM CLPF 9 03678-0-055 Figure 55. AD8362 Configuration for AGC Operation loaded by approximately 20 pF or more. Such loads could potentially overload the output or induce oscillations. The effect Assuming the I and Q channels have the same rms power, the of capacitive loading on the baseband amplifier outputs can be mixer output (or the output of the baseband filter) of one channel mitigated by inserting series resistors of approximately 200 Ω. can be used as the input of the AD8362. The AD8362 should be operated in a region where its linearity error is small. Also, a OUTPUT DC BIAS LEVEL voltage divider should be implemented with an external resistor The dc bias of the mixer outputs and the baseband amplifier in series with the 200 Ω input impedance of the AD8362 input. inputs and outputs is determined by the voltage that is driven This attenuates the AD8348 mixer output so that the AD8362 onto the VCMO pin. The range of this voltage is typically input is not overdriven. The size of the resistor between the between 500 mV and 4 V when operating with a 5 V supply. mixer output and the AD8362 input should be chosen so that the peak signal level at the input of the AD8362 is about 10 dB To achieve maximum voltage swing from the baseband amplifiers, less than the approximately 10 dBm maximum of the AD8362 VCMO should be driven at 2.25 V; this allows a swing of up to dynamic range. 7 V p-p differential (3.5 V p-p single-ended). The other side of the AD8348 baseband output should be INTERFACING TO DETECTOR FOR AGC OPERATION loaded with a resistance equal to the series resistance of the The AD8348 can be interfaced with a detector such as the attenuating resistor in series with the AD8362’s 200 Ω input AD8362 rms-to-dc converter to provide an automatic signal- impedance. This resistor should be tied to the source driving leveling function for the baseband outputs. VCMO so that there is no dc drawn from the mixer output. Rev. A | Page 21 of 28

AD8348 The level of the mixer output (or the output of the baseband Figure 57 shows the schematic for a 100 Ω, fourth-order elliptic filter) can then be set by varying the setpoint voltage fed to low-pass filter with a 3 dB cutoff frequency of 20 MHz. Source Pin 11 (VSET) of the AD8362. and load impedances of approximately 100 Ω ensure that the filter sees a matched source and load. This also ensures that the Care should be taken to ensure that blockers—unwanted signals mixer output is driving an overall load of 200 Ω. Note that the in the band of interest that are demodulated along with the desired shunt termination resistor is tied to the source driving VCMO signal—do not dominate the rms power of the AD8362 input. and not to ground. This ensures that the input to the baseband This can cause an undesired reduction in the level of the mixer amplifier is biased to the proper reference level. VCMO is not output. To overcome this, baseband filtering can be implemented an output pin and must be biased by a low impedance source. to filter out undesired signals before the signal is presented to the AD8362. The frequency response and group delay of this filter are shown in Figure 58 and Figure 59. Figure 56 shows the effectiveness of the AGC loop in maintaining a baseband amplifier output amplitude with less 0 than 0.5 dB of amplitude error over an IF input range of 40 dB –10 while demodulating a QPSK-modulated signal at 380 MHz. The AD8362 is insensitive to crest factor variations and –20 therefore provides similar performance regardless of the modulation of the incoming signal. N (dB) –30 O 140 3 ATI –40 –5.1dBm re 10kΩ U N 130 QPSK 2 TTE –50 A –60 T U UTPms) 120 1 –70 HANNEL VOLTAGE O(IOPP – IOPN) (mV r 11091000 ERROR –0–21 ERROR (dB) –85001 Figure 58. BFRaEseQbUaEn1Nd0C FYi l(tMeHr zR)esponse 100 03678-057 C I 80 –3 45 40 70–55 –45IFIP PO–W35ER INPU–T2 5(dBm, ZO–1 =5 200Ω) –5 5–4 03678-065 s) 35 Figure 56. AD8348 Baseband Amplifier Output vs. Y (n 30 A IF Input Power with AD8362 AGC Loop DEL 25 1 2 BASEBAND FILTERS UP 20 O R G 15 Baseband low-pass or band-pass filtering can be conveniently 10 performed between the mixer outputs (IMXO and QMXO) and the input to the baseband amplifiers. Consideration should be 5 given to the outpuCt1 impeCd2ance of the mixers (40 Ω). 01 FREQUE1N0CY (MHz) 100 03678-058 4.7pF 8.2pF Figure 59. Baseband Filter Group Delay R1 60Ω TOAD8362 L1 L2 INPUT IFAGC 0.68µH 1.2µH LOOP IS USED C5 C6 R2 150pF 82pF 100Ω ADI8M3X4O8 VCMO IAIN 03678-056 Figure 57. Baseband Filter Schematic Rev. A | Page 22 of 28

AD8348 LO GENERATION The device is enabled by moving Switch SW11 (at the bottom left of the evaluation board) to the ENBL position. The device is Analog Devices has a line of PLLs that can be used for disabled by moving SW11 to the DENBL position. If desired, the generating the LO signal. Table 4 lists the PLLs and their device can be enabled and disabled from an external source that maximum frequency and phase noise performance. can be fed into the ENBL SMA connector or the VENB test point, Table 4. ADI PLL Selection Table in which case SW11 should be placed in the DENBL position. @ 1 kHz ΦN Frequency F dBc/Hz, The IF and MX inputs are selected via SW12. The switch should IN ADI Model (MHz) 200 kHz PFD be moved in the direction of the desired input. ADF4001BRU 165 −99 Gain Control ADF4001BCP 165 −99 For convenience, a potentiometer, R15, is provided to allow for ADF4110BRU 550 −91 changes in gain without the need for an additional dc voltage ADF4110BCP 550 −91 source. To use the potentiometer, the SW13 switch must be set ADF4111BRU 1200 −78 to the POT position. Alternatively, an external voltage applied ADF4111BCP 1200 −78 to either the test point or SMA connector labeled VGIN can set ADF4112BRU 3000 −86 the gain. SW13 must be set to the EXT position when an ADF4112BCP 3000 −86 external gain control voltage is used. ADF4116BRU 550 −89 ADF4117BRU 1200 −87 LO Input ADF4118BRU 3000 −90 The local oscillator signal should be fed to the SMA Connector ADI also offers the ADF4360 fully integrated synthesizer and J21. This port is terminated in 50 Ω. The acceptable LO power VCO on a single chip that offers differential outputs for driving input range is from −12 dBm to 0 dBm and must be at a the local oscillator input of the AD8348. This means that the user frequency double that of the IF/MX frequency. Remember that can eliminate the use of a balun for single-ended-to-differential the AD8348 uses a 2:1 frequency divider in the LO path to conversions. The ADF4360 comes as a family of chips with six generate the internally required quadrature-phase-related LO operating frequency ranges. One can be chosen depending on signals. the local oscillator frequency required. Table 5 shows the IF Input options available. The IF input should be fed into the SMA connector IFIP. The VGA must be enabled when this port is used (SW12 in the IF Table 5. ADF4360 Family Operating Frequencies position). When this IF input is chosen, the signal path includes ADI Model Output Frequency Range (MHz) a minimum-loss attenuator to transform a 50 Ω input source to ADF4360-1 2150 to 2450 the 200 Ω source impedance level for which the VGA was ADF4360-2 1800 to 2150 designed. This pad provides a very broadband input match at ADF4360-3 1550 to 1950 the expense of an 11.46 dB power attenuation in the input path. ADF4360-4 1400 to 1800 It is very important to take this into account when measuring ADF4360-5 1150 to 1400 the noise and distortion performance of the unmodified board ADF4360-6 1000 to 1250 using the IFIP input; the apparent noise figure will be degraded ADF4360-7 Lower frequencies set by external L by 11.46 dB, and the apparent IIP3 will be 11.46 dB higher than actual. If full weak-signal performance is desired from the EVALUATION BOARD evaluation board, the attenuator (comprising R31 and R32) Figure 60 shows the schematic for the AD8348 evaluation should be removed and replaced with a low-loss RF transformer board. Note that uninstalled components are indicated with the providing the desired 4:1 impedance ratio. When a transformer OPEN designation. The board is powered by a single supply in is used, IFIN should be ac-coupled to ground and not driven the range of 2.7 V to 5.5 V. Table 6 details the various configu- differentially with IFIP. ration options of the evaluation board. Table 7 shows the various MX Input jumper configurations for operating the evaluation board with different signal paths. The evaluation board is by default set for a differential MX drive through a balun (T41) from a single-ended source fed into the Power to operate the board can be fed to a single VS test point MXIP SMA connector. When the MX inputs are used, the located near the LO input port at the top of the evaluation internal VGA is bypassed. To change to a differential driving board. A GND test point is conveniently provided next to the source, T41 should be removed along with Resistor R42. The VS test point for the return path. 0 Ω R43 and R44 resistors should be installed in place of T41 to bridge the gap between the input traces. This presents a nominal Rev. A | Page 23 of 28

AD8348 differential impedance of 200 Ω (100 Ω per side). The Baseband Outputs differential inputs should then be fed into SMA connectors The baseband outputs are made available at the IOPP, IOPN, MXIP and MXIN. QOPP, and QOPN test points and SMA connectors. These Mixer Outputs outputs are not designed to be connected directly to 50 Ω loads and should be presented with loads of approximately 2 kΩ or The I and Q mixer outputs are available through the IMXO and greater. QMXO SMA connectors. These outputs are biased to VCMO and are not designed to drive loads smaller than 200 Ω. To The dc bias level of the baseband amplifier outputs are by prevent damage to test equipment that cannot tolerate dc biases, default tied to VREF through LK11. If desired, the dc bias level pads for series dc-blocking capacitors are provided. These pads can be changed by removing LK11 and driving a dc voltage are populated with 0 Ω by default. onto the VCMO test point. J21 4 5 +VS LO GND C52 C51 T21 0.1µF 100pF ETC1-1-13 IOPN QOPN J3I 3 1 J3Q IOPN GND OCP9EIN R0Ω5I 100C0p2F1 6R0.241Ω C102020pF R05ΩQ CO9PQEN GND QOPN AD8348 J2I J2Q IOPP IOPP C8I R4I 1 LOIP LOIN28 R4Q C8Q QOPP QOPP OPEN 0Ω 0Ω OPEN 2 VPOS1 COM127 +VS IF MX 3 IOPN QOPN26 VCMO SW12 C13 0.1µF 4 IOPP QOPP25 R3I R3Q IMJ1XIO C10I 49.9ΩLK4I 5 VCMO ENVG24 LK4Q 49.9Ω VCMO C10Q JQ1MQXO 0Ω IMXO LK11 QMXO 0Ω 6 IAIN QAIN23 L3I L2I L1I LK3I LK3Q L1Q L2Q L3Q OPEN OPEN OPEN OPEN OPEN OPEN LK2I C3I C2I C1I LK1I 7 COM3 COM322 LK1Q C1Q C2Q C3Q LK2Q OPEN OPEN OPEN OPEN OPEN OPEN 8 IMXO QMXO21 R1I R1Q R2I C7I C6I C5I C4I OPEN OPEN C4Q C5Q C6Q C7Q R2Q OPEN OPEN OPEN OPEN OPEN 9 COM2 VPOS320 OPEN OPEN OPEN OPEN OPEN VCMO 10 IFIN MXIN19 1C005p5F 0C.15µ5F VCMO C32 +VS ORP4E4N C43 R42 1000pF 11 IFIP MXIP18 1000pF 0Ω MXIN 57R.63Ω1 1R7342Ω 12 VPOS2 VGIN17 C1µ4F1 ETTK441-2T IFIP MXIP C31 13 IOFS QOFS16 C42 R41 1000pF R43 1000pF OPEN +VS OPEN C54 C53 14 VREF ENBL15 0.1µF 100pF LK5I LK5Q R14 10kΩ R12 +VS R15 10kΩ VREF 4C.71µ1F POT C12 1P0OkΩT ENBL VENB SW11 SW13 EXT 0.1µF ENBL DENB4LR9.191Ω C0.01IµFIOFS QOFS C0.01QµF OPRE1N3 VGIN 03678-059 Figure 60. Evaluation Board Schematic Rev. A | Page 24 of 28

AD8348 03678-060 Figure 61. Evaluation Board Top Layer 03678-061 Figure 62. Evaluation Board Top Silkscreen Rev. A | Page 25 of 28

AD8348 03678-062 Figure 63. Evaluation Board Bottom Layer 03678-063 Figure 64. Evaluation Board Bottom Silkscreen Rev. A | Page 26 of 28

AD8348 Table 6. Evaluation Board Configuration Options Component Function Default Condition V, GND Power supply and ground vector pins. Not applicable S SW11, ENBL Device enable: Place SW11 in the ENBL position to connect the ENBL pin to V. Place SW11 in SW11 = ENBL S the DENBL position to disable the device by grounding the Pin ENBL through a 50 Ω pull-down resistor. The device can also be enabled via an external voltage applied to ENBL or VENB. SW13, R15, Gain control selection: With SW13 in the POT position, the gain of the VGA can be set using the SW13 = POT VGIN R15 potentiometer. With SW13 in the EXT position, the VGA gain can be set by an external voltage to the SMA connector VGIN. For VGA operation, the VGA must first be enabled by setting SW12 to the IF position. SW12 VGA enable selection: With SW12 in the IF position, the ENVG pin is connected to V and the SW12 = IF S VGA is enabled. The IF input should be used when SW12 is in the IF position. With SW12 in the MX position, the ENVG pin is grounded and the VGA is disabled. The MX inputs should be used when SW12 is in the MX position. IFIP, R31, R32 IF inputs: The single-ended IF signal should be connected to this SMA connector. R31 and R32 R31 = 57.6 Ω form an L pad that presents a 50 Ω termination to the driving source. This L pad introduces an R32 = 174 Ω 11.46 dB loss in the input signal path and should be taken into consideration when calculating the gain of the AD8348. MXIP, MXIN, Mixer inputs: These inputs can be configured for either differential or single-ended operation. T41 = M/A-COM ETK4-2T; T41, The evaluation board is by default set for differential MX drive through a balun (T41) from a R41= OPEN; C42, C43 = R41, R42, single-ended source fed into the MXIP SMA connector. To change to a differential driving source, 1000 pF; R42 = 0 Ω C42, C43 T41 should be removed along with Resistor R42. The 0 Ω Resistors R43 and R44 should be installed in place of T41 to bridge the gap between the input traces. This will present a nominal differential impedance of 200 Ω (100 Ω per side). The differential inputs should then be fed into SMA connectors MXIP and MXIN. LK11, VCMO Baseband amplifier output bias: Installing LK11 connects VREF to VCMO. This sets the bias level LK11 installed on the baseband amplifiers to VREF, which is equal to approximately 1 V. Alternatively, with LK11 removed, the bias level of the baseband amplifiers can be set by applying an external voltage to the VCMO test point. C8, C9, R4, R5 Baseband amplifier outputs and output filter: Additional low-pass filtering can be provided at R4, R5 = 0 Ω (I and Q) the baseband output with these filters. C10 (I and Q) Mixer output dc-blocking capacitors: The mixer outputs are biased to VCMO. To prevent C10 = 0 Ω damage to test equipment that cannot tolerate dc biases, C10 is provided to block the dc component, thus protecting the test equipment. C1 to C7, Baseband filter: These components are provided for baseband filtering between the mixer All = OPEN R1, R2, outputs and the baseband amplifier inputs. The baseband amplifier input impedance is high L1 to L3 and the filter termination impedance is set by R2. See Table 7 for the jumper settings. (I and Q) LK5 (I and Q) Offset compensation loop disable: Installing these jumpers will disable the offset compensation LK5x = OPEN loop for the corresponding channel. Table 7. Filter-Jumper Configuration Options Condition LK1x LK2x LK3x LK4x xMXO to xAIN Directly • • xMXO to xAIN via Filter • • xMXO to J1x Directly, xAIN Unused • • xMXO to J1x via Filter, xAIN Unused • • Drive xAIN from J1x • Rev. A | Page 27 of 28

AD8348 OUTLINE DIMENSIONS 9.80 9.70 9.60 28 15 4.50 4.40 4.30 6.40 BSC 1 14 PIN 1 0.65 BSC 1.20 MAX 0.15 0.05 8° 0.75 0.30 0.20 0° 0.60 COPL0A.1N0ARITY 0.19 SEPALTAINNGE 0.09 0.45 COMPLIANT TO JEDEC STANDARDS MO-153AE Figure 65. 28-Lead Thin Shrink Small Outline Package [TSSOP] (RU-28) Dimensions shown in millimeters ORDERING GUIDE Model Temperature Range Package Description Package Option AD8348ARU −40°C to +85°C 28-Lead Thin Shrink Small Outline Package [TSSOP] RU-28 AD8348ARU-REEL7 −40°C to +85°C 28-Lead Thin Shrink Small Outline Package [TSSOP] 7” Tape and Reel RU-28 AD8348ARUZ1 −40°C to +85°C 28-Lead Thin Shrink Small Outline Package [TSSOP] RU-28 AD8348ARUZ-REEL71 −40°C to +85°C 28-Lead Thin Shrink Small Outline Package [TSSOP] 7” Tape and Reel RU-28 AD8348-EVAL Evaluation Board 1 Z = Pb-free part. ©2006 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. C03678-0-4/06(A) Rev. A | Page 28 of 28

Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: A nalog Devices Inc.: AD8348ARU AD8348ARU-REEL7 AD8348ARUZ AD8348ARUZ-REEL7 AD8348-EVALZ