140 MHz to 1000 MHz Quadrature Modulator AD8345 FEATURES FUNCTIONAL BLOCK DIAGRAM 140 MHz to 1000 MHz operating frequency AD8345 +2.5 dBm P1dB @ 800 MHz IBBP 1 16 QBBP −155 dBm/Hz noise floor IBBN 2 15 QBBN 0.5 degree RMS phase error (IS95) COM3 3 14 COM3 0.2 dB amplitude balance + Single 2.7 V to 5.5 V supply COM1 4 13 COM3 Pin-compatible with AD8346 and AD8349 LOIN 5 12 VPS2 16-lead TSSOP_EP package PHASE LOIP 6 SPLITTER 11 VOUT APPLICATIONS VPS1 7 10 COM2 Cellular communication systems BIAS WFix-CeDd MbrAo/aCdDbManAd/G aScMce/sPsC sSy/sItSeMm tsr aLnMsDceSi/vMeMrs DS ENBL 8 9 COM3 00932-001 Wireless LAN Figure 1. Wireless local loop Digital TV/CATV modulators Single sideband upconverter PRODUCT DESCRIPTION APPLICATIONS The AD8345 is a silicon RFIC quadrature modulator, designed The AD8345 modulator can be used as the IF transmit for use from 140 MHz to 1000 MHz. Its excellent phase modulator in digital communication systems such as GSM and accuracy and amplitude balance enable the high performance PCS transceivers. It can also directly modulate an LO signal to direct modulation of an IF carrier. produce QPSK and various QAM formats for 900 MHz communication systems as well as digital TV and CATV The AD8345 accurately splits the external LO signal into two systems. quadrature components through the polyphase phase splitter network. The I and Q LO components are mixed with the Additionally, this quadrature modulator can be used with direct baseband I and Q differential input signals. Finally, the outputs digital synthesizers in hybrid phase-locked loops to generate of the two mixers are combined in the output stage to provide a signals over a wide frequency range with millihertz resolution. single-ended 50 Ω drive at VOUT. The AD8345 modulator is supplied in a 16-lead TSSOP_EP package. Its performance is specified over a −40°C to +85°C temperature range. This device is fabricated on Analog Devices’ advanced silicon bipolar process. Rev. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Tel: 781.329.4700 www.analog.com Trademarks and registered trademarks are the property of their respective owners. Fax: 781.461.3113 © 2005 Analog Devices, Inc. All rights reserved.

AD8345 TABLE OF CONTENTS Features..............................................................................................1 Basic Connections..........................................................................12 Applications.......................................................................................1 LO Drive......................................................................................12 Functional Block Diagram..............................................................1 LO Frequency Range.................................................................12 Product Description.........................................................................1 Baseband I and Q Channel Drive............................................13 Applications.......................................................................................1 Reduction of LO Leakage..........................................................13 Revision History...............................................................................2 Single-Ended I and Q Drive......................................................13 Specifications.....................................................................................3 RF Output....................................................................................14 Absolute Maximum Ratings............................................................4 Application with TxDAC®.........................................................14 ESD Caution..................................................................................4 Soldering Information...............................................................15 Pin Configuration and Function Descriptions.............................5 Evaluation Board........................................................................15 Typical Performance Characteristics.............................................6 Characterization Setups.................................................................17 Equivalent Circuits.........................................................................10 SSB Setup.....................................................................................17 Circuit Description.........................................................................11 Modulated Waveform Setup.....................................................18 Overview......................................................................................11 CDMA IS95.................................................................................18 LO Interface.................................................................................11 WCDMA 3GPP..........................................................................18 Differential Voltage-to-Current Converter.............................11 GSM.............................................................................................18 Mixers..........................................................................................11 Outline Dimensions.......................................................................19 Differential-to-Single-Ended Converter.................................11 Ordering Guide..........................................................................19 Bias...............................................................................................11 REVISION HISTORY 12/05—Rev. A to Rev. B Updated Format..................................................................Universal Changes to Ordering Guide..........................................................19 4/05—Rev. 0 to Rev. A Updated Format..................................................................Universal Change to Part Name.........................................................Universal Updated Outline Dimensions.......................................................19 Changes to Ordering Guide..........................................................19 7/01—Revision 0: Initial Version Rev. B | Page 2 of 20

AD8345 SPECIFICATIONS V = 5 V; LO = −2 dBm @ 800 MHz; 50 Ω source and load impedances; I and Q inputs 0.7 V ±0.3 V on each side for a 1.2 V p-p S differential input, I and Q inputs driven in quadrature @ 1 MHz baseband frequency. T = 25°C, unless otherwise noted. A Table 1. Parameter Min Typ Max Unit Test Conditions/Comments RF OUTPUT Operating Frequency1 140 1000 MHz Output Power 0.5 dBm 140 MHz 0.5 dBm 220 MHz −3 −1 +2 dBm 800 MHz Output P1dB 2.5 dBm Noise Floor −155 dBm/Hz 20 MHz offset from LO, all BB inputs at 0.7 V Quadrature Error 0.5 Degree rms CDMA IS95 setup (see Figure 38) I/Q Amplitude Balance 0.2 dB CDMA IS95 setup (see Figure 38) LO Leakage −41 dBm 140 MHz −40 dBm 220 MHz −42 −33 dBm 800 MHz Sideband Rejection −33 dBc 140 MHz −48 −40 dBc 220 MHz −42 −34 dBc 800 MHz Third Order Distortion −52 dBc Second Order Distortion −60 dBc Equivalent Output IP3 25 dBm Equivalent Output IP2 59 dBm Output Return Loss (S22) −20 dB RESPONSE TO CDMA IS95 See Figure 38 BASEBAND SIGNALS ACPR −72 dBc EVM 1.3 % Rho 0.9995 LO INPUT LO Drive level −10 −2 0 dBm LOIP Input Return Loss (S11)2 −5 dB No termination on LOIP, LOIN at ac ground −9 dB 50 Ω terminating resistor, differential drive via balun BASEBAND INPUTS Input Bias Current 10 μA Input Capacitance 2 pF DC Common Level 0.6 0.7 0.8 V Bandwidth (3 dB) 80 MHz Full power (0.7 V ±0.3 V on each input, see Figure 4) ENABLE Turn-On 2.5 μs Enable high to output within 0.5 dB of final value Turn-Off 1.5 μs Enable low to supply current dropping below 2 mA ENBL High Threshold (Logic 1) +V/2 V S ENBL Low Threshold (Logic 0) +V/2 V S POWER SUPPLIES Voltage 2.7 5.5 V Current Active 50 65 78 mA Current Standby 70 μA 1 For information on operation below 140 MHz, see Figure 29. 2 See the LO Interface section for more details on input matching. Rev. B | Page 3 of 20

AD8345 ABSOLUTE MAXIMUM RATINGS Table 2. Parameter Rating Stresses above those listed under Absolute Maximum Ratings Supply Voltage VPS1, VPS2 5.5 V may cause permanent damage to the device. This is a stress Input Power LOIP, LOIN (re 50 Ω) 10 dBm rating only; functional operation of the device at these or any IBBP, IBBN, QBBP, QBBN 0 V, 2.5 V other conditions above those indicated in the operational Internal Power Dissipation 500 mW section of this specification is not implied. Exposure to absolute θ (Exposed Paddle Soldered Down) 30°C/W maximum rating conditions for extended periods may affect JA θ (Exposed Paddle not Soldered Down) 95°C/W device reliability. JA Maximum Junction Temperature 150°C Operating Temperature Range −40°C to +85°C Storage Temperature Range −65°C to +150°C Lead Temperature Range (Soldering 60 sec) 300°C ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degrada- tion or loss of functionality. Rev. B | Page 4 of 20

AD8345 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS IBBP 1 16 QBBP IBBN 2 15 QBBN COM3 3 14 COM3 AD8345 COM1 4 TOP VIEW 13 COM3 LOIN 5 (Not to Scale) 12 VPS2 LOIP 6 11 VOUT VPS1 7 10 COM2 ENBL 8 9 COM3 00932-002 Figure 2. Pin Configuration Table 3. Pin Function Descriptions Pin No. Mnemonic Description Equivalent Circuit 1, 2 IBBP, IBBN I Channel Baseband Differential Input Pins. These high impedance inputs should be Circuit A dc-biased to approximately 0.7 V. Nominal characterized ac swing is 0.6 V p-p on each pin (0.4 V to 1 V). This gives a differential drive of 1.2 V p-p. Inputs are not self-biasing, so external biasing circuitry must be used in ac-coupled applications. 3, 9, 13, 14 COM3 Ground Pin for Input V-to-I Converters and Mixer Core. 4 COM1 Ground Pin for the LO Phase Splitter and LO Buffers. 5, 6 LOIN, LOIP Differential LO Drive Pins. Internal dc bias (approximately 1.8 V @ V = 5 V) is supplied. Circuit B S Pins must be ac-coupled. Single-ended or differential drive is permissible. 7 VPS1 Power Supply Pin for the Bias Cell and LO Buffers. This pin should be decoupled using local 1000 pF and 0.01 μF capacitors. 8 ENBL Enable Pin. A high level enables the device; a low level puts the device in sleep mode. Circuit C 10 COM2 Ground Pin for the Output Stage of Output Amplifier. 11 VOUT 50 Ω DC-Coupled RF Output. Pin should be ac-coupled. Circuit D 12 VPS2 Power Supply Pin for Baseband Input Voltage to Current Converters and Mixer Core. This pin should be decoupled using local 1000 pF and 0.01 μF capacitors. 15, 16 QBBN, QBBP Q Channel Baseband Differential Input Pins. Inputs should be dc-biased to approxi- Circuit A mately 0.7 V. Nominal characterized ac swing is 0.6 V p-p on each pin (0.4 V to 1 V). This gives a differential drive level of 1.2 V p-p. Inputs are not self-biasing, so external biasing circuitry must be used in ac-coupled applications. Rev. B | Page 5 of 20

AD8345 TYPICAL PERFORMANCE CHARACTERISTICS 0 0 –2 VS = 5V, DIFFERENTIAL INPUT = 1.2V p-p –2 TA = –40°C –4 –6 m) –4 m) dB dB –8 B ( –6 R ( 1d TA = +25°C WE–10 T P –8 O U B P–12 UTP –10 S O S–14 VS = 2.7V, DIFFERENTIAL INPUT = 200mV p-p SSB –12 TA = +85°C –16 ––1280 00932-007 ––1164 00932-010 2503003504004505005506006507007508008509009501000 2503003504004505005506006507007508008509009501000 LO FREQUENCY (MHz) LO FREQUENCY (MHz) Figure 3. Single Sideband (SSB) Output Power (POUT) vs. LO Frequency (FLO) Figure 6. SSB Output 1 dB Compression Point (OP1dB) vs. FLO (I and Q Inputs Driven in Quadrature at Baseband Frequency (FBB) = 1 MHz; (VS = 2.7 V, LO Level = −2 dBm, TA = 25°C) I and Q Inputs Driven in Quadrature, FBB = 1 MHz) 1.0 4.0 0.5 3.5 B) 0.0 TA = +85°C d–0.5 3.0 ATION (––11..50 VS = 2.7V, 5V DIFFERENTIAL INPUT = 200mV p-p B (dBm) 2.5 TA = +25°C WERVARI––22..50 VS = 5V DIFFERENTIAL INPUT = 1.2V p-p TPUT P1d 12..50 TA = –40°C O–3.0 U UT P–3.5 SB O 1.0 P S T–4.0 0.5 U O –4.5 ––55..050.1 1 10 1000932-0080 –00..5025030035040045050055060065070075080085090095010000932-0110 BASEBAND FREQUENCY (MHz) LO FREQUENCY (MHz) Figure 4. I and Q Input Bandwidth Figure 7. SSB Output 1 dB Compression Point (OP1dB) vs. FLO (TA = 25°C, FLO = 800 MHz, LO Level = −2 dBm, (VS = 5 V, LO Level = −2 dBm, I and Q Inputs Driven in Quadrature) I and Q Inputs Driven in Quadrature, FBB = 1 MHz) 0 –40 –2 –4 VS = 5V, DIFFERENTIAL INPUT = 1.2V p-p –41 VS = 5V, DIFFERENTIAL INPUT = 1.2V p-p –6 m)–42 B m) –8 H (d–43 B–10 G d U–44 OWER (––1142 DTHRO–45 VS = 2.7V, DIFFERENTIAL INPUT = 200mV p-p P E B –16 VS = 2.7V, DIFFERENTIAL INPUT = 200mV p-p FE–46 SS–18 ER –47 RI –20 R A–48 –22 C ––2264 00932-009 ––5409 00932-012 –40 –20 0 20 40 60 80 2503003504004505005506006507007508008509009501000 TEMPERATURE (°C) LO FREQUENCY (MHz) Figure 5. SSB POUT vs. Temperature Figure 8. Carrier Feedthrough vs. FLO (FLO = 800 MHz, LO Level = −2 dBm, FBB = 1 MHz, (LO Level = −2 dBm, TA = 25°C) I and Q Inputs Driven in Quadrature) Rev. B | Page 6 of 20

AD8345 –30 –26 –32 –28 Bm) –34 Bc) –30 VS = 5V, DIFFERENTIAL INPUT = 1.2V p-p GH (d –36 ON (d –32 U –38 SI O S R E –34 TH –40 VS = 5V, DIFFERENTIAL INPUT = 1.2V p-p PR D P E U –36 E –42 S ER F –44 AND –38 RI B R E CA –46 VS = 2.7V, DIFFERENTIAL INPUT = 200mV p-p SID –40 ––5408 00932-013 ––4424 VS = 2.7V, DIFFERENTIAL INPUT = 200mV p-p 00932-016 –40 –20 0 20 40 60 80 0 5 10 15 20 25 30 35 40 45 50 TEMPERATURE (°C) BASEBAND FREQUENCY (MHz) Figure 9. Carrier Feedthrough vs. Temperature Figure 12. Sideband Suppression vs. FBB (FLO = 800 MHz, LO Level = −2 dBm) (TA = 25°C, FLO = 800 MHz, LO Level = −2 dBm, I and Q Inputs Driven in Quadrature) 30 –35 28 T = +85 –36 26 T = –40 24 c) –37 22 dB VS = 2.7V, DIFFERENTIAL INPUT = 200mV p-p 20 N ( –38 E O G 18 SI –39 A S T 16 E N R CE 14 PP –40 R U PE 12 D S –41 10 N 8 BA –42 6 SIDE –43 VS = 5V, DIFFERENTIAL INPUT = 1.2V p-p 420–86 –82 –78 –74 –70 –66 –62 –58 –54 –5000932-014 ––4445–40 –20 0 20 40 60 80 00932-017 CARRIER FEEDTHROUGH (dBm) TEMPERATURE (°C) Figure 10. Carrier Feedthrough Distribution at Temperature Extremes After Figure 13. Sideband Suppression vs. Temperature Feedthrough Nulled to <−65 dBm at TA = 25°C (FLO = 800 MHz, LO Level = −2 dBm, FBB = 1 MHz, (FLO = 800 MHz, LO Level = −2 dBm) I and Q Inputs Driven in Quadrature) –30 –20 –32 –25 dBc) –34 VS = 2.7V, DIFFERENTIAL INPUT = 200mV p-p dBc)–30 VS = 5V, DIFFERENTIAL INPUT = 1.2V p-p ON ( –36 ON (–35 SSI –38 RTI E O–40 R T P –40 S EBAND SUP ––4424 VS = 5V, DIFFERENTIAL INPUT = 1.2V p-p D ORDER DI––5405 VS = 2.7V, DIFFERENTIAL INPUT = 200mV p-p SID –46 HIR–55 T ––4580 00932-015 ––6650 00932-018 2503003504004505005506006507007508008509009501000 0 5 101 52 02 53 03 54 04 55 0 LO FREQUENCY (MHz) BASEBAND FREQUENCY (MHz) Figure 11. Sideband Suppression vs. FLO Figure 14. Third Order Distortion vs. FBB (TA = 25°C, LO Level = −2 dBm, FBB = 1 MHz, (TA = 25°C, FLO = 800 MHz, LO Level = −2 dBm, I and Q Inputs Driven in Quadrature) I and Q Inputs Driven in Quadrature) Rev. B | Page 7 of 20

AD8345 –45 80 –50 75 c) B d 70 N ( –55 A) VS = 5V, DIFFERENTIAL INPUT = 1.2V p-p DISTORTIO –60 VS = 5V, DIFFERENTIAL INPUT = 1.2V p-p URRENT (m 6605 R –65 C DE LY 55 R P O P RD –70 SU 50 VS = 2.7V, DIFFERENTIAL INPUT = 200mV p-p HI T ––7850 VS = 2.7V, DIFFERENTIAL INPUT = 200mV p-p 00932-019 4405 00932-022 –40 –20 0 20 40 60 80 –40 –20 0 20 40 60 80 TEMPERATURE (°C) TEMPERATURE (°C) Figure 15. Third Order Distortion vs. Temperature Figure 18. Power Supply Current vs. Temperature (FLO = 800 MHz, LO Level = −2 dBm, FBB = 1 MHz, I and Q Inputs Driven in Quadrature) 1GHz SMITH CHART –10 –2 NORMALIZED TO 50Ω –15 –4 WITH 50Ω c) –20 –6 TION (dB ––2350 SSB POUT ––810 R (dBm) OR –35 –12 WE T O ER DIS ––4405 THIRD ORDER DISTORTION ––1146 PUT P 250MHz ORD –50 –18 OUT HIRD –55 –20 SSB T –60 –22 ––76050.0 BAS0.E5BAND D1IF.0FERENT1IA.5L INPUT 2V.0OLTAGE 2(.V5 p-p) 3.0––2246 00932-020 WITH 100Ω 1GHz LOORI NT ENROM BINAALTUIONN 00932-023 Figure 16. Third Order Distortion and SSB POUT vs. Baseband Differential Input Figure 19. Smith Chart of LOIN Port S11 (LOIP Pin AC-Coupled to Ground); Voltage (TA = 25°C, FLO = 800 MHz, LO Level = −2 dBm, FBB = 1 MHz, VS = 2.7 V) Curves with Balun and External Termination Resistors Also Shown (VS = 5 V, TA = 25°C) –5 4 –10 2 0 –15 0 c) dB –20 –2 m) –5 RTION ( ––2350 SSB POUT ––64 ER (dB B) –10 ORDER DISTO ––––34455050 ––––8111024 OUTPUT POW TURN LOSS (d –15 HIRD –55 THIRD ORDER DISTORTION –16 SSB RE –20 VS = 2.7V T –60 –18 ––67500.0 0.5 1.0 1.5 2.0 2.5 3.0––2202 00932-021 ––3205 VS = 5V 00932-024 BASEBAND DIFFERENTIAL INPUT VOLTAGE (V p-p) 2503003504004505005506006507007508008509009501000 FREQUENCY (MHz) Figure 17. Third Order Distortion and SSB POUT vs. Baseband Differential Input Figure 20. Return Loss (S22) of VOUT Output (TA = 25°C) Voltage (TA = 25°C, FLO = 800 MHz, LO Level = −2 dBm, FBB = 1 MHz, VS = 5 V) Rev. B | Page 8 of 20

AD8345 –150 –36 –151 –38 –152 m) B m/Hz)–153 GH (d–40 OOR (dB––115545 VS = 5V DTHROU–42 VS = 5.5V L E–44 F–156 E E F S R NOI–157 RIE–46 R –158 A C –48 ––116509 00932-025 –50 00932-026 –10 –9 –8 –7 –6 –5 –4 –3 –2 –1 0 1 2 –10 –9 –8 –7 –6 –5 –4 –3 –2 –1 0 1 2 LO LEVEL (dBm) LO LEVEL (dBm) Figure 21. Noise Floor vs. LO Input Power Figure 22. LO Feedthrough vs. LO Input Power (TA = 25°C, FLO = 800 MHz, VS = 5 V, All I and Q Inputs Are DC-Biased to 0.7 V) (TA = 25°C, LO = 800 MHz, VS = 5.5 V) Noise Measured at 20 MHz Offset from Carrier Rev. B | Page 9 of 20

AD8345 EQUIVALENT CIRCUITS VPS2 VPS2 BUFFER TO MIXER CORE 100kΩ 100kΩ ENBL INPUT TO BIAS FOR STARTUP/ CURRENT 100kΩ SHUTDOWN MIRROR 00932-003 00932-005 Figure 23. Circuit A Figure 25. Circuit C VPS2 VPS1 40Ω LOIN PHASE VOUT LOIP SPLITTER CONTINUES 00932-004 40Ω 00932-006 Figure 24. Circuit B Figure 26. Circuit D Rev. B | Page 10 of 20

AD8345 CIRCUIT DESCRIPTION OVERVIEW DIFFERENTIAL VOLTAGE-TO-CURRENT CONVERTER The AD8345 can be divided into the following sections: local oscillator (LO) interface, mixer, differential voltage-to-current In this circuit, each baseband input pin is connected to an op amp (V-to-I) converter, differential-to-single-ended (D-to-S) driving a transistor connected as an emitter follower. A resistor converter, and bias. A block diagram of the part is shown in between the two emitters maintains a varying current proportional Figure 27. to the differential input voltage through the transistor. These currents are fed to the two mixers in differential form. LOIP PHASE LOIN SPLITTER MIXERS There are two double-balanced mixers, one for the in-phase IBBP channel (I channel) and one for the quadrature channel IBBN (Q channel). Each mixer uses the Gilbert-cell design with four Σ OUT cross-connected transistors. The bases of the transistors are QQBBBBNP 00932-027 douritvpeunt bcyu rtrheen LtsO fr soimgn tahl eo ft wthoe m coixrreerssp aorne dsuinmg mcheadn tnoegle. tThheer in Figure 27. AD8345 Block Diagram two load resistors. The signal developed across the load resistors The LO interface generates two LO signals at 90° of phase is sent to the differential-to-single-ended converter. difference with each other, to drive two mixers in quadrature. DIFFERENTIAL-TO-SINGLE-ENDED CONVERTER Baseband signals are converted into current form in the differential V-to-I converters, feeding into the two mixers. The The differential-to-single-ended converter consists of two outputs of the mixers are combined to feed the differential-to- emitter followers driving a totem-pole output stage whose single-ended converter, which provides a 50 Ω output interface. output impedance is established by the emitter resistors in the Bias currents to each section are controlled by the enable output transistors. The output of this stage is connected to the (ENBL) signal. A detailed description of each section follows. output pin (VOUT). LO INTERFACE BIAS The LO interface consists of interleaved stages of polyphase A band gap reference circuit based on the Δ-VBE principle generates the proportional-to-absolute temperature (PTAT) as phase splitters and buffer amplifiers. The polyphase phase splitter contains resistors and capacitors connected in a circular well as temperature-stable currents used by the different manner to split the LO signal into I and Q paths in precise sections as references. When the band gap reference is disabled quadrature with each other. The signal on each path goes by pulling down the voltage at the ENBL pin, all other sections through a buffer amplifier to make up for the loss and high are shut off accordingly. frequency roll-off. The two signals then go through another polyphase network to enhance the quadrature accuracy. The broad operating frequency range (140 MHz to 1000 MHz) is achieved by staggering the RC time constants of each stage of the phase splitters. The outputs of the second phase splitter are fed into the driver amplifiers for the mixers’ LO inputs. Rev. B | Page 11 of 20

AD8345 BASIC CONNECTIONS IP AD8345 1 IBBP QBBP 16 QP IN 2 IBBN QBBN 15 C6 3 COM3 COM3 14 QN 1000pF 4 COM1 COM3 13 LO R1 5 T1 1 C7 5 LOIN VPS2 12 C1 C2 +VS 50Ω ETC1-1-13 2 1000pF 6 LOIP VOUT 11 1000pF 0.01μF VOUT 4 3 C5 7 VPS1 COM2 10 1000pF +VS 8 ENBL COM3 9 C0.401μF C10300pF 00932-028 Figure 28. Basic Connections The basic connections for operating the AD8345 are shown in LO FREQUENCY RANGE Figure 28. A single power supply of between 2.7 V and 5.5 V is The frequency range on the LO input is limited by the internal applied to the VPS1 pin and the VPS2 pin. A pair of ESD quadrature phase splitter. The phase splitter generates drive protection diodes is connected internally between the VPS1 pin signals for the internal mixers which are 90° out of phase and the VPS2 pin so these must be tied to the same potential. relative to one another. Both pins should be individually decoupled using 1000 pF and 0.01 μF capacitors, located as close as possible to the device. For Outside of the specified LO frequency range of 140 MHz to 1 GHz, normal operation, the enable pin (ENBL) must be pulled high. this quadrature accuracy degrades, resulting in decreased sideband The turn-on threshold for ENBL is V/2. COM1 to COM3 suppression. See Figure 11 for a plot of sideband suppression vs. S should all be tied to the same low impedance ground plane. LO frequency from 250 MHz to 1 GHz. Figure 29 shows the sideband suppression of a typical device from 70 MHz to 300 MHz. LO DRIVE 0 In Figure 28, a 50 Ω resistor to ground combines with the –5 dimevpiecde’as nhcieg ho fi nappuptr oimximpeadtaenlyc 5e 0to Ω p (rsoevei dFei gaunr eo v1e9r afollr i an ppulot t of dBc) –10 VS = 5V, DIFFERENTIAL INPUT = 1.2V LO port input impedance). For maximum LO suppression at N ( –15 O the output, a differential LO drive is recommended. In SSI –20 E Figure 28, this is achieved using a balun (M/A-COM part PR –25 P number ETC1-1-13). U S –30 D N The outputs of the balun are ac-coupled to the LO inputs, which A –35 B E have a bias level of approximately 1.8 V dc. An LO drive level of D –40 SI −de2g draBdme liisn reeacroitmy mwhenilde eldow foerr lloewveelsst t oenudtp tuot innocirseea. sHe itghhee nr oleisvee ls ––5405 00932-029 floor slightly. For example, reducing the LO power from −2 dBm 40 60 80 100 120 140 160 180 200 220 240 260 280 300 LO FREQUENCY (MHz) to −10 dBm increases the noise floor by approximately 0.3 dB Figure 29. Typical Lower Frequency Sideband Suppression Performance (see Figure 21). The LO input pins can be driven single-ended at the expense of slightly higher LO leakage. LOIN is ac-coupled to ground using a capacitor and LOIP is driven through a coupling capacitor from a (single-ended) 50 Ω source. (This scheme could also be reversed with the drive signal being applied to LOIN.) Rev. B | Page 12 of 20

AD8345 BASEBAND I AND Q CHANNEL DRIVE The procedure for reducing the LO feedthrough is simple. In order to isolate the LO in the output spectrum, a single The I channel and Q channel baseband inputs should be driven sideband configuration is recommended (set I and Q signals to differentially. This is convenient as most modern high-speed sine and cosine waves at, for example, 100 kHz; set LO to DACs have differential outputs. For optimal performance at F − 100 kHz). An offset voltage is applied from the I DAC V = 5 V, the drive signal should be a 1.2 V p-p differential RF S until the LO leakage reaches a trough. With this offset level signal with a bias level of 0.7 V; that is, each input should swing held, an offset voltage is applied to the Q DAC until a (lower) from 0.4 V to 1 V. If the AD8345 is being run on a lower supply trough is reached. voltage, then the peak-to-peak voltage on the I and Q channel inputs must be reduced to avoid input clipping. For example, at LO leakage compensation holds up well over temperature. a supply voltage of 2.7 V, a 200 mV p-p differential drive is Figure 10 shows the effect of temperature on LO leakage after recommended. This results in a corresponding reduction in compensation at ambient. output power (see Figure 3). The I and Q inputs have a large input bandwidth of approximately 80 MHz. At lower baseband Compensated LO leakage degrades somewhat as the frequency input levels, the input bandwidth increases (see Figure 4). is moved away from the frequency at which the compensation was performed. This is due to the effects of LO to RF output If the baseband signal has a high peak-to-average ratio (such as leakage, which is not a result of offsets on the I and Q inputs. CDMA or WCDMA), then the rms signal strength must be backed off from this peak level in order to prevent clipping of SINGLE-ENDED I AND Q DRIVE the signal peaks. Where only single-ended I and Q signals are available, a differential amplifier such as the AD8132 or AD8138 can be Clipping of signal peaks tends to increase signal leakage into used to generate the required differential drive signal for the adjacent channels. Backing off the I and Q signal strength, in AD8345. the manner recommended, reduces the output power by a corresponding amount. This also applies to multicarrier Although most DACs have differential outputs, using a single- applications where the per-carrier output power is lower by ended, low-pass filter between the dual DAC and the I and Q 3 dB for each doubling of the number of output carriers. inputs can be more desirable from the perspective of component count and cost. As a result, the output signal from The I and Q inputs have high input impedances because they the filter must be converted back to differential mode and connect directly to the bases of PNP transistors. If a dc-coupled possibly be rebiased to 0.7 V common mode. filter is being used between a DAC and the modulator inputs, then the filter must be terminated with the appropriate Figure 30 shows a circuit that converts a ground-referenced, resistance. If the filter is differential, then the termination single-ended signal to a differential signal and adds the required resistor should be connected across the I and Q differential 0.7 V bias voltage. Two AD8132 differential op amps configured inputs. for unity gain are used. With a 50 Ω input impedance, this REDUCTION OF LO LEAKAGE circuit is configured to accept a signal from a 50 Ω source (for example, a low-pass filter). The input impedance can be easily Because the I and Q signals are being effectively multiplied with changed by replacing the 49.9 Ω shunt resistor (and the the LO, any internal offset voltages on these inputs result in corresponding 24.9 Ω resistor on the inverting input) with the leakage of the LO. The nominal LO leakage of −42 dBm, which appropriate value. The required dc-bias level is conveniently results from these internal offset voltages, can be reduced further added to the signal by applying 0.7 V to the V pins of the OCM by applying offset compensation voltages on the I and Q inputs. differential amplifiers. (Note that LO feedthrough is reduced by varying the differential offset voltages on the I and Q inputs, not by varying the nominal Differential amplifiers, such as the AD8132 and AD8138, can bias level of 0.7 V.) The reduction is easily accomplished by also be used to implement active filters. For more information programming (and then storing) the appropriate DAC offset on this topic, refer to the data sheets of these devices. code. This does, however, require dc coupling the path from the DAC to the I and Q inputs. (DC coupling is also advantageous from the perspective of I and Q input biasing if the DAC is capable of delivering a bias level of 0.7 V.) Rev. B | Page 13 of 20

AD8345 +5V 10kΩ + 0.1μF 10μF 0.01μF 1000pF 1000pF 0.01μF 1.5kΩ 348Ω 348Ω IIN 8 3 49.9Ω 5 VPS1 VPS2 2 AD8132 0.1μF IBBP 348Ω 4 1 6 VOUT 24.9Ω IBBN Σ 348Ω 0.1μF 10μF LOIP –5V + PHASE QBBP SPLITTER +5V LOIN + QBBN AD8345 0.1μF 10μF 348Ω COM1 COM2 COM3 348Ω QIN 8 3 49.9Ω 5 2 AD8132 0.1μF 348Ω 4 1 6 24.9Ω 348Ω + 10μF 0.1μF 00932-030 –5V Figure 30. Single-Ended 1Q Drive Circuit Note that this circuit assumes that the single-ended I and Q APPLICATION WITH TxDAC® signals are ground-referenced. Any differential dc-offsets result Figure 31 shows the AD8345 driven by the AD9761 TxDAC. in increased LO leakage at the output of the AD8345. (Any of the devices in the Analog Devices’ TxDAC family can also be used in this application.) It is possible to drive the baseband inputs with a single-ended signal biased to 0.7 V, with the unused inputs being biased to a The I and Q DACs generate differential output currents of 0 mA dc level of 0.7 V. However, this mode of operation is not recom- to 10 mA and 10 mA to 0 mA, respectively. The combination of mended because any dc level difference between the bias level 140 Ω resistors shunted to ground off each DAC output, along of the drive signal and the dc level on the unused input with 210 Ω resistors shunted between each differential DAC (including the effect of temperature drift) results in increased pair, produces a baseband signal into the AD8345 I and Q LO leakage. In addition, the maximum output power is reduced inputs that has a differential peak-to-peak swing of 1.2 V with a by 6 dB. dc common-mode bias of 700 mV. RF OUTPUT The RF output is designed to drive a 50 Ω load but should be ac coupled as shown in Figure 28. If the I and Q inputs are driven in quadrature by 1.2 V p-p signals, then the resulting output power is approximately −1 dBm (see Figure 3). The RF output impedance is very close to 50 Ω. As a result, no additional matching circuitry is required if the output is driving a 50 Ω load. Rev. B | Page 14 of 20

AD8345 DVDD DCOM AVDD VPS1 VPS2 IOUTA IBBP LATCH "I" 2⋅ 210Ω "I" DAC VOUT IOUTB 140Ω 140Ω IBBN Σ DAC DATA AD9761 INPUTS LOIP QOUTA QBBP PHASE SPLITTER LATCH "Q" LOIN 2⋅ 210Ω "Q" DAC SEWLREICTET COMNUTRXOL QOUTB 140Ω 140Ω QBBN AD8345 CLOCK SLEEP FSADJ REFIO 2RkSΩET 0.1μF 00932-031 Figure 31. AD8345/TxDAC Interface SOLDERING INFORMATION The board is powered by a single supply (V) in the range 2.7 V S to 5.5 V. The power supply is decoupled by 0.01 μF and 1000 pF The AD8345 is packaged in a 16-lead TSSOP_EP package. For capacitors. The circuit closely follows the basic connection optimum thermal conductivity, the exposed pad can be schematic with SW1 in Position B. If SW1 is in Position A, the soldered to the exposed metal of a ground plane. This results in enable pin (ENBL) is pulled to ground by a 10 kΩ resistor, and a junction-to-air thermal impedance (θ ) of 30°C/W. However, JA the device is in its power-down mode. soldering is not necessary for safe operation. If the exposed pad is not soldered down, then the θ is equal to 95°C/W. JA All connectors are SMA-type. The I and Q inputs are dc-coupled to EVALUATION BOARD allow a direct connection to a dual DAC with differential outputs. Resistor pads are provided in case termination at the I and Q inputs Figure 32 shows the schematic of the AD8345 evaluation board. is required. The local oscillator input (LO) is terminated to approxi- Note that uninstalled components are marked as open. This is a mately 50 Ω with an external 50 Ω resistor to ground. A 1:1 wide- 4-layer board, with the two center layers used as ground plane, band transformer (ETC1-1-13) provides a differential drive to the and top and bottom layers used as signal and power planes. AD8345’s differential LO input. R1 AD8345 R9 (OPEN) (OPEN) IP 1 IBBP QBBP 16 QP IN 2 IBBN QBBN 15 QN R2 R10 (OPEN) (OPEN) 3 COM3 COM3 14 R11 4 COM1 COM3 13 0Ω C1 VPOS 1000pF C5 C6 LO 5 1 5 LOIN VPS2 12 1000pF 0.01μF R6 T1 C2 R12 50Ω ETC1-1-13 2 1000pF 0Ω 4 3 6 LOIP VOUT 11 VOUT R14 R15 C7 (OPEN) (OPEN) 1000pF VPOS 7 VPS1 COM2 10 C3 R7 C4 0.01μF 0Ω 1000pF 8 ENBL COM3 9 A ENBL R8 10kΩ VBPOSSW1 00932-032 Figure 32. Evaluation Board Schematic Rev. B | Page 15 of 20

AD8345 00932-033 Figure 33. Evaluation Board Silkscreen 00932-034 Figure 34. Layout of Evaluation Board, Top Layer 00932-035 Figure 35. Layout of Evaluation Board, Bottom Layer Rev. B | Page 16 of 20

AD8345 CHARACTERIZATION SETUPS SSB SETUP Essentially, two primary setups are used to characterize the 0 AD8345. These setups are shown in Figure 37 and Figure 38. –10 Figure 37 shows the setup used to evaluate the product as a single sideband modulator. The interface board converts the –20 single-ended I and Q inputs from the arbitrary function –30 m) generator to differential inputs with a dc bias of approximately B d–40 0.7 V. The interface board also provides connections for power E ( supply routing. The HP34970A and its associated plug-in 34901 TUD–50 are used to monitor power supply currents and voltages being PLI–60 M supplied to the AD8345 characterization board. Two HP34907 A–70 plug-ins are used to provide additional miscellaneous dc and –80 control signals to the interface board. The LO inputs are driven ddiirreeccttllyy wbyit ahn a R sFp escigtrnuaml g aennaelryazteorr., Wanidth t hthe eo Iu ctphuatn inse ml deraisvuerne d –1–0900 00932-037 CENTER = 900MHz SPAN = 1MHz with a sine wave and the Q channel driven with a cosine wave, Figure 36. Typical SSB Output Spectrum the lower sideband is the single sideband output. The typical SSB output spectrum is shown in Figure 36. IEEE HP34970A D1 D2 D3 34901 34907 34907 D1 D2 D3 +15V MAX VPS1 TEKAFG2020 COM INTERFACE I_IN OUTPUT_1 IEEE +25V MAX BOARD IEEE Q_IN OUTPUT_2 –25V MAX VN HP3631 GND ARB FUNCTION GEN VP P1 IN IP QP QN IP QP IN AD8345 QN HP8648C CHARACTERIZATION HP8593E LO BOARD IEEE RFOUT SWEEP OUT ENBL VOUT RF I/P P1 28V SPECTRUM IEEE ANALYZER IEEE PC CONTROLLER 00932-036 Figure 37. Characterization Board SSB Test Setup Rev. B | Page 17 of 20

AD8345 MODULATED WAVEFORM SETUP WCDMA 3GPP To evaluate the AD8345 with modulated waveforms, the setup To evaluate the AD8345 for WCDMA, the 3GPP standard is shown in Figure 38 is used. A Rohde & Schwarz AMIQ signal used with a chip rate of 3.84 MHz. The plot in Figure 40 is an generator with differential outputs is used to generate the ACPR plot of the AD8345 using Test Model 1 from the 3GPP baseband signals. For all measurements, the input level on each specification with 64 channels active. baseband input pin is 0.7 V ±0.3 V peak. The output is –10 measured with a Rohde & Schwarz FSIQ spectrum/vector CH PWR = –10.95dBm analyzer. –20 ACP UP = –52.51dB ACP LOW = –52.41dB –30 PC CONTROL m)–40 AMIQ B d–50 IN IP QP QN E ( IEEE UD–60 T PC CONTROLLER PLI–70 M A IP QP –80 HP8648C IN AD8345 QN –90 CHARACTERIZATION IEEE RFOUT LEONBL BOPA1RD VOUT RF I/PFSIQ IEEE ––110100 00932-040 SPECTRUM CENTER = 380MHz SPAN = 14.7MHz ANALYZER Figure 40. Typical AD8345 WCDMA 3GPP Output Spectrum +15V MAX COM GSM IEEE +25V MAX HP3631–25V MAX 00932-038 Tanod c oQm spiganrea ltsh aer eA gDe8n3e4ra5t oedu tupsuitn tgo M thSeK G mSMod utrlaantisomn,i tG mSaMsk , I Figure 38. Test Setup for Evaluating AD8345 with Modulated Waveforms differential coding, a Gaussian filter, and a symbol rate of 270.833 kHz. The transmit mask is manually generated on the CDMA IS95 FSIQ using the GSM BTS specification for reference. The plot in To measure ACPR, the I and Q input signals used are generated Figure 41 shows that the AD8345 meets the GSM transmit with Pilot channel (Walsh Code 00), Sync channel (WC 32), Paging mask requirements. channel (WC 01), and six Traffic (WC 08, 09, 10, 11, 12, 13) 0 channels active. Figure 39 shows the typical output spectrum for this configuration. –10 –20 To perform EVM, Rho, phase, and amplitude balance –30 measurements, the I and Q input signals used are generated m) B with only the Pilot channel (Walsh Code 00) active. d–40 E ( –10 UD–50 T –20 CAHC PP WUPR = = – –7122.9.4d1BdBm MPLI–60 ACP LOW = –72.9dB A –70 –30 –80 –40 UDE (dBm)––5600 –1–0900 CENTER = 900MHz SPAN = 1MHz 00932-041 T PLI–70 Figure 41. Typical AD8345 GSM Output Spectrum M A –80 –90 ––110100 00932-039 CENTER = 880MHz SPAN = 7.5MHz Figure 39. Typical IS95 Output Spectrum Rev. B | Page 18 of 20

AD8345 OUTLINE DIMENSIONS 5.10 5.00 BOTTOM 4.90 VIEW 16 9 TOP 4.50 6.40 EXPOSED 3.00 VIEW 4.40 BSC PAD SQ 4.30 (Pins Up) 1 8 1.05 1.20 MAX 1.00 0.80 0.15 0.20 8° 0.00 SPELAANTIENG B0.S6C5 00..3109 0.09 0° 00..7650 0.45 COMPLIANT TO JEDEC STANDARDS MO-153-ABT Figure 42. 16-Lead Thin Shrink Small Outline with Exposed Pad (TSSOP_EP) (RE-16-2) Dimensions shown in millimeters ORDERING GUIDE Model Temperature Range Package Description Package Option AD8345ARE −40°C to +85°C 16-Lead TSSOP with Exposed Pad, Tube RE-16-2 AD8345ARE-REEL7 −40°C to +85°C 16-Lead TSSOP with Exposed Pad, 7" Tape and Reel RE-16-2 AD8345AREZ1 −40°C to +85°C 16-Lead TSSOP with Exposed Pad, Tube RE-16-2 AD8345AREZ-RL71 −40°C to +85°C 16-Lead TSSOP with Exposed Pad, 7" Tape and Reel RE-16-2 AD8345-EVAL Evaluation Board 1 Z = Pb-free part. Rev. B | Page 19 of 20

AD8345 NOTES © 2005 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. C00932-0-12/05(B) Rev. B | Page 20 of 20

Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: A nalog Devices Inc.: AD8345ARE AD8345ARE-REEL7 AD8345AREZ AD8345AREZ-RL7 AD8345-EVALZ