DC to 50 MHz, Dual I/Q Demodulator and Phase Shifter Data Sheet AD8333 FEATURES FUNCTIONAL BLOCK DIAGRAM Dual integrated I/Q demodulator H11 H10 FIPFIN NBL P P RR E 16 phase select options on each output (22.5° per step) Quadrature demodulation accuracy BIAS Phase accuracy: ±0.1° PH12 CH 1 ΦSEL Amplitude balance: ±0.05 dB LOGIC 0° PH13 I1NO Bandwidth Φ I1PO COMM 4 × LO: 10 kHz to 200 MHz 90° Q1PO RF: dc to 50 MHz Φ 4LOP Q1NO Baseband: determined by external filtering BUF ÷4 90° Output dynamic range: 159 dB/Hz 4LON Q2NO Φ Q2PO LO drive > 0 dBm (50 Ω); 4 × LO > 1 MHz Supply: ±5 V 0° I2PO Φ Power consumption: 190 mW/channel (380 mW total) PH23 I2NO CH 2 ΦSEL Power-down LOGIC PH22 APPLICATIONS RF2PRF2N 05543-001 Medical imaging (CW ultrasound beamforming) Figure 1. Phased array systems (radar and adaptive antennas) Communication receivers GENERAL DESCRIPTION The AD83331 is a dual phase-shifter and I/Q demodulator that Phase shift is defined by the output of one channel relative to enables coherent summing and phase alignment of multiple another. For example, if the code of Channel 1 is adjusted to analog data channels. It is the first solid-state device suitable for 0000 and that of Channel 2 is adjusted to 0001 and the same beamformer circuits, such as those used in high performance signal is applied to both RF inputs, the output of Channel 2 medical ultrasound equipment featuring CW Doppler. The RF leads that of Channel 1 by 22.5°. inputs interface directly with the outputs of the dual-channel, The I and Q outputs are provided as currents to facilitate sum- low noise preamplifiers included in the AD8332. mation. The summed current outputs are converted to voltages A divide-by-4 circuit generates the internal 0° and 90° phases by a high dynamic range, current-to-voltage (I-V) converter, such of the local oscillator (LO) that drive the mixers of a pair of as the AD8021, configured as a transimpedance amplifier. The matched I/Q demodulators. resultant signal is then applied to a high resolution ADC, such as the AD7665 (16 bit/570 kSPS). The AD8333 can be applied as a major element in analog beamformer circuits in medical ultrasound equipment. The two I/Q demodulators can be used independently in other nonbeamforming applications. In that case, a transimpedance The AD8333 features an asynchronous reset pin. When used amplifier is needed for each of the I and Q outputs, four in total in arrays, the reset pin sets all the LO dividers in the same state. for the dual I/Q demodulator. Sixteen discrete phase rotations in 22.5° increments can be selected independently for each channel. For example, if Channel 1 is used The dynamic range is 159 dB/Hz at the I and Q outputs, but the as a reference and the RF signal applied to Channel 2 has an I/Q following transimpedance amplifier is an important element in phase lead of 45°, Channel 2 can be phase aligned with Channel 1 maintaining the overall dynamic range, and attention needs to by choosing the correct code. be paid to optimal component selection and design. The AD8333 is available in a 32-lead LFCSP (5 mm × 5 mm) package for the industrial temperature range of −40°C to +85°C. 1 Protected by US Patent 7,760,833. Rev. F Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Tel: 781.329.4700 ©2005–2016 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com

AD8333 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Channel Summing ..................................................................... 21 Applications ....................................................................................... 1 Dynamic Range Inflation .......................................................... 23 Functional Block Diagram .............................................................. 1 Disabling the Current Mirror and Decreasing Noise ............ 23 General Description ......................................................................... 1 Applications Information .............................................................. 25 Revision History ............................................................................... 3 Logic Inputs and Interfaces ....................................................... 25 Specifications ..................................................................................... 4 Reset Input .................................................................................. 25 Absolute Maximum Ratings ............................................................ 6 Connecting to the LNA of the ESD Caution .................................................................................. 6 AD8331/AD8332/AD8334/AD8335 VGAs ............................ 25 Pin Configuration and Function Descriptions ............................. 7 Interfacing to Other Amplifiers ............................................... 26 Equivalent Input Circuits ................................................................ 8 LO Input ...................................................................................... 26 Typical Performance Characteristics ............................................. 9 Evaluation Board ............................................................................ 27 Test Circuits ..................................................................................... 15 Features and Options ................................................................. 27 Theory of Operation ...................................................................... 18 Measurement Setup.................................................................... 28 Quadrature Generation ............................................................. 18 Evaluation Board Schematic and Artwork .................................. 29 I/Q Demodulator and Phase Shifter ........................................ 18 Board Layout ............................................................................... 31 Dynamic Range and Noise ........................................................ 19 Outline Dimensions ....................................................................... 32 Summation of Multiple Channels (Analog Beamforming) .. 20 Ordering Guide .......................................................................... 32 Phase Compensation and Analog Beamforming ................... 20 Rev. F | Page 2 of 32

Data Sheet AD8333 REVISION HISTORY 5/2016—Rev. E to Rev. F Changes to Dynamic Range and Noise Section .......................... 18 Change to Features Section and General Description Section ......... 1 Changes to Connecting to the LNA of the AD8331/AD8332/ Change to Quiescent Power Parameter, Table 1............................ 5 AD8334/AD8335 VGAs Section ................................................... 24 Changes to Figure 2 and Table 3 ..................................................... 7 Added Interfacing to Other Amplifiers Heading........................ 25 Change to Figure 52 ........................................................................ 18 Changes to Figure 61 ...................................................................... 25 Change to Figure 61 ........................................................................ 28 Incorporated AD8333-EVALZ Data Sheet .................................. 26 Change to Figure 64 ........................................................................ 29 Changes to Evaluation Board Section .......................................... 26 Updated Outline Dimensions ........................................................ 32 Changes to Features and Options Section ................................... 26 Changes to Ordering Guide ........................................................... 32 Changes to Table 5 .......................................................................... 26 Replaced the Phase Bits Section with the Phase Nibble 8/2012—Rev. D to Rev. E Section .............................................................................................. 26 Changes to Figure 1 and General Description Section ................ 1 Deleted Table 2 .................................................................................. 3 Moved Revision History Section ..................................................... 3 Changes to LNA Input Impedance Section ................................. 26 Changes to Table 3 ............................................................................ 7 Changes to Current Summing Section ......................................... 26 Changes to Table 5 .......................................................................... 27 Changes to Measurement Setup Section ...................................... 27 Updated Outline Dimensions ........................................................ 33 Moved Figure 63; Changes to Figure 63 ....................................... 27 Changes to Figure 64 ...................................................................... 28 9/2010—Rev. C to Rev. D Moved Figure 70 .............................................................................. 30 Change to I2NO, Q2NO, Q1NO, and I1NO Pin Description, Changes to Table 7 .......................................................................... 31 Table 3 ................................................................................................. 6 Deleted Figure 62; Renumbered Sequentially ............................. 26 Changes to Figure 62, Features and Options Section, Table 5, Updated Outline Dimensions........................................................ 32 Phase Nibble Section, and Enable and Reset Switches Changes to Ordering Guide ........................................................... 32 Section .............................................................................................. 26 Changes to Reset Input Section, Measurement Setup Section, 5/2007—Rev. A to Rev. B and Figure 63 ................................................................................... 27 Changes to Features and Figure 1 ................................................... 1 Changes to Figure 64 ...................................................................... 28 Changes to Table 1 ............................................................................ 3 Changes to Figure 65 ...................................................................... 29 Changes to Figure 41 to Figure 43 ................................................ 14 Changes to Figure 66 Through Figure 70 .................................... 30 Changes to Figure 44 to Figure 47 ................................................ 15 Deleted Ordering Information Section ........................................ 37 Changes to Figure 48 to Figure 51 ................................................ 16 Deleted Table 7; Renumbered Sequentially ................................. 37 Changes to Figure 55 ...................................................................... 20 Changes to Evaluation Board Section .......................................... 25 9/2008—Rev. B to Rev. C Changes to Ordering Guide ........................................................... 27 Changes to Figure 1........................................................................... 1 Changes to General Description Section ....................................... 1 5/2006—Rev. 0 to Rev. A Change to Table 2 .............................................................................. 5 Changes to Figure 62 ...................................................................... 26 Changes to Figure 4 and Figure 6 .................................................... 7 Change to Figure 18 .......................................................................... 9 10/2005—Revision 0: Initial Version Rev. F | Page 3 of 32

AD8333 Data Sheet SPECIFICATIONS V = ±5 V, T = 25°C, f = 20 MHz, f = 5.01 MHz, f = 10 kHz, P ≥ 0 dBm, single-ended, sine wave; per channel performance, dBm S A 4LO RF BB LO (50 Ω), unless otherwise noted (see Figure 41). Table 1. Parameter Test Conditions/Comments Min Typ Max Unit OPERATING CONDITIONS LO Frequency Range 4× internal LO at Pin 4LOP and Pin 4LON Square wave 0.01 200 MHz Sine wave, see Figure 22 2 200 MHz RF Frequency Range Mixing DC 50 MHz Baseband Bandwidth Limited by external filtering DC 50 MHz LO Input Level See Figure 22 0 13 dBm V (V) ±4.5 ±5 ±6 V SUPPLY S Temperature Range −40 +85 °C DEMODULATOR PERFORMANCE RF Differential Input Impedance 6.7||6.5 kΩ||pF LO Differential Input Capacitance 0.6 pF Transconductance Demodulated I /V , each I or Q output after low-pass 2.17 mS OUT IN filtering measured from RF inputs, all phases Dynamic Range IP1dB, input-referred noise (dBm) 159 dB/Hz Maximum RF Input Swing Differential; inputs biased at 2.5 V; Pin RFxP and Pin RFxN 2.8 V p-p Peak Output Current (No Filtering) 0° phase shift ±4.7 mA 45° phase shift ±6.6 mA Input P1dB Reference = 50 Ω 14.5 dBm Reference = 1 V rms 1.5 dBV Third-Order Intermodulation (IM3) f = 5.010 MHz, f = 5.015 MHz, f = 5.023 MHz RF1 RF2 LO Equal Input Levels Baseband tones: −7 dBm at 8 kHz and 13 kHz −75 dBc Unequal Input Levels Baseband tones: −1 dBm at 8 kHz and −31 dBm at 13 kHz −77 dBc Third-Order Input Intercept (IP3) f = 5.010 MHz, f = 5.015 MHz, f = 5.023 MHz 30 dBm RF1 RF2 LO LO Leakage Measured at RF inputs, worst phase, measured into 50 Ω <−97 dBm (limited by measurement) Measured at baseband outputs, worst phase, AD8021 disabled, −60 dBm measured into 50 Ω Conversion Gain All codes 4.7 dB Input-Referred Noise Output noise/conversion gain 10 nV/√Hz Output Current Noise Output noise ÷ 787 Ω 22 pA/√Hz Noise Figure With AD8332 LNA R = 50 Ω, R = ∞ 7.8 dB S FB R = 50 Ω, R = 1.1 kΩ 9.0 dB S FB R = 50 Ω, R = 274 Ω 11.0 dB S FB Bias Current Pin 4LOP and Pin 4LON −3 µA Pin RFxP and Pin RFxN −70 µA LO Common-Mode Voltage Range Pin 4LOP and Pin 4LON (each pin) 0.2 3.8 V RF Common-Mode Voltage For maximum differential swing; Pin RFxP and Pin RFxN 2.5 V (dc-coupled to AD8332 LNA output) Output Compliance Range Pin IxPO and Pin QxPO −1.5 +0.7 V PHASE ROTATION PERFORMANCE One channel is reference; the other channel is stepped Phase Increment 16 phase steps per channel 22.5 Degrees Quadrature Phase Error I1xO to Q1xO and I2xO to Q2xO, 1σ −2 ±0.1 +2 Degrees I/Q Amplitude Imbalance I1xO to Q1xO and I2xO to Q2xO, 1σ ±0.05 dB Channel-to-Channel Matching Phase match I1xO/I2xO and Q1xO/Q2xO; −40°C < T < 85°C ±1 Degrees A Amplitude match I1xO/I2xO and Q1xO/Q2xO; −40°C < T < 85°C ±0.25 dB A Rev. F | Page 4 of 32

Data Sheet AD8333 Parameter Test Conditions/Comments Min Typ Max Unit LOGIC INTERFACES Logic Level High Pin PHxx, Pin RSET, and Pin ENBL 1.7 5 V Logic Level Low Pin PHxx, Pin RSET, and Pin ENBL 0 1.3 V Bias Current Pin PHxx and Pin ENBL Logic high 10 40 90 µA Logic low −30 −7 +10 µA Pin RSET Logic high 50 120 180 µA Logic low −70 −20 0 µA Input Resistance Pin PHxx and Pin ENBL 60 kΩ Pin RSET 20 kΩ Reset Hold Time Reset is asynchronous; clock disabled when RSET goes high 300 ns until 300 ns after RSET goes low; see Figure 58 Minimum Reset Pulse Width 300 ns Reset Response Time See Figure 35 300 ns Phase Shifting Response Time See Figure 38 5 µs Enable Response Time See Figure 34 300 ns POWER SUPPLY Pin VPOS and Pin VNEG Supply Voltage ±4.5 ±5 ±6 V Quiescent Current, All Phase Bits = 0 At 25°C Pin VPOS 38 44 51 mA Pin VNEG −24 −20 −16 mA Over Temperature −40°C < T < 85°C A Pin VPOS, all phase bits = 0 40 54 mA Pin VNEG −24 −19 mA Quiescent Power Per channel, all phase bits = 0 160 mW Per channel, any 0 or 1 combination of phase bits 190 mW Disable Current All channels disabled Pin VPOS 1.0 1.25 1.5 mA Pin VNEG −300 −200 −100 µA PSRR Pin VPOS to I/Q outputs (measured at AD8021 output) −81 dB Pin VNEG to I/Q outputs (measured at AD8021 output) −75 dB Rev. F | Page 5 of 32

AD8333 Data Sheet ABSOLUTE MAXIMUM RATINGS Stresses at or above those listed under Absolute Maximum Table 2. Ratings may cause permanent damage to the product. This is a Parameter Rating stress rating only; functional operation of the product at these Voltages or any other conditions above those indicated in the operational Supply Voltage, V 6 V S section of this specification is not implied. Operation beyond RF Pins Input V, GND S the maximum operating conditions for extended periods may LO Inputs V, GND S affect product reliability. Code Select Inputs Voltage V, GND S Thermal Data1 ESD CAUTION θ 41.0°C/W JA θ 23.6°C/W JB θ 4.4°C/W JC Ψ 0.4°C/W JT Ψ 22.4°C/W JB Maximum Junction Temperature 150°C Maximum Power Dissipation 1.5 W (Exposed Pad Soldered to PC Board) Operating Temperature Range −40°C to +85°C Storage Temperature Range −65°C to +150°C Lead Temperature (Soldering, 60 sec) 300°C 1 4-layer JEDEC board no airflow (exposed pad soldered to PCB). Rev. F | Page 6 of 32

Data Sheet AD8333 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 11HP01HPSOPVP1FRN1FRSOPVLBNEON1I 21098765 33322222 PH12 1 24 I1PO PH13 2 23 Q1PO COMM 3 22 Q1NO AD8333 4LOP 4 21 VNEG TOP VIEW 4LON 5 20 COMM (Not to Scale) LODC 6 19 Q2NO PH23 7 18 Q2PO PH22 8 17 I2PO 910111213141516 10SPNSTO 2HP2HPOPV2FR2FROPVESRN2I NOTES 1. THE EXPOSED PAD IS NOT CONNECTED INTERNALLY. FJRTOOOEIC RNTO THINMSEC M AGRENRENDOAD SUMEENADDDX T IRPMHELAULATMINA TETBH.HILEEI TRPYAM DAODLFL CTEAH BPEEA S BSOIOLLLIDTDEYER, RITE DIS 05543-002 Figure 2. 32-Lead LFCSP Pin Configuration Table 3. Pin Function Descriptions Pin No. Mnemonic Description 1, 2, PH12, PH13, Quadrant Select LSB, MSB. Binary code. These logic inputs select the quadrant: 0° to 90°, 90° to 180°, 180° to 270°, 7, 8 PH23, PH22 270° to 360° (see Table 4). Logic threshold is at about 1.5 V and therefore can be driven by 3 V CMOS logic (see Figure 3). 3, 20 COMM Ground. These two pins are internally tied together. 4, 5 4LOP, 4LON LO Inputs. No internal bias; therefore, these pins need to be biased by external circuitry. For optimum performance, these inputs must be driven differentially with a signal level that is not less than what is shown in Figure 22. Bias current is only −3 µA. Single-ended drive is also possible if the inputs are biased correctly (see Figure 4). 6 LODC Decoupling Pin for LO. A 0.1 µF capacitor must be connected between this pin and ground (see Figure 5). 9, 10, PH21, PH20, Phase Select LSB, MSB. Binary code. These logic inputs select the phase for a given quadrant: 0°, 22.5°, 45°, 67.5° 31, 32 PH10, PH11 (see Table 4). Logic threshold is at about 1.5 V and therefore can be driven by 3 V CMOS logic (see Figure 3). 11, 14, VPOS Positive Supply. These pins must be decoupled with a ferrite bead in series with the supply, plus a 0.1 µF and 27, 30 100 pF capacitor between the VPOS pins and ground. Because the VPOS pins are internally connected, one set of supply decoupling components for all four pins must be sufficient. 12, 13, RF2P, RF2N, RF Inputs. These pins are biased internally; however, it is recommended that they be biased by dc coupling to 28, 29 RF1N, RF1P the output pins of the AD8332 LNA. The optimum common-mode voltage for maximum symmetrical input differential swing is 2.5 V if ±5 V supplies are used (see Figure 6 and Figure 60). 15 RSET Reset for Divide-by-4 in LO Interface. Logic threshold is at about 1.5 V and therefore can be driven by 3 V CMOS logic (see Figure 3). Reset when high, enable when low. 16, 19, I2NO, Q2NO, Negative I/Q Outputs. Not connected for typical applications. 22, 25 Q1NO, I1NO 17, 18, I2PO, Q2PO, Positive I/Q Outputs. These outputs provide a bidirectional current that can be converted back to a voltage via 23, 24 Q1PO, I1PO a transimpedance amplifier. Multiple outputs can be summed together by connecting them together. The bias voltage must be set to 0 V or less by the transimpedance amplifier (see Figure 7). 21 VNEG Negative Supply. This pin must be decoupled with a ferrite bead in series with the supply, plus a 0.1 µF and 100 pF capacitor between the pin and ground. 26 ENBL Chip Enable. Logic threshold is at about 1.5 V and therefore can be driven by 3 V CMOS logic (see Figure 3). EPAD Exposed Pad. The exposed pad is not connected internally. For increased reliability of the solder joints and maximum thermal capability, it is recommended that the paddle be soldered to the ground plane. Rev. F | Page 7 of 32

AD8333 Data Sheet EQUIVALENT INPUT CIRCUITS VPOS VPOS RFxP PHxx LOGIC ERNSBELT INTERFACE RFxN COMM 05543-003 COMM 05543-006 Figure 3. Logic Inputs Figure 6. RF Inputs COMM VPOS IxNO QxNO 4LOP IxPO QxPO 4LON COMM 05543-004 VNEG 05543-007 Figure 4. Local Oscillator Inputs Figure 7. Output Drivers VPOS LODC COMM 05543-005 Figure 5. Local Oscillator Decoupling Pin Rev. F | Page 8 of 32

AD8333 Data Sheet TYPICAL PERFORMANCE CHARACTERISTICS V = ±5 V, T = 25°C, f = 20 MHz, f = 5 MHz, f = 5.01 MHz, f = 10 kHz, P ≥ 0 dBm (50 Ω); single-ended sine wave; S A 4LO LO RF BB LO per channel performance, differential voltages, dBm (50 Ω), phase select code = 0000, unless otherwise noted (see Figure 41). 1.5 f = 1MHz 2 CODE 0100 f = 5MHz QI CODE 0011 1 zed) 1.0 CODE 0010 0 ali CODE 0001 s) m e SE (Nor 0.5 CODE 1000 CODE 0000 R (Degre ––12 A 0 O Y PH ERR 2 GINAR –0.5 HASE 1 f = 1MHz A P IM –1.0 0 –1.5 CODE1100 05543-008 ––21 05543-011 –2.0 –1.5 –1.0 –0.5 0 0.5 1.0 1.5 2.0 0000 0010 0100 0110 1000 1010 1100 1110 1111 REAL PHASE (Normalized) CODE (Binary) Figure 8. Normalized Vector Plot of Phase, Channel 2 with Respect to Figure 11. Phase Error of Channel 2 with Respect to Channel 1 vs. Channel 1; Channel 1 Is Fixed at 0°, Channel 2 Stepped 22.5°/Step, Code at 1 MHz and 5 MHz All Codes Displayed 360 500mV 1MHz 315 5MHz 270 s) e 225 e gr e E (D 180 S A H 135 P 90 450 05543-009 20µs 05543-012 0000 0010 0100 0110 1000 1010 1100 1110 1111 CODE (Binary) Figure 9. Phase of Channel 2 with Respect to Channel 1 vs. Code Figure 12. I or Q Output of Channel 2 with Respect to Channel 1, at 1 MHz and 5 MHz First Quadrant Shown 1.0 7 f = 5MHz CHANNEL 1, I OUTPUT SHOWN 0.5 0 B) 6 R (d –0.5 CCOODDEE 00000001 E ERRO –1.0 N (dB) 5 CCOODDEE 00001101 UD 1.0 GAI LIT f = 1MHz P 0.5 M A 4 0 ––01..50 05543-010 3 05543-013 0000 0010 0100 0110 1000 1010 1100 1110 1111 1M 10M 50M CODE (Binary) RF FREQUENCY (Hz) Figure 10. Amplitude Error of Channel 2 with Respect to Channel 1 vs. Code Figure 13. Conversion Gain vs. RF Frequency, First Quadrant, at 1 MHz and 5 MHz Baseband Frequency = 10 kHz Rev. F | Page 9 of 32

AD8333 Data Sheet 2.0 0.5 es) 1.5 0.4 R (Degre 1.0 CE (dB) 00..32 O N HASE ERR 0.50 DE IMBALA 0.10 E P –0.5 TU –0.1 R LI TU MP –0.2 DRA –1.0 Q A –0.3 A I/ QU ––12..50 05543-014 ––00..45 05543-017 1M 10M 100M 100 1k 10k 100k RF FREQUENCY (Hz) BASEBAND FREQUENCY (Hz) Figure 14. Representative Range of Quadrature Phase Errors vs. Figure 17. Representative Range of I/Q Amplitude Imbalance vs. RF Frequency, Channel 1 or Channel 2, All Codes Baseband Frequency, Channel 1 and Channel 2 (see Figure 43) 2.0 2.0 CODE 0000 fBB = 10kHz es) 1.5 1.5 –+4205°°CC I2/I1 DISPLAYED gre +85°C R (De 1.0 dB) 1.0 C–4O0D°CE 0001 ERRO 0.5 ATCH ( 0.5 ++2855°°CC E M RATURE PHAS ––01..050 AMPLITUDE ––01..500 C–++428O055D°°°CCCE 0010 D CODE 0011 A –40°C QU ––12..50 05543-015 ––12..50 ++2855°°CC 05543-018 100 1k 10k 100k 1M 10M 50M BASEBAND FREQUENCY (Hz) RF FREQUENCY (Hz) Figure 15. Representative Range of Quadrature Phase Error vs. Baseband Figure 18. Typical I2xO/I1xO or Q2xO/Q1xO Amplitude Match vs. RF Frequency, Frequency, Channel 1 and Channel 2 (see Figure 43) First Quadrant, at Three Temperatures 0.5 8 CODE0000 CODE0010 0.4 –40°C –40°C +25°C +25°C B) 0.3 6 +85°C +85°C d E ( s) CODE0001 CODE0011 ANC 0.2 gree 4 –+4205°°CC –+4205°°CC AL 0.1 De +85°C +85°C E IMB 0 ROR ( 2 D R TU –0.1 E E MPLI –0.2 HAS 0 A P Q –0.3 I/ –2 ––00..45 05543-016 –4 fI2B/BI1=D1I0SkPHLzAYED 05543-043 1M 10M 50M 1M 10M 50M RF FREQUENCY (Hz) RFFREQUENCY(Hz) Figure 16. Representative Range of I/Q Amplitude Imbalance vs. Figure 19. I2xO/I1xO or Q2xO/Q1xO Phase Error vs. RF Frequency, RF Frequency, Channel 1 or Channel 2, All Codes Baseband Frequency = 10 kHz, at Three Temperatures Rev. F | Page 10 of 32

Data Sheet AD8333 2.8 10 CHANNEL 1, I OUTPUT SHOWN GAIN=VBB/VRF 2.7 TRANSCONDUCTANCE = [(VBB/787Ω)VRF] 5 mS) 2.6 0 ++8255°°CC UCTANCE ( 22..54 CCCCOOOODDDDEEEE 0000000000111010 N (dB) –1–05 –40°C OND GAI C 2.3 –15 S N A R 2.2 –20 T 22..10 05543-020 ––2350 05543-019 1M 10M 50M 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 RF FREQUENCY (Hz) COMMON-MODEVOLTAGE(V) Figure 20. Transconductance vs. RF Frequency, First Quadrant Figure 23. LO Common-Mode Range at Three Temperatures 10 20 0 18 f = 5MHz –10 GAIN = VBB/VRF 16 14 –20 GAIN (dB) ––3400 CCCOOODDDEEE 000000001010 P1dB (dBm) 11208 CODE 0011 I –50 6 –60 4 ––7800 05543-021 20 05543-023 –20 –15 –10 –5 0 1M 10M 50M POWER (dBm) RF FREQUENCY (Hz) Figure 21. Conversion Gain vs. LO Level, First Quadrant Figure 24. IP1dB vs. RF Frequency, Baseband Frequency = 10 kHz, First Quadrant (see Figure 42) 5 0 ALL CODES BOTH CHANNELS 0 –10 –7dBm m) –5 REGION OF USEABLE –20 B LO LEVELS EL (d –10 –30 I3M3 P8ROD13UCT1S8 M LO LEV ––1250 IM3 (dBc) ––4500 RRLFFO12 === 555...000211350MMMHHHzzz U NIM –25 –60 MI –30 –70 ––3450 05543-022 ––8900 05543-024 100k 1M 10M 100M 1M 10M 50M RF FREQUENCY (Hz) RF FREQUENCY (Hz) Figure 22. Minimum LO Level vs. RF Frequency, Single-Ended, Figure 25. Representative Range of IM3 vs. RF Frequency, Sine Wave LO Drive to Pin 4LOP or Pin 4LON First Quadrant (see Figure 49) Rev. F | Page 11 of 32

AD8333 Data Sheet 40 0 BOTH CHANNELS LOLEVEL=0dBm 35 –20 30 –40 m) B OIP3 (dBm) 221505 O LEAKAGE (d ––6800 RRRRFFFF1212NNPP L –100 10 –120 50 05543-025 –140 05543-028 1M 10M 50M 1M 10M 50M RF FREQUENCY (Hz) RFFREQUENCY(Hz) Figure 26. Representative Range of OIP3 vs. RF Frequency, Figure 29. LO Leakage vs. RF Frequency at RF Inputs First Quadrant (see Figure 49) 35 16 –142.9 30 14 –144.1 I1 Q1 12 –145.4 25 CHANNEL 1 RF OIP3 (dBm) 2105 CHANNEL 2 RF NOISE (nV/Hz)1086 –––111445781...094 NOISE (dBm) 10 4 –154.9 5 01k BASEBAND F1R0EkQUENCY (Hz) 100k05543-026 201M RF FREQUENC1Y0M (Hz) 50M–161.0 05543-029 Figure 27. OIP3 vs. Baseband Frequency (see Figure 48) Figure 30. Input-Referred Noise vs. RF Frequency 0 20 LO LEVEL = 0dBm –10 18 16 –20 m) B) 14 E (dB –30 II12 RE (d 12 AG –40 Q1 GU 10 O LEAK –50 Q2 OISE FI 8 L N 6 –60 4 ––7800 05543-027 20 05543-064 1M 10M 50M 1M 10M 50M RF FREQUENCY (Hz) RF FREQUENCY (Hz) Figure 28. LO Leakage vs. RF Frequency at Baseband Outputs Figure 31. Noise Figure vs. RF Frequency with AD8332 LNA Rev. F | Page 12 of 32

Data Sheet AD8333 172 I1 Q1 2V 170 I1 + I2 Q1 + Q2 168 B) 166 d GE ( 164 N A R 162 C AMI 160 N Y D 158 156 115542 05543-030 500mV 200ns 05543-046 1M 10M 50M RF FREQUENCY (Hz) Figure 32. Dynamic Range vs. RF Frequency, IP1dB Minus Noise Level, Figure 35. Reset Response—Top: Signal at RSET Pin, Single Channel and Two Channels Summed Bottom: Output Signal (see Figure 45) 6 5V 4 GAIN = VBB/VRF 2 CODE 0000 B) 0 CODE 0010 d N ( –2 AI G –4 –6 ––180 05543-044 1V 1V 40µs 05543-047 –3.0 –2.5 –2.0 –1.5 –1.0 –0.5 0 0.5 1.0 VOLTAGE (V) Figure 33. Output Compliance Range (IxPO, QxPO) (see Figure 50) Figure 36. Phase Switching Response—Channel 2 Leads Channel 1 by 45°, Top: Input to PH21, Select Code = 0010; Bottom (Red): Reference Channel 1 IOUT; Bottom (Gray): Channel 2 IOUT Phase Shifted 45°, Channel 1 Reference Phase Select Code = 0000 500mV 5V 2V 200ns 05543-045 1V 1V 40µs 05543-048 Figure 34. Enable Response—Top: Enable Signal, Figure 37. Phase Shifting Response—Channel 2 Leads Channel 1 by 90°, Bottom: Output Signal (see Figure 44) Top: Input to PH21, Select Code = 0100; Bottom (Red): Reference Channel 1 IOUT; Bottom (Gray): Channel 2 IOUT Phase Shifted 90°, Channel 1 Reference Phase Code = 0000 Rev. F | Page 13 of 32

AD8333 Data Sheet 60 5V mA) 50 VPOS T ( N E R 40 R U C Y PL 30 P U S T EN 20 VNEG C S E 1V 1V 40µs 05543-049 QUI 100 05543-051 –50 –30 –10 10 30 50 70 90 TEMPERATURE (°C) Figure 38. Phase Shifting Response—Channel 2 Leads Channel 1 by 180°, Figure 40. Quiescent Supply Current vs. Temperature Top: Input to PH23 Select Code = 1000; Bottom (Red): Reference Channel 1 IOUT; Bottom (Gray): Channel 2 IOUT Phase Shifted 180°, Channel 1 Reference Phase Code = 0000 0 –10 –20 –30 B) d –40 R ( R S –50 P –60 VNEG VPOS –70 ––8900 05543-050 100k 1M 10M 50M FREQUENCY (Hz) Figure 39. PSRR vs. Frequency (see Figure 51) Rev. F | Page 14 of 32

Data Sheet AD8333 TEST CIRCUITS AD8021 AD8332 787Ω 120nH LNA FB 0.1µF 20Ω 2.2nF RFxP IxxO LPF AD8333 OSCILLOSCOPE 2.2nF 50Ω RFxN QxxO 0.1µF 20Ω 4LOP SIGNAL 787Ω GENERATOR 50Ω SIGNAL AD8021 GENERATOR 05543-032 Figure 41. Default Test Circuit AD8021 AD8332 100Ω 120nH LNA FB 0.1µF 20Ω 10nF RFxP IxxO LPF AD8333 OSCILLOSCOPE 10nF 50Ω RFxN QxxO 0.1µF 20Ω 4LOP SIGNAL 100Ω GENERATOR 50Ω SIGNAL AD8021 GENERATOR 05543-033 Figure 42. P1dB Test Circuit AD8021 AD8332 120nH LNA FB 1µF 20Ω RFxP 787Ω IxxO LPF AD8333 OSCILLOSCOPE 787Ω 50Ω RFxN QxxO 1µF 20Ω 4LOP SIGNAL GENERATOR 50Ω AD8021 SIGNAL GENERATOR 05543-034 Figure 43. Phase and Amplitude vs. Baseband Frequency AD8021 AD8332 120nH LNA FB 1µF 20Ω RFxP 787Ω IxxO LPF AD8333 OSCILLOSCOPE 787Ω 50Ω RFxN QxxO 1µF 20Ω ENBL 4LOP SIGNAL GENERATOR 50Ω 50Ω AD8021 GENESRIGATNOARL SGIEGNNEARLATOR 05543-035 Figure 44. Enable Response Rev. F | Page 15 of 32

AD8333 Data Sheet AD8021 AD8332 120nH LNA FB 1µF 20Ω RFxP 787Ω IxxO LPF AD8333 OSCILLOSCOPE 787Ω 50Ω RFxN QxxO 1µF 20Ω RST 4LOP SIGNAL GENERATOR 50Ω 50Ω AD8021 GENESRIGATNOARL SGIEGNNEARLATOR 05543-036 Figure 45. Reset Response AD8332 120nH LNA FB 0.1µF 20Ω RFxP IxxO LPF OSCILLOSCOPE AD8333 50Ω RFxN QxxO 0.1µF 20Ω SIGNAL 4LOP 50Ω 50Ω GENERATOR 50Ω SIGNAL GENERATOR 05543-037 Figure 46. RF Input Range AD8021 6.98kΩ 270pF RFxP IxxO SPECTRUM 0.1µF AD8333 270pF ANALYZER RFxN QxxO 4LOP 6.98kΩ 50Ω GENESRIGATNOARL AD8021 05543-052 Figure 47. Noise Test Circuit AD8021 COMBINER AD8332 787Ω –6dB 120nH LNA 50Ω FB 0.1µF 20Ω 100pF RFxP IxxO SPECTRUM GENESRIGATNOARL AD8333 100pF ANALYZER RFxN QxxO 50Ω 0.1µF 20Ω 4LOP SIGNAL 787Ω GENERATOR 50Ω GENESRIGATNOARL AD8021 05543-053 Figure 48. OIP3 vs. Baseband Frequency Rev. F | Page 16 of 32

Data Sheet AD8333 AD8021 COMBINER AD8332 787Ω –6dB 120nH LNA 50Ω FB 0.1µF 20Ω 2.2nF RFxP IxxO SPECTRUM GENESRIGATNOARL AD8333 2.2nF ANALYZER RFxN QxxO 50Ω 0.1µF 20Ω 4LOP SIGNAL 787Ω GENERATOR 50Ω GENESRIGATNOARL AD8021 05543-054 Figure 49. OIP3 and IM3 vs. RF Frequency AD8021 AD8332 787Ω 120nH LNA FB 0.1µF 20Ω 2.2nF RFxP IxxO LPF AD8333 OSCILLOSCOPE 2.2nF 50Ω 0.1µF 20Ω RFxN QxxO 4LOP SIGNAL 787Ω GENERATOR 50Ω SIGNAL AD8021 GENERATOR 05543-055 Figure 50. Output Compliance Range AD8332 120nH LNA FB 0.1µF 20Ω RFxP IxxO NETWORK LPF AD8333 ANALYZER 50Ω RFxN QxxO 0.1µF 20Ω 4LOP SIGNAL GENERATOR 50Ω SIGNAL GENERATOR 05543-056 Figure 51. PSRR Test Circuit Rev. F | Page 17 of 32

AD8333 Data Sheet THEORY OF OPERATION The AD8333 is a dual I/Q demodulator with a programmable For optimum performance, the 4LOx inputs are driven differ- phase shifter for each channel. The primary applications are entially but can also be driven in a single-ended fashion. A good phased array beamforming in medical ultrasound, phased array choice for a drive is an LVDS device. The common-mode range radar, and smart antennae for mobile communications. The on each pin is approximately 0.2 V to 3.8 V with nominal ±5 V AD8333 can also be used in applications that require two well- supplies. matched I/Q demodulators. The minimum LO level is frequency dependent (see Figure 22). Figure 52 shows the block diagram and pinout of the AD8333. For optimum noise performance, it is important to ensure that Three analog and nine quasilogic level inputs are required. Two the LO source has very low phase noise (jitter) and adequate input RF inputs accept signals from the RF sources and a local oscillator level to ensure stable mixer-core switching. The gain through the (applied to the differential input pins marked 4LOx) common divider determines the LO signal level vs. RF frequency. The to both channels constitute the analog inputs. Four logic inputs AD8333 can be operated to very low frequencies at the LO inputs per channel define one of 16 delay states/360° (or 22.5°/step), if a square wave is used to drive the LO. selectable with PHx0 to PHx3. The reset input is used to Beamforming applications require a precise channel-to-channel synchronize AD8333 devices used in arrays. phase relationship for coherence among multiple channels. A PH11 PH10 VPOS RF1P RF1N VPOS ENBL I1NO rceirsceut iptsin w (hReSnE AT)D i8s 3p3r3o vdiedveidce tso a srye nucsherdo inni zaer rtahyes 4. LTOhex RdSivEiTde pri n 32 31 30 29 28 27 26 25 resets the counters to a known state after power is applied to BIAS PH12 1 24 I1PO multiple AD8333 devices. A logic input must be provided to the CHANNEL 1 Φ SEL RSET pin when using more than one AD8333. See the Reset LOGIC 0° PH13 2 23 Q1PO Φ Input section for more details. AD8333 COMM 3 22 Q1NO I/Q DEMODULATOR AND PHASE SHIFTER 90° Φ 4LOP 4 21 VNEG The I/Q demodulators consist of double-balanced Gilbert cell BUF ÷4 90° mixers. The RF input signals are converted into currents by 4LON 5 20 COMM Φ transconductance stages that have a maximum differential input signal capability of 2.8 V p-p. These currents are then presented LODC 6 19 Q2NO 0° to the mixers, which convert them to baseband: RF − LO and Φ PH23 7 CHANNEL 2 18 Q2PO RF + LO. The signals are phase shifted according to the code Φ SEL LOGIC applied to Pin PHx0 to Pin PHx3 (see Table 4). The phase shift PH22 8 17 I2PO function is an integral part of the overall circuit (patent pending). 9 10 11 12 13 14 15 16 The phase shift listed in Column 1 of Table 4 is defined as being PH21 PH20 VPOS RF2P RF2N VPOS RSET I2NO 05543-057 between the baseband I or Q channel outputs. As an example, for a common signal applied to the RF inputs of an AD8333, the Figure 52. Block Diagram and Pinout baseband outputs are in phase for matching phase codes. However, Each of the current formatted I and Q outputs sum together for if the phase code for Channel 1 is 0000 and that of Channel 2 is beamforming applications. Multiple channels are summed and 0001, Channel 2 leads Channel 1 by 22.5°. converted to a voltage using a transimpedance amplifier. If desired, Following the phase shift circuitry, the differential current signal is channels can also be used individually. converted from differential to single ended via a current mirror. QUADRATURE GENERATION An external transimpedance amplifier is needed to convert the I The internal 0° and 90° LO phases are digitally generated by a and Q outputs to voltages. divide-by-4 logic circuit. The divider is dc-coupled and inherently broadband; the maximum LO frequency is limited only by its switching speed. The duty cycle of the quadrature LO signals is intrinsically 50% and is unaffected by the asymmetry of the externally connected 4LOx inputs. Furthermore, the divider is implemented such that the 4LOx signals reclock the final flip- flops that generate the internal LO signals and thereby minimizes noise introduced by the divide circuitry. Rev. F | Page 18 of 32

Data Sheet AD8333 Judicious selection of the RF amplifier ensures the least Table 4. Phase Nibble Select Codes degradation in dynamic range. The input-referred spectral voltage φ Shift PHx3 PHx2 PHx1 PHx0 noise density (e ) of the AD8333 is nominally 9 nV/√Hz to 0° 0 0 0 0 n 10 nV/√Hz. For the noise of the AD8333 to degrade the system 22.5° 0 0 0 1 noise figure (NF) by 1 dB, the combined noise of the source and 45° 0 0 1 0 the LNA must be about twice that of the AD8333, or 18 nV/√Hz. If 67.5° 0 0 1 1 90° 0 1 0 0 the noise of the circuitry before the AD8333 is <18 nV/√Hz, the 112.5° 0 1 0 1 system NF degrades more than 1 dB. For example, if the noise 135° 0 1 1 0 contribution of the LNA and source is equal to the AD8333, or 157.5° 0 1 1 1 9 nV/√Hz, the degradation is 3 dB. If the circuit noise preceding 180° 1 0 0 0 the AD8333 is 1.3× as large as that of the AD8333 (or about 202.5° 1 0 0 1 11.7 nV/√Hz), the degradation is 2 dB. For a circuit noise of 1.45× 225° 1 0 1 0 that of the AD8333 (13.1 nV/√Hz), the degradation is 1.5 dB. 247.5° 1 0 1 1 To determine the input-referred noise, it is important to know 270° 1 1 0 0 the active low-pass filter (LPF) values R and C , shown in FILT FILT 292.5° 1 1 0 1 Figure 53. Typical filter values (for example, those used on the 315° 1 1 1 0 evaluation board) are 787 Ω and 2.2 nF and implement a 90 kHz 337.5° 1 1 1 1 single-pole LPF. If the RF and LO are offset by 10 kHz, the demod- ulated signal is 10 kHz and is passed by the LPF. The single-channel DYNAMIC RANGE AND NOISE mixing gain from the RF input to the AD8021 output (for example, Figure 53 is an interconnection block diagram of the AD8333. For ΣI, ΣQ) is approximately 1.7 × 4.7 dB. This together with the optimum system noise performance, the RF input signal is pro- 9 nV/√Hz AD8333 noise results in about 15.3 nV/√Hz at the vided by a very low noise amplifier, such as the LNA of an AD8332 AD8021 output. Because the AD8021, including the 787 Ω or the preamplifier of an AD8335. In beamformer applications, feedback resistor, contributes another 4.4 nV/√Hz, the total the I and Q outputs of a number of receiver channels are summed output-referred noise is about 16 nV/√Hz. This value can be (for example, the two channels illustrated in Figure 53). The adjusted by increasing the filter resistor while maintaining the dynamic range of the system increases by the factor 10 log10(N), corner frequency, thereby increasing the gain. The factor limiting where N is the number of channels (assuming random the magnitude of the gain is the output swing and drive capability uncorrelated noise). The noise in the two-channel example of of the operational amplifier selected for the I-to-V converter, in Figure 53 is increased by 3 dB while the signal doubles (6 dB), this instance the AD8021. yielding an aggregate SNR improvement of (6 dB − 3 dB) = 3 dB. RFB TRANSMITTER T/R SW AD8332 LNA OR AD8335 PREAMP TRANSDUCER CH1 CHPAHNANSEEL 1 RF SELECT AD8333 0° 2 2 4 2 I1 CFILT Φ * RFILT ΣI ADC 16-BIT I DATA 90° 2 2 Q1 AD8021 570kSPS Φ GECNLEORCAKTOR ÷4 90° 2 2 Q2 CFILT ADA7D676658 6OR Φ 0° 2 Φ 2 I2 * RAFDIL8T021 ΣQ A5D7C0 k1S6P-BSIT Q DATA 2 4 CH2 CHANNEL 2 RF PHASE *UPTO EIGHT CHANNELS TRANSMITTER AD8332 LNA OR SELECT PERAD8021 T/R AD8335 PREAMP SW TRANSDUCER RFB 05543-038 Figure 53. Interconnection Block Diagram Rev. F | Page 19 of 32

AD8333 Data Sheet SUMMATION OF MULTIPLE CHANNELS Alternatively, the RF signal can be processed by downconversion (ANALOG BEAMFORMING) on each channel individually, phase shifting the downconverted signal and then combining all channels. The AD8333 provides Beamforming, as applied to medical ultrasound, is defined as the means to implement this architecture. The downconversion the phase alignment and summation of signals generated from a is done by an I/Q demodulator on each channel, and the summed common source but received at different times by a multielement current output is the same as in the delay line approach. The ultrasound transducer. Beamforming has two functions: it imparts subsequent filters after the I-to-V conversion and the ADCs directivity to the transducer, enhancing its gain, and it defines are similar. a focal point within the body from which the location of the returning echo is derived. The primary application for the The AD8333 integrates the phase shifter, frequency conversion, AD8333 is in analog beamforming circuits for ultrasound. and I/Q demodulation into a single package and directly yields the baseband signal. To illustrate this, Figure 54 is a simplified PHASE COMPENSATION AND ANALOG diagram showing two channels. The ultrasound wave (USW) BEAMFORMING is received by two transducer elements, TE1 and TE2, in an Modern ultrasound machines used for medical applications ultrasound probe and generates the E1 and E2 signals. In this employ a 2n binary array of receivers for beamforming, with example, the phase at TE1 leads the phase at TE2 by 45°. typical array sizes of 16 or 32 receiver channels phase-shifted TRANSDUCER ELEMENTSTE1 and summed together to extract coherent information. When ANDTE2 AD8333 ucwashneed rb eie nN s mu ismu tlmhtiepe ndleu stm,o t byheieer ldodef asci hrlaeardng neseirgl ssn)i,ga wlnsa hflir l(oeim nthc eere anacoshie sdoef ib sty hi nea c cfrahecaatsnoenrd e N ls, LUAESTAWDT4AES5T°2UTBSEYW1COENLVSEEIGCR4TNT5RA°UILCSSAWLEETSSO12LBEYA4D5S°A1LD9Nd8AB332 (PSNCHEOLHATEPS1TAHIERDNAEB)GSFISTE ASR1PEAHNNAODSWES 2IN SOSUU1MT+MPSUE2TD E1 S1 by the square root of the number of channels. This technique cernihtiacnacl eesle tmhee nsitgsn inal -at ob-enaomisfoe rpmerefro drmesaignnc ea roef tthhee mmeaacnhsin teo. aTlihgen E2 1L9NdAB LPECHAHADS24E5° S2 05543-063 the incoming signals in the time domain and the means to sum Figure 54. Simplified Example of the AD8333 Phase Shifter the individual signals into a composite whole. In a real application, the phase difference depends on the element In traditional analog beamformers incorporating Doppler, a spacing, λ (wavelength), speed of sound, angle of incidence, and V-to-I converter per channel and a crosspoint switch precede other factors. The ES1 and ES2 signals are amplified 19 dB by passive delay lines used as a combined phase shifter and summing the low noise amplifiers in the AD8332. For optimum signal-to- circuit. The system operates at the receive frequency (RF) through noise performance, the output of the LNA is applied directly to the delay line, and then the signal is down-converted by a very the input of the AD8333. To sum the ES1 and ES2 signals, ES2 large dynamic range I/Q demodulator. is shifted 45° relative to ES1 by setting the phase code in Channel 2 to 0010. The phase-aligned current signals at the output of the The resultant I and Q signals are filtered and sampled by two AD8333 are summed in an I-to-V converter to provide the high resolution ADCs. The sampled signals are processed to combined output signal with a theoretical improvement in extract the relevant Doppler information. dynamic range of 3 dB for the sum of two channels. Rev. F | Page 20 of 32

Data Sheet AD8333 CHANNEL SUMMING When determining the large signal requirements of the first- order summing amplifiers and low-pass filters, the very small CW In a beamformer using the AD8333, the bipolar currents at signal can be ignored. The number of channels that can be the I and Q outputs are summed directly. Figure 55 illustrates summed is limited by the output drive current capacity of the 16 summed channels (for clarity, these channels are shown as operational amplifier selected: 60 mA to 70 mA for a linear current sources) as an example of an active current summing output current for ±5 V and ±12 V, respectively, for the AD8021. circuit using the AD8333. This figure also illustrates the AD8021 Because the AD8021 implements an active LPF together with as first-order current summing circuits and AD797 devices as R1x and C1x, it must absorb the worst-case current provided by low noise second-order summing circuits. Beginning with the the AD8333, for example, 6.6 mA. Therefore, the maximum operational amplifiers, there are a few important considerations number of channels that the AD8021 can sum is 10 for ±12 V or in the circuit shown in Figure 55. eight for ±5 V supplies. In practical applications, CW channels The operational amplifiers selected for the first-order summing are used in powers of two, thus the maximum number per amplifiers must have good frequency response over the full AD8021 is eight. operating frequency range of the AD8333 devices and be able to Another consideration for the operational amplifier selected as source the current required at the AD8333 I and Q outputs. an I-to-V converter is the compliance voltage of the AD8333 I The total current of each AD8333 is 6.6 mA for the multiples of and Q outputs. The maximum compliance voltage is 0.5 V, and the 45° phase settings (Code 0010, Code 0110, Code 1010, and a dc bias must be provided at these pins. The AD8021 active Code 1110) and is divided nearly equally between the baseband LPF satisfies these requirements; it keeps the outputs at 0 V via frequencies (including a dc component) and the second harmonic the virtual ground at the operational amplifier inverting input of the local oscillator frequency. The desired CW signal tends to be while providing any needed dc bias current. much less (<40 dB) than the unwanted interfering signals. FIRST-ORDER SUMMINGAMPLIFIERS C1A 18nF LPF1A 88kHz +2.8V BASEBAND R1A SIGNAL 100Ω EIGHTAD83336 .I6 OmRA QP EOAUKT PEUATCSH, +5V H10P0FH1zA L81PkFH2zA (IF THE PHASE SETTING IS 45°) 3.3mAAT DC + 3.3mAAT 2 × LO 2 – 0.1µF C1µ2FA6R928AΩ 6R938AΩ ΣA 3 + AD8021 C5.36AnF SUSMEMCIONNGDA-OMRPDLIEFRIER –5V 0.1µF R4 +10V C1B 2 0.1µF 18nF – AD797 3 + R1B 100Ω –10V (SAMEASABOVE) +5V 0.1µF 2 – 0.1µF C1µ2FB 6R928BΩ 6R938BΩ ΣB 3 + AD8021 C5.36BnF –5V 0.1µF 05543-058 Figure 55. A 16-Channel Beamformer Rev. F | Page 21 of 32

AD8333 Data Sheet As previously noted, a typical CW signal has a large dc and The filter LPF1A establishes the upper frequency limit of the very low frequency component compared with its desired low baseband frequency and is selected well below the 2 × LO CW Doppler baseband frequency, and another unwanted frequency, typically 100 kHz or less (for example, 88 kHz in component at the 2 × LO. The dc component flows through the Figure 55). gain resistors R1x, and the 2 × LO flows through the capacitors A useful equation for calculating C1 is C1x. The smaller desired CW Doppler baseband signal is in the 1 frequency range of 1 kHz to 50 kHz. C1= (1) 2πR1f Because the output current of the AD8333 contains the baseband LPF1 frequency, a dc component, and the 2 × LO frequency voltages, As previously mentioned, the AD8333 output current contains a the desired small amplitude baseband signal must be extracted dc current component. This dc component is converted to a after a series of filters. These are shown in Figure 55 as LPFnA, large dc voltage by the AD8021 LPF. Capacitor C2 filters this dc HPFnA, and gain stages. component and, with R2 + R3, establishes a high-pass filter with a low frequency cutoff of about 100 Hz. Capacitor C3 is much Before establishing the value of C , the resistor R is selected LPF1 LPF1 smaller than C2 and, consequently, can be neglected. C2 can be based on the peak operating current and the linear range of the calculated by operational amplifier. Because the peak current for each AD8333 is 6.6 mA and there are eight channels to be summed, the total peak 1 C2= (2) current required is 52.8 mA. Approximately half of this current is 2π(R2+R3)f HPF1 dc, and the other half is at a frequency of 2 × LO. Therefore, about To achieve maximum attenuation of the 2 × LO frequency, a 26.4 mA flows through the resistor, and the remaining 26.4 mA second low-pass filter, LPF2, is established using the parallel flows through the capacitor. R1 was selected as 100 Ω and, after combination of R2 and R3, and C3. Its −3 dB frequency is filtering, generates a peak dc and very low frequency voltage of 2.64 V at the AD8021 output. For power supplies of ±5 V, 100 Ω f = 1 (3) is a good choice for R1. LPF2 2π(R2||R3)C3 However, because the CW signal needs to be amplified as much In the example shown in Figure 55, fLPF2 = 81 kHz. as possible and the noise degradation of the signal path minimized, Finally, the feedback resistor of the AD797 must be calculated. the value of R1 must be as large as possible. A larger supply helps in This is a function of the input current (number of channels) this regard, and the only factor limiting the largest supply and the supply voltage. voltage is the required power. The second-order summing amplifier requires a very low noise For a ±10 V supply on the AD8021, R1 can be increased to operational amplifier, such as the AD797, with 0.9 nV/√Hz, 301 Ω to realize the same headroom as with a ±5 V supply. If a because the amplifier gain is determined by Feedback Resistor higher value of R1 is used, C1 must be adjusted accordingly (in R4 divided by the parallel combination of the LPF2A resistors this example, 1/3 the value of the original value) to maintain the seen looking back toward the AD8021 devices. Referring to desired LPF roll-off. The principal advantage of a higher supply Figure 55, the AD797 in-band (100 Hz to 88 kHz) gain is is greater dynamic range, and the trade-off is power consumption. expressed as The user must weigh the trade-offs associated with the supply R4 voltage, R1, C1, and the following circuitry. A suggested design (4) [(R2A+R3A)||(R2B+R2B)] sequence is as follows: Select a low noise, high speed operational amplifier. The The AD797 noise gain can increase to unacceptable levels because spectral density noise (e ) must be <2 nV/√Hz, and the 3 dB the denominator of the gain equation is the parallel resistance of n bandwidth must be ≥3× the expected maximum 2 × LO all the R2 + R3 resistors in the AD8021 outputs. For example, for a frequency. 64-channel beamformer, the resistance seen looking back toward the AD8021 devices is about 1.4 kΩ/8 = 175 Ω. For this reason, Divide the maximum linear output current by 6.6 mA to the value of (R2x + R3x) must be as large as possible to minimize determine the maximum number of AD8333 channels that can the noise gain of the AD797. (Note that this is the case for the be summed. AD8021 stages because they look back into the high impedance Select the largest value of R1 that permits the output voltage current sources of the AD8333 devices.) swing within the power supply rails. Due to these considerations, it is advantageous to increase the Calculate the value of C1 to implement the LPF corner that gain of the AD8021 devices as much as possible because the value allows the CW Doppler signal to pass with maximum of (R2x + R3x) can be increased proportionally. Resistors (R2x + attenuation of the 2 × LO signal. R3x) convert the CW voltages to currents that are summed at the inverting inputs of the AD797 operational amplifier, and then amplified and converted to voltages by R4. Rev. F | Page 22 of 32

Data Sheet AD8333 The value of R4 needs to be chosen iteratively as follows: The summed signal level increases by a factor of N, whereas the 1. Determine the number of AD8021 first-order summing noise increases only as √N. In the case of 64 channels, this is an increase in dynamic range of 18 dB. Note that the AD8333 dynamic amplifiers. In Figure 55, there are two; for a 32-channel range is already about 160 dB/Hz; the summed dynamic range beamformer, there must be four, and for a 64-channel is 178 dB/Hz (equivalent to about 29.5 bits/Hz). In a 50 kHz beamformer, there must be eight. 2. Determine the output noise from the AD8021 devices. A noise bandwidth, this is 131 dB (21.7 bits). first-order calculation can be based on a value of AD8333 DISABLING THE CURRENT MIRROR AND output current noise of about 20 pA/√Hz. For the values in DECREASING NOISE Figure 55, this results in about 6 nV/√Hz for eight channels The noise contribution of the AD8333 can potentially be reduced after the AD8021 devices. Adding the noise of the AD8021 if the current mirrors that convert the internal differential signals to and the 100 Ω feedback resistor results in about 6.5 nV/√Hz single-ended signals are bypassed (see Figure 56). Current mirrors total noise after the AD8021 LPF in the CW Doppler band. interface to the AD8021 I-V converters shown in Figure 53, and 3. Determine the noise of the circuitry after the AD797 and output capacitors across the positive and negative outputs provide determine the desired signal level. low-pass filtering. The AD8021 devices force the AD8333 output 4. Determine the voltage and current noise of the second- voltage to 0 V and then process the bipolar output current; order summing amplifiers. however, the internal current mirrors introduce a significant 5. Choose a value for (R2x + R3x) and for R4. Determine the amount of noise. This noise can be reduced if the mirrors are resulting output noise after the AD797 for one channel, and disabled and the outputs are externally biased. then multiply this value by the square root of the number of summed AD8021 devices. Next, check AD797 output The mirrors are disabled by connecting VNEG to ground and noise (both current and voltage noise). Ideally, the sum of providing external bias networks, as shown in Figure 56. The the noise of the resistors and the AD797 must be less than a larger the drop across the resistors, the less noise they contribute to factor of 3 than the noise due to the AD8021 outputs. the output; however, the voltage on the I and Q output nodes 6. Check the following stages output noise against the calculated cannot exceed 0.5 V. Voltages exceeding approximately 0.7 V noise from the combiner circuit and AD8333 devices. Ideally, turn on the PNP devices and forward bias the ESD protection the noise from the following stage must be less than 1/3 of diodes. Inductors provide an alternative to resistors, enabling the calculated noise. reduced static power by eliminating the power dissipation in the 7. If the combined noise is too large, experiment with bias resistors. increasing/decreasing values for (R2x + R3x) and R4. COMM To simplify, the user can also simulate or build a combiner circuit for optimum performance. It must be noted that the ~20 pA/√Hz OTHER IxNO CHANNELS output from the AD8333 is for the AD8333 with shorted RF inputs. QxNO I-V In an actual system, the current noise output from the AD8333 I-V is most likely dominated by the noise from the AD8332 LNA and IxPO the noise from the source and other circuitry before the LNA. QxPO This helps ease the design of the combiner. The preceding procedures for determining the optimum values for the combiner VNEG1 are based on the noise floor of the AD8333 only. As an example, for a 32-channel beamformer using four low- 1NAORETE C TOHNANTE PCITNE VDN TEOGG AENTHDE PRIN. COMM 05543-039 pass filters, as shown in Figure 55, (R2x + R3x) = 1.4 kΩ and R4 = 6.19 kΩ. The theoretical noise increase of √N is degraded Figure 56. Bypassing the Internal Current Mirrors by only about 1 dB. With inductors, the main limitation might be low frequency DYNAMIC RANGE INFLATION operation, as is the case in CW Doppler in ultrasound where the frequency range of interest goes from a few hundred hertz Although all 64 channels can theoretically be summed together to about 30 kHz. In addition, it is still important to provide at a single amplifier, it is important to realize that the dynamic enough gain through the I-to-V circuitry to ensure that the bias range of the summed output increases by 10 log (N) if all channels 10 resistor and I-to-V converter noise do not contribute significantly have uncorrelated noise, where N is the number of channels to to the noise from the AD8333 outputs. Another approach is to be summed. provide a single external current mirror that combines all channels; it is also possible to implement a high-pass filter with this circuit to help with offset and low frequency reduction. Rev. F | Page 23 of 32

AD8333 Data Sheet The main disadvantage of the external bias approach is that two Excessive noise or distortion at high signal levels degrades the I-V amplifiers are needed because of the differential output (see dynamic range of the signal. Transmitter leakage and echoes Figure 56). For beamforming applications, the outputs are still from slow moving tissue generate the largest signal amplitudes summed, but there is twice the number of lines. Only two bias in ultrasound CW Doppler mode and are largest near dc and at resistors are needed for all outputs that are connected together. low frequencies. A high-pass filter introduced immediately The resistors are scaled by dividing the value of a single output following the AD8333 reduces the dynamic range. This is bias resistor through N, the number of channels connected in shown by the two coupling capacitors after the external bias parallel. The bias current depends on the phase selected: for resistors in Figure 56. Users have to determine what is acceptable phase 0°, it is about 2.5 mA per side, whereas in the case of 45°, for a particular application. Care must be taken in designing the it is about 3.5 mA per side. The bias resistors must be chosen external circuitry to avoid introducing noise via the external based on the larger bias current value of 3.5 mA and the chosen bias and low frequency reduction circuitry. VNEG. VNEG must be at least −5 V and can be larger for additional noise reduction. Rev. F | Page 24 of 32

Data Sheet AD8333 APPLICATIONS INFORMATION The AD8333 is the key component of a phase-shifter system The rising edge of the active high RSET pulse can occur at any that aligns time-skewed information contained in RF signals. time, but the duration must be ≥300 ns minimum (t ). When PW-MIN Combined with a variable gain amplifier (VGA) and low noise the RSET pulse transitions from high to low, the LO dividers are amplifier (LNA), the AD8333 forms a complete analog receiver reactivated; however, there is a short delay until the divider for a high performance ultrasound system. Figure 57 is a block recovers to a valid state. To guarantee synchronous operation of diagram of a complete receiver using the AD8333, AD8331, an array of AD8333 devices, the 4 × LO clock must be disabled AD8332, and AD8334. when the RSET transitions high, and then remain disabled for at least 300 ns after RSET transitions low. LNA1 AD8332 I1 TRTA/NRS SDWFURICTOCEMRH Q1 1A6-DBCIT PROCESSOR 4×LO t LNA2 AD8333 I2 RSET tPW-MIN HOLD TRTA/NRS SDWFURICTOCEMRH Q2 1A6-DBCIT PROCESSOR THETIMING OFTHERISING EDGE OFRSET ISNOT CRITICALASLONGASTHE tPW-MIN ISSATISFIED HS ADC PROCESSOR ttHPWOL-MDIN==HOMLINDIMTUIMMEPULSEWIDTH 05543-060 HS ADC PROCESSOR 05543-059 SynchronizatioFing uorfe m58u. Tltiimpline gA oDf t8h3e 3R3SE dTe Svigicneasl ctoa n4 ×b eL Oc hecked as Figure 57. Block Diagram—Ultrasound Receiver Using the AD8333 follows: and AD8332 LNA 1. Set the phase code of all AD8333 channels to the same As a major element of an ultrasound system, it is important to setting, for example, 0000. consider the many input/output options of the AD8333 that are 2. Apply a test signal to a single channel that generates a sine necessary to perform its intended function. Figure 61 shows the wave in the baseband output, and then measure the output. basic connections. 3. Apply the same test signal to all channels simultaneously, LOGIC INPUTS AND INTERFACES and then measure the output. The logic inputs of the AD8333 are all bipolar-level sensitive Because all the phase codes of the AD8333 devices are the same, inputs. They are not edge triggered, nor are they to be confused the combined signal must be N times bigger than the single with classic TTL or other logic family input topologies. The channel. The combined signal is less than N times one channel if voltage threshold for these inputs is VPOS × 0.3, so for a 5 V any of the LO phases of individual AD8333 devices are in error. supply the threshold is 1.5 V, with a hysteresis of ±0.2 V. CONNECTING TO THE LNA OF THE Although the inputs are not of themselves logic inputs, any 5 V AD8331/AD8332/AD8334/AD8335 VGAs logic family can drive them. +5V RESET INPUT The RSET pin is used to synchronize the LO dividers in AD8333 arrays. Because they are driven by the same internal RFxP LO, the two channels in any AD8333 are inherently synchronous. AD8332 AD8333 LNA However, when multiple AD8333 devices are used, it is possible RFxN tfhuantc tthioenir odfi vtihdee RrsS wETak pei nu pis itno dpihfafesree anlitg pnh aalsl eth set aLtOes .s Tighnea ls in –5V 05543-061 multiple AD8333 devices. Figure 59. Connecting the AD8333 to the LNA of an AD8332 The 4 × LO divider of each AD8333 can initiate in one of four The RFxx inputs (Pin 12, Pin 13, Pin 28, and Pin 29) are possible states: 0°, 90°, 180°, or 270°. The internally generated optimized for maximum dynamic range when dc-coupled to I/Q signals of each AD8333 LO are always at a 90° angle relative the differential output pins of the LNA of the AD8331/AD8332/ to each other, but a phase shift can occur during power-up AD8334 or the AD8335 series of VGAs and can be connected between the internal LOs of the different AD8333 devices. directly, as shown in Figure 59. The RSET pin provides an asynchronous reset of the LO dividers by forcing the internal LO to hang. This mechanism also allows the measurement of nonmixing gain from the RF input to the output. Rev. F | Page 25 of 32

AD8333 Data Sheet INTERFACING TO OTHER AMPLIFIERS To realize the full range of performance, the AD8333 must be driven from a differential source. Using a single-ended source is If amplifiers other than the AD8332 LNA are connected to the strongly discouraged because of internal supply headroom input, attention must be paid to their bias and drive levels. For constraints. maximum input signal swing, the optimum bias level is 2.5 V, and the RF input must not exceed 5 V to avoid turning on the LO INPUT ESD protection circuitry. If ac coupling is used, a bias circuit, The LO input is a high speed, fully differential analog input such as that illustrated in Figure 60, is recommended. An internal that responds to differences in the input levels, not in the logic bias network is provided; however, additional external biasing levels. The LO inputs can be driven with a low common-mode can center the RF input at 2.5 V. voltage amplifier, such as the National Semiconductor DS90C401 +5V LVDS driver. Figure 22 and Figure 23 show the range of common-mode voltages 5.23kΩ 1.4kΩ and useable LO levels when the LO input is driven with a single- 0.1µF AD8333 ended sine wave. Logic families, such as TTL or CMOS, are RFxP unsuitable for direct coupling to the LO input. RF IN 0.1µF RFxN 1.4kΩ 3.74kΩ –5V 05543-062 Figure 60. AC Coupling the AD8333 RF Input VPOS CHANNEL 1– 120nH FB RF IN+ +5V CHANNEL 1 PHASE 0.1µF SELECT BITS 32 31 30 29 28 27 26 25 * +5V 12 PPHH1211PH10 VPOS RF1P RF1N VPOS ENBLI1IN1POO 2243 C+ HI AONUNTEL 1 PH13 Q1PO CHANNEL 1 33.2kΩ 33.2kΩ 3 COMM Q1NO 22 + Q1 2O0UnTH FB + 0.1µF 4 21 LOCAL 4LOP AD8333 VNEG –5V OSCILLATOR– 301..16µkFΩ 31.6kΩ 0.1µF56 4LLOODNC CQO2MNMO 2109 0.1µF 7 18 CHANNEL 2 PH23 Q2PO + Q OUT 8 PH22 H20 POS F2P F2N POS SET I2PO 17 C+ HI AONUNTEL 2 PH21P V R R V RI2NO CHANNEL 2 9 10 11 12 13 14 15 16 PHASE SELECT BITS CHANNEL 2+ 0.1µF RF IN– VPOS RESET INPUT *AONPTLIVODNSA LS OBUIARSC NEE BTIWASOERDKA. TT H1E.2SVE. COMPONENTS CAN BE DELETED IF THE LO IS DC-COUPLED FROM 05543-040 Figure 61. AD8333 Basic Connections Rev. F | Page 26 of 32

Data Sheet AD8333 EVALUATION BOARD The AD8333-EVALZ evaluation board provides a platform for Phase Nibble test and evaluation of the AD8333 I/Q demodulator and phase The phase nibble configures the phase delay for each channel in shifter. The board is shipped fully assembled and tested and is sixteen 22.5° increments from 0° to 337.5°. The increments increase signal ready. A pair of AD8332 low-noise amplifiers (LNA) proportionally in a simple binary format from 0H (hexadecimal) provide input matching and amplification for the differential to FH. Table 4 lists the phase shift and corresponding code for input of the AD8333. A photograph of the board is shown in each bit. The bits are labeled 0 and 1, corresponding to low and Figure 62 and a schematic diagram is shown in Figure 64. The high, respectively, on the silkscreen. The switches select the board requires dual 5 V supplies capable of supplying 300 mA desired state. or greater. Except for the optional components shown in Enable and Reset Switches grayscale, the board is completely built and tested. For normal operation, place a switch in the upper position of ENBL. To disable the AD8333, move the switch to the lower position. For normal operation, the switch for RST is in its right position. When the switch is in the left position, the device counter is held in reset and no mixing occurs. Fixed Options Several options can be realized by adding or changing resistors. LNA Input Impedance The shipping configuration of the input impedance of the LNA is 50 Ω to match the output impedance of most signal generators. Input impedances up to 6 kΩ are obtained by selecting the R9 and R10 values. Details concerning this circuit feature are found in the AD8332 data sheet. For reference, Table 6 lists common values 05543-067 oTfa ibnlpeu 6t. iLmNpAed Eaxntceer annadl Ccoormrepsopnonendtin Vga fleueedsb faocrk T reyspisictoarl Vvaalluueess. Figure 62. Evaluation Board (Actual Size) of Source Impedance FEATURES AND OPTIONS R (Ω) R , Nearest STD 1% Value (Ω) C (pF) IN FB SH The evaluation board has several user-configurable features and 50 280 22 options. Table 5 lists the configuration switches and their 75 412 12 functions. 100 562 8 200 1.13 k 1.2 Table 5. Switch Functions 500 3.01 k None Switch Function Configuration 6 k ∞ None ENBL Enable or disable Bottom = disable; top = enable the AD8333 Current Summing PH10 Channel 1 Phase Top = 0; bottom = 1 Bit 0 (LSB) The output transimpedance amplifiers, A1 through A4, are PH11 Channel 1 Phase Top = 0; bottom = 1 configured as I-to-V converters to convert the output current of Bit 1 the AD8333 to a voltage. The low-pass filters formed by the PH12 Channel 1 Phase Top = 0; bottom = 1 feedback components are designed for single-channel operation Bit 2 with ±5 V supplies. PH13 Channel 1 Phase Top = 0; bottom = 1 Optional Resistors R4 and R5 sum the two channels. With R4 Bit 3 (MSB) and R5 installed, R2 and R3 are removed, and then the sum of PH20 Channel 2 Phase Top = 1; bottom = 0 Bit 0 (LSB) the outputs is seen at the I1xO and Q1xO output SMA connectors. PH21 Channel 2 Phase Top = 1; bottom = 0 The user has the option to adjust the values of R39, R40, R41, or Bit 1 R42 according to the power supply voltages and expected input PH22 Channel 2 Phase Top = 1; bottom = 0 current levels. For the same supply voltages, if two channels are Bit 2 summed together, the feedback resistors are halved and the filter PH23 Channel 2 Phase Top = 1; bottom = 0 capacitor values doubled to optimize the output swing. Bit 3 (MSB) RST Reset Left = run; right = reset Rev. F | Page 27 of 32

AD8333 Data Sheet Filter Capacitors C26, C29, C31, and C 32 establish the roll-off For ease in observing waveforms, the signal generators can be characteristic according to the following well-known equation: synchronized. Remember that the f signal generator 4LO frequency is four times that of the nominal frequency of the RF 1 f  source. For example, to detect signals with a nominal center RC frequency of 5 MHz, an f frequency of 20 MHz is applied to 4LO where R is the value of R39, R40, R41, or R42, and C is the value the oscillator input. For an applied RF signal of 5.01 MHz, the of C26, C29, C31, or C32. mix frequencies are 10 kHz and 10.01 MHz. Because of the low- Reset Input pass active filter of the transconductance amplifiers (A1 through A4), the 10.01 MHz component is suppressed, and only For normal operation, the reset input is high (no reset). To drive the 10 kHz is observed at the output. the reset with a dynamic signal, a provision is made to connect a signal generator at the RST input. A 49.9 Ω, 0603 surface-mount Take care to avoid overdriving the LNA input of the AD8332. resistor can be installed at R15 to terminate the reset input for The LNA gain is 19 dB (9.5×) and the maximum output swing pulsed experiments. In this configuration, the switch at RST is must not be exceeded; −10 dBm suffices for many experiments. not used and must be removed to avoid loading the power supply. The f input is ac-coupled to a 5 V LVDS buffer to provide an 4LO ideal interface to the AD8333. MEASUREMENT SETUP The f level is frequency dependent; refer to Figure 22 for Figure 63 is a layout of the AD8333-EVALZ showing the con- 4LO minimum signal levels, and then adjust the generator output level nectors and switches. Figure 65 shows a typical board and test accordingly. equipment setup with two signal generators, a power splitter, and a ±5 V, 300 mA (minimum) power supply. G 05543-066 Figure 63. Evaluation Board Assembly Rev. F | Page 28 of 32

Data Sheet AD8333 EVALUATION BOARD SCHEMATIC AND ARTWORK 240-34550 5VSR39787Ω C262.2NF 27-R32I10Ω16A1AD802185L7+C273120NHFB45PF-5V C450.1µF-5VS +5VSR40787ΩC460.1µFC292.2NF 27-R33Q10Ω1A26AD802185+C28345PF-5VSC470.1µFL4120NHFB-5VC48C360.1µF0.1µFR5OPT+5VSR41C49R3787Ω0.1µF0ΩC312.2NF 27-R35Q210ΩA36AD802185+C30345PF-5VSC50R420.1µF787Ω C322.2NF 27-R38I20Ω16A4AD802185+5VS+C33345PF-5VSC520.1µF L6+-5V120NHFB C44-5V0.1µFC810µF+10VTP6 +5VSTP5 L3120NHFB ENBLH C240.1µF 252627LSI1NOBONP24EVI1PO23Q1PO22R4Q1NOOPT21VNEG3320COMM19Q2NO18Q2PO17I2POSTOESPRVI2NOR20Ω151614VPOSH+5VRST+5VSC410.1µFL R15OPTRST+5VS C510.1µFTP7 TP8 +5V C710µF10V 28NPIIFFRR DUTAD83 NP22FFRR 13 GND4D3+5V + PH13 LH PH12 LH PH11 LH PH10VPOSLH 302932310SPH111OHPPVPH12 PH13 COMM 4LOP 4LON LODC PH23 PH22S0O2HPH21PVP 9101112 LH PH20LH PH21LH PH22LH PH23+5V N G 1 2 3 4 5 6 7 8 2 ND Ω Ω ND1G C170.1µF R71.5K R1349.9 G 2 R2620Ω R2520Ω +5V L5120NHFB C431NF R1100Ω 3 4 C9µF LOP 2µF Z3C401 0.1 24 23 VPS22C40.121 20 19 18 17 FDS90 R63.48KΩ R2220Ω R2320Ω PS 25LENBVBNECOMM VOH1 VOL1 VPSV NC VOL2 VOH2 COMMNIAGRCLMP16C130.1µ 17 6 C14V0.1µF 29282627O11NMLIICVHV Z1AD8332 2EDM2NOCIMVV 14131215 C110.1µF+5VC120.1µF 8Z3SPARE 5 1PIV 2PIV 30 11 1MOC 2MOC 3132 LOP1 LON1 VPS1 INH1 LMD1 LMD2 INH2 VPS2 LON2 LOP2910 1 2 3 4 5 6 7 8 R9274Ω VPS C5µF VPS R10274Ω C39.018µF C10.1µFTP4 C222PFTP3 C60.1µF0.1C40.1µFTP2 C322PFTP1 C40.018µF L1NHFB N1 L2NHFB N2 120 I 120 I Figure 64. Evaluation Board Schematic Rev. F | Page 29 of 32

AD8333 Data Sheet TOP GENERATOR: BOTTOM GENERATOR: SIGNAL GENERATOR FORf4LO INPUT, SIGNAL GENERATOR FOR RF INPUT, TYPICAL SETTING: 20MHz TYPICAL SETTING: 5.01MHz SIGNAL 1V p-p POWER SUPPLY +5V –5V POWER SPLITTER INSPIGUNT(ASL) 05543-065 Figure 65. Typical Board Test Connections (One Channel Shown) Rev. F | Page 30 of 32

Data Sheet AD8333 BOARD LAYOUT The AD8333 evaluation board has four layers. The interconnecting circuitry is located on the outer layers with the inner layers dedicated as power and ground planes. Figure 66, Figure 67, Figure 69, and Figure 70 illustrate the copper patterns. 05543-068 05543-070 Figure 66. Component Side Copper Figure 69. Ground Plane Copper 05543-069 05543-071 Figure 67. Wiring Side Copper Figure 70. Power Plane Copper 05543-072 Figure 68. Component Side Silkscreen Rev. F | Page 31 of 32

Data Sheet AD8333 OUTLINE DIMENSIONS 5.10 0.30 5.00 SQ 0.25 PIN 1 4.90 0.18 INDICATOR PIN 1 25 32 INDICATOR 24 1 0.50 BSC EXPOSED 3.25 PAD 3.10 SQ 2.95 17 8 0.50 16 9 0.25 MIN TOP VIEW 0.40 BOTTOM VIEW 0.30 FOR PROPER CONNECTION OF 0.80 THE EXPOSED PAD, REFER TO 0.75 THE PIN CONFIGURATION AND 0.05 MAX FUNCTION DESCRIPTIONS 0.70 0.02 NOM SECTION OF THIS DATA SHEET. COPLANARITY 0.08 SEATING 0.20 REF PLANE COMPLIANT TO JEDEC STANDARDS MO-220-WHHD. 112408-A Figure 71. 32-Lead Lead Frame Chip Scale Package [LFCSP] 5 mm × 5 mm Body and 0.75 mm Package Height (CP-32-7) Dimensions shown in millimeters ORDERING GUIDE Model1, 2 Temperature Range Package Description Package Option AD8333ACPZ-REEL −40°C to +85°C 32-Lead Lead Frame Chip Scale Package [LFCSP] CP-32-7 AD8333ACPZ-REEL7 −40°C to +85°C 32-Lead Lead Frame Chip Scale Package [LFCSP] CP-32-7 AD8333ACPZ-WP −40°C to +85°C 32-Lead Lead Frame Chip Scale Package [LFCSP] CP-32-7 AD8333-EVALZ Evaluation Board 1 Z = RoHS Compliant Part. 2 WP = waffle pack. ©2005–2016 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D05543-0-5/16(F) Rev. F | Page 32 of 32

Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: A nalog Devices Inc.: AD8333ACPZ-REEL AD8333ACPZ-REEL7 AD8333ACPZ-WP AD8333-EVALZ