Low Cost, DC to 150 MHz, Variable Gain Amplifier Data Sheet AD8330 FEATURES FUNCTIONAL BLOCK DIAGRAM Fully differential signal path, also used with single-sided signals ENBL OFST CNTR Inputs from 0.3 mV to 1 V rms, rail-to-rail outputs Differential RIN = 1 kΩ; ROUT (each output) 75 Ω CM AND Automatic offset compensation (optional) BIAS AND VREF COOFNFTSREOTL Linear-in-dB and linear-in-magnitude gain modes 0 dB to 50 dB, for 0 V < V < 1.5 V (30 mV/dB) INHI OPHI DBS VGA CORE OUTPUT Inverted gain mode: 50 dB to 0 dB at −30 mV/dB STAGES INLO OPLO ×0.03 to ×10 nominal gain for 15 mV < V < 5 V MAG Constant bandwidth: 150 MHz at all gains OUTPUT MODE GAIN INTERFACE CONTROL CMOP Low noise: 5 nV/√Hz typical at maximum gain LLooww dpioswtoerrt:i 2o0n :m ≤A−6 t2yp diBcacl t aytp VicSa ol f 2.7 V to 6 V VDBS CMGN COMM VMAG 03217-101 Available in a space-saving, 3 mm × 3 mm LFCSP package Figure 1. APPLICATIONS Pre-ADC signal conditioning 75 Ω cable driving adjust AGC amplifiers GENERAL DESCRIPTION The AD8330 is a wideband variable gain amplifier for applications 30 dB lower (that is, –30 dB to +20 dB) to suit the application, requiring a fully differential signal path, low noise, well-defined thereby providing an unprecedented gain range of over 100 dB. gain, and moderately low distortion, from dc to 150 MHz. The A unique aspect of the AD8330 is that its bandwidth and pulse input pins can also be driven from a single-ended source. The response are essentially constant for all gains, over both the peak differential input is ±2 V, allowing sine wave operation at basic 50 dB linear-in-dB range, but also when using the linear- 1 V rms with generous headroom. The output pins can drive in-magnitude function. The exceptional stability of the HF single-sided loads essentially rail-to-rail. The differential output response over the gain range is of particular value in those VGA resistance is 150 Ω. The output swing is a linear function of the applications where it is essential to maintain accurate gain law- voltage applied to the VMAG pin that internally defaults to 0.5 V, conformance at high frequencies. providing a peak output of ±2 V. This can be raised to 10 V p-p, An external capacitor at Pin OFST sets the high-pass corner of limited by the supply voltage. an offset reduction loop, whose frequency can be as low as 5 Hz. The basic gain function is linear-in-dB, controlled by the voltage When this pin is grounded, the signal path becomes dc-coupled. applied to Pin VDBS. The gain ranges from 0 dB to 50 dB for When used to drive an ADC, an external common-mode control control voltages between 0 V and 1.5 V—a slope of 30 mV/dB. voltage at Pin CNTR can be driven to within 0.5 V of either ground The gain linearity is typically within ±0.1 dB. By changing the or V to accommodate a wide variety of requirements. By default, S logic level on Pin MODE, the gain decreases over the same range, the two outputs are positioned at the midpoint of the supply, V/2. S with an opposite slope. A second gain control port is provided Other features, such as two levels of power-down (fully off and at the VMAG pin and allows the user to vary the numeric gain a hibernate mode), further extend the practical value of this from a factor of 0.03 to 10. All the parameters of the AD8330 exceptionally versatile VGA. have low sensitivities to temperature and supply voltages. Using The AD8330 is available in 16-lead LFCSP and 16-lead QSOP VMAG, the basic 0 dB to 50 dB range can be repositioned to packages and is specified for operation from −40°C to +85°C. any value from 20 dB higher (that is, 20 dB to 70 dB) to at least Rev. H Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Tel: 781.329.4700 ©2002–2016 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com

AD8330 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1  Applications Information .............................................................. 26  Applications ....................................................................................... 1  ADC Driving ............................................................................... 26  Functional Block Diagram .............................................................. 1  Simple AGC Amplifier .............................................................. 26  General Description ......................................................................... 1  Wide Range True RMS Voltmeter ............................................ 27  Revision History ............................................................................... 2  Evaluation Board ............................................................................ 29  Specifications ..................................................................................... 3  General Description ................................................................... 29  Absolute Maximum Ratings ............................................................ 5  Basic Operation .......................................................................... 29  ESD Caution .................................................................................. 5  Options ........................................................................................ 30  Pin Configurations and Function Descriptions ........................... 6  Measurement Setup.................................................................... 30  Typical Performance Characteristics ............................................. 8  AD8330-EVALZ Board Design ................................................. 30  Theory of Operation ...................................................................... 15  Outline Dimensions ....................................................................... 32  Circuit Description..................................................................... 15  Ordering Guide .......................................................................... 32  Using the AD8330 ...................................................................... 21  REVISION HISTORY 5/2016—Rev. G to Rev. H 1/2008—Rev. C to Rev. D Changes to Figure 2 and Table 3 ..................................................... 6 Changes to Figure 28 and Figure 29............................................. 12 Moved Figure 3 ................................................................................. 7 Added Evaluation Board Section ................................................. 28 Changes to Table 4 ............................................................................ 7 Changes to Ordering Guide .......................................................... 33 Change to Figure 45 ....................................................................... 15 Changes to Simple AGC Amplifier Section ................................ 27 6/2006—Rev. B to Rev. C Updated Outline Dimensions ....................................................... 32 Updated Format .................................................................. Universal Changes to Ordering Guide .......................................................... 32 Changes to Figure 1 ........................................................................... 1 Deleted Figure 2; Renumbered Sequentially ................................. 1 5/2014—Rev. F to Rev. G Changes to Specifications Section ................................................... 3 Changes to Table 1 ............................................................................ 3 Change to Absolute Maximum Ratings ......................................... 5 Changes to Typical Performance Characteristics Summary 11/2012—Rev. E to Rev. F Statement ............................................................................................ 7 Changes to Figure 1 .......................................................................... 1 Changes to Figure 14 and Figure 15................................................ 8 Changes to Output (Input) Common-Mode Control ............... 20 Changes to Figure 31 and Figure 32............................................. 11 Updated Outline Dimensions ....................................................... 31 Updated Outline Dimensions ....................................................... 28 Changes to Ordering Guide .......................................................... 31 10/2004—Rev. A to Rev. B 3/2010—Rev. D to Rev. E Changes to Absolute Maximum Ratings Section and Ordering Changes to Figure 2 and Table 3 ..................................................... 6 Guide Section ..................................................................................... 4 Changes to Figure 69 ...................................................................... 28 Change to TPC 14 ............................................................................. 8 Changes to Figure 71 ...................................................................... 29 Note Added to CP-16 Package ...................................................... 26 Changes to Figure 72 ...................................................................... 30 Deleted Table 7; Renumbered Sequentially ................................ 31 4/2003—Rev. 0 to Rev. A Changes to Ordering Guide .......................................................... 32 Updated Outline Dimensions ....................................................... 26 10/2002—Revision 0: Initial Version Rev. H | Page 2 of 32

Data Sheet AD8330 SPECIFICATIONS V = 5 V, T = 25°C, C = 12 pF on OPHI and OPLO, R = ∞, V = 0.75 V, V = high, V = Pin VMAG open circuit (0.5 V), S A L L DBS MODE MAG V = 0 V, differential operation, unless otherwise noted. OFST Table 1. Parameter Test Conditions/Comments Min Typ Max Unit INPUT INTERFACE Pin INHI, Pin INLO Full-Scale Input V = 0 V, differential drive ±1.4 ±2 V DBS V = 1.5 V ±4.5 ±6.3 mV DBS Input Resistance Pin-to-pin 800 1 k 1.2 k Ω Input Capacitance Either pin to COMM 4 pF Voltage Noise Spectral Density f = 1 MHz, V = 1.5 V; inputs ac-shorted 5 nV/√Hz DBS Common-Mode Voltage Level 2.75 3.0 3.25 V Input Offset Pin OFST connected to Pin COMM 1 mV rms Drift 2 µV/°C Permissible CM Range1 0 V V S Common-Mode AC Rejection f = 1 MHz, 0.1 V rms −60 dB f = 50 MHz −55 dB OUTPUT INTERFACE Pin OPHI, Pin OPLO Small Signal –3 dB Bandwidth 0 V < V < 1.5 V 150 MHz DBS Peak Slew Rate V = 0 V 1500 V/µs DBS Peak-to-Peak Output Swing ±1.8 ±2 ±2.2 V V ≥ 2 V (peaks are supply limited) ±4 ±4.5 V MAG Common-Mode Voltage Pin CNTR O/C 2.4 2.5 2.6 V Offset Voltage Offset Correction Enabled 1 ±5 mV Offset Correction Disabled Pin OFST connected to ground 8 ±40 mV Voltage Noise Spectral Density f = 1 MHz, V = 0 V 62 nV/√Hz DBS Differential Output Impedance Pin-to-pin 120 150 180 Ω HD22 V = 1 V p-p, f = 10 MHz, R = 1 kΩ −62 dBc OUT L HD32 V = 1 V p-p, f = 10 MHz, R = 1 kΩ −53 dBc OUT L OUTPUT OFFSET CONTROL Pin OFST AC-Coupled Offset C on Pin OFST (0 V < V < 1.5 V) 10 mV rms HPF DBS High-Pass Corner Frequency C = 3.3 nF, from OFST to CNTR (scales as 1/C ) 100 kHz HPF HPF COMMON-MODE CONTROL Pin CNTR Usable Voltage Range 0.5 4.5 V Input Resistance From Pin CNTR to V/2 4 kΩ S DECIBEL GAIN CONTROL VDBS, CMGN, and MODE pins Normal Voltage Range CMGN connected to COMM 0 to 1.5 V Elevated Range CMGN O/C (V rises to 0.2 V) 0.2 to 1.7 V CMGN Gain Scaling Mode high or low 27 30 33 mV/dB Gain Linearity Error 0.3 V ≤ V ≤ 1.2 V −0.35 ±0.1 +0.35 dB DBS Absolute Gain Error V = 0 V −2 ±0.5 +2 dB DBS Bias Current Flows out of Pin VDBS 100 nA Incremental Resistance 100 MΩ Gain Settling Time to 0.5 dB Error V stepped from 0.05 V to 1.45 V or 1.45 V to 0.05 V 250 ns DBS Mode Up/Down Pin MODE Mode Up Logic Level Gain increases with V , MODE = O/C 1.5 V DBS Mode Down Logic Level Gain decreases with V 0.5 V DBS Rev. H | Page 3 of 32

AD8330 Data Sheet Parameter Test Conditions/Comments Min Typ Max Unit LINEAR GAIN INTERFACE Pin VMAG, Pin CMGN Peak Output Scaling, Gain vs. V See the Circuit Description section 3.8 4.0 4.2 V/V MAG Gain Multiplication Factor vs. V Gain is nominal when V = 0.5 V ×2 MAG MAG Usable Input Range 0 5 V Default Voltage V O/C 0.48 0.5 0.52 V MAG Incremental Resistance 4 kΩ Bandwidth For V ≥ 0.1 V 150 MHz MAG CHIP ENABLE Pin ENBL Logic Voltage for Full Shutdown 0.5 V Logic Voltage for Hibernate Mode Output pins remain at CNTR 1.3 1.5 1.7 V Logic Voltage for Full Operation 2.3 V Current in Full Shutdown 20 100 µA Current in Hibernate Mode 1.5 mA Minimum Time Delay3 1.7 µs POWER SUPPLY VPSI, VPOS, VPSO, COMM, and CMOP pins Supply Voltage 2.7 6 V Quiescent Current V = 0.75 V 20 27 mA DBS 1 The use of an input common-mode voltage significantly different from the internally set value is not recommended due to its effect on noise performance. See Figure 56. 2 See the Typical Performance Characteristics section for more detailed information on distortion in a variety of operating conditions. 3 For minimum sized coupling capacitors. Rev. H | Page 4 of 32

Data Sheet AD8330 ABSOLUTE MAXIMUM RATINGS Table 2. Stresses at or above those listed under Absolute Maximum Parameter Rating Ratings may cause permanent damage to the product. This is a Supply Voltage 6 V stress rating only; functional operation of the product at these Power Dissipation or any other conditions above those indicated in the operational 16-Lead QSOP Package1 0.62 W section of this specification is not implied. Operation beyond 16-Lead LFCSP Package 1.67 W the maximum operating conditions for extended periods may Input Voltage at Any Pin V + 200 mV affect product reliability. S Storage Temperature Range −65°C to +150°C ESD CAUTION θ JA 16-Lead QSOP Package 105.4°C/W 16-Lead LFCSP Package 60°C/W θ JC 16-Lead QSOP Package 39°C/W Operating Temperature Range −40°C to +85°C Lead Temperature (Soldering 60 sec) 300°C 1 4-layer JEDEC Board (252P). Rev. H | Page 5 of 32

AD8330 Data Sheet PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS L T S R B S O T N F P N E O V C 6 5 4 3 1 1 1 1 VPSI 1 12 VPSO INHI 2 AD8330 11 OPHI INLO 3 (NToOt Pto V SIEcWale) 10 OPLO MODE 4 9 CMOP 5 6 7 8 S N M G B G M A DV MC OC MV NOTES 1. THE EXPOSEDPAD IS NOT CONNECTED INTERNALLY. AFTNOHADRT MI NTACHXREIMEPAUASMDE BTDEH R ESEROLMLIAADBLEI RLCIEATDYP ATOBOFI LTTIHHTEYE, GSITOR IOLSDU RENERDC JPOOLMIANMNTEESN.DED 03217-003 Figure 2. 16-Lead LFCSP Pin Configuration Table 3. 16-Lead LFCSP Pin Function Descriptions Pin No. Mnemonic Description 1 VPSI Positive Supply for Input Stages. 2 INHI Differential Signal Input, Positive Polarity. 3 INLO Differential Signal Input, Negative Polarity. 4 MODE Logic Input: Selects Gain Slope. High = gain up vs. V . DBS 5 VDBS Input for Linear-in-dB Gain Control Voltage, V . DBS 6 CMGN Common Baseline for Gain Control Interfaces. 7 COMM Ground for Input and Gain Control Bias Circuitry. 8 VMAG Input for Gain/Amplitude Control, V . MAG 9 CMOP Ground for Output Stages. 10 OPLO Differential Signal Output, Negative Polarity. 11 OPHI Differential Signal Output, Positive Polarity. 12 VPSO Positive Supply for Output Stages. 13 CNTR Common-Mode Output Voltage Control. 14 VPOS Positive Supply for Inner Stages. 15 OFST Internal Offset Compensation Feature. When the OFST pin is unconnected, this feature is enabled. When the OFST pin is grounded, this feature is disabled. See the Offset Compensation section. 16 ENBL Power Enable, Active High. EPAD Exposed Pad. The exposed pad is not connected internally. For increased reliability of the solder joints and maximum thermal capability, it is recommended that the pad be soldered to the ground plane. Rev. H | Page 6 of 32

Data Sheet AD8330 OFST 1 16 VPOS ENBL 2 15 CNTR VPSI 3 AD8330 14 VPSO INHI 4 TOPVIEW 13 OPHI (Not to Scale) INLO 5 12 OPLO MODE 6 11 CMOP CVMDGBNS 78 190 VCMOAMGM 03217-004 Figure 3. 16-Lead QSOP Pin Configuration Table 4. 16-Lead QSOP Pin Function Descriptions Pin No. Mnemonic Description 1 OFST Internal Offset Compensation Feature. When the OFST pin is unconnected, this feature is enabled. When the OFST pin is grounded, this feature is disabled. See the Offset Compensation section. 2 ENBL Power Enable, Active High. 3 VPSI Positive Supply for Input Stages. 4 INHI Differential Signal Input, Positive Polarity. 5 INLO Differential Signal Input, Negative Polarity. 6 MODE Logic Input: Selects Gain Slope. High = gain up vs. V . DBS 7 VDBS Input for linear-in-dB Gain Control Voltage, V . DBS 8 CMGN Common Baseline for Gain Control Interfaces. 9 COMM Ground for Input and Gain Control Bias Circuitry. 10 VMAG Input for Gain/Amplitude Control, V . MAG 11 CMOP Ground for Output Stages. 12 OPLO Differential Signal Output, Negative Polarity. 13 OPHI Differential Signal Output, Positive Polarity. 14 VPSO Positive Supply for Output Stages. 15 CNTR Common-Mode Output Voltage Control. 16 VPOS Positive Supply for Inner Stages. Rev. H | Page 7 of 32

AD8330 Data Sheet TYPICAL PERFORMANCE CHARACTERISTICS V = 5 V, T = 25°C, C = 12 pF, V = 0.75 V, V = high (or O/C) V = O/C (0.5 V), R = ∞, V = 0, differential operation, unless S A L DBS MODE MAG L OFST otherwise noted. 50 2.0 NORMALIZED @VDBS = 0.75V 45 1.5 LO MODE HI MODE 40 1.0 35 B) 100MHz 50MHz B) 30 R (d 0.5 10MHz, 50MHz AIN (d 25 ERRO 0 G 20 N AI–0.5 G 15 1MHz 1MHz –1.0 10 10MHz 100MHz 5 –1.5 00 0.25 0.50 VD0B.7S5 (V) 1.00 1.25 1.50 03217-005 –2.00 0.2 0.4 0.6 VD0B.S8 (V) 1.0 1.2 1.4 1.6 03217-008 Figure 4. Gain vs. VDBS Figure 7. Gain Error vs. VDBS at Various Frequencies 10 20 2340 UNITS 9 MODE = LO 15 R O 8 CT 10 A 7 F PLICATION 65 F UNITS 2005–30.6–30.5–30.4–30.3–30.2–30.1–30.0–29.9–29.8–29.7–29.6–29.5–29.4–29.3–29.2–29.1–29.0 LTI 4 % O MODE = HI U N M 3 15 AI G 2 10 1 5 00 1 2 VMAG (V) 3 4 5 03217-006 029.1 29.2 29.3 29.4 29.5 G29A.6IN29 .S7C2A9.8LI2N9G.9 (3m0.0V/3d0.B1)30.2 30.3 30.4 30.5 30.6 03217-009 Figure 5. Linear Gain Multiplication Factor vs. VMAG Figure 8. Gain Slope Histogram 1.0 60 VDBS = 1.5V 0.8 50 1.2V 40 0.6 0.9V 30 0.4 ERROR (dB) 0.20 T = –40°C AIN (dB) 12000 000..63VVV N –0.2 G GAI T = +85°C –10 –0.4 –20 T = +25°C –0.6 –30 –0.8 –40 –1.00 0.2 0.4 0.6 VD0B.S8 (V) 1.0 1.2 1.4 1.6 03217-007 –51000k 1M FREQUEN1C0MY (Hz) 100M 500M 03217-010 Figure 6. Gain Linearity Error Normalized at 25°C vs. VDBS, Figure 9. Frequency Response in 10 dB Steps for Various Values of VDBS at Three Temperatures, f = 1 MHz Rev. H | Page 8 of 32

Data Sheet AD8330 50 25 VMAG = 4.8V 1048 UNITS 40 ENABLE MODE 1.52V 30 20 0.48V 20 0.15V dB) 10 0.048V NITS15 AIN ( 0 0.015V OF U G % 10 –10 –20 5 –30 –41000k 1M FREQUEN1C0MY (Hz) 100M 500M 03217-011 0 –0.9 –0.8 –0.7 –0.6 –0.5 –0.4DIF–0.3FE–0.2REN–0.1TI0AL 0.1OF0.2FSE0.3T (0.4mV0.5) 0.6 0.7 0.8 0.9 1.0 03217-014 Figure 10. Frequency Response for Various Values of VMAG, Figure 13. Differential Input Offset Histogram VDBS = 0.75 V 10 10 VDBS = 0.1V 0 8 B)–10 d s) OR (–20 n R LAY ( 6 E ER–30 E C D N–40 P A ROU 4 BAL–50 G T PU–60 T 2 OU–70 –80 1000k 1M FREQUENC1Y0 M(Hz) 100M 300M03217-012 –91000k 1MFREQUENCY (Hz1)0M 100M 03217-015 Figure 11. Group Delay vs. Frequency Figure 14. Output Balance Error vs. Frequency for a Representative Part 0 200 –1 190 180 E (mV)–2 T = –40°C CE (Ω)170 VOLTAG–3 PEDAN115600 T–4 T = +25°C M FSE UT I140 F P O–5 UT130 O 120 –6 T = +85°C 110 –70 0.2 0.4 0.6 VD0B.S8 (V) 1.0 1.2 1.4 1.6 03217-013 101000k 1M FREQUENC1Y0 (MHz) 100M 300M 03217-016 Figure 12. Differential Output Offset vs. VDBS for Three Temperatures, Figure 15. Output Impedance vs. Frequency for a Representative Part Rev. H | Page 9 of 32

AD8330 Data Sheet 90 6000 VDBS = 1.5V OFST:ENABLED VDBS = 1.5V 80 DISABLED f = 1MHz VDBS = 0.75V 5000 70 60 4000 B) 50 √Hz) RR (d 40 VDBS = 0V E (nV/3000 M S C 30 OI N 2000 20 10 1000 0 –1050k 100k F1RMEQUENCY (Hz) 10M 100M 03217-017 00 0.5 1.0VMAG (V)1.5 2.0 2.5 03217-020 Figure 16. CMRR vs. Frequency Figure 19. Output Referred Noise vs. VMAG 1500 80 f = 1MHz T = +85°C VMAG = 0.5V VMAG = 0.5V f = 1MHz T = +25°C 70 1200 60 T = +85°C NOISE (nV/√Hz)690000 T = –40°C NOISE (nV/√Hz) 345000 T = +25°C T = –40°C 20 300 10 00 0.2 0.4 0.6 VDB0.S8 (V) 1.0 1.2 1.4 1.6 03217-018 00 0.2 0.4 0.6 VD0B.S8 (V) 1.0 1.2 1.4 1.6 03217-021 Figure 17. Output Referred Noise vs. VDBS for Three Temperatures Figure 20. Input Referred Noise vs. VDBS for Three Temperatures 700 180 f = 1MHz f = 1MHz 600 160 140 500 VMAG = 0.125V NOISE (nV/√Hz)340000 NOISE (nV/√Hz)11208000 VMAG = 0.5V 60 200 40 100 20 VMAG = 2V 00 0.5 1.0VMAG (V)1.5 2.0 2.5 03217-019 00 0.2 0.4 0.6 VD0B.S8 (V) 1.0 1.2 1.4 1.6 03217-022 Figure 18. Output Referred Noise vs. VMAG, VDBS = 0.75 V Figure 21. Input Referred Noise vs. VDBS for Three Values of VMAG Rev. H | Page 10 of 32

Data Sheet AD8330 7 0 VDBS = 1.5V f = 10MHz 6 –10 –20 5 Hz) dBc)–30 NOISE (nV/√ 34 STORTION (––5400 HD3, RL = 1kΩ DI 2 –60 1 –70 HD2, RL = 1kΩ 1000k 1MFREQUENCY (Hz)10M 100M 03217-023 –800 0.3 0.6VOUT (V p-p0).9 1.2 1.5 03217-026 Figure 22. Input Referred Noise vs. Frequency Figure 25. Harmonic Distortion vs. VOUT , VMAG = 0.5 V 0 0 VDBS = 0.75V –10 RVOL U=T 1 =k Ω1V p-p –10 f = 10MHz –20 –20 N (dBc)–30 N (dBc)–30 HD2 AND HD3, RL = 150Ω1 DISTORTIO––4500 HD3 HD2 DISTORTIO––5400 HD3, RL = 1kΩ –60 –60 –70 –70 HD2, RL = 1kΩ 1OUTPUT AMPLITUDE HARD LIMITED –81000k 1MFREQUENCY (Hz)10M 100M 03217-024 –800 1 2VOUT (V p-p3) 4 5 03217-027 Figure 23. Harmonic Distortion vs. Frequency Figure 26. Harmonic Distortion vs. VOUT , VMAG = 2.0 V 0 0 VDBS = 0.75V f = 10MHz –10 VOUT = 1V p-p VOUT = 1V p-p RL = 1kΩ –10 RL = 1kΩ –20 –20 DISTORTION (dBc)–––543000 HD3 DISTORTION (dBc)––4300 HD3 –50 –60 HD2 HD2 –70 –60 –800 10 20CLOAD (pF)30 40 50 03217-025 –700 0.2 0.4 0.6 VD0B.S8 (V) 1.0 1.2 1.4 1.6 03217-028 Figure 24. Harmonic Distortion vs. CLOAD Figure 27. Harmonic Distortion vs. VDBS Rev. H | Page 11 of 32

AD8330 Data Sheet 10 23 30 33 f = 10MHz f = 10MHz s) m 0 13 25 28 V r B d N (–10 3 20 23 O Ω) s) B COMPRESSI––3200 ––177P1dB (REF 50 OIP3 (dBV rm1150 f = 50MHz 1138 OIP3 (dBm) d 1 V T U P–40 –27 5 8 N I –500 0.2 0.4 0.6 VDB0S.8 (V) 1.0 1.2 1.4 1.6–37 03217-029 00 0.2 0.4 0.6 VD0B.S8 (V) 1.0 1.2 1.4 1.63 03217-032 Figure 28. Input V1dB Compression vs. VDBS Figure 31. OIP3 vs. VDBS 20 33 40 43 f = 10MHz s) 35 38 m 10 23 V r f = 10MHz B 30 33 d N ( 0 13 B COMPRESSIO ––2100 –37 P1dB (REF 50Ω) OIP3 (dBV rms)122550 f = 50MHz 122883 OIP3 (dBm) d 1 T V 10 13 U P –30 –17 IN 5 8 –400 1 2 VMA3G (V) 4 5 6–27 03217-030 00 0.2 0.4 0.6 VM0A.G8 (V) 1.0 1.2 1.4 1.63 03217-033 Figure 29. Output V1dB Compression vs. VMAG Figure 32. OIP3 vs. VMAG 0 1.5 VDBS = 0.75V –10 VOUT = 1V p-p 1.0 –20 –30 0.5 Bc)–40 V) VDBS = 0V D3 (d–50 (OUT 0 M V I –60 –0.5 –70 –1.0 –80 –901M FREQU1E0NMCY (Hz) 100M 03217-031 –1.5–50 –25 0 TIM2E5 (ns) 50 75 100 03217-034 Figure 30. IMD3 Distortion vs. Frequency Figure 33. Full-Scale Transient Response, VDBS = 0 V Rev. H | Page 12 of 32

Data Sheet AD8330 1.5 1V 1.0 0.5 V) VDBS = 0.75V (UT 0 O V –0.5 –1.0 –1.5–50 –25 0 TIM2E5 (ns) 50 75 100 03217-035 1V 400ns 03217-038 Figure 34. Full-Scale Transient Response, VDBS = 0.75 V, Figure 37. VDBS Interface Response, Top: VDBS, Bottom: VOUT f = 1 MHz, VOUT = 2 V p-p 1.5 2V 1.0 0.5 V) VDBS = 1.5V (UT 0 O V –0.5 –1.0 –1.5–50 –25 0 TIM2E5 (ns) 50 75 100 03217-036 1mV 400ns 03217-039 Figure 35. Full-Scale Transient Response, VDBS = 1.5 V, Figure 38. VMAG Interface Response, Top: VMAG, Bottom: VOUT f = 1 MHz, VOUT = 2 V p-p 500mV 1V VMAG = 5V CL = 12pF VMAG = 0.5V CL = 54pF CL = 24pF VMAG = 0.05V 12.5ns 03217-037 100mV 12.5ns 03217-040 Figure 36. Transient Response vs. Various Load Capacitances, G = 25 dB Figure 39. Transient Response vs. VMAG Rev. H | Page 13 of 32

AD8330 Data Sheet 26 4.00V OUTPUT 24 A) T (m 22 +85°C N E R R 20 U C INPUT LY +25°C PP 18 U S –40°C 16 50mV 25ns 03217-041 140 0.2 0.4 0.6 VD0B.S8 (V) 1.0 1.2 1.4 1.603217-044 Figure 40. Overdrive Response, VDBS = 1.5 V, VMAG = 0.5 V, 18.5 dB Overdrive Figure 43. Supply Current vs. VDBS at Three Temperatures 2V 3.125V 2.5V 1.875V 3.125V 2.5V 1V 400ns 03217-042 1.875V 100ns 03217-045 Figure 41. ENBL Interface Response. Top: VENBL; Bottom: VOUT, f = 10 MHz Figure 44. CNTR Transient Response, Top: Input to CNTR, Bottom: VOUT Single-Ended –10 VDBS= 0.75V –20 –30 –40 VPSI B)–50 d RR (–60 VPSO PS–70 VPOS –80 –90 –100 –1101M FR1E0QMUENCY (Hz) 100M 200M03217-043 Figure 42. PSRR vs. Frequency Rev. H | Page 14 of 32

Data Sheet AD8330 THEORY OF OPERATION CIRCUIT DESCRIPTION INPUT IS xlD G = IN/ID OUTPUT IS xlN LOOP AMPLIFIER Many monolithic variable gain amplifiers use techniques that (1+x) ID (1–x) ID (1–x) IN (1+x) IN share common principles that are broadly classified as translinear. 2 2 2 2 + – This term refers to circuit cells whose functions depend directly on the very predictable properties of bipolar junction transistors, Q1 Q4 notably the linear dependence of their transconductance on collector Q2 Q3 current. Since the discovery of these cells in 1967, and their c1o9m70ms, earccciaulr aetxep wloiidtaet iboann dinw pidrothd uanctasl odge vmeluolptiepdli edrusr, idnigv itdheer es,a rly ID DBEIANSO CMUINRARTEONRT BIANSU MCEURRARTEONRT IN 03217-046 and variable gain amplifiers have invariably employed translinear Figure 45. Basic Core principles. Although these techniques are well understood, the realization ENBL OFST VPOS CNTR of a high performance variable gain amplifier (VGA) requires VPSI BIAS AND CM MODE AND VPSO special technologies and attention to many subtle details in its VREF OFFSET CONTROL design. The AD8330 is fabricated on a proprietary silicon-on- insulator, complementary bipolar IC process and draws on INHI AD8330 OPHI decades of experience in developing many leading edge products using translinear principles to provide an unprecedented level of OUTPUT STAGES versatility. INLO VGA CORE OPLO Figure 45 shows a basic representative cell comprising just four transistors. This, or a very closely related form, is at the heart of most translinear multipliers, dividers, and VGAs. The key concepts MODE GAIN INTERFACE OUTPUT are as follows: CONTROL CMOP First, the ratio of the currents in the left-hand and right-hand VDBS CMGN COMM VMAG 03217-047 pairs of transistors is identical, represented by the modulation Figure 46. Block Schematic factor, x, with values between −1 and +1. Second, the input Overall Structure signal is arranged to modulate the fixed tail current, I , to cause D the variable value of x, introduced in the left-hand pair, to be Figure 46 shows a block schematic of the AD8330 locating the replicated in the right-hand pair, and, thus, generate the output key sections. More detailed descriptions of its structure and by modulating its nominally fixed tail current, I . Third, the features are provided throughout the Theory of Operation N current gain of this cell is exactly G = I /I over many decades section; however, Figure 46 provides a general overview of its N D of variable bias current. capabilities. In practice, the realization of the full potential of this circuit The VGA core contains a more elaborate version of the cell involves many other factors, but these three elementary ideas shown in Figure 45. The current, ID, is controlled exponentially remain essential. (linear-in-decibels) through the decibel gain interface at Pin VDBS and its local common, Pin CMGN. The gain span By varying I , the overall function is that of a two-quadrant N (that is, the decibel difference between maximum and minimum analog multiplier, exhibiting a linear relationship to both the values) provided by this control function is slightly more than signal modulation factor (x) and this numerator current. On 50 dB. The absolute gain from input to output is a function of the other hand, by varying I , a two-quadrant analog divider D source and load impedance, and depends on the voltage on a is realized, having a hyperbolic gain function with respect to second gain control pin (VMAG), explained in the Normal the input factor, x, controlled by this denominator current. The Operating Conditions section. AD8330 exploits both modes of operation. However, because a hyperbolic gain function is generally of less value than one in which the decibel gain is a linear function of a control input, a special interface is included to provide either increasing or decreasing exponential control of I . D Rev. H | Page 15 of 32

AD8330 Data Sheet Normal Operating Conditions The differential impedance measured between OPHI and OPLO is 150 Ω ± 20%. It follows that both the gain and the full-scale To minimize confusion, normal operating conditions are voltage swing depend on the load impedance; both are nominally defined as follows: halved when this is also 150 Ω. A fixed impedance output • The input pins are voltage driven (the source impedance is interface, rather than an op amp style voltage-mode output, is assumed to be zero). preferable in high speed applications because the effects of complex • The output pins are open circuited (the load impedance is reactive loads on the gain and phase can be better controlled. assumed to be infinite). The top end of the AD8330 ac response is optimally flat for a 12 pF • Pin VMAG is unconnected setting up the output bias load on each pin, but this is not critical, and the system remains current (IN in the four-transistor gain cell) to its nominal stable for any value of load capacitance including zero. value. Another useful feature of this VGA in connection with the • Pin CMGN is grounded. driving of an ADC is that the peak output magnitude can be • MODE is either tied to a logic high or left unconnected, to precisely controlled by the voltage on Pin VMAG. Usually, this set the up gain mode. voltage is internally preset to 500 mV, and the peak differential The effects of other operating conditions are considered unloaded output swing is ±2 V ± 3%. However, any voltage from separately. zero to at least 5 V can be applied to this pin to alter the peak output in an exactly proportional way. Because either output Throughout this data sheet, the end-to-end voltage gain for the pin can swing rail-to-rail, which in practice means down to at normal operating conditions is referred to as the basic gain. least 0.35 V and to within the same voltage below the supply, the Under these conditions, it runs from 0 dB when V = 0 V DBS peak-to-peak output between these pins can be as high as 10 V (where this voltage is more exactly measured with reference to using V = 6 V. Pin CMGN, which is not necessarily tied to ground) up to 50 dB S CM MODE for V = 1.5 V. The gain does not fold over when the VDBS DBS VPSI FEEDBACK VPSO pin is driven below ground or above its nominal full-scale value. TRANSIMPEDANCE The input is accepted at the INHI/INLO differential port. These OUTPUT STAGE pins are internally biased to roughly the midpoint of the supply, INHI 500Ω OPHI VS (it is actually ~2.75 V for VS = 5 V, VDBS = 0 V, and 1.5 V for ΔV = 0 ΔV = 0 ROUT =150Ω VS = 3 V), but the AD8330 is able to accept a forced common- INLO 500Ω OPLO mode value, from zero to V, with certain limitations. This interface O/P CM-MODE S NORMALLY provides good common-mode rejection up to high frequencies AT VP/2 (see Figure 16) and, thus, can be driven in either a single-sided CNTR or differential manner. However, operation using a differential LINEAR-IN-dB INTERFACE MAGNITUDE drive is preferable, and this is assumed in the specifications, INTERFACE 100µA MODE unless otherwise stated. VMAG VDBS The pin-to-pin input resistance is specified as 950 Ω ± 20%. The driving-point impedance of the signal source can range from VDBS 12.65µA–4mA OR VMAG zero up to values considerably in excess of this resistance, with a COMM 4mA–12.65µA 5kΩCOMM 03217-048 corresponding variation in noise figure (see Figure 53). In most Figure 47. Schematic of Key Components cases, the input is coupled via two capacitors, chosen to provide Linear-in-dB Gain Control (V ) adequate low frequency transmission. This results in the minimum DBS input noise that increases when some other common-mode volt- All Analog Devices, Inc., VGAs featuring a linear-in-dB gain age is forced onto these pins. The short-circuit, input-referred law, such as the X-AMP® family, provide exact, constant gain noise at maximum gain is approximately 5 nV/√Hz. scaling over the fully specified gain range, and the deviation from the ideal response is within a small fraction of a dB. For Output Pin OPHI and Output Pin OPLO operate at a common- the AD8330, the scaling of both of its gain interfaces is mode voltage at the midpoint of the supply, V/2, within a few S substantially independent of process, supply voltage, or millivolts. This ensures that an analog-to-digital converter (ADC) temperature. The basic gain, G , is simply attached to these outputs operates within the often narrow B range permitted by their design. When a common-mode voltage V G (dB)= DBS (1) other than VS/2 is required at this interface, it can easily be forced B 30mV by applying an externally provided voltage to the output centering where V is in volts. pin, CNTR. This voltage can run from zero to the full supply, DBS though the use of such extreme values leaves only a small range for the differential output signal swing. Rev. H | Page 16 of 32

Data Sheet AD8330 Alternatively, this can be expressed as a numerical gain provided by V . The latter modifies the basic numerical gain MAG magnitude G to generate a total gain, expressed here in magnitude terms. BN GBN =100V.D6BVS (2) GT =GBNV0.M5AVG (3) The gain can be increased or decreased by changing the voltage, Using this to calculate the output voltage, V , applied to the VMAG pin. The internally set default value MAG V = 2 × G × V × V (4) of 500 mV is derived from the same band gap reference that OUT IN IN MAG determines the decibel scaling. The tolerance on this voltage, from which it is apparent that the AD8330 implements a linear, and mismatches in certain on-chip resistors, cause small gain two-quadrant multiplier with a bipolar VIN and a unipolar VMAG. errors (see the Specifications section). Though not all applications Because the AD8330 is a dc-coupled system, it can be used in of VGAs demand accurate gain calibration, it is a valuable asset many applications where a wideband two-quadrant multiplier in many situations, for example, in reducing design tolerances. function is required, from dc up to about 100 MHz from either input (V or V ). Figure 47 shows the core circuit in more detail. The range and IN MAG scaling of VDBS is independent of the supply voltage, and the gain As VMAG is varied, so also is the peak output magnitude, up to a control pin, VDBS, presents a high incremental input resistance point where this is limited by the absolute output limit imposed (~100 MΩ) with a low bias current (~100 nA), making the by the supply voltage. In the absence of the latter effect, the AD8330 easy to drive from a variety of gain control sources. peak output into an open-circuited load is just Inversion of the Gain Slope V = ±4 V (5) OUT_PK MAG The AD8330 supports many features that further extend the whereas for a load resistance of R directly across OPHI and L versatility of this VGA in wide bandwidth gain control systems. OPLO, it is For example, the logic pin, MODE, allows the slope of the gain ±2V R function to be inverted, so that the basic gain starts at +50 dB V = MAG L (6) OUT_PK (R +150) for a gain voltage, V , of zero and runs down to 0 dB when L DBS this voltage is at its maximum specified value of 1.5 V. The basic These capabilities are illustrated in Figure 49, where V = 6 V, S forms of these two gain control modes are shown in Figure 48. R = O/C, V = 0 V, V is swept from −2.5 V dc to +2.5 V dc, and L DBS IN 50 VMAG is set to 0.25 V, 0.5 V, 1 V, and 2 V. Except for the last value MODE PIN MODE PIN LOW, GAIN HIGH, GAIN of VMAG, the peak output follows Equation 5. This exceeds the DECREASES INCREASES supply-limited value when V = 2 V and the peak output is 40 WITH VDBS WITH VDBS MAG ±5.65 V, that is, ±6 V − 0.35 V. Figure 50 demonstrates the high speed multiplication capability. The signal input is a 100 MHz, B)30 0.1 V sine wave, VDBS is set to 0.6 V, and VMAG is a square wave at d N ( 5 MHz alternating from 0.25 V to 1 V. The output is ideally a AI G20 sine wave switching in amplitude between 0.5 V and 2 V. 8 10 6 VMAG = 2V 1V 4 00 0.25 0.50 0.V7D5BS (V) 1.0 1.25 1.50 03217-049 V) 2 0.5V Figure 48. Two Gain Directions of the AD8330 (UT 0 0.25V O V Gain Magnitude Control (VMAG) –2 In addition to the basic linear-in-dB control, two more gain –4 control features are provided. The voltage applied to Pin VMAG –6 provides accurate linear-in-magnitude gain control with a very rapid response. The bandwidth of this interface is >100 MHz. –8 W50h0 emn Vth (isse pei nF iigsu urne c4o7n) ntoec steetd u, pV MthAeG basassuicm 0e ds Bit st od e5f0a udlBt vraalnugee o. f –3 –2 –1 VIN0 ( V) 1 2 3 03217-050 Figure 49. Effect of VMAG on Gain and Peak Output However, any voltage from ~15 mV to 5 V can be applied either to lower the gain by up to 30 dB or to raise it by 20 dB. The combined gain span is thus 100 dB, that is, the 50 dB basic gain span provided by V plus a 60 dB linear-in-magnitude span DBS Rev. H | Page 17 of 32

AD8330 Data Sheet 0.10 VIN Amplitude/Phase Response 0.05 The ac response of the AD8330 is remarkably consistent not 0 only over the full 50 dB of its basic gain range, but also with –0.05 changes of gain due to alteration of V , as demonstrated in MAG –0.10 VMAG Figure 51. This is an overlay of two sets of results: first, with a 1.2 1.0 very low V of 16 mV that reduces the overall gain by 30 dB MAG 0.8 0.6 [20 × log10(500 mV/16 mV)]; second, with VMAG = 5 V that 0.4 increases the gain by 20 dB = 20 × log10(5 V/0.5 V). 0.2 2.50 VOUT 90 2.0 70 1.5 ––1100....00550 AIN (dB) 513000 ––21..–05400 –300 –200 –1T00IME (ns0) 100 200 300 03217-051 G –––315000 100k 1M 10M 100M 300M Figure 50. Using VMAG in Modulation Mode 0 G = +70dB Another gain related feature allows both gain control ranges es) –50 to be accurately raised by 200 mV. To enable this offset, open Degre––110500 circuit CMGN (Pin 6, LFCSP; Pin 8, QSOP) and add a 0.1 µF E (–200 S capacitor to ground. In use, the nominal range for VDBS extends PHA–250 –300 fsorpfo eDmcAi f0iCc.2as tVwio hntoos s 1ae.p 7op uVlyt p afuontrd ra aVnnyMg AseGu dfpropoelmsy n v0oo.t2l ti anVgc eltu.o dT 5eh. g2isr V oau.l lTnodhw easss et sh oeu urcsees –35010k 100k FRE1QMUENCY (Hz)10M G =1 0–02M0dB300M 03217-052 Figure 51. AC Performance over a 100 dB Gain Range Obtained by for the gain control function(s). Using Two Values of VMAG Note that the 200 mV that appears on this pin affects the This 50 dB step change in gain produces two sets of gain curves, response to an externally applied V , but when Pin VMAG is MAG having a total gain span of 100 dB. It is apparent that the ampli- unconnected, the internally set default value of 0.5 V still applies. tude and phase response are essentially independent of the gain Furthermore, Pin CMGN can, if desired, be driven by a user- over this wide range, an aspect of the AD8330 performance supplied voltage to reposition the baseline for V (or for an DBS potential unprecedented in any prior VGA. externally applied V ) to any other voltage up to 500 mV. In MAG It is unusual for an application to require such a wide range of all cases, the gain scaling, its law conformance, and temperature gains; and, as a practical matter, the peak output voltage for stability are unaffected. V = 16 mV is reduced by the factor 16/500, compared to its MAG Two Classes of Variable Gain Amplifiers nominal value of ±2 V, to only ±64 mV. As previously noted, Note that there are two broad classes of VGAs. The first type is most applications of VGAs require that they operate in a mode designed to cope with a very wide range of input amplitudes that is predominantly of either an IVGA or OVGA style, rather and, by virtue of its gain control function, compress this range than mixed modes. down to an essentially constant output. This is the function With this limitation in mind, and simply to illustrate the needed in an AGC system. Such a VGA is called an IVGA, unusual possibilities afforded by the AD8330, note that, with referring to a structure optimized to address a wide range of appropriate drive to V and V in tandem, the gain span is a DBS MAG input amplitudes. By contrast, an OVGA is optimized to deliver remarkable 120 dB, extending from −50 dB to +70 dB, as shown a wide range of output values while operating with an essentially in Figure 52 for operation at 1 MHz and 100 MHz. In this case, constant input amplitude. This function might be needed, for V and V are driven from a common control voltage, DBS MAG example, in providing a variable drive to a power amplifier. V , that varies from 1.2 mV to 5 V, with 30% (1.5/5) of V GAIN GAIN It is apparent from the foregoing sections that the AD8330 is applied to V , and 100% applied to V . DBS MAG both an IVGA and an OVGA in one package. This is an unusual The gain varies in a linear-in-dB manner with V , although DBS and possibly confusing degree of versatility for a VGA; therefore, the response from V is linear-in-magnitude. Consequently, the MAG these two distinct control functions are described at separate overall numerical gain as the product of these two functions is points throughout this data sheet to explain the operation and applications of this product. It is, nevertheless, useful to briefly VGAIN GAIN=V /0.5V×0.3×10 0.6V describe the capabilities of these features when used together. GAIN (7) In rare cases where such a wide gain range is of value, the calibration is still accurate and the temperature is stable. Rev. H | Page 18 of 32

Data Sheet AD8330 80 perfect, the noise figure cannot be better than 3 dB. The 1 kΩ 60 internal termination resistance results in a minimum noise AIN (dB) 24000 Hfigouwree voefr ,3 t hdiBs fios rn aont tRhSe o cfa 1s ek, Ωan idf tthhee amminpilimfiuerm w neoreis ne ofiisgeu-rfer ee. G –20 occurs at a slightly different value of R (for an example, see S –40 Figure 53 and the Using the AD8330 section). –60 100k 15 Hz) 10k 14 √ nV/ 1k 13 SE ( 100 12 OI N 10 URE11 01.001 0.01 VGA0I.N1 (V) 1 10 03217-053 OISE FIG109 Figure 52. Gain Control Function and Input Referred Noise Spectral Density N over a 120 dB Range 8 Noise, Input Capacity, and Dynamic Range 7 6 The design of variable gain amplifiers invariably incurs some cthoem ApDro8m33is0e iss i snu nchoi tshe apt etrhfiosr pmeannacltey. His omwienvimer,a tlh. Ee xsatrmuicntuatrieo onf 510 100 RS (Ω) 1k 10k 03217-054 of the simplified schematic (Figure 47) shows that the input Figure 53. Noise Figure for Source Resistance of 50 Ω to 5 kΩ, at f = 10 MHz (Lower) and 100 MHz (Simulation) voltage is converted to current-mode form by the two 500 Ω resistors at Pin INHI and Pin INLO, whose combined Johnson 144 noise contributes 4.08 nV/√Hz. The total input noise at full 140 gain, when driven from a low impedance source, is typically CONSTANT 1V rms 5 nV/√Hz after accounting for the voltage and current noise Hz)136 OUTPUT, BOTH CASES √ contributions of the loop amplifier. For a 200 kHz channel B/ d bandwidth, this amounts to 2.24 μV rms. The peak input at full NGE (132 XO-FA MGAP INW IATNHD 4 A0dNB gain is ±6.4 mV, or +4.5 mV rms for a sine wave signal. The A INPUT NSD R signal-to-noise ratio at full input, that is, the dynamic range, for MIC 128 OF nV/√Hz A these conditions is, thus, 20 log10(4.5 mV/2.24 μV), or 66 dB. YN124 The value of V has essentially no effect on the input referred D MAG noise, but it is assumed to be 0.5 V. 120 Below midgain (25 dB, V = 0.75 V), noise in the output section dominates, and thDeB Stotal input noise is 11 nV/√Hz, or 1160 0.1 0.2 0.3 0.4 0.5 0.6V0D.7BS0 (.V8)0.9 1.0 1.1 1.2 1.3 1.4 1.5 03217-055 4.9 µV rms in a 200 kHz bandwidth, and the peak input is Figure 54. Dynamic Range in dB/√Hz vs. VDBS (VMAG = 0.5 V, 1 V rms Output) 78 mV rms. Thus, the dynamic range increases to 84 dB. Compared with a Representative X-AMP (Simulation) At minimum gain, the input noise is up to 120 nV/√Hz, or Dynamic Range 53.7 mV rms in the assumed 200 kHz bandwidth, while the input capacity is ±2 V, or +1.414 V rms (sine), a dynamic range The ratio of peak output swing, expressed in rms terms, to the of 88.4 dB. In calculating the dynamic range for other channel output-referred noise spectral density provides a measure of bandwidths, ∆f, subtract 10 log10(∆f/200 kHz) from these dynamic range, in dB/√Hz. For a certain class of variable gain illustrative values. A system operating with a 2 MHz bandwidth, amplifiers, exemplified by the Analog Devices X-AMP® family, for example, exhibits dynamic range values that are uniformly the dynamic range is essentially independent of the gain setting 10 dB lower; used in an audio application with a 20 kHz band- because the peak output swing and noise are both constant. The width, they are 10 dB higher. AD8330 provides a different dynamic range profile because there is no longer a constant relationship between these two Noise figure is a misleading metric for amplifiers that are not parameters. Figure 54 compares the dynamic range of the impedance matched at their input, which is the special condi- AD8330 to a representative X-AMP. tion resulting only when both the voltage and current components of a signal, that is, the signal power, are used at the input port. Input Common-Mode Range and Rejection Ratio When a source of impedance (RS) is terminated using a resistor AC-couple the input pins, INHI and INLO, in most applications of RS (a condition that is not to be confused with matching), to achieve the stated noise performance. In general, when direct only one of these components is used, either the current (as in coupling is used, care must be taken in setting the dc voltage the AD8330) or the voltage. Then, even if the amplifier is level at these inputs, and particularly when minimizing noise is Rev. H | Page 19 of 32

AD8330 Data Sheet critical. This objective is complicated by the fact that the For example, using a reduced value of V = 0.25 V that lowers all MAG common-mode level varies with the basic gain voltage, V . gain values by 6 dB, the peak output swing is ±1 V (differentially) DBS Figure 55 shows this relationship for a supply voltage of 5 V, for and the output noise spectral density evaluates to 102.5 nV/√Hz. temperatures of −40°C, +25°C, and +85°C. Figure 56 shows the The peak output swing is no different at full gain, but the noise input noise spectral density (R = 0) vs. the input common- becomes S mode voltage, for V = 0.5 V, 0.6 V, 0.75 V, and 1.5 V. It is DBS V = (0.1 + 0.32 V ) µV/√Hz (10) NOISE_OUT MAG apparent that there is a broad range over which the noise is for R = 0 and V = 1.5 V, assuming an input noise of 5 nV/√Hz. unaffected by this dc level. The input CMRR is excellent (see S DBS The output noise for very small values of V (at or below 15 mV) Figure 16). MAG is not precise, partly because the small input offset associated 3.2 T = +85°C with this interface has a large effect on the gain. Offset Compensation V) 3.1 T = +25°C O ( The AD8330 includes an offset compensation feature that is L NHI, IN 3.0 T = –40°C oTpheirsa ltoioonpa iln intr othdeu dceefsa au lht icgohn-dpiatisosn f i(lnteor cfounnnceticotino nin ttoo P tihne O siFgSnTa)l . T I E A 2.9 path, whose −3 dB corner frequency is at G VOLTA 2.8 fHPF =(2πR1 C ) C INT HP (11) D 2.7 where: C is the external capacitance added from OFST to CNTR. 2.60 0.2 0.4 0.6 VDB0S.8 (V) 1.0 1.2 1.4 1.603217-056 RmIHNaPTx iims aunm in utnercneartl arienstiys toafn acbe oouf ta ±pp20ro%x.i m ately 480 Ω, having a Figure 55. Common-Mode Voltage at Input Pins vs. VDBS, for VS = 5 V, T = −40°C, + 25°C, and + 85°C This evaluates to 26 330µ f = 24 HPF C Hz)22 VDBS = 0.5V HP (CHP in μF) (12) V/√20 A small amount of peaking at this corner when using small n NOISE (1186 VDBS = 0.6V cUaspeafucilt ocor mvabliuneast icoanns b aer ea vCoHiPd e=d 3 b nyF a, dRdHiPn =g a1 8s0e rΩie,s f r =es 1is0t0o rk. Hz; D C = 33 nF, R = 10 Ω, f = 10 kHz; C = 0.33 μF, R = 0 Ω, RE14 HP HP HP HP FER12 VDBS = 0.75V f = 1 kHz; CHP = 3.3 μF, RHP = 0 Ω, f = 100 Hz. E R The offset compensation feature can be disabled simply by T 10 U P grounding the OFST pin. This provides a dc-coupled signal N 8 I 6 SIMULATION VDBS = 1.5V path, with no other effects on the overall ac response. Input offsets must be externally nulled in this mode of operation, as 40 0.4 0C.8OMM1.O2N-1M.6ODE2.V0OL2T.A4GE2A.8T IN3H.2I,IN3L.6O (4V.)0 4.4 4.8 03217-057 shown in Figure 58. Effects of Loading on Gain and AC Response Figure 56. Input Noise vs. Common-Mode Input Voltage for VDBS = 0.5 V, 0.6 V, 0.75 V, and 1.5 V The differential output impedance (RO) is 150 Ω, and the fre- Output Noise and Peak Swing quency response of the output stage is optimized for operation with a certain load capacitance on each output pin (OPHI and The output noise of the AD8330 is the input noise multiplied by OPLO) to ground, in combination with a load resistance (R) the overall gain, including any optional change to the voltage, L directly across these pins. In the absence of these capacitances, V , applied to Pin VMAG. The peak output swing is also MAG there is a small amount of peaking at the top extremity of the ac proportional to this voltage, which, at low gains and high values response. Suitable combinations are: R = ∞, C = 12 pF; R = of V , affects the output noise. L L L MAG 150 Ω, C = 25 pF; R = 75 Ω, C = 40 pF; or R = 50 Ω, C = 50 pF. L L L L L The scaling for V = 0 V is as follows: DBS The gain calibration is specified for an open-circuited load, VOUT_PK = ±4 VMAG (8) such as the high input resistance of an ADC. When resistively V = (85 + 70 V ) nV/√Hz (9) loaded, all gain values are nominally lowered as follows: NOISE_OUT MAG G R G = (UNLOADED L) LOADED 150Ω+RL (13) Rev. H | Page 20 of 32

Data Sheet AD8330 Thus, when R = 150 Ω, the gain is reduced by 6 dB; for R = 75 Ω, the output stage where decoupling can be useful in maintaining L L the reduction is 9.5 dB; and for R = 50 Ω, it is 12 dB. a glitch-free output. Figure 57 shows the general case, where VPSI L Gain Errors Due to On-Chip Resistor Tolerances and VPSO are each provided with their own decoupling network, but this is not needed in all cases. In all cases where external resistors are used, keep in mind that all on-chip resistances, including the R and the input resistance O VS 2.7V TO 6V (R), are subject to variances of up to ±20%. I RD1 CHPF CD2 RD2 These variances need to be accounted for when calculating the gain with input and output loading. This sensitivity can be avoided by adjusting the source and load resistances to bear an inverse CD1 ENBL OFST VPOS CNTR CD3 relationship as follows: VPSI BIAS AND CM MODE AND VPSO V-REF OFFSET CONTROL If R = αR, then make R = R /α; or, S I L O if R = αR , then make R = R/α L O S I The simplest case is when R = 1 kΩ and R = 150 Ω, therefore, INHI OPHI S L the gain is 12 dB lower than the basic value. The reduction of INPUT, OUTPUT OUTPUT, peak swing at the load can be corrected by using V = 1 V, 0V TO±2V MAX VGA CORE STAGES ±2V MAX MAG thereby restoring 6 dB of gain; using VMAG = 2 V restores the full INLO OPLO basic gain and doubles the peak available output swing. Output (Input) Common-Mode Control The output voltages are nominally positioned at the midpoint of NC MODE GAIN INTERFACE COOUNTTPRUOTL CMOP the supply, VS/2, over the range 2.7 V < VS < 6 V, and this voltage VDBS CMGN COMM VMAG appears at Pin CNTR, which is not normally expected to be loaded (rgterhqoeuu isnrodeu acr acsnem rlaeolslw icsehtraa ntnhcgiees iivnso ~tlht4ai sgk evΩ,o )wlt. ahHgeeor,ew aanesvd ae a rr ,er sesosisimsttoeor r ct fiorr octumhme CssuNtapTnpRclye ts o BVDABSSI:C 0 GVA TION B1.I5AVS NCGROUND 03217-058 raises it. On the other hand, this pin can be driven by an external Figure 57. Power Supply Decoupling and Basic Connections voltage source to set the common-mode level to satisfy, for Because of the differential nature of the signal path, power example, the needs of a following ADC. Any value from 0.5 V supply decoupling is, in general, much less critical than in a above ground to 0.5 V below the supply is permissible. Of course, single-sided amplifier; and where the minimization of board- when using an extreme common-mode level, the available level components is especially crucial, it is possible that these output swing is limited, and it is recommended that a value equal pins need no decoupling at all. On the other hand, when the or close to the default of VCNTR = VS/2 be used. There may be a signal source is single-sided, giving extra attention to the few millivolts of offset between the applied voltage and the decoupling on Pin VPSI is sometimes required. Likewise, care is actual common-mode level at the output pins. required in decoupling the VPSO pin if the output is loaded on only one of its two output pins. The general common (COMM) The input common-mode voltage, V , at Pin INHI and CMI and the output stage common (CMOP) are usually grounded as Pin INLO is slaved to the output. It bears a y = mx + b linear shown in the Figure 57; however, the Applications Information and offset relationship to V as shown in Equation 14 where CNTR section shows how a negative supply can optionally be used. y = V , m = 0.757, x = V , and b = 1.12 V for V = 0.75 V CMI CNTR DBS and T = 25°C. The AD8330 is enabled by taking the ENBL pin to a logical high (or, in all cases, the supply). The UP gain mode is enabled either V = 0.757 V + 1.12 V (14) CMI CNTR by leaving the MODE pin unconnected or taking it to a logical The effects of V and ambient temperature on V are shown DBS CMI high. When the opposite gain direction is needed, ground the in Figure 55. Thus, the default value for V for V = 0.75V, CMI DBS MODE pin or drive it to a logical low. The CHPF capacitor T = 25°C and V = 5 V is 3.01 V. S determines the low-pass corner of the offset loop; this is USING THE AD8330 preferably tied to the CNTR pin that in turn, must be decoupled to ground. The gain interface common pin (CMGN) is This section describes a few general aspects of using the AD8330. grounded, and the output magnitude control pin (VMAG) is Applying the AD8330 to a wide variety of circumstances requires left unconnected, or can optionally be connected to a 500 mV very few precautions. source for basic gain calibration. As in all high frequency circuits, careful observation of the ground Connections to the input and output pins are not shown in Figure 57 nodes associated with each function is important. Three positive because of the many options that are available. When the AD8330 is supply pins are provided: VPSI supports the input circuitry that used to drive an ADC, connect the OPHI and OPLO pins directly often operates at a relatively high sensitivity; VPOS supports to the differential inputs of a suitable converter, such as an AD9214. general bias sources and needs no decoupling; and VPSO biases Rev. H | Page 21 of 32

AD8330 Data Sheet If an adjustment is needed to this common-mode level, it can be DC-Coupled Signal Path introduced by applying that voltage to the CNTR pin, or, more In many cases, where the VGA is not required to provide its simply, by using a resistor from this pin to either ground or the lowest noise, the full common-mode input range of zero to V S supply (see the Applications Information section). The CNTR pin can be used without problems, avoiding the need for any ac can also supply the common-mode voltage to an ADC that coupling means. However, such direct coupling at both the input supports such a feature. and output does not automatically result in a fully dc-coupled When the loads to be driven introduce a dc resistive path to signal path. The internal offset compensation loop must also be ground, coupling capacitors must be used. These must be of disengaged by connecting the OFST pin to ground. Note that at sufficient value to pass the lowest frequency components of the the maximum basic gain of 50 dB (×316), every millivolt of offset at signal without excessive attenuation. Keep in mind that the voltage the input, arising from whatever source, causes an output offset of swing on such loads alternates both above and below ground, 316 mV, which is an appreciable fraction of the peak output swing. requiring that the subsequent component must be able to cope Because the offset correction loop is placed after the front-end with negative signal excursions. variable gain sections of the AD8330, the most effective way of Gain and Swing Adjustments When Loaded dealing with such offsets is at the input pins, as shown in Figure 58. For example, assume, for illustrative purposes, that the resistances The output can also be coupled to a load via a transformer to associated with each side of the source in a certain application achieve a higher load power by impedance transformation. For are 50 Ω. If this source has a very low (op amp) output impedance, example, using a 2:1 turns ratio, a 50 Ω final load presents a 200 Ω insert the extra resistors, with a negligible noise penalty and an load on the output. The gain loss (relative to the basic value with no attenuation of only 0.83 dB. The resistor values shown provide a termination) is 20 log10{(200+150)/200} or 4.86 dB, which can trim range of about ±2 mV. be restored by raising the voltage on the VMAG pin by a factor of 104.86/20 or × 1.75, from its basic value of 0.5 V to 0.875 V. This Using Single-Sided Sources and Loads also restores the peak swing at the 200 Ω level to ±2 V, or ±1 V Where the source provides a single-sided output, either INHI or into the 50 Ω final load. INLO can be used for the input, with a polarity change when using Whenever a stable supply voltage is available, additional voltage INLO. The unused pin must be connected either through a capacitor swing can be provided by adding a resistor from the VMAG pin to ground, or through a dc bias point that corresponds closely to to the supply. The calculation is based on knowing that the internal the dc level on the active signal pin. The input CMRR over the bias is delivered via a 5 kΩ source; because an additional 0.375 V is full frequency range is illustrated in Figure 59. In some cases, an needed, the current in this external resistor must be 0.375 V/ additional element such as a SAW filter (having a single-sided 5 kΩ = 75 μA. Thus, using a 5 V supply, a resistor of 5 V − 0.875 V/ balanced configuration) or a flux-coupled transformer can be 75 μA = 55 kΩ is used. Based on this example, the corrections interposed. Where this element must be terminated in the correct for other load conditions are easy to calculate. If the effects on impedance, other than 1 kΩ, it is necessary to add either shunt gain and peak output swing due to supply variations cannot be or series resistors at this interface. tolerated, VMAG must be driven by an accurate voltage. VS 2.7V TO 6V Input Coupling RD1 CD2 RD2 The dc common-mode voltage at the input pins varies with the supply, the basic gain bias, and temperature (see Figure 55); for ENBL OFST VPOS CNTR CD1 CD3 this reason, many applications need to use coupling capacitors from the source that are large enough to support the lowest VPSI BIAS AND CM MODE AND VPSO V-REF OFFSET CONTROL frequencies to be transmitted. Using one capacitor at each input pin, their minimum values can be readily found from the expression INHI OPHI CIN_CPL= (320 µF/fHPF) (15) TROS ABSES 5U0MΩED 50kΩ OUTPUT OUTPUT, where f is the –3dB frequency expressed in hertz. Thus, for ON EACH VGA CORE STAGES ±2VMAX HPF SIDE an f of 10 kHz, 33 nF capacitors are used. HPF INLO OPLO 75kΩ Occasionally, it is possible to avoid the use of coupling capacitors when the dc level of the driving source is within a certain range, as shown in Figure 56. This range extends from 3.5 V to 4.5 V when MODE GAIN INTERFACE COOUNTTPRUOTL CMOP using a 5 V supply, and at high basic gains, where the effect of an VDBS CMGN COMM VMAG incorrect dc level degrades the noise level due to internal aspects of the input stage. For example, suppose the driver, IC, is an LNA BASIC GAIN BIAS NC htoa vtihneg saunp poulyt,p auntd t othpeo loougtyp uint iws hbiucfhf eirtse dlo bayd ermesiitstteorr sfo alrloew taekrse.n VDBS: 0V TO 1.5V GROUND 03217-059 This presents a source for the AD8330 that can be directly coupled. Figure 58. Input Offset Nulling in a DC-Coupled System Rev. H | Page 22 of 32

Data Sheet AD8330 90 In Case 3 and Case 4, a further factor of ×1.33 is needed to make VDBS = 1.5V OFST:ENABLED 80 VDBS = 0.75V DISABLED up the 2.5 dB loss, that is, raise VMAG to 2 V. With the restoration 70 of gain, the peak output swing at the load is, likewise restored to ±2 V. 60 Pulse Operation B) 50 R (d 40 VDBS = 0V When using the AD8330 in applications where its transient R M response is of greater interest and the outputs are conveyed to C 30 their loads via coaxial cables, the added capacitances can slightly 20 differ in value, and can be placed either at the sending or load 10 end of the cables, or divided between these nodes. Figure 61 0 shows an illustrative example where dual, 1 meter, 75 Ω cables –1050k 100k F1RMEQUENCY (Hz) 10M 100M 03217-060 aterrem dirnivaetend t hatr oguroguhn ddc -lebvloecl.k ing capacitors and are independently Figure 59. Input CMRR vs. Frequency for Various Values of VDBS Because of the considerable variation between applications, only 30 general recommendations can be made with regard to minimizing LINE 1 20 pulse overshoot and droop. The former can be optimized by LINE 3 B) 10 adding small load capacitances, if necessary; the latter requires d N ( 0 the use of sufficiently large capacitors (C1). AI LINE 4 G –10 Figure 62 shows typical results for V = 0.24 V, a square wave DBS –20 LINE 2 input amplitude of 450 mV (the actual combination is not –30 0 LINE 2 important), a rise time of 2 ns, and VMAG raised to 2.0 V. In the es)–100 LINE 3 upper waveforms, the load capacitors are both zero, and a small gre–200 amount of overshoot is visible; with 40 pF, the response is cleaner. e LINE 4 E (D–300 A shunt capacitance of 20 pF from OPHI to OPLO has a similar AS–400 LINE 1 effect. Coupling capacitors for this demonstration are sufficiently H P–500 large to prevent any visible droop over this time scale. The outputs –6001M 10FMREQUENCY (Hz) 100M 500M 03217-061 ante tghaeti vloea adn sdi dpeo esivteivnetu eaxlclyu rassisounms ed eap menedanin vga olune t hofe zdeuroty, wcyitchle . Figure 60. AC Gain and Phase for Various Loading Conditions VS 2.7V–6V When driving a single-sided load, either OPHI or OPLO can be CD2 RD2 used. These outputs are very symmetric, so the only effect of this choice is to select the desired polarity. However, when the ENBL OFST VPOS CNTR frequency range of interest extends to the upper limits of the CD3 AD8330, attach a dummy resistor of the same value to the VPSI BIAS AND CM MODE AND VPSO V-REF OFFSET CONTROL unused output. Figure 60 illustrates the ac gain and phase RL1 response for various loads and VDBS = 0.75 V. Line 1 shows the C1 INHI OPHI unloaded (C = 12 pF) case for reference; the gain is 6 dB lower L CL1 (20 dB) using only the single-sided output. Adding a 75 Ω load VGA CORE OSTUATGPUEST from OPHI to an ac ground results in Line 2. The gain becomes C1 a factor of ×1.5 V or 3.54 dB lower, but artifacts of the output INLO OPLO CL2 RL2 common-mode control loop appear in both the magnitude and phase response. MODE GAIN INTERFACE COOUNTTPRUOTLCMOP Adding a dummy 75 Ω to OPLO results in Line 3: the gain is a VDBS CMGN COMM VMAG further 2.5 dB lower, at about 14 dB. The CM artifacts are no longer present but a small amount of peaking occurs. If objectionable, this NC coauntp buet epliinms itnoa t2e5d p bFy, aras isshinogw bno itnh Loifn teh e4 coaf pFaicgiutorer s6 o0n. the 03217-062 Figure 61. Driving Dual Cables with Grounded Loads The gain reduction incurred both by using only one output and by the additional effect of loading can be overcome by taking advantage of the VMAG feature, provided primarily for just such circumstances. Thus, to restore the basic gain in the first case (Line 1), apply a 1 V source to this pin; to restore the gain in the second case, this voltage must be raised by a factor of ×1.5 to 1.5 V. Rev. H | Page 23 of 32

AD8330 Data Sheet 11..02 Table 5. Preserving Absolute Gain 0.8 000...462 Uncorrected Loss VMAG Required to –0.20 RS (Ω) RL (Ω) Factor dB Correct Loss 0.2 0 10 15 k 0.980 0.17 0.510 –0.2 ––00..46 15 10 k 0.971 0.26 0.515 –0.8 –1.0 20 7.5 k 0.961 0.34 0.520 –1.2 1.2 1.0 30 5.0 k 0.943 0.51 0.530 0.8 00..64 50 3.0 k 0.907 0.85 0.551 0.2 0 75 2.0 k 0.865 1.26 0.578 –0.2 0.2 0 100 1.5 k 0.826 1.66 0.605 –0.2 –0.4 150 1.0 k 0.756 2.43 0.661 –0.6 –––011...8020 5ns 10ns 15ns 20ns 25ns 03217-063 230000 755000 00..659942 34..1576 00..782405 Figure 62. Typical Pulse Response for Figure 61 500 300 0.444 7.04 1.125 The bandwidth from Pin VMAG to these outputs is somewhat 750 200 0.327 9.72 1.531 higher than from the normal input pins. Thus, when this pin is 1 k 150 0.250 12.0 2.000 used to rapidly modulate the primary signal, some further 1.5 k 100 0.160 15.9 3.125 experimentation with response optimization may be required. 2 k 75 0.111 19.1 4.500 In general, the AD8330 is very tolerant of a wide range of loading conditions. Calculation of Noise Figure Preserving Absolute Gain The AD8330 noise is a consequence of its intrinsic voltage noise spectral density (E ) and the current noise spectral density (I ). Although the AD8330 is not laser trimmed, its absolute gain NSD NSD Their combined effect generates a net input noise, V , that calibration, based mainly on ratios, is very good. Full details are NOISE_IN is a function of the input resistance of the device (R), nominally found in the Specifications section and in the typical performance I 1 kΩ, and the differential source resistance (R) as follows: curves (see the Typical Performance Characteristics section). S Nevertheless, having finite input and output impedances, the V = {E 2+I 2(R +R )2} (16) NOISE_IN NSD NSD I S gain is necessarily dependent on the source and load conditions. The loss that is incurred when either of these is finite causes an Note that purely resistive source and input impedances as a conces- error in the absolute gain. The absolute gain can also be sion to simplicity is assumed. A more thorough treatment of uncertain due to the approximately ±20% tolerance in the noise mechanisms, for the case where the source is reactive, is absolute value of the input and output impedances. beyond the scope of these brief notes. Also note that VNOISE_IN is the voltage noise spectral density appearing across INHI and Often, such losses and uncertainties can be tolerated and INLO, the differential input pins. In preparing for the calculation accommodated by a correction to the gain control bias. On the of the noise figure, V is defined as the open-circuit signal SIG other hand, the error in the loss can be essentially nulled by voltage across the source, and V is defined as the differential IN using appropriate modifications to either the source impedance input to the AD8330. The relationship is simply (R) or the load impedance (R), or both (in some cases by S L padding them with series or shunt components). VIN =(RVSI+GRRI ) (17) The formulation for this correction technique was previously I S described. However, to simplify its use, Table 5 shows spot At maximum gain, E is 4.1 nV/√Hz, and I is 3 pA/√Hz. NSD NSD values for combinations of RS and RL resulting in an overall loss Thus, the short-circuit voltage noise is that is not dependent on sample-to-sample variations in on chip resistances. Furthermore, this fixed and predictable loss can be V = {(4.1nV/ Hz)2+(3pA/ Hz)2(1kΩ+0)2}= NOISE_IN corrected by an adjustment to V , as indicated in Table 5. MAG 5.08 nV/√Hz (18) Next, examine the net noise when R = R = 1 kΩ, often incor- S I rectly called the matching condition, rather than source impedance termination, which is the actual situation in this case. Repeating the procedure, V = (4.1nV/ Hz)2 +(3pA/ Hz)2(1kΩ+1kΩ)2 NOISE_IN = 7.3 nV/√Hz (19) Rev. H | Page 24 of 32

Data Sheet AD8330 The noise figure is the decibel representation of the noise factor, N , commonly defined as follows: FAC In practice, however, the effect of device mismatches and junc- SNRatInput tion resistances in the core cell, and other mechanisms in its N = FAC SNRatOutput supporting circuitry inevitably cause distortion, further aggravated (20) by other effects in the later output stages. Some of these effects However, this is equivalent to are very consistent from one sample to the next, while those due to mismatches (causing predominantly even-order distortion SNRattheSource N = components) are quite variable. Where the highest linearity FAC SNRattheInputPins (21) (and lowest noise) is demanded, consider using one of the X- AMP products such as the AD603 (single-channel), AD604 Let V be the voltage noise spectral density √kTRS due to the NSD (dual-channel), or AD8332 (wideband dual-channel with source resistance. Using Equation 17 gives ultralow noise LNAs). { ( )} V R /R +R /V NFAC =V S/IG{V I I R S/(R +NRSD )} P1dB and V1dB IN NOISE_IN S I S In addition to the nonlinearities that arise within the core of the RV = I NOISE_IN AD8330, at moderate output levels, another metric that is more R V S NSD commonly stated for RF components that deliver appreciable power to a load is the 1 dB compression point. This is defined (22) in a very specific manner: it is that point at which, with increasing Then, using the result from Equation 19 for a source resistance output level, the power delivered to the load eventually falls to a of 1 kΩ, having a noise-spectral density of 4.08 nV/√Hz produces value that is 1 dB lower than it would be for a perfectly linear ( )( ) system. (Although this metric is sometimes called the 1 dB gain 1kΩ 7.3nV/ Hz N = ( )( )=1.79 compression point, it is important to note that this is not the FAC 1kΩ 4.08nV/ Hz (23) output level at which the incremental gain has fallen by 1 dB). Finally, converting this to decibels using As shown in Figure 49, the output of the AD8330 limits quite abruptly, and the gain drops sharply above the clipping level. NFIG = 10 log10(NFAC) (24) The output power, on the other hand, using an external resistive Thus, the resultant noise figure in this example is 5.06 dB, load, R , continues to increase. In the most extreme case, the L which is somewhat lower than the value shown in Figure 53 for waveform changes from the sinusoidal form of the test signal, this operating condition. with an amplitude just below the clipping level, V , to a CLIP Noise as a Function of VDBS square wave of precisely the same amplitude. The change in The chief consequence of lowering the basic gain using VDBS is power over this range is from (VCLIP/√2)2/RL to (VCLIP)2/RL, that that the current noise spectral density I increases with the is, a factor of 2, or 3 dB in power terms. It can be shown that for NSD square root of the basic gain magnitude, G such that an ideal limiting amplifier, the 1 dB compression point occurs BN for an overdrive factor of 2 dB. I = (3 pA/√Hz)(√G ) (25) NSD BN For example, if the AD8330 is driving a 150 Ω load and V is MAG Therefore, at the minimum basic gain of ×0, I rises to NSD set to 2 V, the peak output is nominally ±4 V (as noted previously, 53.3 pA/√Hz. However, the noise figure rises to 17.2 db if it the actual value, when loaded. can differ because of a mismatch is recalculated using the procedures in Equation 16 through between on-chip and external resistors), or 2.83 V rms for a sine Equation 24. wave output that corresponds to a power of 53.3 mW, that is, Distortion Considerations 17.3 dBm in 150 Ω. Thus, the P1dB level, at 2 dB above Continuously variable gain amplifiers invariably employ clipping, is 19.3 dBm. nonlinear circuit elements; consequently, it is common for their Though not involving power transfer, it is sometimes useful distortion to be higher than well-designed fixed gain amplifiers. to state the V1dB, which is the output voltage (unloaded or The translinear multiplier principles used in the AD8330, in loaded) that is 2 dB above clipping for a sine waveform. In the theory, yield extremely low distortion, a result of the funda- above example, this voltage is still 2.83 V rms, which can be mental linearization technique that is an inherent aspect of expressed as 9.04 dBV (0 dBV corresponds to a 1 V sine wave). these circuits. Thus, the V1dB is at 11.04 dBV. Rev. H | Page 25 of 32

AD8330 Data Sheet APPLICATIONS INFORMATION The versatility of the AD8330, its very constant ac response over from VMAG to ground. An overrange condition is signaled by a a wide range of gains, the large signal dynamic range, output high state on Pin OR of the AD9214. DFS/GAIN is unconnected swing, single supply operation, and low power consumption in this example producing an offset-binary output. To provide a commend this VGA to a diverse variety of applications. Only a twos complement output, connect it to the REF pin. few can be described here, including the most basic uses and some For ADCs running at sampling rates substantially below the unusual ones. bandwidth of the AD8330, an intervening noise filter is ADC DRIVING recommended to limit the noise bandwidth. A one-pole filter can easily be created with a single differential capacitor between The AD8330 is well-suited to drive a high speed converter. the OPHI and OPLO outputs. For a corner frequency of f , the There are many high speed converters available, but to illustrate C capacitor must have a value of the general features, the example in this data sheet uses one of the least expensive, the AD9214. This is available in three CFILT = 1/942 fC (26) grades for operation at 65 MHz, 80 MHz, and 105 MHz; the For example, a 10 MHz corner requires about 100 pF. AD9214BRSZ-80 is a good complement to the general SIMPLE AGC AMPLIFIER capabilities of this VGA. Figure 64 illustrates the use of the inverted gain mode and the Figure 63 shows the connections to drive an ADC. A 3.3 V offset gain range (0.2 V < V < 1.7 V) in supporting a low cost supply is used for both parts. The ADC requires that its input DBS AGC loop. Q1 is used as a detector. When OPHI is sufficiently pins be positioned at one third of the supply, or 1.1 V. Given higher than CNTR, due to the signal swing, it conducts and that the default output level of the VGA is one-half the supply charges C1. This raises V and rapidly lowers the gain. Note or 1.65 V, a small correction is introduced by the 8 kΩ resistor DBS that MODE is grounded (see Figure 48). The minimum voltage from CNTR to ground. The ADC specifications require that the needed across R1 to set up the full gain is 0.2 V because CMGN common-mode input be within ±0.2 V of the nominal 1.1 V; is dc open-circuited (this does not alter V ) and the maximum variations of up to ±20% in the AD8330 on-chip resistors change MAG voltage is 1.7 V. this voltage by only ±70 mV. With the connections shown in Figure 63, the AD9214 is able to receive an input of 2 V p-p; the peak output of the AD8330 can be reduced if desired by adding a resistor VS,3.3V 3.3Ω 3.3Ω 0.1µF 0.1µF OVER- 8kΩ RANGE CHPF 0.1µF 10Ω ENBL OFST VPOS CNTR OR VPSI BIAS AND CM MODE AND VPSO AVDD DrVDDD9 V-REF OFFSET CONTROL PWRDN 0.1µF D8 DFS/GAIN D7 S INHI OPHI AIN D6 UT P I±N2PVU MTA,X VGA CORE OSTUATGPUEST AD9214BRS-80 DD45 A OUT T INLO OPLO AIN D3 DA REFSENSE D2 D1 REF NC MODE GAIN INTERFACE COOUNTTPRUOTL CMOP D0 AGND DGND VDBS CMGN COMM VMAG CLK 0.1µF NC GAIN BIAS, CLOCK VDBS,0V–1.5V ANALOG GROUND GDRIGOIUTANLD 03217-064 Figure 63. Driving an Analog-to-Digital Converter (Preliminary) Rev. H | Page 26 of 32

Data Sheet AD8330 VS,2.7V–6V This simple detector exhibits a temperature variation in the 33nF differential output amplitude of about 4 mV/°C. It provides a fast attack time (an increase in the input is quickly leveled to the 10Ω ENBL OFST VPOS CNTR 4.7Ω nominal output, due to the high peak currents in Q1) and a VPSI BIAS AND CM MODE AND VPSO 0.1µF slow release time (a decrease in the input is not restored as V-REF OFFSET CONTROL 0.1µF quickly). The voltage at the VDBS pin can be used as an RSSI output, scaled 30 mV/dB. Note that the attack time can be INHI OPHI halved by adding a second transistor, labeled Q2 in Figure 64. I5NmPVU TT,O 1V rms VGA CORE OSTUATGPUEST STEEXET O~1UVT rPmUsT, For operation at lower frequencies, the AGC hold capacitor INLO OPLO must be increased. WIDE RANGE TRUE RMS VOLTMETER MODE GAIN INTERFACE COOUNTTPRUOTLCMOP Q2 Q1 The AD8362 is an rms responding detector providing a dynamic VDBS CMGN COMM VMAG range of 60 dB from low frequencies to 2.7 GHz. This can increase 0.1µF NC to 110 dB using an AD8330 as a preconditioner, provided the 10RkΩ1 0.1µF 0.1Cµ1F 03217-065 pnaosisse f ibltaenr.d width is limited by an interstage low-pass or band- Figure 64. Simple AGC Amplifier (Preliminary) The VGA also provides an input port that is easier to drive than When the loop is settled, the average current in Q1 is VDBS/R1, the 200 Ω input of the AD8362. Figure 67 shows the general which varies from 20 µA at maximum gain (VDBS = 0.2 V) to scheme. 170 µA at minimum gain (V = 1.7 V). This change in the Q1 DBS Both the AD8330 and AD8362 provide linear-in-decibel control current causes an increase of ~0.25 dB over the full gain range interfaces. Thus, when the output of the AD8362 is used to control in the differential output of nominally 0.75 dBV at midrange the gain of the AD8330, the functional form is unaffected. The (3.08 V p-p), corresponding to a 200:1 compression ratio. This overall scaling is 33 mV/dB. Figure 68 shows the time domain is plotted in Figure 65 for a representative 100 kHz input. response using a loop filter capacitor of 10 nF, for inputs ranging 1.0 from 10 μV to 1 V rms, that is, a 100 dB measurement range. 1.75 0.9 1.50 VDBS V) 1.25 dB 1.00 UT ( 0.8 0.75 TP B)0.50 U d LEVELED O 0.7 AIN ERROR (0.25032 0.6 G 1 0 –1 0.5–F5i0gure 65. A–G40C OutIpNuPtU– vT3s0.T IOn pAuDt8 3A3m–02 p(0dlBitVu)de (Si–m10ulation) 0 03217-066 –––4320 10 20 30 40 50 60TI7M0E (8µ0s)90 100 110O1U20TP1U30T140 150 03217-067 The upper panel in Figure 66 shows the time-domain output for Figure 66. Time Domain Waveforms (Simulation) fourteen 3 dB steps in input amplitude from 5.4 mV to 1.7 V. The waveforms in Figure 65 show the AGC voltage (V ). DBS Rev. H | Page 27 of 32

AD8330 Data Sheet 5V 3.3Ω 3.3Ω 3.3Ω 0.1µF 0.1µF 0.1µF AD8362 0.1µF 1 COMM ACOM 16 3.6V 10µF 2 CHPF VREF 15 ENBL OFST VPOS CNTR VPS1 VPSO 3 DECL VTGT 14 INHI OPHI 4 INHI VPOS 13 INPUT AD8330 CFLT 3.6V 18nF INLO OPLO 5 INLO VOUT 12 VOUT MODE CMOP 6 DECL VSET 11 0.1µF VDBS CMGN COMM VMAG 7 PWDN ACOM 10 10µF 8 COMM CLPF 9 6.04kΩ 4.02kΩ 03217-068 Figure 67. Wide Range True RMS Voltmeter (Preliminary) 4 3 V) T ( PU 2 T U O 1 00 0.4 0.8 1.2 1.6 2.0TIM2.E4 (m2s.8) 3.2 3.6 4.0 4.4 4.8 03217-069 Figure 68. Time Domain Response of RMS Voltmeter (Simulation) Rev. H | Page 28 of 32

Data Sheet AD8330 EVALUATION BOARD GENERAL DESCRIPTION BASIC OPERATION The AD8330-EVALZ is an easy-to-use accessory that enables a The input SMA connector IN is terminated with a 49.9 Ω hands-on evaluation of the AD8330 variable gain amplifier resistor (see Figure 70). For convenience, the board includes an (VGA). It includes test pins for connections to all of the functional AD8131 high speed differential amplifier to convert a single- device inputs. Figure 69 is a full size photograph of the board. ended signal source to the differential input of the AD8330. If desired, the AD8131 can be removed and the AD8330 can be driven at one of its inputs from a single-ended source. The AD8330 output is observed at the SMA connectors OUT_HI and OUT_LO or by using the 2-pin header OUT_HI/OUT_LO adjacent to the device. The AD8330 requires only a +5 V power supply; however, because of the AD8131 buffer bipolar power supply requirements, ±5 V supplies are required to power the board. The current required for the board is approximately 40 mA from the +5 V supply and 10 mA from the −5 V supply. 03217-070 Figure 69. Photograph of the AD8330 Evaluation Board FILTER_OFFSET C13 R3 GND1GND2GND3GND4 OFST FLTR 1nF 1kΩ 1 16 OFST VPOS +5V +5V R4 ENBL C12 0Ω 2 15 0.1µF C1 + ENBL CNTR CNTR 10µF C19 10V C2 0.1µF C14 0.1µF 3 14 +5V C15 10nF VPSI VPSO 0.1µF C11 C4 4 0.1µF 0.1µF R2 C3 13 IN 49.9Ω AD8131 8 3 4 0.1µF INHI OPHI C9 OUT_HI 2 DUT1 12pF 0.C1µ1F8 1 A1 5 IN_TEST AD8330 C8 OUT_TEST 24.9RΩ1 6 C5 5 INLO OPLO 12 12pF OUT_ LO 0.1µF UP C10 +5V 6 11 0.1µF GAIN_SLOPE MODE CMOP C16 10nF DOWN 7 10 –5V VDBS VDBS VMAG VMAG C6 C7 C17 C20 0.1µF 0.1µF + 1100µVF 0.1µF 8 CMGN COMM 9 CMGN 03217-071 Figure 70. Schematic Diagram Rev. H | Page 29 of 32

AD8330 Data Sheet OPTIONS MEASUREMENT SETUP Table 6 lists the jumpers on the board and their functions. The basic board connections for a typical measurement are shown in Figure 71. To minimize circuit-loading effects, a low Table 6. Functions of Jumpers capacitance FET probe is recommended for observing input or Name Function output waveforms. Two-pin headers, IN_TEST and OUT_TEST, FLTR Connects a high-pass filter to the offset control loop are provided for this purpose. The SMA connectors OUT_HI pin. This jumper is normally not installed. and OUT_LO can also be used, but the user may need to OFST Disables the offset correction loop. This jumper is account for load capacitance effects. installed for dc or low frequency operation. UP Mode up. Install for ascending gain with increasing AD8330-EVALZ BOARD DESIGN VDBS gain control voltage. The AD8330-EVALZ is a 4-layer design for maximum ground- DOWN Mode down. Install for descending gain with plane area. The evaluation board side silkscreen and wiring increasing VDBS gain control voltage. patterns are shown in Figure 72 through Figure 77. NETWORK ANALYZER PROBE POWER SUPPLY SIGNAL INPUT DIFFERENTIAL PROBE POWER SUPPLY +5V GND PRECISIO(FNO VRO VLDTBASG, EV MREAFGE)RENCES 03217-072 Figure 71. Typical Connections Rev. H | Page 30 of 32

Data Sheet AD8330 03217-073 03217-076 Figure 72. Component Side Silkscreen Figure 75. Wiring Side Silkscreen 03217-074 03217-077 Figure 73. Component Side Wiring Figure 76. Wiring Side Pattern 03217-075 03217-078 Figure 74. Ground Plane Figure 77. Inner Layer 2 Rev. H | Page 31 of 32

AD8330 OUTLINE DIMENSIONS 3.10 0.30 3.00 SQ 0.25 PIN 1 2.90 0.20 INDICATOR PIN 1 0.50 13 16 INDICATOR BSC 12 1 EXPOSED 1.65 PAD 1.50 SQ 1.45 9 4 0.50 8 5 0.20 MIN TOP VIEW 0.40 BOTTOM VIEW 0.30 0.80 FOR PROPER CONNECTION OF 0.75 0.05 MAX THE EXPOSED PAD, REFER TO 0.70 THE PIN CONFIGURATION AND 0.02 NOM FUNCTION DESCRIPTIONS COPLANARITY SECTION OF THIS DATA SHEET. SEATING 0.08 PLANE 0.20 REF COMPLIANTTOJEDEC STANDARDS MO-220-WEED-6. 01-26-2012-A Figure 78. 16-Lead Lead Frame Chip Scale Package [LFCSP] 3 mm × 3 mm Body and 0.75 mm Package Height (CP-16-27) Dimensions shown in millimeters 0.197 (5.00) 0.193 (4.90) 0.189 (4.80) 16 9 0.158 (4.01) 0.154 (3.91) 0.150 (3.81) 0.244 (6.20) 1 8 0.236 (5.99) 0.228 (5.79) 0.010 (0.25) 0.020 (0.51) 0.065 (1.65) 0.069 (1.75) 0.006 (0.15) 0.010 (0.25) 0.049 (1.25) 0.053 (1.35) 0.010 (0.25) CO0P.0L0A4 N(0A.1R0I)TY 0.02B5S (C0.64) 0.012 (0.30) SPLEAATNIENG 80°° 0.050 (1.27) 0R.E0F41 (1.04) 0.004 (0.10) 0.016 (0.41) 0.008 (0.20) COMPLIANTTO JEDEC STANDARDS MO-137-AB C(RINEOFNPEATRRREOENNLCLTEIHN EOGSN EDLSIYM)AEANNRDSEI AORRNOESU NANORDEET DAIN-PO IPFNRFCO HINPECRSHI;A METEQIL UFLIOIVMRAE LUTEESNRET DISNI M FDOEERNSSIGIONN.S 09-12-2014-A Figure 79. 16-Lead Shrink Small Outline Package [QSOP] (RQ-16) Dimensions shown in inches and (millimeters) ORDERING GUIDE Model1 Temperature Range Package Description Package Option Branding AD8330ACPZ-R2 −40°C to +85°C 16-Lead Lead Frame Chip Scale Package [LFCSP] CP-16-27 JFZ AD8330ACPZ-RL −40°C to +85°C 16-Lead Lead Frame Chip Scale Package [LFCSP] CP-16-27 JFZ AD8330ACPZ-R7 −40°C to +85°C 16-Lead Lead Frame Chip Scale Package [LFCSP] CP-16-27 JFZ AD8330ARQZ −40°C to +85°C 16-Lead Shrink Small Outline Package [QSOP] RQ-16 AD8330ARQZ-RL −40°C to +85°C 16-Lead Shrink Small Outline Package [QSOP] RQ-16 AD8330ARQZ-R7 −40°C to +85°C 16-Lead Shrink Small Outline Package [QSOP] RQ-16 AD8330-EVALZ Evaluation Board 1 Z = RoHS Compliant Part. ©2002–2016 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D03217-0-5/16(H) Rev. H | Page 32 of 32

Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: A nalog Devices Inc.: AD8330ARQZ AD8330-EVALZ AD8330ACPZ-R2 AD8330ACPZ-R7 AD8330ACPZ-RL AD8330ARQZ-R7 AD8330ARQZ-RL