1 MHz to 8 GHz, 70 dB Logarithmic Detector/Controller Data Sheet AD8318 FEATURES FUNCTIONAL BLOCK DIAGRAM Wide bandwidth: 1 MHz to 8 GHz VPSI ENBL TADJ VPSO High accuracy: ±1.0 dB over 55 dB range (f < 5.8 GHz) Stability over temperature: ±0.5 dB TEMP SETNEMSOPR GBIAAISN SLOPE I V VSET Low noise measurement/controller output (VOUT) Pulse response time: 10 ns/12 ns (fall/rise) I V VOUT Integrated temperature sensor DET DET DET DET CLPF Small footprint LFCSP INHI Power-down feature: <1.5 mW at 5 V INLO SFainbgrileca-stuedp pulsyi nogp ehriagthio snp:e 5e dV SaitG 6e8 p mroAc ess CMIP CMOP 04853-001 Figure 1. APPLICATIONS RF transmitter PA setpoint control and level monitoring RSSI measurement in base stations, WLAN, WiMAX, and radars GENERAL DESCRIPTION The AD8318 is a demodulating logarithmic amplifier, capable a decreasing linear-in-dB function of the RF input signal of accurately converting an RF input signal to a corresponding amplitude. decibel-scaled output voltage. It employs the progressive The logarithmic slope is nominally −25 mV/dB but can be compression technique over a cascaded amplifier chain, each adjusted by scaling the feedback voltage from VOUT to the stage of which is equipped with a detector cell. The device is VSET interface. The intercept is 20 dBm (referenced to 50 Ω, used in measurement or controller mode. The AD8318 maintains CW input) using the INHI input. These parameters are very accurate log conformance for signals of 1 MHz to 6 GHz and stable against supply and temperature variations. provides useful operation to 8 GHz. The input range is typically The AD8318 is fabricated on a SiGe bipolar IC process and is 60 dB (referenced to 50 Ω) with error less than ±1 dB. The available in a 4 mm × 4 mm, 16-lead LFCSP for the operating AD8318 has a 10 ns response time that enables RF burst temperature range of –40oC to +85oC. detection to beyond 45 MHz. The device provides unprecedented logarithmic intercept stability vs. ambient temperature conditions. 2.4 6 A 2 mV/°C slope temperature sensor output is also provided for 2.2 5 additional system monitoring. A single supply of 5 V is required. 2.0 4 1.8 3 Current consumption is typically 68 mA. Power consumption 1.6 2 decreases to <1.5 mW when the device is disabled. The AD8318 can be configured to provide a control voltage (V)UT 11..42 10 OR (dB) to a VGA, such as a power amplifier or a measurement output, VO 1.0 –1 RR E from Pin VOUT. Because the output can be used for controller 0.8 –2 applications, wideband noise is minimal. 0.6 –3 0.4 –4 In this mode, the setpoint control voltage is applied to VSET. 0.2 –5 The feedback loop through an RF amplifier is closed via VOUT, 0 –6 tchoer roeustppount doifn wgh tioc hV rSeEgTu.l aTtehse t hAeD a8m3p1l8if iperro ovuidtpeust 0 t oV a tmo a4g.9n iVtu de –65–60–55–50–45–40–35P–IN3 0(d–B2m5)–20–15–10 –5 0 5 10 04853-052 output capability at the VOUT pin, suitable for controller Figure 2. Typical Logarithmic Response and Error vs. Input Amplitude at 5.8 GHz applications. As a measurement device, Pin VOUT is externally connected to VSET to produce an output voltage, V which is OUT, Rev. D Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Tel: 781.329.4700 ©2004–2017 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com

AD8318 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Temperature Compensation of Output Voltage ..................... 13 Applications ....................................................................................... 1 Temperature Sensor ................................................................... 14 Functional Block Diagram .............................................................. 1 Measurement Mode ................................................................... 14 General Description ......................................................................... 1 Device Calibration and Error Calculation .............................. 15 Revision History ............................................................................... 2 Selecting Calibration Points to Improve Accuracy over a Specifications ..................................................................................... 3 Reduced Range ........................................................................... 16 Absolute Maximum Ratings ............................................................ 6 Variation in Temperature Drift from Device to Device ........ 17 ESD Caution .................................................................................. 6 Temperature Drift at Different Temperatures ........................ 17 Pin Configuration and Function Descriptions ............................. 7 Setting the Output Slope in Measurement Mode .................. 17 Typical Performance Characteristics ............................................. 8 Response Time Capability ......................................................... 18 Theory of Operation ...................................................................... 11 Output Filtering .......................................................................... 18 Using the AD8318 .......................................................................... 12 Controller Mode ......................................................................... 19 Basic Connections ...................................................................... 12 Characterization Setup and Methods ...................................... 21 Enable Interface .......................................................................... 12 Evaluation Board ............................................................................ 22 Input Signal Coupling ................................................................ 12 Outline Dimensions ....................................................................... 24 Output Interface ......................................................................... 13 Ordering Guide .......................................................................... 24 Setpoint Interface ....................................................................... 13 REVISION HISTORY 12/2017—Rev. C to Rev. D Changes to Table 1 ............................................................................. 3 Updated Outline Dimensions ....................................................... 24 Changes to Figure 5, Figure 6, and Figure 7 Captions .................. 8 Changes to Ordering Guide .......................................................... 24 Changes to Figure 12 Caption ......................................................... 9 Changes to Figure 15 Caption ......................................................... 9 8/2017—Rev. B to Rev. C Changed General Description Heading to Theory of Change to Figure 3 ........................................................................... 7 Operation ......................................................................................... 11 Updated Outline Dimensions ...................................................... 24 Changes to Enable Interface Section............................................ 12 Changes to Ordering Guide .......................................................... 24 Inserted Figure 24 ........................................................................... 12 Changes to Input Signal Coupling Section ................................. 12 4/2007—Rev. A to Rev. B Changes to Measurement Mode Section ..................................... 14 Added Figure 2; Renumbered Sequentially .................................. 1 Changes to Figure 36 ...................................................................... 17 Changes to Table 1 ............................................................................ 3 Added Output Filtering Section ................................................... 19 Changes to Figure 23 ...................................................................... 12 Changes to Controller Mode Section .......................................... 19 Changes to Characterization Setup and Methods Section ........ 21 Changes to Response Time Capability Section .......................... 18 Changes to Figure 48 ...................................................................... 23 Changes to Table 6 .......................................................................... 22 Updated Outline Dimensions ....................................................... 24 Changes to Figure 47, Figure 48, and Figure 49 ......................... 23 Changes to Ordering Guide .......................................................... 24 Updated Outline Dimensions ....................................................... 24 Changes to Ordering Guide .......................................................... 24 1/2006—Rev. 0 to Rev. A Changed TADJ Resistor to R Resistor ........................ Universal 7/2004—Rev. 0: Initial Version TADJ Changes to Applications .................................................................. 1 Rev. D | Page 2 of 24

Data Sheet AD8318 SPECIFICATIONS V = 5 V, C = 220 pF, T = 25°C, 52.3 Ω termination resistor at INHI, unless otherwise noted. POS LPF A Table 1. Parameter Conditions Min Typ Max Unit SIGNAL INPUT INTERFACE INHI (Pin 14) and INLO (Pin 15) Specified Frequency Range 0.001 8 GHz DC Common-Mode Voltage V – 1.8 V POS MEASUREMENT MODE VOUT (Pin 6) shorted to VSET (Pin 7), sinusoidal input signal f = 900 MHz R = 500 Ω TADJ Input Impedance 957||0.71 Ω||pF ±3 dB Dynamic Range T = 25°C 65 dB A ±1 dB Dynamic Range T = 25°C 57 dB A −40°C < T < +85°C 48 dB A Maximum Input Level ±1 dB error −1 dBm Minimum Input Level ±1 dB error −58 dBm Slope −26 −24.5 −23 mV/dB Intercept 19.5 22 24 dBm Output Voltage—High Power In P = −10 dBm 0.7 0.78 0.86 V IN Output Voltage—Low Power In P = −40 dBm 1.42 1.52 1.62 V IN Temperature Sensitivity P = −10 dBm IN 25°C ≤ T ≤85°C 0.0011 dB/°C A −40°C ≤ T ≤ +25°C 0.003 dB/°C A f = 1.9 GHz R = 500 Ω TADJ Input Impedance 523||0.68 Ω||pF ±3 dB Dynamic Range T = 25°C 65 dB A ±1 dB Dynamic Range T = 25°C 57 dB A −40°C < T < +85°C 50 dB A Maximum Input Level ±1 dB error −2 dBm Minimum Input Level ±1 dB error −59 dBm Slope −27 −24.4 −22 mV/dB Intercept 17 20.4 24 dBm Output Voltage—High Power In P = −10 dBm 0.63 0.73 0.83 V IN Output Voltage—Low Power In P = −35 dBm 1.2 1.35 1.5 V IN Temperature Sensitivity P = –10 dBm IN 25°C ≤ T ≤ 85°C 0.0011 dB/°C A −40°C ≤ T ≤ +5°C 0.0072 dB/°C A f = 2.2 GHz R = 500 Ω TADJ Input Impedance 391||0.66 Ω||pF ±3 dB Dynamic Range T = 25°C 65 dB A ±1 dB Dynamic Range T = 25°C 58 dB A −40°C < T < +85°C 50 dB A Maximum Input Level ±1 dB error −2 dBm Minimum Input Level ±1 dB error −60 dBm Slope −28 −24.4 −21.5 mV/dB Intercept 15 19.6 25 dBm Output Voltage—High Power In P = −10 dBm 0.63 0.73 0.84 V IN Output Voltage—Low Power In P = −35 dBm 1.2 1.34 1.5 V IN Temperature Sensitivity P = −10 dBm IN 25°C ≤ T ≤ 85°C −0.0005 dB/°C A −40°C ≤ T ≤ +25°C 0.0062 dB/°C A Rev. D | Page 3 of 24

AD8318 Data Sheet Parameter Conditions Min Typ Max Unit f = 3.6 GHz R = 51 Ω TADJ Input Impedance 119||0.7 Ω||pF ±3 dB Dynamic Range T = 25°C 70 dB A ±1 dB Dynamic Range T = 25°C 58 dB A −40°C < T < +85°C 42 dB A Maximum Input Level ±1 dB error −2 dBm Minimum Input Level ±1 dB error –60 dBm Slope −24.3 mV/dB Intercept 19.8 dBm Output Voltage—High Power In P = −10 dBm 0.717 V IN Output Voltage—Low Power In P = −40 dBm 1.46 V IN Temperature Sensitivity P = −10 dBm IN 25°C ≤ T ≤ 85°C 0.0022 dB/°C A −40°C ≤ T ≤ +25°C 0.004 dB/°C A f = 5.8 GHz R = 1000 Ω TADJ Input Impedance 33||0.59 Ω||pF ±3 dB Dynamic Range T = 25°C 70 dB A ±1 dB Dynamic Range T = 25°C 57 dB A −40°C < T < +85°C 48 dB A Maximum Input Level ±1 dB error −1 dBm Minimum Input Level ±1 dB error −58 dBm Slope −24.3 mV/dB Intercept 25 dBm Output Voltage—High Power In P = −10 dBm 0.86 V IN Output Voltage—Low Power In P = −40 dBm 1.59 V IN Temperature Sensitivity P = −10 dBm IN 25°C ≤ T ≤ 85°C 0.0033 dB/°C A −40°C ≤ T ≤ +25°C 0.0069 dB/°C A f = 8.0 GHz R = 500 Ω TADJ ±3 dB Dynamic Range T = 25°C 60 dB A −40°C < T < +85°C 58 dB A Maximum Input Level ±3 dB error 3 dBm Minimum Input Level ±3 dB error −55 dBm Slope −23 mV/dB Intercept 37 dBm Output Voltage—High Power In P = −10 dBm 1.06 V IN Output Voltage—Low Power In P = −40 dBm 1.78 V IN Temperature Sensitivity P = −10 dBm IN 25°C ≤ T ≤ 85°C 0.028 dB/°C A −40°C ≤ T ≤ +25°C −0.0085 dB/°C A OUTPUT INTERFACE VOUT (Pin 6) Voltage Swing V = 0 V; P = −10 dBm, no load1 4.9 V SET IN V = 2.1 V; P = −10 dBm, no load1 25 mV SET IN Output Current Drive V = 1.5 V; P = −50 dBm 60 mA SET IN Small Signal Bandwidth P = −10 dBm; from CLPF to VOUT 60 MHz IN Video Bandwidth (or Envelope Bandwidth) 45 MHz Output Noise P = 2.2 GHz; −10 dBm, f = 100 kHz, C = 220 pF 90 nV/√Hz IN NOISE LPF Fall Time P = Off to −10 dBm, 90% to 10% 10 ns IN Rise Time P = −10 dBm to off, 10% to 90% 12 ns IN Rev. D | Page 4 of 24

Data Sheet AD8318 Parameter Conditions Min Typ Max Unit VSET INTERFACE VSET (Pin 7) Nominal Input Range P = 0 dBm; measurement mode2 0.5 IN P = −65 dBm; measurement mode2 2.1 V IN Logarithmic Scale Factor −0.04 dB/mV Bias Current Source P = −10 dBm; V = 2.1 V 2.5 μA IN SET TEMPERATURE REFERENCE TEMP (Pin 13) Output Voltage T = 25°C, R = 10 kΩ 0.57 0.6 0.63 V A LOAD Temperature Slope −40°C ≤ T ≤ +85°C, R = 10 kΩ 2 mV/°C A LOAD Current Source/Sink T = 25°C 10/0.1 mA A POWER-DOWN INTERFACE ENBL (Pin 16) Logic Level to Enable Device 1.7 V ENBL Current When Enabled ENBL = 5 V <1 μA ENBL Current When Disabled ENBL = 0 V; sourcing 15 μA POWER INTERFACE VPSI (Pin 3 and Pin 4), VPSO (Pin 9) Supply Voltage 4.5 5 5.5 V Quiescent Current ENBL = 5 V 50 68 82 mA vs. Temperature −40°C ≤ T ≤ +85°C 150 μA/°C A Supply Current when Disabled ENBL = 0 V, total currents for VPSI and VPSO 260 μA vs. Temperature −40°C ≤ T ≤ +85°C 350 μA A 1 Controller mode. 2 Gain = 1. For other gains, see the Measurement Mode section. Rev. D | Page 5 of 24

AD8318 Data Sheet ABSOLUTE MAXIMUM RATINGS Table 2. Stresses at or above those listed under Absolute Maximum Parameter Rating Ratings may cause permanent damage to the product. This is a Supply Voltage: Pin VPSO, Pin VPSI 5.7 V stress rating only; functional operation of the product at these ENBL, V Voltage 0 to V or any other conditions above those indicated in the operational SET POS Input Power (Single-Ended, Referenced 12 dBm section of this specification is not implied. Operation beyond to 50 Ω) the maximum operating conditions for extended periods may Internal Power Dissipation 0.73 W affect product reliability. θ 1 55°C/W JA ESD CAUTION Maximum Junction Temperature 125°C Operating Temperature Range −40°C to +85°C Storage Temperature Range −65°C to +150°C Lead Temperature 260°C 1 With package die paddle soldered to thermal pads with vias connecting to inner and bottom layers. Rev. D | Page 6 of 24

Data Sheet AD8318 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS ENBL INLO INHI TEMP 16 15 14 13 CMIP 1 12 CMIP CMIP 2 AD8318 11 CMIP TOP VIEW VPSI 3 (Not to Scale) 10 TADJ VPSI 4 9 VPSO 5 6 7 8 F T T P P U E O N1.OETTOPEA CSDM. IIPN T(SECLORLNDAVOELRLY VST OCO CMGNRNOEUCNTDE)D. 04853-002 Figure 3. Pin Configuration Table 3. Pin Function Descriptions Pin No. Mnemonic Description 1, 2, 11, 12 CMIP Device Common (Input System Ground). 3, 4 VPSI Positive Supply Voltage (Input System): 4.5 V to 5.5 V. Voltage on Pin 3, Pin 4, and Pin 9 should be equal. 5 CLPF Loop Filter Capacitor. 6 VOUT Measurement and Controller Output. 7 VSET Setpoint Input for Controller Mode or Feedback Input for Measurement Mode. 8 CMOP Device Common (Output System Ground). 9 VPSO Positive Supply Voltage (Output System): 4.5 V to 5.5 V. Voltage on Pin 3, Pin 4, and Pin 9 should be equal. 10 TADJ Temperature Compensation Adjustment. 13 TEMP Temperature Sensor Output. 14 INHI RF Input. Nominal input range: −60 dBm to 0 dBm (referenced to 50 Ω), ac-coupled. 15 INLO RF Common for INHI. AC-coupled RF common. 16 ENBL Device Enable. Connect to VPSI for normal operation. Connect pin to ground for disable mode. EPAD Internally Connected to CMIP (Solder to Ground). Rev. D | Page 7 of 24

AD8318 Data Sheet TYPICAL PERFORMANCE CHARACTERISTICS V = 5 V; T = +25°C, −40°C, +85°C; C = 220 pF; R = 500 Ω; unless otherwise noted. Colors: +25°C  Black; −40°C  Blue; POS A LPF TADJ +85°C  Red. 2.2 2.0 2.2 2.0 2.0 1.6 2.0 1.6 1.8 1.2 1.8 1.2 1.6 0.8 1.6 0.8 1.4 0.4 B) 1.4 0.4 B) (V)UT1.2 0 OR (d (V)UT1.2 0 OR (d O R O R V 1.0 –0.4 ER V 1.0 –0.4 ER 0.8 –0.8 0.8 –0.8 0.6 –1.2 0.6 –1.2 00..42 ––21..06 04853-003 00..42 ––21..06 04853-006 –65 –55 –45 –35 –25 –15 –5 5 15 –65 –55 –45 –35 –25 –15 –5 5 15 PIN (dBm) PIN (dBm) Figure 4. VOUT and Log Conformance vs. Input Amplitude at 900 MHz, Figure 7. VOUT and Log Conformance vs. Input Amplitude at 3.6 GHz, Typical Device Typical Device, RTADJ = 51 Ω 2.2 2.0 2.2 2.0 2.0 1.6 2.0 1.6 1.8 1.2 1.8 1.2 1.6 0.8 1.6 0.8 1.4 0.4 B) 1.4 0.4 B) (V)UT1.2 0 OR (d (V)UT1.2 0 OR (d O R O R V 1.0 –0.4 ER V 1.0 –0.4 ER 0.8 –0.8 0.8 –0.8 0.6 –1.2 0.6 –1.2 00..42 ––21..06 04853-004 00..42 ––21..06 04853-007 –65 –55 –45 –35 –25 –15 –5 5 15 –65 –55 –45 –35 –25 –15 –5 5 15 PIN (dBm) PIN (dBm) Figure 5. VOUT and Log Conformance vs. Input Amplitude at 1.9 GHz, Figure 8. VOUT and Log Conformance vs. Input Amplitude at 5.8 GHz, Typical Device Typical Device, RTADJ = 1000 Ω 2.2 2.0 2.2 4.5 2.0 1.6 2.0 3.6 1.8 1.2 1.8 2.7 1.6 0.8 1.6 1.8 1.4 0.4 B) 1.4 0.9 B) (V)UT1.2 0 OR (d (V)UT1.2 0 OR (d O R O R V 1.0 –0.4 ER V 1.0 –0.9 ER 0.8 –0.8 0.8 –1.8 0.6 –1.2 0.6 –2.7 00..42 ––21..06 04853-005 00..42 ––43..56 04853-008 –65 –55 –45 –35 –25 –15 –5 5 15 –65 –55 –45 –35 –25 –15 –5 5 PIN (dBm) PIN (dBm) Figure 6. VOUT and Log Conformance vs. Input Amplitude at 2.2 GHz, Figure 9. VOUT and Log Conformance vs. Input Amplitude at 8 GHz, Typical Device Typical Device Rev. D | Page 8 of 24

Data Sheet AD8318 2.0 2.0 1.6 1.6 1.2 1.2 0.8 0.8 B) 0.4 B) 0.4 d d R ( 0 R ( 0 O O R R ER–0.4 ER–0.4 –0.8 –0.8 –1.2 –1.2 ––21..06 04853-009 ––21..06 04853-012 –65 –55 –45 –35 –25 –15 –5 5 15 –65 –55 –45 –35 –25 –15 –5 5 15 PIN (dBm) PIN (dBm) Figure 10. Distribution of Error over Temperature After Ambient Figure 13. Distribution of Error at Temperature After Ambient Normalization vs. Input Amplitude at 900 MHz for at Least 70 Devices Normalization vs. Input Amplitude at 3.6 GHz for at Least 70 Devices, RTADJ = 51 Ω 2.0 2.0 1.6 1.6 1.2 1.2 0.8 0.8 B) 0.4 B) 0.4 d d R ( 0 R ( 0 O O R R ER–0.4 ER–0.4 –0.8 –0.8 –1.2 –1.2 ––21..06 04853-010 ––21..06 04853-013 –65 –55 –45 –35 –25 –15 –5 5 15 –65 –55 –45 –35 –25 –15 –5 5 15 PIN (dBm) PIN (dBm) Figure 11. Distribution of Error at Temperature After Ambient Figure 14. Distribution of Error at Temperature After Ambient Normalization vs. Input Amplitude at 1900 MHz for at Least 70 Devices Normalization vs. Input Amplitude at 5.8 GHz for at Least 70 Devices, RTADJ = 1000 Ω 2.0 4.5 1.6 3.6 1.2 2.7 0.8 1.9 B) 0.4 B) 0.9 d d R ( 0 R ( 0 O O R R ER–0.4 ER–0.9 –0.8 –1.8 –1.2 –2.7 ––21..06 04853-011 ––43..56 04853-014 –65 –55 –45 –35 –25 –15 –5 5 15 –65 –55 –45 –35 –25 –15 –5 5 PIN (dBm) PIN (dBm) Figure 12. Distribution of Error at Temperature After Ambient Figure 15. Distribution of Error at Temperature After Ambient Normalization vs. Input Amplitude at 2.2 GHz for at Least 70 Devices Normalization vs. Input Amplitude at 8 GHz for at Least 70 Devices Rev. D | Page 9 of 24

AD8318 Data Sheet j1 j2 j0.5 10k RF OFF j0.2 Hz) V/ n Y ( 1k T 0 0.28GHz 0.5 1 2 0.1GHz ENSI –40dBm–60dBm D L –20dBm A 5.8GHz R 0.9GHz CT –j0.2 E100 P 1.9GHz S E S –10dBm OI SSTTAORPT F FRREEQQUUEEN–NCj0CY.5Y = = 8 G0.H1GzHz –3j1.6GHz 2.2GHz–j2 04853-015 N 10 1 3 10 F3R0EQUE1N00CY (k3H00z) 01dkBm 3k 10k 04853-018 Figure 16. Input Impedance vs. Frequency; No Termination Resistor on Figure 19. Noise Spectral Density of Output; CLPF = Open INHI, ZO = 50 Ω 0.07 1k 0.06 Hz) V/ NT (A)0.05 SITY (n E0.04 N CURR DECREASING VENBL INCREASING VENBL AL DE100 Y 0.03 R L T P C P E U P S0.02 S E S OI 0.010 04853-016 N 10 04853-019 1.4 1.5 1.6 1.7 1.8 1 3 10 30 100 300 1k 3k 10k VENBL (V) FREQUENCY (kHz) Figure 17. Supply Current vs. Enable Voltage Figure 20. Noise Spectral Density of Output Buffer (from CLPF to VOUT); CLPF = 0.1 μF 2.2 2.0 2.0 1.6 VOUT 1.8 1.2 1.6 0.8 200mV/VERTICAL DIVISION 1.4 0.4 B) (V)UT1.2 0 OR (d O R V 1.0 –0.4 ER PULSED RF INPUT 0.1GHz, 0.8 –0.8 –10dBm GND 0.6 –1.2 04853-017 00..42–65 –55 –45 –35 –25 –15 –5 5 15––21..06 04853-020 20ns PER HORIZONTAL DIVISION PIN (dBm) Figure 18. VOUT Pulse Response Time; Pulsed RF Input 0.1 GHz, –10 dBm; Figure 21. Output Voltage Stability vs. Supply Voltage at 1.9 GHz CLPF = Open When VP Varies by 10%, Multiple Devices Rev. D | Page 10 of 24

Data Sheet AD8318 THEORY OF OPERATION The AD8318 is a 9-stage demodulating logarithmic amplifier CMIP, the input system common pin, provides a quality low that provides RF measurement and power amplifier control impedance connection to the printed circuit board (PCB) functions. The design of the AD8318 is similar to the AD8313 ground via four package pins. Ground the package paddle, logarithmic detector/controller. However, the AD8318 input which is internally connected to the CMIP pin, to the PCB to frequency range extends to 8 GHz with a 60 dB dynamic range. reduce thermal impedance from the die to the PCB. Other improvements include: reduced intercept variability vs. The logarithmic function is approximated in a piecewise temperature, increased dynamic range at higher frequencies, fashion by nine cascaded gain stages. For a more complete low noise measurement and controller output (VOUT), explanation of the logarithm approximation, refer to the adjustable low-pass corner frequency (CLPF), temperature AD8307 data sheet. The cells have a nominal voltage gain of sensor output (TEMP), negative transfer function slope for 8.7 dB each and a 3 dB bandwidth of 10.5 GHz. higher accuracy, and 10 ns response time for RF burst detection Using precision biasing, the gain is stabilized over temperature capability. A block diagram is shown in Figure 22. and supply variations. Because the cascaded gain stages are VPSI ENBL TADJ VPSO dc-coupled, the overall dc gain is high. An offset compensation loop is included to correct for offsets within the cascaded cells. TEMP SETNEMSOPR GBIAAISN SLOPE I V VSET At the output of each of the gain stages, a square-law detector cell rectifies the signal. The RF signal voltages are converted to a I V VOUT fluctuating differential current with an average value that DET DET DET DET increases with signal level. Along with the nine gain stages and CLPF INHI detector cells, an additional detector is included at the input of the AD8318, altogether providing a 60 dB dynamic range. After INLO CMIP CMOP 04853-021 the dIet e×c tloorg cu(Vrre/nVts are sum) med and filtered, the function (1) D 10 IN INTERCEPT Figure 22. Block Diagram is formed at the summing node, A fully differential design, using a proprietary high speed SiGe where: process, extends high frequency performance. Input INHI I is the internally set detector current. receives the signal with a low frequency impedance of nominally D V is the input signal voltage. 1200 Ω in parallel with 0.7 pF. The maximum input with ±1 dB IN V is the intercept voltage (that is, when V = V , log conformance error is typically 0 dBm (referenced to 50 Ω). INTERCEPT IN INTERCEPT the output voltage would be 0 V if capable of going to 0 V). The noise spectral density referred to the input is 1.15 nV/√Hz, which is equivalent to a voltage of 118 μV rms in a 10.5 GHz bandwidth, or a noise power of −66 dBm (referenced to 50 Ω). This noise spectral density sets the lower limit of the dynamic range. However, the low end accuracy of the AD8318 is enhanced by specially shaping the demodulating transfer characteristic to partially compensate for errors due to internal noise. Rev. D | Page 11 of 24

AD8318 Data Sheet USING THE AD8318 BASIC CONNECTIONS VPSI 40kΩ The AD8318 is specified for operation up to 8 GHz. As a result, DISCHARGE ENBL low impedance supply pins with adequate isolation between 200Ω 2 ×VBE functions are essential. In the AD8318, VPSI and VPSO, the two positive supply pins, must be connected to the same positive pVoPtSeOnt ipailn. T bhiaes VesP tShIe p lionw b niaosiesse tohuet pinupt udtr civirecru fiotrr yV, OwhUiTle. the CMIP 40kΩ 2 ×VBE ENABLE 04853-023 Figure 24. ENBL Interface Separate commons are also included in the device. CMOP is used as the common for the output drivers. Connect Pin CMIP Δ: 2.07V @:2.07V and Pin CMOP to a low impedance ground plane. Apply a power supply voltage of between 4.5 V and 5.5 V to VPSO and VPSI. In addition, 100 pF and 0.1 μF power supply decoupling capacitors connect close to each power supply pin. The two adjacent VPSI pins can share a pair of decoupling capacitors due to their proximity. VS 1 499Ω C5 NOTE 1 0.1µF 12 11 10 9 C1060pF 04853-051 CMIP CMIP TADJ VPSO CH1 500mV M400ns A CH1 920mV T 425.200ns TEMP C1 13 TEMP CMOP 8 Figure 25. ENBL Response Time; VPOS = 5.0 V; INPRUFT R1 1Cn2F 14 INHI AD8318 VSET 7 Input AC-Coupling Caps = 18 pF; CLPF = Open 52.3Ω 1nF 15 INLO VOUT 6 VOUT INPUT SIGNAL COUPLING 16 ENBL CLPF 5 NOTE 2 The RF input to the AD8318 (INHI) is single ended and must CMIP CMIP VPSI VPSI be ac-coupled. INLO (input common) must be ac-coupled to VS 1 2 3 4 ground (see Figure 23). Suggested coupling capacitors are 1 nF ceramic, 0402-style capacitors for input frequencies of 1 MHz to C7 100pF 8 GHz. The coupling capacitors must be mounted close to the C8 INHI pin and the INLO pin. These capacitor values can be 0.1µF increased to lower the input stage high-pass cutoff frequency. VS The high-pass corner is set by the input coupling capacitors and 12SSEEEE TREEMSPPOERNASTEU TRIME EC SOEMCPTEIONSNA.TION SECTION. 04853-022 the internal 10 pF capacitor. The dc voltage on INHI and INLO is approximately one diode voltage drop below the voltage Figure 23. Basic Connections applied to the VPSI pin. The paddle of the AD8318 LFCSP is internally connected to The Smith Chart in Figure 16 shows the AD8318 input CMIP. For optimum thermal and electrical performance, solder impedance vs. frequency. Table 4 lists the reflection coefficient the paddle to a low impedance ground plane. and impedance at select frequencies. For Figure 16 and Table 4, ENABLE INTERFACE the 52.3 Ω input termination resistor is removed. At dc, the To enable the AD8318, the ENBL pin must be pulled high. resistance is typically 2 kΩ. At frequencies up to 1 GHz, the Taking ENBL low puts the AD8318 in sleep mode, reducing impedance is approximated as 1000 Ω||0.7 pF. The RF input current consumption to 260 µA at ambient. The voltage on pins are coupled to a network as shown in the simplified ENBL must be greater than 2 V (~1.7 V) to enable the device. schematic in Figure 26. BE When enabled, the ENBL pin draws less than 1 µA. When ENBL is pulled low, the pin sources 15 µA. The enable interface has high input impedance. An internal 200 Ω resistor is placed in series with the ENBL input for added protection. Figure 24 depicts a simplified schematic of the enable interface. The response time of the AD8318 ENBL interface is shown in Figure 25. Rev. D | Page 12 of 24

Data Sheet AD8318 VPSO VPSI CURRENT CLPF 10pF 10pF 10Ω VOUT + FIRST 0.2V 20kΩ 20kΩ GAIN – 150Ω STAGE INHI 2kΩ A = 8.6dB CMOP 200Ω 04853-025 INLO Figure 27. Output Interface STgAmGE OCOFFMSPET 04853-024 SETPOINT INTERFACE Figure 26. Input Interface The setpoint interface is shown in Figure 28. The VSET input drives the high impedance (250 kΩ) input of an internal While the input can be reactively matched, this is typically not operational amplifier. The VSET voltage appears across the necessary. An external 52.3 Ω shunt resistor (connected on the internal 3.13 kΩ resistor to generate I . When a portion signal side of the input coupling capacitors, see Figure 23) SET of VOUT is applied to VSET, the feedback loop forces combines with the relatively high input impedance to provide an adequate broadband 50 Ω match. −I × log (V /V ) = I (2) D 10 IN INTERCEPT SET If V = V /X, I = V /(X × 3.13 kΩ). The result is Table 4. Input Impedance for Select Frequency SET OUT SET OUT V = (−I × 3.13 kΩ × X) × log (V /V ). Frequency S11 Impedance Ω OUT D 10 IN INTERCEPT (MHz) Real Imaginary (Series) ISET 100 +0.918 −0.041 927-j491 VSET 450 +0.905 −0.183 173-j430 900 +0.834 −0.350 61-j233 1900 +0.605 −0.595 28-j117 3.13kΩ 23260000 ++00..502740 −−00..661061 2286--jj14092 CMOP 04853-026 Figure 28. VSET Interface 5300 −0.369 −0.305 20-j16 5800 −0.326 −0.286 22-j16 The slope is given by −ID × X × 3.13 kΩ = −500 mV × X. For 8000 −0.390 −0.062 22-j3 example, if a resistor divider to ground is used to generate a VSET voltage of VOUT/2, X = 2. The slope is set to −1 V/decade or −50 mV/dB. The coupling time constant, 50 × C /2, forms a high-pass C corner with a 3 dB attenuation at f = 1/(2π × 50 × C ), where TEMPERATURE COMPENSATION OF OUTPUT HP C C1 = C2 = CC. Using the typical value of 1 nF, this high-pass VOLTAGE corner is ~3.2 MHz. In high frequency applications, f must be HP The AD8318 functionality includes the capability to externally as large as possible to minimize the coupling of unwanted low trim the temperature drift. Attaching a ground-referenced frequency signals. Likewise, in low frequency applications, a resistor to the TADJ pin alters an internal current, minimizing simple RC network forming a low-pass filter must be added, intercept drift vs. temperature. As a result, the R can be TADJ generally placed at the generator side of the coupling capacitors, optimized for operation at different frequencies. thereby lowering the required capacitance value for a given high-pass corner frequency. ICOMP 2V OUTPUT INTERFACE The logarithmic output interface is shown in Figure 27. The VINTERNAL VOUT pin is driven by a PNP output stage. An internal 10 Ω ~0.4V resistor is placed in series with the emitter follower output and 2kΩ tthhee VsleOwU oTn p CinL.P TFh. eT rhies ef atlilm tiem oef tish ea no uRtCpu litm isi tleimd istleedw m paroinvliyd ebdy TADJ 04853-027 Figure 29. TADJ Interface by the load capacitance and the pull-down resistance at VOUT. R , nominally 499 Ω for optimal temperature compensation There is an internal pull-down resistor of 350 Ω. Any resistive TADJ at 2.2 GHz input frequency, is connected between the TADJ pin load at VOUT is placed in parallel with the internal pull-down and ground (see Figure 23). The value of this resistor partially resistor and provides additional discharge current. determines the magnitude of an analog correction coefficient that is employed to reduce intercept drift. Rev. D | Page 13 of 24

AD8318 Data Sheet Table 5 lists recommended resistors for various frequencies. MEASUREMENT MODE These resistors provide the best overall temperature drift based When the VOUT voltage, or a portion of the VOUT voltage, is on measurements of a diverse population of devices. fed back to VSET, the device operates in measurement mode. The relationship between output temperature drift and frequency As shown in Figure 31, the AD8318 has an offset voltage, a is nonlinear and is not easily modeled. Experimentation is negative slope, and a VOUT measurement intercept greater required to choose the correct RTADJ resistor at frequencies than its input signal range. not listed in Table 5. 2.4 2.0 VOUT 25°C Table 5. Recommended RTADJ Resistors 2.1 ERROR 25°C 1.5 Frequency Recommended R TADJ 1.8 1.0 900 MHz 500 Ω 1.9 MHz 500 Ω 1.5 0.5 B) 2.2 GHz 500 Ω (V)UT 1.2 0 OR (d 3.6 GHz 51 Ω O R V R 5.8 GHz 1 kΩ 0.9 –0.5 E 8 GHz 500 Ω RANGE OF 0.6 CALCULATION –1.0 OF SLOPE AND INTERCEPT TThEeM APDE8R31A8T iUntRerEn aSllEyN geSnOerRat es a voltage that is proportional 0.30 –1.5 04853-029 –65–60–55–50–45–40–35–30–25–20–15–10 –5 0 5 10 15 to absolute-temperature (VPTAT). The VPTAT voltage is multiplied PIN (dBm) INTERCEPT by a factor of 5, resulting in a 2 mV/°C output at the TEMP pin. Figure 31. Typical Output Voltage vs. Input Signal The output voltage at 27°C is typically 600 mV. An emitter The output voltage vs. input signal voltage of the AD8318 is follower drives the TEMP pin, as shown in Figure 30. linear-in-dB over a multidecade range. The equation for this VPSI function is INTERNAL V = X × V × log (V /V ) (3) OUT SLOPE/DEC 10 IN INTERCEPT TEMP = X × V × 20 × log (V /V ) (4) SLOPE/dB 10 IN INTERCEPT 4kΩ where: 1kΩ X is the feedback factor in V = V /X. CMIP 04853-028 VVINTERCEPT iiss nexopmreinssaelldy i−n5 V00rm mSs.E TV/deOcUaTde and V is Figure 30. TEMP Sensor Interface SLOPE/DEC SLOPE/dB nominally −25 mV/dB. The internal pull-down resistance is 5 kΩ. The temperature V , expressed in dBV, is the x-axis intercept of the linear- INTERCEPT sensor has a slope of 2 mV/°C. in-dB transfer function shown in Figure 31. The temperature sensor output varies with output current due V is 7 dBV (20 dBm, referenced to 50 Ω or 2.239 V ) INTERCEPT rms to increased die temperature. Output loads less than 1 kΩ draw for a sinusoidal input signal. enough current from the output stage causing this increase to The slope of the transfer function can be increased to occur. An output current of 10 mA results in the voltage on the accommodate various converter mV per dB (LSB per dB) temperature sensor to increase by 1.5°C, or ~3 mV. requirements. However, increasing the slope can reduce the Best precision from the temperature sensor is obtained when dynamic range. This is due to the limitation of the minimum the supply current to AD8318 remains fairly constant, that is, and maximum output voltages, determined by the chosen no heavy load drive. scaling factor X. The minimum value for V is X × V . The offset voltage, OUT OFFSET V , is equal to 0.5 V and is internally added to the detector OFFSET output signal. V = (X × V ) (5) OUT(MIN) OFFSET Rev. D | Page 14 of 24

Data Sheet AD8318 The maximum output voltage is 2.1 V × X, and cannot exceed DEVICE CALIBRATION AND ERROR CALCULATION 400 mV below the positive supply. The measured transfer function of the AD8318 at 2.2 GHz is V = (2.1 V × X) when X < (V − 400 mV)/(2.1 V) (6) shown in Figure 32. The figure shows plots of both output OUT(MAX) POS voltage vs. input power and calculated log conformance error V = (V − 400 mV) when X ≥ (V − 400 mV)/ (2.1 V) OUT(MAX) POS POS vs. input power. (7) As the input power varies from −65 dBm to 0 dBm, the output When X = 1, the typical output voltage swing is 0.5 V to 2.1 V. voltage varies from 2 V to about 0.5 V. The output voltage swing is modeled using Equation 5 to Equation 7 and restricted by Equation 8: VOUT +25°C VOUT(MIN) < VOUT < VOUT(MAX) (8) VSOLOUPTEID E=A (LV O= USTL1O –P VEO ×U T(2P)I/N(P –IN I1N T– EPRINC2E)PT) VVEOORUURTTO –+R48 05+°°2CC5°C INTERCEPT = PIN1 – (VOUT1/SLOPE) ERROR –40°C When X = 4 and VPOS = 5 V, 2.2ERROR (dB) = (VOUT ×VOUTIDEAL)/SLOPE ERROR +85°C 2.5 (X × V ) < V < (V − 400 mV) OFFSET OUT POS 2.0 2.0 (4 × 0.5 V) < VOUT < (2.1 V × 4) 1.8 1.5 VOUT2 2 V < V < 4.6 V 1.6 1.0 OUT uFsoarb Xle =d y4n, asmloipce r a=n −ge1 0is0 r emdVuc/eddB t;o V 2O6U Td Bca fnro smw i0n gd B2m.6 tVo, –a2n6d dthBem . (V)UT11..42 00.5 OR (dB) The slope is very stable vs. process and temperature variation. VO1.0 –0.5 ERR When base-10 logarithms are used, VSLOPE/DECADE represents the VOUT1 0.8 –1.0 output voltage per decade of input power. One decade is equal 0.6 –1.5 tsolo 2p0e dinB ;V V/dSLBO.P E/DEC/20 = VSLOPE/dB represents the output voltage 00..42 –2.0 04853-030 –65–60–55 –45–40–35–30–25–20–15 –5 0 5 As noted in Equation 3, the VOUT voltage has a negative slope. PIN2 PIN (dBm) PIN1 INTERCEPT This is the correct slope polarity to control the gain of many Figure 32. Transfer Function at 2.2 GHz power amplifiers and other VGAs in a negative feedback Because the slope and intercept vary from device to device, configuration. Because both the slope and intercept vary board-level calibration is performed to achieve high accuracy. slightly with frequency, refer to Table 1 for application-specific values for the slope and intercept. The equation can be rewritten for output voltage, from the Measurement Mode section, using an intercept expressed Although demodulating log amps respond to input signal in dBm. voltage, not input signal power, it is customary to discuss the amplitude of high frequency signals in terms of power. In this V = Slope × (P – Intercept) (14) OUT IN case, the characteristic impedance of the system, Z, must be 0 In general, the calibration is performed by applying two known known to convert voltages to corresponding power levels. signal levels to the AD8318 input and measuring the corre- Beginning with the definitions of dBm and dBV, sponding output voltages. The calibration points are generally P (dBm) = 10 × log (V 2/(Z × 1 mW)) (9) chosen to be within the linear-in-dB operating range of the 10 rms 0 device (see Figure 32). Calculation of the slope and intercept is V (dBV) = 20 × log (V /1 V ) (10) 10 rms rms done by: When Equation 9 is expanded Slope = (V − V )/(P − P ) (15) OUT1 OUT2 IN1 IN2 P (dBm) = 20 × log (V ) − 10 × log (Z × 1 mW) (11) 10 rms 10 0 Intercept = P − V /Slope (16) IN1 OUT1 and given Equation 10, Equation 11 can be rewritten as Once the slope and intercept are calculated, an equation can be P (dBm) = V (dBV) − 10 × log (Z × 1 mW) (12) 10 0 written to allow calculation of an (unknown) input power based For example, P for a sinusoidal input signal, expressed on the output voltage of the detector. INTERCEPT in terms of dBm (decibels referred to 1 mW), in a 50 Ω system is P (unknown) = V (measured)/Slope + Intercept (17) IN OUT P (dBm) = V (dBV) INTERCEPT INTERCEPT − 10 × log (Z × 1 mW) = (13) 10 0 7 dBV − 10 × log (50 × 10−3) = 20 dBm 10 For further information on the intercept variation dependence upon waveform, refer to the AD8313 and AD8307 data sheets. Rev. D | Page 15 of 24

AD8318 Data Sheet Using the equation for the ideal output voltage (see Equation 13) as Figure 34 shows how calibration points can be adjusted to a reference, the log conformance error of the measured data can increase dynamic range but at the expense of linearity. In this be calculated as case, the calibration points for slope and intercept are set at −4 dBm and −60 dBm. These points are at the end of the linear Error (dB) = (V − V )/Slope (18) OUT(MEASURED) OUT(IDEAL) range of the device. = Figure 32 includes a plot of the error at 25°C, the temperature at Once again, at 25°C, an error of 0 dB is seen at the calibration which the log amp is calibrated. Note that the error is not zero. points. Note also that the range over which the AD8318 This is because the log amp does not perfectly follow the ideal maintains an error of < ±1 dB is extended to 60 dB at 25°C and V vs. P equation, even within its operating region. The error at OUT IN 58 dB over temperature. The disadvantage of this approach is the calibration points (−12 dBm and −52 dBm, in this case) is, that linearity suffers, especially at the top end of the input range. however, equal to 0 by definition. 2.2 2.5 Figure 32 includes error plots for the output voltage at −40°C VOUT +25°C ERROR +25°C and +85°C. These error plots are calculated using the slope 2.0 VOUT –40°C ERROR –40°C 2.0 VOUT +85°C ERROR +85°C and intercept at 25°C. This method is consistent with a mass- 1.8 1.5 production environment where calibration at temperature is 1.6 1.0 not practical. 1.4 0.5 B) SELECTING CALIBRATION POINTS TO IMPROVE (V)UT1.2 0 OR (d ACCURACY OVER A REDUCED RANGE VO1.0 –0.5 ERR In some applications, very high accuracy is required at just one 0.8 –1.0 power level or over a reduced input range. For example, in a 0.6 –1.5 w(HirPeAle)s sis t rmanossmt cirtitteirc,a tlh aet ,a occr ucrloacsey toof, tfhuell hpiogwh epro. wer amplifier 00..42 58dB DYNAMIC RANGE (±1dB ERROR) ––22..50 04853-038 Figure 33 shows the same measured data as Figure 32. Note –65 –60–55–50–45 –40–35 –30–25–20–15–10 –5 0 5 PIN (dBm) that accuracy is very high from −10 dBm to −30 dBm. Below Figure 34. Dynamic Range Extension by Choosing Calibration Points −30 dBm, the error increases to about −1 dB. This is because Close to the End of the Linear Range the calibration points have changed to −14 dBm and −26 dBm. Another way of presenting the error function of a log amp VOUT +25°C ERROR +25°C VOUT –40°C ERROR –40°C detector is shown in Figure 35. In this case, the dB error at hot 2.2 VOUT +85°C ERROR +85°C 2.5 and cold temperatures is calculated with respect to the output voltage at ambient. This is a key difference in comparison to the 2.0 2.0 plots in Figure 33 and Figure 34. Previously, all errors were 1.8 1.5 calculated with respect to the ideal transfer function at ambient. 1.6 1.0 When this alternative technique is used, the error at ambient 1.4 0.5 B) VOUT2 V (V)OUT11..20 0–0.5 ERROR (d bife tchoem deesv, ibcey tdreafninsfietiro fnu,n ecqtuioanl tpoe 0rf e(scetely F fioglulorwe s3 5th).e T idheisa li s valid V = Slope × (P − Intercept) equation. However, because a OUT IN VOUT1 –1.0 log amp in practice never perfectly follows this equation 0.6 –1.5 (especially outside of its linear operating range), this plot tends 00..42 ––22..05 04853-031 tToh aisr tpifliocti aisll ya iumsepfruolv teo oliln feoarr ietsyt iamnadt ienxgt etnemd tpheer adtyunrea mdriicf tr aant gae . –65–60–55–50 –45–40–35–30 –20 –10 –5 0 5 PIN (dBm) particular power level with respect to the (nonideal) output PIN2 PIN1 voltage at ambient. However, to achieve this level of accuracy in Figure 33. Output Voltage and Error vs. P with 2-Point Calibration at an end application requires calibration at multiple points in the IN −10 dBm and −30 dBm operating range of the device. Calibration points are chosen to suit the application at hand. In general, the calibration points are never chosen in the nonlinear portion of the transfer function of the log amp (above −5 dBm or below −60 dBm, in this case). Rev. D | Page 16 of 24

Data Sheet AD8318 2.2 2.5 TEMPERATURE DRIFT AT DIFFERENT VOUT +25°C ERROR +25°C wrt VOUT 2.0 VOUT –40°C ERROR –40°C wrt VOUT 2.0 TEMPERATURES VOUT +85°C ERROR +85°C wrt VOUT 1.8 1.5 Figure 37 shows the log slope and error over temperature for 1.6 1.0 a 5.8 GHz input signal. Error due to drift over temperature 1.4 0.5 B) consistently remains within ±0.5 dB, and only begins to exceed (V)UT1.2 0 OR (d this limit when the ambient temperature drops below −20°C. O R When using a reduced temperature range, higher measurement V 1.0 –0.5 ER accuracy is achievable for all frequencies. 0.8 –1.0 VOUT +25°C VOUT –40°C VOUT +85°C 0.6 –1.5 VOUT 0°C VOUT +70°C ERROR +25°C ERROR –10°C ERROR –20°C ERROR 0°C 00..42 ––22..50 04853-032 2.2 ERROR +70°C VEROURTO –R1 0–°4C0°C VEROURTO –R2 0+°8C5°C 2.5 –65–60–55–50–45–40–35–30–25–20–15–10 –5 0 5 2.0 2.0 PIN (dBm) 1.8 1.5 Figure 35. Error vs. Temperature with Respect to Output Voltage at 25°C (Does Not Take Transfer Function Nonlinearities at 25°C into Account) 1.6 1.0 VARIATION IN TEMPERATURE DRIFT FROM 1.4 0.5 B) DEVICE TO DEVICE (V)UT1.2 0 OR (d O R Figure 36 shows a plot of output voltage and error for multiple V 1.0 –0.5 ER AD8318 devices measured at 5.8 GHz. The concentration of 0.8 –1.0 black error plots represents the performance of the population 0.6 –1.5 Tath 2e5 r°eCd (asnlodp bel aune dc uinrtveersc einpdt iacraet ec athlceu mlateeads uforerd e abcehh adveivoirc eo)f. a 00..42 ––22..50 04853-039 population of devices over temperature. This suggests a range –65–60–55–50–45–40–35–30–25–20–15–10 –5 0 5 on the drift (from device to device) of 1.2 dB. PIN (dBm) Figure 37. Typical Drift at 5.8 GHz for Various Temperatures 2.2 2.0 SETTING THE OUTPUT SLOPE IN MEASUREMENT 2.0 1.6 MODE 1.8 1.2 1.6 0.8 To operate in measurement mode, VOUT is connected to VSET. This yields the typical logarithmic slope of −25 mV/dB. The 1.4 0.4 B) (V)OUT1.2 0 ROR (d oapuptprouxt ismwaintegl yc o0r.5re Vsp toon 2d.i1n Vg .t To hthe es lsoppeec iafniedd oinuptpuut tr sawngineg i sc athne bne V 1.0 –0.4 ER increased by placing a resistor divider between VOUT and 0.8 –0.8 VSET (that is, one resistor from VOUT to VSET and one 0.6 –1.2 resistor from VSET to common). 00..42 ––21..06 04853-050 Ausse adn, tehxea mslopplee, difo tuwbole esq tuoa alp rpersoisxtoimrsa, tseulyc h− 5as0 1m0 Vk/Ωd/B1.0 T khΩe ,i narpeu t –65 –55 –45 –35 –25 –15 –5 5 15 impedance of VSET is approximately 500 kΩ. Keep slope setting PIN (dBm) resistors below ~50 kΩ to prevent this input impedance from Figure 36. Output Voltage and Error vs. Temperature (+25°C, −40°C, and +85°C) of a Population of Devices Measured at 5.8 GHz affecting the resulting slope. When increasing the slope, the new output voltage range cannot exceed the output voltage swing capability of the output stage. Refer to the Measurement Mode section for further details. AD8318 VOUT –50mV/dB 10kΩ VSET 10kΩ 04853-033 Figure 38. Increasing the Slope Rev. D | Page 17 of 24

AD8318 Data Sheet AD8318 +5V OUTPUT PULSED RF +5V INPUT 1nF VPOS 40Ω 50Ω INHI VOUT 52.3Ω AD8318 ADCMP563 INLO VSET 1nF GND 50Ω 50Ω 50Ω 100Ω 100Ω COMPARATOR VREF = 1.8V–1.2V –5.2V –5.2V OUTPUT 04853-040 Figure 39. AD8318 Operating with the High Speed ADCMP563 Comparator RESPONSE TIME CAPABILITY Figure 40 shows the response of the AD8318 and the comparator for a 500 MHz pulsed sine wave of varying amplitudes. The The AD8318 has a 10 ns rise/fall time capability (10% to 90%) output level of the AD8318 is the signal strength of the input for input power switching between the noise floor and 0 dBm. signal. For applications where these RF bursts are very small, This capability enables RF burst measurements at repetition the output level does not change by a large amount. Using a rates beyond 45 MHz. In most measurement applications, the comparator is beneficial in this case because it turns the output AD8318 has an external capacitor connected to CLPF to provide of the log amp into a limiter-like signal. While this configuration additional filtering for VOUT. However, using the CLPF capacitor does result in the loss of received signal power level, it does slows the response time as does stray capacitance on VOUT. For allow for presence-only detection of low power RF bursts. an application requiring maximum RF burst detection capability, the CLPF pin is left unconnected. In this case, the integration OUTPUT FILTERING function is provided by the 1.5 pF on-chip capacitor. For applications in which maximum video bandwidth and, There is a 10 Ω internal resistor in series with the output driver. consequently, fast rise time are desired, it is essential that the Because of this resistor, it is necessary to add an external 40 Ω CLPF pin be left unconnected and free of any stray capacitance. back-terminating resistor in series with the output when driving To reduce the nominal output video bandwidth of 45 MHz, a 50 Ω load. Place the back-terminating resistor close to the connect a ground-referenced capacitor (C ) to the CLPF pin, FLT VOUT pin. The AD8318 has the drive capability to drive a 50 Ω as shown in Figure 41. Generally, this is done to reduce output load at the end of a coaxial cable or transmission line when back ripple (at twice the input frequency for a symmetric input terminated (see Figure 39). waveform, such as sinusoidal signals). The circuit diagram in Figure 39 shows the AD8318 used with a high speed comparator circuit. The 40 Ω series resistor at the AD8318 output of the AD8318 combines with an internal 10 Ω to ILOG VOUT properly match to the 50 Ω input of the comparator. +4 3.13kΩ 1.5pF CLPF PULSED RF –50dB –30dB –20dB –10dB INPUT CFLT 04853-042 Figure 41. Lowering the Postdemodulation Bandwidth C is selected by AD8318 FLT OUTPUT 1 COOUMTPPUATRATOR CFLT  π3.13kΩVideoBandwidth1.5pF (19) 04853-041 Steent tthh eth vei dmeoin bimanudmw iidntphu tto f rae qfrueeqnuceyn. cTyh eisq uenals utor easb tohuatt othnee - 0 100 200 300 400 500 600 700 800 output ripple of the demodulated log output, which is at twice TIME (ns) the input frequency, is well filtered. Figure 40. Pulse Response of AD8318 and Comparator for RF Pulses of Varying Amplitudes Rev. D | Page 18 of 24

Data Sheet AD8318 In many log amp applications, it may be necessary to lower the The basic connections for operating the AD8318 as an analog corner frequency of the postdemodulation filtering to achieve controller with the AD8367 are shown in Figure 43. The low output ripple while maintaining a rapid response time to AD8367 is a low frequency to 500 MHz VGA with 45 dB of changes in signal level. For an example of a 4-pole active filter, dynamic range. This configuration is very similar to the one see the AD8307 data sheet. shown in Figure 42. For applications working at high input CONTROLLER MODE frequencies, such as cellular bands or WLAN, or those requiring large gain control ranges, the AD8318 can control The AD8318 provides a controller mode feature at the VOUT the 10 MHz to 3 GHz ADL5330 RF VGA. For further details pin. Using V for the setpoint voltage, it is possible for the SET and an application schematic, refer to the ADL5330 data sheet. AD8318 to control subsystems, such as power amplifiers (PAs), The voltage applied to the GAIN pin controls the gain of the variable gain amplifiers (VGAs), or variable voltage attenuators AD8367. This voltage, V , is scaled linear-in-dB with a slope (VVAs) that have output power that increases monotonically GAIN of 20 mV/dB and runs from 50 mV at −2.5 dB of gain up to with respect to their gain control signal. 1.0 V at +42.5 dB. To operate in controller mode, the link between VSET and The incoming RF signal to the AD8367 has a varying amplitude VOUT is broken. A setpoint voltage is applied to the VSET level. Receiving and demodulating it with the lowest possible input; VOUT is connected to the gain control terminal of the error requires that the signal levels be optimized for the highest VGA, and the detector RF input is connected to the output of signal-to-noise ratio (SNR) feeding into the analog-to-digital the VGA (usually using a directional coupler and some converters (ADC). This is done by using an automatic gain additional attenuation). Based on the defined relationship control (AGC) loop. In Figure 43, the voltage output of the between V and the RF input signal when the device is in OUT AD8318 modifies the gain of the AD8367 until the incoming measurement mode, the AD8318 adjusts the voltage on VOUT RF signal produces an output voltage that is equal to the (VOUT is now an error amplifier output) until the level at the setpoint voltage V . RF input corresponds to the applied V . SET SET +3V When the AD8318 operates in controller mode, there is no RF INPUT SIGNAL RF OUTPUT SIGNAL defined relationship between V and V voltage; V settles VPOS GND to a value that results in the corrSEeTct inputO UsiTgnal level aOpUpTearing INPT ADV8G3A67 VOUT 0.1µF 174Ω at INHI/INLO. 57.6Ω GAIN HPFL In order for this output power control loop to be stable, a CHP 100pF ground-referenced capacitor is connected to the CLPF pin. 26R12Ω R1k1Ω +5V R10H0PΩ 1B0A0NMDHPzASS This capacitor, C , integrates the error signal (in the form of a FILTER FLT current) to set the loop bandwidth and ensure loop stability. For DAC +VSET VVSOEUTT VPINOHSI 1nF further details on control loop dynamics, refer to the AD8315 SVEOTLPTOAGINET AD8318 INLO data sheet. 10C0FpLFT CLPFGND 1nF 04853-047 Figure 43. AD8318 Operating in Controller Mode to Provide Automatic Gain VGA/VVA RFIN Control Functionality in Combination with the AD8367 DIRECTIONAL The AGC loop is capable of controlling signals over ~45 dB COUPLER GAIN dynamic range. The output of the AD8367 is designed to drive ATTENUATOR CONTROL VOLTAGE loads ≥ 200 Ω. As a result, it is not necessary to use the 53.6 Ω 1nF VOUT resistor at the input of the AD8318; the nominal input imped- INHI ance of 2 kΩ is sufficient. AD8318 52.3Ω VSET DAC If the AD8367 output drives a 50 Ω load, such as an oscilloscope INLO 1nF CLPF or spectrum analyzer, use a simple resistive divider network. CFLT 04853-034 TFihgeu rdei v4i4d esrh uowsesd t hine Ftriganusrefe 4r 3fu hnacst aionn i nosf eorutitopnu tl opsosw oef r1 v1s.5. VdSBE.T Figure 42. AD8318 Controller Mode voltage for a 100 MHz sine wave at −40 dBm into the AD8367. Decreasing V , which corresponds to demanding a higher SET signal from the VGA, tends to increase V . The gain control OUT voltage of the VGA must have a positive sense. A positive control voltage to the VGA increases the gain of the device. Rev. D | Page 19 of 24

AD8318 Data Sheet 0 1.2 10 –5 1.0 0 –10 0.8 MAXIMUM INPUT LEVEL –10 –15 0.6 –20 0.4 –20 P (dBm)OUT–––332505 –000.2.2 ERROR (dB) P (dBm)IN––4300 MINIMUM INPUT LEVEL –40 –0.4 –50 –45 –0.6 –60 –50 –0.8 ––6505 ––11..20 04853-048 ––8700 04853-049 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 VSET (V) VSET (V) Figure 44. AD8367 Output Power vs. AD8318 Setpoint Voltage Figure 46. Setpoint Voltage vs. Input Power. Optimal signal levels must be used to achieve the full 45 dB For the AGC loop to remain locked, the AD8318 must track the dynamic range capabilities of the AD8367. envelope of the VGA output signal and provide the necessary In some cases, if V is >1.0 V it can take an unusually long voltage levels to the AD8367 gain control input. Figure 45 GAIN time for the AGC loop to recover; that is, the output of the shows an oscilloscope screen image of the AGC loop depicted AD8318 remains at an abnormally high value and the gain is set in Figure 43. A 50 MHz sine wave with 50% AM modulation is to its maximum level. A voltage divider is placed between the applied to the AD8367. The output signal from the VGA is a output of the AD8318 and the AD8367 GAIN pin to ensure that constant envelope sine wave with an amplitude corresponding V does not exceed 1.0 V. to a setpoint voltage at the AD8318 of 1.0 V. GAIN In Figure 43, C and R are configured to reduce oscillation HP HP AM MODULATED INPUT and distortion due to harmonics at higher gain settings. Some additional filtering is recommended between the output of the 1 AD8367 and the input of the AD8318. This helps to decrease the output noise of the AD8367, which can reduce the dynamic AD8318 VOUT range of the loop at higher gain settings (smaller V ). SET 2 Response time and the amount of signal integration are controlled by C . This functionality is analogous to the feedback capacitor FLT AD8367 OUTPUT around an integrating amplifier. Though it is possible to use large capacitors for C , in most applications, values under 1 nF FLT 3 provide sufficient filtering. 04853-045 Calibration in controller mode is similar to the method used in CH1 50.0mV CH2 200mV M4.00ms A CH2 64.0mV measurement mode. Do a simple 2-point calibration by applying CH3 20.0mV two known V voltages or DAC codes and measuring the Figure 45. Oscilloscope Screen Image Showing an AM Modulated SET Input Signal to the AD8367. The AD8318 tracks the envelope output power from the VGA. Slope and intercept are calculated of this input signal and applies the appropriate voltage to ensure using Equation 20 to Equation 22: a constant output from the AD8367. Slope = (V − V )/(P − P ) (20) The 45 dB control range is constant for the range of V SET1 SET2 OUT1 OUT2 SET voltages. The input power levels to the AD8367 must be optimized Intercept = POUT1 − VSET1/Slope (21) to achieve this range. In Figure 46, the minimum and maximum V = Slope × (Px − Intercept) (22) SET input power levels are shown vs. setpoint voltage. For more information on AGC applications, refer to the AD8367 data sheet or ADL5330 data sheet. Rev. D | Page 20 of 24

Data Sheet AD8318 CHARACTERIZATION SETUP AND METHODS To measure noise spectral density, the 0 Ω resistor in series with the VOUT pin is replaced with a 1 μF dc blocking capacitor. The general hardware configuration used for the AD8318 The capacitor is used because the Rohde & Schwarz FSEA characterization is shown in Figure 47. The primary setup used spectrum analyzer cannot handle dc voltages at its RF input. for characterization is measurement mode. The characterization The CLPF pin is left open for data collected for Figure 19. For board is similar to the customer evaluation board with the Figure 20, a 1 μF capacitor is placed between CLPF and ground. exception that the RF input has a Rosenberger SMA connector The large capacitor filters the noise from the detector stages and R10 has changed to a 1 kΩ resistor to remove cable of the log amp. Noise spectral density measurements are taken capacitance from the bench characterization setup. Slope and using the FSEA spectrum analyzer and the SMT06 signal intercept are calculated in this data sheet and in the production generator. The signal generator frequency is set to 2.2 GHz. environment using linear regression from −50 dBm to −10 dBm. The spectrum analyzer has a span of 10 Hz, resolution The slope and intercept generate an ideal line. Log conformance bandwidth of 50 Hz, video bandwidth of 50 Hz, and averages error is the difference from the ideal line and the measured the signal 100×. Data is adjusted to account for the dc blocking output voltage for a given temperature in dB. For additional capacitor impedance on the output at lower frequencies. information on the error calculation, refer to the Device Calibration and Error Calculation section. The hardware configuration for pulse response measurement replaces the 0 Ω series resistor at the VOUT pin with a 40 Ω resistor; the CLPF pin remains open. Pulse response time is measured using a Tektronix TDS5104 digital phosphor oscilloscope. Both channels on the scope are configured for 50 Ω termination. The 10 Ω internal series resistance at VOUT, combined with the 40 Ω resistor, attenuates the output voltage level by two. RF input frequency is set to 100 MHz with −10 dBm at the input of the device. The RF burst is generated using a Rohde & Schwarz SMT06 with the pulse option with a period of 1.5 μs, a width of 0.1 μs, and a pulse delay of 0.04 μs. The output response is triggered using the video output from the SMT06. Refer to Figure 47 for an overview of the test setup. ROHDE & SCHWARZ SMT06 TEKTRONIX VIDEO RF OUT TDS5104 OUT –7dBm 5V CH1* CH3* TRIGGER 3dB SPLITTER 1nF VPOS 40Ω *T5E0RΩMINATION INHI VOUT 52.3Ω AD8318 INLO VSET 1nF GND 04853-046 Figure 47. Pulse Response Measurement Test Setup Rev. D | Page 21 of 24

AD8318 Data Sheet EVALUATION BOARD Table 6. Evaluation Board (Rev. A) Bill of Materials Component Function Default Conditions VP, GND Supply and Ground Connections Not Applicable SW1, R3 Device Enable. When in Position A, the ENBL pin is connected to VP and the SW1 = A AD8318 is in operating mode. In Position B, the ENBL pin is grounded through R3 = 10 kΩ (Size 0603) R3, putting the device in power-down mode. The ENBL pin may be exercised by a pulse generator connected to ENBL SMA and SW1 in Position B. R1, C1, C2 Input Interface. The 52.3 Ω resistor (R1) combines with the AD8318 internal R1 = 52.3 Ω (Size 0402) input impedance to give a broadband input impedance of 50 Ω. C1 and C2 are C1 = 1 nF (Size 0402) dc-blocking capacitors. A reactive impedance match can be implemented by C2 = 1 nF (Size 0402) replacing R1 with an inductor and C1 and C2 with appropriately valued capacitors. R2 Temperature Sensor Interface. The temperature sensor output voltage is R2 = 1 kΩ (Size 0402) available at the SMA labeled TEMP via the current limiting resistor, R2. R4 Temperature Compensation Interface. The internal temperature compensation R4 = 499 Ω (Size 0603) resistor is optimized for an input signal of 2.2 GHz when R4 is 500 Ω. This circuit can be adjusted to optimize performance for other input frequencies by changing the value of Resistor R4. See the Temperature Compensation of Output Voltage section. R7, R8, R9, R10 Output Interface—Measurement Mode. In measurement mode, a portion of R7 = 0 Ω = (Size 0402) the output voltage is fed back to the VSET pin via R7. The magnitude of the R8 = open (Size 0402) slope at VOUT can be increased by reducing the portion of VOUT that is fed back R9 = open (Size 0402 to VSET. R10 can be used as a back-terminating resistor or as part of a single- R10 = 0 Ω (Size 0402) pole, low-pass filter. R7, R8, R9, R10 Output Interface—Controller Mode. In this mode, R7 must be open. In R7 = open (Size 0402) controller mode, the AD8318 can control the gain of an external component. A R8 = open (Size 0402) setpoint voltage is applied to the VSET pin, the value of which corresponds to R9 = 0 Ω (Size 0402) the desired RF input signal level applied to the AD8318 RF input. The R10 = 0 Ω (Size 0402) magnitude of the control voltage is optionally attenuated via the voltage divider comprised of R8 and R9, or a capacitor can be installed in R8 to form a low-pass filter along with R9. See the Controller Mode section for more details. C5, C6, C7, C8, R5, R6 Power Supply Decoupling. The nominal supply decoupling consists of a 100 pF C5 = 0.1 µF (Size 0603) filter capacitor placed physically close to the AD8318, a 0 Ω series resistor, and C6 = 100 pF (Size 0402) a 0.1 µF capacitor placed closer to the power supply input pin. C7 = 100 pF (Size 0402) C8 = 0.1 µF (Size 0603) R5 = 0 Ω (Size 0603) R6 = 0 Ω (Size 0603) C9 Loop Filter Capacitor. The low-pass corner frequency of the circuit that drives C9 = open (Size 0603) the VOUT pin can be lowered by placing a capacitor between CLPF and ground. Increasing this capacitor increases the overall rise/fall time of the AD8318 for pulsed input signals. See the Output Filtering section for more details. Rev. D | Page 22 of 24

Data Sheet AD8318 VPOS R4 C5 499Ω R5 0.1µF 0Ω C6 12 11 10 9 100pF R2 CMIP CMIP TADJ VPSO 1kΩ TEMP 13 TEMP CMOP 8 R8 OPEN R1 C1 1nF 14 INHI AD8318 VSET 7 R7 R9 VSET RFIN 52.3Ω C2 1nF 15 INLO VOUT 6 0Ω OPEN 16 ENBL CLPF 5 R10 VOUT 0Ω A B CMIP CMIP VPSI VPSI ENBL VPOS 1 2 3 4 C9 R3 SW1 OPEN 10kΩ C7 R6 100pF GND VP 0Ω VPOS C0.81µF 04853-035 Figure 48. Evaluation Board Schematic 04853-036 04853-037 Figure 49. Component Side Layout Figure 50. Component Side Silkscreen Rev. D | Page 23 of 24

AD8318 Data Sheet OUTLINE DIMENSIONS DETAIL A (JEDEC 95) 4.10 0.35 4.00 SQ 0.30 PIN 1 3.90 0.25 INDICATOR PIN 1 0.65 13 16 1 I(NSDEEIC DAETTAOIRL AAR)EA OPTIONS BSC 12 2.25 EXPOSED 2.10 SQ PAD 1.95 9 4 0.70 8 5 0.20 MIN TOP VIEW 0.60 BOTTOM VIEW 0.50 0.80 FOR PROPER CONNECTION OF 0.75 SIDE VIEW 0.05 MAX THE EXPOSED PAD, REFER TO 0.70 THE PIN CONFIGURATION AND 0.02 NOM FUNCTION DESCRIPTIONS COPLANARITY SECTION OF THIS DATA SHEET. SEATING 0.08 PLANE 0.203 REF PKG-004025/5112 COMPLIANTTOJEDEC STANDARDS MO-220-WGGC. 10-11-2017-B Figure 51. 16-Lead Lead Frame Chip Scale Package [LFCSP] 4 mm × 4 mm Body and 0.75 mm Package Height (CP-16-23) Dimensions shown in millimeters ORDERING GUIDE Ordering Model1, 2 Temperature Range Package Description Package Option Quantity AD8318ACPZ-REEL7 −40°C to +85°C 16-Lead Lead Frame Chip Scale Package [LFCSP] CP-16-23 1,500 AD8318ACPZ-R2 −40°C to +85°C 16-Lead Lead Frame Chip Scale Package [LFCSP] CP-16-23 250 AD8318ACPZ-WP −40°C to +85°C 16-Lead Lead Frame Chip Scale Package [LFCSP] CP-16-23 64 AD8318-EVALZ Evaluation Board 1 Z = RoHS Compliant Part. 2 WP = waffle pack. ©2004–2017 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D04853-0-12/17(D) Rev. D | Page 24 of 24

Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: A nalog Devices Inc.: AD8318ACPZ-REEL7 AD8318-EVALZ AD8318-EP-EVALZ AD8318SCPZ-EP-RL7