50 dB GSM PA Controller Data Sheet AD8315 FEATURES Its high sensitivity allows control at low signal levels, thus reducing the amount of power that must be coupled to Complete RF detector/controller function the detector. >50 dB range at 0.9 GHz (−49 dBm to +2 dBm, re 50 Ω) Accurate scaling from 0.1 GHz to 2.5 GHz For convenience, the signal is internally ac-coupled. This Temperature-stable linear-in-dB response high-pass coupling, with a corner at approximately 0.016 GHz, Log slope of 23 mV/dB, intercept at −60 dBm at 0.9 GHz determines the lowest operating frequency. Therefore, the True integration function in control loop source can be dc grounded. Low power: 20 mW at 2.7 V, 38 mW at 5 V The AD8315 provides a voltage output, VAPC, that has the Power-down to 10.8 μW voltage range and current drive to directly connect to most APPLICATIONS handset power amplifiers’ gain control pin. VAPC can swing from 250 mV above ground to within 200 mV below the supply Single, dual, and triple band mobile handset (GSM, DCS, EDGE) voltage. Load currents of up to 6 mA can be supported. Transmitter power control The setpoint control input is applied to the VSET pin and has GENERAL DESCRIPTION an operating range of 0.25 V to 1.4 V. The associated circuit The AD8315 is a complete low cost subsystem for the precise determines the slope and intercept of the linear-in-dB control of RF power amplifiers operating in the frequency range measurement system; these are nominally 23 mV/dB and 0.1 GHz to 2.5 GHz and over a typical dynamic range of 50 dB. −60 dBm for a 50 Ω termination (−73 dBV) at 0.9 GHz. It is intended for use in cellular handsets and other battery- Further simplifying the application of the AD8315, the input operated wireless devices. The log amp technique provides a much resistance of the setpoint interface is over 100 MΩ, and the bias wider measurement range and better accuracy than controllers current is typically 0.5 μA. using diode detectors. In particular, the temperature stability is The AD8315 is available in MSOP and LFCSP packages and excellent over a specified range of −30°C to +85°C. consumes 8.5 mA from a 2.7 V to 5.5 V supply. When powered down, the sleep current is 4 μA. FUNCTIONAL BLOCK DIAGRAM VPOS LOW NOISE OUTPUT LOW NOISE BAND GAP ENABLE ENBL GAIN BIAS REFERENCE DELAY VAPC ×1.35 HI-Z DET DET DET DET DET LOW NOISE (25nV/√Hz) RFIN RAIL-TO-RAIL BUFFER FLTR 10dB 10dB 10dB 10dB VSET V-I OFFSET INTERCEPT 23mV/dB COMM COMP’N POSITIONING 215.40Vm =V 5T0OdB 01520-001 Figure 1. Rev. D Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Tel: 781.329.4700 ©1999–2016 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com

AD8315 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1  Practical Loop ............................................................................. 15  Applications ....................................................................................... 1  A Note About Power Equivalency ........................................... 15  General Description ......................................................................... 1  Basic Connections ...................................................................... 16  Functional Block Diagram .............................................................. 1  Range on VSET and RFIN ........................................................ 16  Revision History ............................................................................... 2  Transient Response .................................................................... 16  Specifications ..................................................................................... 3  Mobile Handset Power Control Example ............................... 18  Absolute Maximum Ratings ............................................................ 5  Enable and Power-On ................................................................ 18  ESD Caution .................................................................................. 5  Input Coupling Options ............................................................ 19  Pin Configuration and Function Descriptions ............................. 6  Using the Chip Scale Package ................................................... 19  Typical Performance Characteristics ............................................. 7  Evaluation Board ........................................................................ 19  Theory of Operation ...................................................................... 12  Outline Dimensions ....................................................................... 21  Basic Theory ................................................................................ 12  Ordering Guide .......................................................................... 21  Controller-Mode Log Amps ..................................................... 13  Control Loop Dynamics ............................................................ 13  REVISION HISTORY 8/2016—Rev. C to Rev. D Edit to Figure 3 ............................................................................... 10 Changes to Figure 2 and Table 4 ..................................................... 6 Edit to Equation 9 ........................................................................... 10 Added Figure 3; Renumbered Sequentially .................................. 6 Edit to Equation 10 ......................................................................... 10 Updated Outline Dimensions ....................................................... 21 Edit to Equation 11 ......................................................................... 10 Changes to Ordering Guide .......................................................... 21 Edits to Example section ............................................................... 10 Edit to Basic Connections Section ............................................... 12 6/2006—Rev. B to Rev. C Edits to Input Coupling Options Section .................................... 14 Updated Format .................................................................. Universal Table III Becomes Table II ............................................................. 15 Changes to Ordering Guide .......................................................... 23 Table II Recommended Components Deleted ........................... 15 Using the Chip-Scale Package Section Added ............................ 15 1/2003—Rev. 0 to Rev. B Edits to Evaluation Board Section ................................................ 15 Edits to Product Description Section ............................................ 1 Figure 12 Title Edited ..................................................................... 16 Edit to Functional Block Diagram ................................................. 1 Figure 13 Title Edited ..................................................................... 16 Edits to Specifications ...................................................................... 2 8-Lead Chip Scale Package (CP-8) Added .................................. 17 Edits to Absolute Maximum Ratings ............................................. 3 Updated Outline Dimensions ....................................................... 17 Ordering Guide Updated ................................................................. 3 TPC 9 Replaced with New Figure .................................................. 5 10/1999—Revision 0: Initial Version Edits to TPC 27 ................................................................................. 8 Edit to Figure 1 .................................................................................. 9 Rev. D | Page 2 of 22

Data Sheet AD8315 SPECIFICATIONS V = 2.7 V, T = 25°C, 52.3 Ω termination on RFIN, unless otherwise noted. S Table 1. Parameter Test Conditions/Comments Min Typ Max Unit OVERALL FUNCTION Frequency Range1 To meet all specifications 0.1 2.5 GHz Input Voltage Range ±1 dB log conformance, 0.1 GHz −57 −11 dBV Equivalent dBm Range −44 +2 dBm Logarithmic Slope2 0.1 GH 21.5 24 25.5 mV/dB Logarithmic Intercept2 0.1 GHz −79 −70 −64 dBV Equivalent dBm Level −66 −57 −51 dBm RF INPUT INTERFACE Pin RFIN Input Resistance3 0.1 GHz 2.8 kΩ Input Capacitance3 0.1 GHz 0.9 pF OUTPUT Pin VAPC Minimum Output Voltage V ≤ 200 mV, ENBL high 0.25 0.27 0.3 V SET ENBL low 0.02 V Maximum Output Voltage R ≥ 800 Ω 2.45 2.6 V L vs. Temperature4 85°C, V = 3 V, I = 6 mA 2.54 V POS OUT General Limit 2.7 V ≤ V ≤ 5.5 V, R = ∞ V − 0.1 V POS L POS Output Current Drive Source/Sink 5/200 mA/μA Output Buffer Noise 25 nV√Hz Output Noise RF input = 2 GHz, 0 dBm, f = 100 kHz, C = 220 pF 130 nV/√Hz NOISE FLT Small Signal Bandwidth 0.2 V to 2.6 V swing 30 MHz Slew Rate 10% to 90%, 1.2 V step (V ), open loop5 13 V/μs SET Response Time FLTR = open, see Figure 27 150 ns SETPOINT INTERFACE Pin VSET Nominal Input Range Corresponding to central 50 dB 0.25 1.4 V Logarithmic Scale Factor 43.5 dB/V Input Resistance 100 kΩ Slew Rate 16 V/μs ENABLE INTERFACE Pin ENBL Logic Level to Enable Power 1.8 V V POS Input Current when Enable 20 μA High Logic Level to Disable Power 0.8 V Enable Time Time from ENBL high to V within 1% of final value, 4 5 μs APC V ≤ 200 mV, refer to Figure 24 SET Disable Time Time from ENBL low to V within 1% of final value, 8 9 μs APC V ≤ 200 mV, refer to Figure 24 SET Power-On/Enable Time Time from VPOS/ENBL high to V within 1% of final value, 2 3 μs APC V ≤ 200 mV, refer to Figure 29 SET Time from VPOS/ENBL low to V within 1% of final value, 100 200 ns APC V ≤ 200 mV, refer to Figure 29 SET Rev. D | Page 3 of 22

AD8315 Data Sheet Parameter Test Conditions/Comments Min Typ Max Unit POWER INTERFACE Pin VPOS Supply Voltage 2.7 5.5 V Quiescent Current ENBL high 8.5 10.7 mA Over Temperature −30°C ≤ T ≤ +85°C 12.9 mA A Disable Current6 ENBL low 4 10 μA Over Temperature −30°C ≤ T ≤ +85°C 13 μA A 1 Operation down to 0.02 GHz is possible. 2 Mean and standard deviation specifications are available in Table 2 3 See Figure 12 for plot of input impedance vs. frequency. 4 This parameter is guaranteed but not tested in production. Limit is −3 sigma from the mean. 5 Response time in a closed-loop system depends on the filter capacitor (CFLT) used and the response of the variable gain element. 6 This parameter is guaranteed but not tested in production. Maximum specified limit on this parameter is the 6 sigma value. Table 2. Typical Specifications at Selected Frequencies at 25°C (Mean and Sigma) ±1 dB Dynamic Range Slope (mV/dB) Intercept (dBV) Low Point (dBV) High Point (dBV) Frequency (GHz) Mean Sigma Mean Sigma Mean Sigma Mean Sigma 0.1 23.8 0.3 −70.1 1.8 −57.7 1.3 −10.6 0.8 0.9 23.2 0.4 −72.6 1.8 −61.0 1.3 −11.2 0.8 1.9 22.2 0.3 −73.8 1.6 −62.9 0.9 −18.5 1.7 2.5 22.3 0.4 −75.6 1.5 −64.0 1.1 −20.0 1.7 Rev. D | Page 4 of 22

Data Sheet AD8315 ABSOLUTE MAXIMUM RATINGS Stresses at or above those listed under Absolute Maximum Table 3. Ratings may cause permanent damage to the product. This is a Parameter Rating stress rating only; functional operation of the product at these Supply Voltage VPOS 5.5 V or any other conditions above those indicated in the operational Temporary Overvoltage VPOS section of this specification is not implied. Operation beyond (100 cycles, 2 sec duration, ENBL Low) 6.3 V the maximum operating conditions for extended periods may VAPC, VSET, ENBL 0 V, VPOS affect product reliability. RFIN 17 dBm ESD CAUTION Equivalent Voltage 1.6 V rms Internal Power Dissipation 60 mW θ (MSOP) 200°C/W JA θ (LFCSP, Paddle Soldered) 80°C/W JA θ (LFCSP, Paddle Not Soldered) 200°C/W JA Maximum Junction Temperature 125°C Operating Temperature Range −40°C to +85°C Storage Temperature Range −65°C to +150°C Lead Temperature (Soldering 60 sec) MSOP 300°C LFCSP 240°C Rev. D | Page 5 of 22

AD8315 Data Sheet PIN CONFIGURATION AND FUNCTION DESCRIPTIONS RFIN 1 8 VPOS RFIN 1 8 VPOS ENBL 2 7 VAPC ENBL 2 AD8315 7 VAPC AD8315 TOP VIEW VSET 3 TOP VIEW 6 NC VSET 3 (Not to Scale) 6 NC (Not to Scale) FLTR 4 5 COMM NOTES FLTR 4 5 COMM NC = NO CONNECT 01520-002 1. NC = NO CONNECTION. 2.THE EXPOSED PADDLE ON THE UNDERSIDE OGELFRE OTCUHTNERD IPC APALCLAK CNAHEGA EWR MIATUCHST LTEO RBWIES TTSIHOCESLR.DMEARLE DA NTOD A 01520-046 Figure 2. LFCSP Pin Configuration Figure 3. MSOP Pin Configuration Table 4. Pin Function Descriptions Pin No. Mnemonic Description 1 RFIN RF Input. 2 ENBL Connect to VPOS for Normal Operation Connect Pin to Ground for Disable Mode. 3 VSET Setpoint Input. Nominal input range 0.25 V to 1.4 V. 4 FLTR Integrator Capacitor. Connect between FLTR and COMM. 5 COMM Device Common (Ground). 6 NC No Connection. 7 VAPC Output. Control voltage for gain control element. 8 VPOS Positive Supply Voltage: 2.7 V to 5.5 V. EPAD Exposed Paddle. The exposed paddle, on the underside of the LFCSP package only, must be soldered to a ground plane with low thermal and electrical characteristics. Rev. D | Page 6 of 22

Data Sheet AD8315 TYPICAL PERFORMANCE CHARACTERISTICS 10 23 4 0 13 3 2.5GHz V)–10 3 m) 2 B B 0.1GHz 1.9GHz 0.9GHz d d E (–20 –7 E ( 1 LITUD–30 0.1GHz –17LITUD R (dB) 0 P P O AM–40 –27AM RR T 0.9GHz T E–1 U 2.5GHz U P–50 –37P N N F I F I –2 R–60 –47R 1.9GHz –3 –70 –57 –800.2 0.4 0.6 0V.S8ET (V) 1.0 1.2 1.4 –67 01520-003 –40.2 0.4 0.6 0.8VSET (V1).0 1.2 1.4 1.6 01520-006 Figure 4. Input Amplitude vs. VSET Figure 7. Log Conformance vs. VSET 10 4 10 4 –30°C 0 3 0 3 +25°C (+3dBm) –10 2 (+3dBm)–10 2 +85°C +85°C RF INPUTMPLITUDE (dBV) –––234000 +25°C –30°C +85°C 10–1ERROR (dB) RF INPUTMPLITUDE (dBV) –––234000 +25°C –30°C 10–1ERROR (dB) A A –50 –2 –50 –2 +25°C (–47dBm) –60 ERROR AT +85°C AND –30°C –3 (–47dBm)–60 ERROR AT +85°C AND –30°C –3 BASED ON DEVIATION FROM +85°C BASED ON DEVIATION FROM –700.1 0.3 0.5 SLO0P.7VES AENT D(V 0I)N.9TERCE1P.1T AT +215.3°C 1.5–4 01520-004 –700.1 0.3–30°C0.5SLOPE0. 7AVNSEDT I N(VT0).E9RCEPT1 .A1T +25°1C.3 1.5–4 01520-007 Figure 5. Input Amplitude and Log Conformance vs. VSET at 0.1 GHz Figure 8. Input Amplitude and Log Conformance vs. VSET at 1.9 GHz 10 4 10 4 +85°C 0 3 0 3 –30°C (+3dBm)–10 +25°C 2 (+3dBm)–10 2 RF INPUTAMPLITUDE (dBV) –––234000 ++2855°°CC –30°C 10–1ERROR (dB) RF INPUTAMPLITUDE (dBV)–––234000 +25°C –30°C +85°C 10–1ERROR (dB) –50 –2 –50 –2 +25°C (–47dBm)––67000.1 0.3 0.5 EBSRLAORS0OEP.7VDERS AOAENTNT D (+DV 08IE)N.59VT°CIEA RATCINOED1NP. 1– TF3 RA0°OTC M+215.3°C 1.5––34 01520-005 (–47dBm)––67000.+185°C 0.3–30°C0.5EBSRLAORSOEPDE0R. 7AOAVNNSTED +DT 8I EN(5VVT0°)IC.EA9 RTACINOEDNP – TF13 .R0A1°OTC M+25°1C.3 1.5––34 01520-008 Figure 6. Input Amplitude and Log Conformance vs. VSET at 0.9 GHz Figure 9. Input Amplitude and Log Conformance vs. VSET at 2.5 GHz Rev. D | Page 7 of 22

AD8315 Data Sheet 4 4 –30°C +85°C 3 3 2 2 1 1 B) B) d d R ( 0 R ( 0 O O R R R R E –1 E –1 +85°C –30°C –2 –2 ERROR AT +85°C AND –30°C –3 BASED ON DEVIATION FROM –3 ERROR AT +85°C AND –30°C BASED ON DEVIATION FROM SLOPE AND INTERCEPT AT +25°C SLOPE AND INTERCEPT AT +25°C –4 –4 –80 –70 –60 –50 –40 –30 –20 –10 0 –80 –70 –60 –50 –40 –30 –20 –10 0 (–47dBRmF) INPUT AMPLITUDE (dBV) (+3dBm) 01520-009 (–47dRBFm I)NPUT AMPLITUDE (dBV) (+3dBm) 01520-012 Figure 10. Distribution of Error at Temperature After Ambient Normalization vs. Figure 13. Distribution of Error at Temperature After Ambient Normalization vs. Input Amplitude, 3 Sigma to Either Side of Mean, 0.1 GHz Input Amplitude, 3 Sigma to Either Side of Mean, 1.9 GHz 4 4 3 3 –30°C 2 2 B) 1 B) 1 d d OR ( 0 OR ( 0 R R R R E –1 E –1 –2 +85°C –2 –30°C –3 ERROR AT +85°C AND –30°C –3 ERROR AT +85°C AND –30°C +85°C BASED ON DEVIATION FROM BASED ON DEVIATION FROM SLOPE AND INTERCEPT AT +25°C SLOPE AND INTERCEPT AT +25°C –4 –4 –80 –70 –60 –50 –40 –30 –20 –10 0 –80 –70 –60 –50 –40 –30 –20 –10 0 (–47dBRmF) INPUT AMPLITUDE (dBV) (+3dBm) 01520-010 (–47dBRmF) INPUT AMPLITUDE (dBV) (+3dBm) 01520-013 Figure 11. Distribution of Error at Temperature After Ambient Normalization vs. Figure 14. Distribution of Error at Temperature After Ambient Normalization vs. Input Amplitude, 3 Sigma to Either Side of Mean, 0.9 GHz Input Amplitude, 3 Sigma to Either Side of Mean, 2.5 GHz 3000 0 10 2700 –200 2400 –400 8 FREQUENCY MSOPCHIP SCALE (LFCSP) 2100 0(G.1Hz) 290R0 ––jjX19Ω00 270R0 ––jjX15Ω00 –600 mA) STANCE (Ω)11850000 X (LFCSP) 012...995 711037000 –––jjj2874000 744364000 –––jjj211231000 ––1800000CTANCE (Ω) CURRENT ( 6 RESI1200 R X –1200 REA PPLY 4 DECREASING INCREASING 900 X (MSOP) –1400 SU VENBL VENBL 600 R (LFCSP) –1600 2 300 –1800 R (MSOP) 00 0.5 FR1E.0QUENCY (G1.H5z) 2.0 2.5–2000 01520-011 01.3 1.4 VEN1B.5L (V) 1.6 1.7 01520-014 Figure 12. Input Impedance Figure 15. Supply Current vs. VENBL Rev. D | Page 8 of 22

Data Sheet AD8315 25 –66 –68 24 +85°C –70 mV/dB) 23 +85°C T (dBV)–72 SLOPE ( 22 –30°C +25°C NTERCEP–74 +25°C –30°C I –76 21 –78 200 0.5 FR1E.0QUENCY (1G.H5z) 2.0 2.5 01520-015 –800 0.5 FRE1Q.0UENCY (G1H.z5) 2.0 2.5 01520-018 Figure 16. Slope vs. Frequency; −30°C, +25°C, and +85°C Figure 19. Intercept vs. Frequency; −30°C, +25°C, and +85°C 24 –68 0.1GHz 0.1GHz –70 0.9GHz B) 23 BV)–72 0.9GHz mV/d T (d SLOPE ( 22 1.9GHz NTERCEP––7746 1.9GHz I 2.5GHz 2.5GHz –78 21 –80 2.5 3.0 3.5 V4S. 0(V) 4.5 5.0 5.5 01520-016 2.5 3.0 3.5 VS4 .(0V) 4.5 5.0 5.5 01520-019 Figure 17. Slope vs. Supply Voltage Figure 20. Intercept vs. Supply Voltage 45 0 10000 40 CFLT= 0pF –10 CFLT= 220pF, RF INPUT = 2GHz 35 –20 30 –30 Hz) R–F5 1INdPBUVT 25 –40 V/√ AMPLITUDE (dB)–11–210550050 –––––––6815791000000100HASE (Degrees) ECTRAL DENSITY (n1010000 –23dBV –13–d4B8VdB–3V3dBV–43dBV –15 CFLT= 220pF –120P SP –20 –130 E S –25 OI –53dBV AND –30 N –63dBV –35 –4010 100 1kFREQU1E0NkCY (Hz)100k 1M 10M 01520-017 10100 1k F1R0EkQUENCY1 (0H0zk) 1M 10M 01520-020 Figure 18. AC Response from VSET to VAPC Figure 21. VAPC Noise Spectral Density Rev. D | Page 9 of 22

AD8315 Data Sheet 3.5 2.8 3.3 2mA 2.7 3.1 0mA V) V) (APC2.9 4mA (APC2.6 V V 6mA 2.7 2.5 2.5 SHADINGINDICATES ±3 SIGMA 2.32.7 2.8 2.9 S3U.P0PLYV3O.1LTAGE3 .(2V) 3.3 3.4 3.5 01520-021 2.42.7 2S.8UPPLY VOLTAGE (2V.)9 3.0 01520-024 Figure 22. Maximum VAPC Voltage vs. Supply Voltage by Load Current Figure 25. Maximum VAPC Voltage vs. Supply Voltage with 4 mA Load Current AVERAGE=16SAMPLES AVERAGE = 16 SAMPLES VAPC 200mVPERVERTICAL DIVISION 1V PER VERTICAL DIVISION VAPC GND GND 2µs PER PULSED RF 1V PER HORIZONTAL 0.1GHz,–13dBV VERTICAL DIVISION RF DIVISION INPUT GND VENBL 100ns PER GND 01520-022 HDOIVRISIZIOONNTAL 01520-025 Figure 23. ENBL Response Time Figure 26. VAPC Response Time, Full-Scale Amplitude Change, Open-Loop GERSNS IAEMGRNNTAD0AT3 LSOR 1O0UMTHPzU RTEF TIMEBASE STAGNENFPOEURRLASDET DOSR345 TORUITG RG AENSPNDIUEG SLRN SAASETMLOTR03 P1O0UUMLTHSPEzU RTMEOFDE IN EXTTORUIGT PPIUCLOPSUSELE SCLEAOBNSD TORUITG RF OUT PULSE OUT MODMUOLDAETION GENERATOR RF OUT PULSE OUT 2.7V RF SPLITTER –3dB 0.1µF TEK P6205 –3dB 2.7V FET PROBE AD8315 0.1µF TRIG 1 RFIN VPOS 8 AD8315 TRIG 52.3Ω 2 ENBL VAPC 7 FTEETK P PR6O20B5E TEKSCTDOSP6E94C 52.3Ω 2.7V 12 RENFIBNL VVAPPOCS 78 FTEETK P PR6O20B5E TEKSTCDOSP6E94C 3 VSET NC 6 0.3V 3 VSET NC 6 4 FLTR COMM 5 220pF NC = NO CONNECT 01520-023 NC 4NCF L=T RNO COCONNMEMCT5 01520-026 Figure 24. Test Setup for ENBL Response Time Figure 27. Test Setup for VAPC Response Time Rev. D | Page 10 of 22

Data Sheet AD8315 AVERAGE=16SAMPLES 500mV PER VERTICAL VAPC DIVISION 200mV PER GND VAPC VERTICAL GND DIVISION 1V PER 2µs PER 1V PER 2µs PER VERTICAL HORIZONTAL VERTICAL HORIZONTAL VS DIVISION DIVISION DIVISION DIVISION AND VENBL VS GND 01520-027 GND AVERAGE=16SAMPLES 01520-029 Figure 28. Power-On and Power-Off Response with VSET Grounded Figure 30. Power-On and Power-Off Response with VSET and ENBL Grounded RS AMNTD03 S 1O0UMTHPzU RTEF EXTTRIG STANFPOURLDSE DS345 TORUITG RS AMNTD03 S 1O0UMTHPzU RTEF EXTTRIG STANFPOURLDSE DS345 TORUITG SIGNAL GENERATOR SIGNAL GENERATOR GENERATOR GENERATOR PULSE OUT PULSE OUT RF OUT RF OUT AD811 AD811 49.9Ω 49.9Ω 732Ω 732Ω AD8315 AD8315 TEK P6205 TEK P6205 1 RFIN VPOS 8 FET PROBE TRIG 1 RFIN VPOS 8 FET PROBE TRIG 52.3Ω 52.3Ω 2 ENBL VAPC 7 2 ENBL VAPC 7 TEK P6205 TEKTDS694C TEK P6205 TEKTDS694C FET PROBE SCOPE FET PROBE SCOPE 3 VSET NC 6 3 VSET NC 6 4 FLTR COMM 5 4 FLTR COMM 5 220pF NC = NO CONNECT 01520-028 220pF NC = NO CONNECT 01520-030 Figure 29. Test Setup for Power-On and Power-Off Response with VSET Grounded Figure 31. Test Setup for Power-On and Power-Off Response with VSET and ENBL Grounded Rev. D | Page 11 of 22

AD8315 Data Sheet THEORY OF OPERATION The AD8315 is a wideband logarithmic amplifier (log amp) This corresponds to a power level of −57 dBm when the net similar in design to the AD8313 and AD8314. However, it is resistive part of the input impedance of the log amp is 50 Ω. strictly optimized for use in power control applications rather However, both the slope and the intercept are dependent on than as a measurement device. Figure 32 shows the main features frequency (see Figure 16 and Figure 19). in block schematic form. The output (Pin 7, VAPC) is intended Keeping in mind that log amps do not respond to power but to be applied directly to the automatic power-control (APC) pin only to voltages and that the calibration of the intercept is of a power amplifier module. waveform dependent and is only quoted for a sine wave signal, BASIC THEORY the equivalent power response can be written as Logarithmic amplifiers provide a type of compression in which VOUT = VDB (PIN − PZ) (2) a signal having a large range of amplitudes is converted to one where: of smaller range. The use of the logarithmic function uniquely P , the input power, and P , the equivalent intercept, are both IN Z results in the output representing the decibel value of the input. expressed in dBm (thus, the quantity in parentheses is simply a The fundamental mathematical form is: number of decibels). V V log VIN (1) VDB is the slope expressed as so many mV/dB. OUT SLP 10 V For a log amp having a slope VDB of 24 mV/dB and an intercept Z at −57 dBm, the output voltage for an input power of –30 dBm Here V is the input voltage, V is called the intercept (voltage) IN Z is 0.024 [−30 − (−57)] = 0.648 V. because when V = V the argument of the logarithm is unity IN Z Further details about the structure and function of log amps can and thus the result is zero, and V is called the slope (voltage), SLP be found in data sheets for other log amps produced by Analog which is the amount by which the output changes for a certain Devices, Inc. Refer to the AD640 data sheet and AD8307 data change in the ratio (V /V). When BASE-10 logarithms are used, IN Z sheet, both of which include a detailed discussion of the basic denoted by the function log , V represents the volts/decade, 10 SLP principles of operation and explain why the intercept depends and since a decade corresponds to 20 dB, V /20 represents the SLP on waveform, an important consideration when complex volts/dB. For the AD8315, a nominal (low frequency) slope of modulation is imposed on an RF carrier. 24 mV/dB was chosen, and the intercept V was placed at the Z equivalent of −70 dBV for a sine wave input (316 μV rms). (PRECISE GAIN (PRECISE SLOPE (ELIMINATES CONTROL) CONTROL) GLITCH) VPOS LOW NOISE OUTPUT LOW NOISE BAND GAP ENABLE ENBL GAIN BIAS REFERENCE DELAY (CURRENT-MODE SIGNAL) VAPC ×1.35 HI-Z DET DET DET DET DET LOW NOISE (25nV/√Hz) RFIN RAIL-TO-RAIL BUFFER FLTR 10dB 10dB 10dB 10dB (CURRENT- (CURRENT-MODE NULLING FEEDBACK) VSET MODE) V-I OFFSET INTERCEPT 23mV/dB (PACDODMLEM) (WEACKO GMMP ’SNTAGE) POSITIONING (FFSIOLMTRAE GLRLH C zIN ARTPIEPARPCLNITEAO)LR 215.40Vm =V 5T0OdB 01520-031 Figure 32. Block Schematic Rev. D | Page 12 of 22

Data Sheet AD8315 The intercept need not correspond to a physically realizable In a device intended for measurement applications, this current part of the signal range for the log amp. Therefore, the specified is converted to an equivalent voltage, to provide the log (V ) IN intercept is −70 dBV, at 0.1 GHz, whereas the smallest input for function shown in Equation 1. However, the design of the AD8315 accurate measurement (a +1 dB error, see Table 2) at this frequency differs from standard practice in that the output must be a low is higher, being about −58 dBV. At 2.5 GHz, the +1 dB error point noise control voltage for an RF power amplifier not a direct shifts to −64 dBV. This positioning of the intercept is deliberate measure of the input level. Furthermore, it is highly desirable that and ensures that the V voltage is within the capabilities of this voltage be proportional to the time integral of the error SET certain DACs, whose outputs cannot swing below 200 mV. between the actual input V and the dc voltage V (applied to IN SET Figure 33 shows the 100 MHz response of the AD8315; the Pin 3, VSET) that defines the setpoint, that is, a target value for vertical axis does not represent the output (at pin VAPC) but the power level, typically generated by a DAC. the value required at the power control pin, VSET, to null the This is achieved by converting the difference between the sum control loop. of the detector outputs (still in current form) and an internally 1.5 generated current proportional to VSET to a single-sided, current- 1.416V @ –11dBV mode signal. This, in turn, is converted to a voltage (at Pin 4, FLTR, the low-pass filter capacitor node) to provide a close approximation to an exact integration of the error between the B 1.0 mV/d power present in the termination at the input of the AD8315 VSET SLOPE = 24 ACTUAL athned g trhoeu nsedt-proefienrte vnoceltda gfiel.t eFri ncaapllayc, ittohre CvoFLlTt aisg be udfefevreeldo pbeyd a ascpreocsias l low noise amplifier of low voltage gain (×1.35) and presented at 0.5 Pin 7 (VAPC) for use as the control voltage for the RF power amplifier. This buffer can provide rail-to-rail swings and can 0.288V @ –58dBV drive a substantial load current, including large capacitors. Note that the RF power amplifier is assumed to have a positive slope –70dBV IDEAL 0 with RF power increasing monotonically with an increasing 100µV 1mV 10mV 100mV 1V (RMS) –80dBV –60dBV –40dBV –20dBV 0dBV APC control voltage. –67dBm –47dBm VIN,– d27BdVBINm, PIN –7dBm +13dBm (RE 50Ω) 01520-032 CONTROL LOOP DYNAMICS Figure 33. Basic Calibration of the AD8315 at 0.1 GHz To understand how the AD8315 behaves in a complete control CONTROLLER-MODE LOG AMPS loop, an expression for the current in the integration capacitor as a function of the input V and the setpoint voltage V must The AD8315 combines the two key functions required for the IN SET be developed (see Figure 34). measurement and control of the power level over a moderately wide dynamic range. First, it provides the amplification needed VSET SETPOINT ISET = VSET/4.15kΩ to respond to small signals in a chain of four amplifier/limiter 3 VSET INTERFACE cells (see Figure 32), each having a small signal gain of 10 dB and a bandwidth of approximately 3.5 GHz. At the output of each of RFIN FLTR VAPC LOGARITHMIC these amplifier stages is a full-wave rectifier, essentially a square 1 RF DETECTION 4 ×1.35 7 VIN SUBSYSTEM IDET IERR lcauwr rdeentte chtaovri cnegl l atnh aatv ceornavgeer vtsa tluhee RthFa ts iignncarle vaosletsa gweist hto s aig fnluaclt uleavteinl.g IDET = ISLPlog10 (VIN/VZ) CFLT 01520-033 A further passive detector stage is added before the first stage. Figure 34. Behavioral Model of the AD8315 These five detectors are separated by 10 dB, spanning some 50 dB First, the summed detector currents are written as a function of of dynamic range. Their outputs are each in the form of a the input differential current, making summation a simple matter. It is I = I log (V /V ) (3) readily shown that the summed output can closely approximate DET SLP 10 IN Z a logarithmic function. The overall accuracy at the extremes of where: this total range, viewed as the deviation from an ideal logarithmic IDET is the partially filtered demodulated signal, whose response, that is, the log conformance error, can be judged by exact average value is extracted through the subsequent referring to Figure 7, which shows that errors across the central integration step. 40 dB are moderate. Other performance curves show how ISLP is the current-mode slope and has a value of 115 μA per conformance to an ideal logarithmic function varies with decade (that is, 5.75 μA/dB). supply voltage, temperature, and frequency. VIN is the input in V rms. V is the effective intercept voltage, which, as previously noted, Z is dependent on waveform but is 316 μV rms (−70 dBV) for a sine wave input. Rev. D | Page 13 of 22

AD8315 Data Sheet Now the current generated by the setpoint interface is simply Furthermore, to characterize the gain control function, this form is used I = V /415 kΩ (4) SET(4) SET   The difference between this current and I is applied to the V G V 10VAPCVGBC (9) DET PA O CW loop filter capacitor C . It follows that the voltage appearing FLT where: on this capacitor, V , is the time integral of the difference FLT G is the gain of the power amplifier when V = 0. current: O APC V is the gain scaling. GBC V (s) = (I − I )/sC (5) FLT SET DET FLT While few amplifiers conform so conveniently to this law, it   VSET 4.15kΩISLP log10 VIN VZ (6) provides a clearer starting point for understanding the more sC complex situation that arises when the gain control law is less ideal. FLT The control output V is slightly greater than this, because the This idealized control loop is shown in Figure 35. With some APC gain of the output buffer is ×1.35. In addition, an offset voltage manipulation, it is found that the characteristic equation of this is deliberately introduced in this stage; this is inconsequential system is because the integration function implicitly allows for an arbitrary V V V V log kG V V  V s SET GBC SLP GBC 10 O CW Z (10) constant to be added to the form of Equation 6. The polarity is APC 1sT such that V rises to the maximum value for any value of V O APC SET greater than the equivalent value of V . In practice, the V where: IN APC output rails to the positive supply under this condition unless k is the coupling factor from the output of the power amplifier the control loop through the power amplifier is present. In other to the input of the AD8315 (for example, ×0.1 for a 20 dB coupler). words, the AD8315 seeks to drive the RF power to the maximum TO is a modified time constant (VGBC/VSLP)T. value whenever it falls below the setpoint. The use of exact This is quite easy to interpret. First, it shows that a system of integration results in a final error that is theoretically 0, and the this sort exhibits a simple single-pole response, for any power logarithmic detection law ideally results in a constant response level, with the customary exponential time domain form for time following a step change of either the setpoint or the power either increasing or decreasing step polarities in the demand level, if the power-amplifier control function were likewise linear in level V or the carrier input V . Second, it reveals that the SET CW dB. However, this latter condition is rarely true, and it follows that final value of the control voltage V is determined by several APC in practice, the loop response time depends on the power level, fixed factors: and this effect can strongly influence the design of the control loop.       V τ  V V V log kG V V (11) APC SET GBC SLP 10 O CW Z Equation 6 can be restated as Example   V V log V V V s SET SLP 10 IN Z Assume that the gain magnitude of the power amplifier runs APC sT (7) from a minimum value of ×0.316 (−10 dB) at V = 0 to ×100 APC where V is the volts-per-decade slope from Equation 1, having a (40 dB) at V = 2.5 V. Applying Equation 9, G = 0.316 and SLP APC O value of 480 mV/decade, and T is an effective time constant for V = 1 V. Using a coupling factor of k = 0.0316 (that is, a GBC the integration, being equal to 4.15 kΩ × C /1.35; the resistor 30 dB directional coupler) and recalling that the nominal value FLT value comes from the setpoint interface scaling Equation 4 and of V is 480 mV and V = 316 μV for the AD8315, first calculate SLP Z the factor 1.35 arises because of the voltage gain of the buffer. the range of values needed for V to control an output range of SET Therefore, the integration time constant can be written as +33 dBm to −17 dBm. This can be found by noting that, in the steady state, the numerator of Equation 7 must be 0, that is: T = 3.07 C in μs, when C is expressed in nF (8) FLT V = V log (kV /V ) (12) To simplify our understanding of the control loop dynamics, SET SLP 10 PA Z begin by assuming that the power amplifier gain function is where V is expanded to kV , the fractional voltage sample of IN PA actually linear in dB, and for the moment, use voltages to the power amplifier output. For 33 dBm, V = 10 V rms, which PA express the signals at the power amplifier input and output. evaluates to Let the RF output voltage be V and let the input be V . PA CW V (max) = 0.48 log (316 mV/316 μV) = 1.44 V (13) SET 10 For a delivered power of −17 dBm, V = 31.6 mV rms PA V (min) = 0.48 log (1 mV/316 μV) = 0.24 V (14) SET 10 Check that the power range is 50 dB, which must correspond to a voltage change in V of 50 dB × 24 mV/dB = 1.2 V, SET which agrees. Rev. D | Page 14 of 22

Data Sheet AD8315 Now, the value of V is of interest, although it is a dependent Then, it is readily shown that APC parameter, inside the loop. It depends on the characteristics of V = 20 (V − V)/(P − P) (18) GBC 2 1 2 1 the power amplifier, and the value of the carrier amplitude V . CW This must be used to calculate the filter capacitance. The Using the control values previously derived, that is, G = 0.316 O response time at high and low power levels (on the shoulders and V = 1 V, and assuming the applied power is fixed at GBC of the curve shown in Figure 36) is slower. Note also that it is −7 dBm (so V = 100 mV rms), the following is true using CW sometimes useful to add a 0 in the closed-loop response by Equation 11 placing a resistor in series with C . For more information on FLT V (max) = (V V )/V − log kG V /V APC SET GBC SLP 10 O CW Z this, see the Transient Response section. = (1.44 × 1)/0.48 − log10(0.0316 × 0.316 × 0.1/316 μV) V2, P2 33 = 3.0 − 0.5 = 2.5 V (15) V (min) = (V V )/V − log kG V /V APC SET GBC SLP 10 O CW Z = (0.24 × 1)/0.48 − log (0.0316 × 0.316 × 0.1/316 μV) 23 10 = 0.5 − 0.5 = 0 (16) m) both of which results are consistent with the assumptions made dB13 about the amplifier control function. Note that the second term (RF P is independent of the delivered power and a fixed function of the drive power. 3 DIRECTIONAL COUPLER VRF RFPA RTOFVD2C.RW5IGVHEz:UP –70 0.5 V1, P1 1.0VAPC (V)1.5 2.0 2.5 01520-035 Figure 36. Typical Power-Control Curve VIN= kVRF A NOTE ABOUT POWER EQUIVALENCY VSET AD8315 VAPC In using the AD8315, it must be understood that log amps do RESPONSE-SHAPING not fundamentally respond to power. It is for this reason that OLFOOOVPE (REAXTLELRCNOANLT RCOAPL-) CFLT 01520-034 duBseVd (mdeectirbice los fa bdoBvme .1 T Vh erm dsB)V ar sec uasliendg r iast hfiexre tdh,a inn dtheep ceonmdemnot nolfy Figure 35. Idealized Control Loop for Analysis termination impedance, while the corresponding power level is Finally, using the loop time constant for these parameters and not. For example, 224 mV rms is always −13 dBV (with one an illustrative value of 2 nF for the filter capacitor CFLT further condition of an assumed sinusoidal waveform; see the T = (V /V ) T AD640 data sheet for more information about the effect of O GBC SLP waveform on logarithmic intercept), and this corresponds to a = (1/0.48)3.07 μs × 2 (nF) = 12.8 μs (17) power of 0 dBm when the net impedance at the input is 50 Ω. PRACTICAL LOOP When this impedance is altered to 200 Ω, however, the same At present time, power amplifiers, or VGAs preceding such voltage corresponds to a power level that is four times smaller (P = V2/R) or −6 dBm. A dBV level can be converted to dBm in amplifiers, do not provide an exponential gain characteristic. It the special case of a 50 Ω system and a sinusoidal signal by follows that the loop dynamics (the effective time constant) simply adding 13 dB (0 dBV is then, and only then, equivalent varies with the setpoint because the exponential function is to 13 dBm). unique in providing constant dynamics. The procedure must therefore be as follows. Beginning with the curve usually provided Therefore, the external termination added ahead of the AD8315 for the power output vs. the APC voltage, draw a tangent at the determines the effective power scaling. This often takes the form of point on this curve where the slope is highest (see Figure 36). a simple resistor (52.3 Ω provides a net 50 Ω input), but more Using this line, calculate the effective minimum value of the elaborate matching networks can be used. The choice of impedance variable VGBC and use it in Equation 17 to determine the time determines the logarithmic intercept, that is, the input power constant. Note that the minimum in VGBC corresponds to the for which the VSET vs. PIN function crosses the baseline if that maximum rate of change in the output power vs. VAPC. relationship were continuous for all values of VIN. For example, suppose it is found that, for a given drive power, This is never the case for a practical log amp; the intercept (so many the amplifier generates an output power of P1 at VAPC = V1 and dBV) refers to the value obtained by the minimum error straight P2 at VAPC = V2. line fit to the actual graph of VSET vs. PIN (more generally, VIN). Rev. D | Page 15 of 22

AD8315 Data Sheet Where the modulation is complex, as in CDMA, the calibration In a power control loop, the AD8315 provides both the detector of the power response must be adjusted; the intercept remains and controller functions. A sample of the power amplifier (PA) stable for any given arbitrary waveform. When a true power output power is coupled to the RF input of the AD8315, usually (waveform independent) response is needed, a mean-responding via a directional coupler. In dual-mode applications, where detector, such as the AD8361, must be considered. there are two PAs and two directional couplers, the outputs of the directional couplers can be passively combined (both PAs The logarithmic slope, V in Equation 1, which is the amount SLP will never be turned on simultaneously) before being applied to by which the setpoint voltage must be changed for each decibel of the AD8315. input change (voltage or power), is, in principle, independent of waveform or termination impedance. In practice, it usually falls A setpoint voltage is applied to VSET from the controlling off somewhat at higher frequencies, due to the declining gain of source (generally, this is a DAC). Any imbalance between the the amplifier stages and other effects in the detector cells (see RF input level and the level corresponding to the setpoint voltage is Figure 16). corrected by the AD8315 VAPC output that drives the gain control terminal of the PA. This restores a balance between the actual BASIC CONNECTIONS power level sensed at the input of the AD8315 and the value Figure 37 shows the basic connections for operating the determined by the setpoint. This assumes that the gain control AD8315, and Figure 38 shows a block diagram of a typical sense of the variable gain element is positive, that is, an increasing application. The AD8315 is typically used in the RF power voltage from VAPC tends to increase gain. control loop of a mobile handset. V can swing from 250 mV to within 100 mV of the supply APC A supply voltage of 2.7 V to 5.5 V is required for the AD8315. rail and can source up to 6 mA. If the control input of the PA The supply to the VPOS pin must be decoupled with a low must source current, a suitable load resistor can be connected inductance 0.1 μF surface-mount ceramic capacitor, close to the between VAPC and COMM. The output swing and current device. The AD8315 has an internal input coupling capacitor. sourcing capability of VAPC is shown in Figure 22. This negates the need for external ac coupling. This capacitor, RANGE ON VSET AND RFIN along with the low frequency input impedance of the device of approximately 2.8 kΩ, sets the minimum usable input frequency to The relationship between the RF input level and the setpoint around 0.016 GHz. A broadband 50 Ω input match is achieved voltage follows from the nominal transfer function of the device in this example by connecting a 52.3 Ω resistor between RFIN (see Figure 5, Figure 6, Figure 8, and Figure 9). At 0.9 GHz, for and ground. A plot of input impedance vs. frequency is shown example, a voltage of 1 V on VSET indicates a demand for −30 dBV in Figure 12. Other coupling methods are also possible (see (−17 dBm, re 50 Ω) at RFIN. The corresponding power level at the Input Coupling Options section). output of the power amplifier is greater than this amount due to the attenuation through the directional coupler. R1 C1 52.3Ω AD8315 0.1µF For setpoint voltages of less than approximately 250 mV, V APC RFIN 1 RFIN VPOS 8 +VS (2.7VTO5.5V) remains unconditionally at the minimum level of approximately +VS 2 ENBL VAPC 7 +VAPC 250 mV. This feature can prevent any spurious emissions during VSET 3 VSET NC 6 power-up and power-down phases. CFLT 4NCF L=T NRO COCNONMEMCT5 01520-036 cAobrorevsep 2o5n0d minVg , tVo SaE Td hyansa ma liicn reaanr gceo notfr 5o0l rdaBn.g Te huips rteos 1u.l4ts V in, a Figure 37. Basic Connections slope of 23 mV/dB or approximately 43.5 dB/V. TRANSIENT RESPONSE DIRECTIONAL POWER RFIN COUPLER AMP The time domain response of power amplifier control loops, using any kind of controller, is only partially determined by the ATTENUATOR GAIN choice of filter, which, in the case of the AD8315, has a true CONTROL VOLTAGE integrator form 1/sT, as shown in Equation 7, with a time constant VAPC given by Equation 8. The large signal step response is also strongly AD8315 dependent on the form of the gain-control law. Nevertheless, some RFIN VSET DAC simple rules can be applied. When the filter capacitor C is very FLT 52.3Ω large, it dominates the time domain response, but the incremental FLTR bandwidth of this loop still varies as V traverses the nonlinear CFLT 01520-037 gain-control function of the PA, as shAPoCwn in Figure 36. Figure 38. Typical Application Rev. D | Page 16 of 22

Data Sheet AD8315 This bandwidth is highest at the point where the slope of the This is a classic aspect of control loop design. The lowest tangent drawn on this curve is greatest, that is, for power outputs permissible value of C must be determined experimentally for a FLT near the center of the PA range, and is much reduced at both particular amplifier. For GSM and DCS power amplifiers, C FLT the minimum and the maximum power levels, where the slope typically ranges from 150 pF to 300 pF. of the gain control curve is lowest due to the S-shaped form. In many cases, some improvement in the worst-case response Using smaller values of C , the loop bandwidth generally time can be achieved by including a small resistance in series FLT increases in inverse proportion to the value. Eventually, however, a with C ; this generates an additional 0 in the closed-loop transfer FLT secondary effect appears due to the inherent phase lag in the power function, that serves to cancel some of the higher order poles in amplifier control path, some of which can be due to parasitic or the overall loop. A combination of main capacitor C shunted FLT deliberately added capacitance at the VAPC pin. This results in by a second capacitor and resistor in series is also useful in the characteristic poles in the ac loop equation moving off the minimizing the settling time of the loop. real axis and thus becoming complex (and somewhat resonant). 3.5V 4.7µF 4.7µF 1000pF 1000pF BAND SELECT 0V/2V TO LDC15D190A0007A POUTGSM ANTENNA 7 1 35dBm MAX VCTL PINGSM 3dBm 8 4 49.9Ω PF08107B 5 3 PINDCS 2 6 POUTDCS VAPC 3dBm 32dBm MAX ATTN 500Ω 20dB (OPTIONAL, SEETEXT) 0.1µF R1 AD8315 52.3Ω 1 RFIN VPOS 8 +VS 2.7V R21 E0NVA/2B.L7EV 2 ENBL VAPC 7 8-BIT 600Ω RAMPDAC 3 VSET NC 6 0V TO 2.55V R31 1kΩ 4 FLTR COMM 5 150pF S1RE2E, TRE3 XOTPTIONAL, 1.5kΩ NC = NO CONNECT 01520-038 Figure 39. Dual-Mode (GSM/DCS) PA Control Example Rev. D | Page 17 of 22

AD8315 Data Sheet MOBILE HANDSET POWER CONTROL EXAMPLE A smaller filter capacitor can be used by inserting a series resistor between VAPC and the control input of the PA. A Figure 39 shows a complete power amplifier control circuit for a series resistor works with the input impedance of the PA to dual-mode handset. The PF08107B (Hitachi), a dual mode create a resistor divider and reduces the loop gain. The size of (GSM, DCS) PA, is driven by a nominal power level of 3 dBm. the resistor divider ratio depends upon the available output The PA has a single gain control line; the band to be used is swing of V and the required control voltage on the PA. selected by applying either 0 V or 2 V to the PA VCTL input. APC This technique can also be used to limit the control voltage in Some of the output power from the PA is coupled off using a situations where the PA cannot deliver the power level being dual-band directional coupler (Murata LDC15D190A0007A). demanded by VAPC. Overdrive of the control input of some This has a coupling factor of approximately 19 dB for the GSM PAs causes increased distortion. It must be noted, however, that band and 14 dB for DCS and an insertion loss of 0.38 dB and if the control loop opens (that is, V goes to the maximum 0.45 dB, respectively. Because the PF08107B transmits a maximum APC value in an effort to balance the loop), the quiescent current of power level of 35 dBm for GSM and 32 dBm for DCS, additional the AD8315 increases somewhat, particularly at supply voltages attenuation of 20 dB is required before the coupled signal is greater than 3 V. applied to the AD8315. This results in peak input levels to the AD8315 of −4 dBm (GSM) and −2 dBm (DCS). While the Figure 40 shows the relationship between VSET and output AD8315 gives a linear response for input levels up to 2 dBm, power (POUT) at 0.9 GHz . The overall gain control function is for highly temperature-stable performance at maximum PA linear in dB for a dynamic range of over 40 dB. Note that for output power, the maximum input level must be limited to VSET voltages below 300 mV, the output power drops off steeply approximately −2 dBm (see Figure 6 and Figure 8). This does, as VAPC drops toward the minimum level of 250 mV. however, reduce the sensitivity of the circuit at the low end. 40 4 +85°C The operational setpoint voltage, in the range 250 mV to 1.4 V, 30 3 is applied to the VSET pin of the AD8315. This is typically supplied +25°C by a DAC. The AD8315 VAPC output drives the level control 20 2 +25°C +85°C pin of the power amplifier directly. V reaches a maximum APC 10 1 vthaelu 3e mofA a prpeqrouxirimeda bteyl yt h2e.5 l eVv eol nc oan 2t.r7o lV in spuuptp olyf wthhei lPeA d. eTlihviesr iins g (dBm)UT 0 –30°C 0 ROR (dB) more than sufficient to exercise the gain control range of the PA. PO–10 –1ER –30°C During initialization and completion of the transmit sequence, –20 –2 V must be held at the minimum level of 250 mV by keeping APC V below 200 mV. –30 –3 SET Ionu ttphuist erxanamgep flreo, mVS 0ET Vis tsou p2.p5l5ie Vd boyr a1n0 8m-bVi tp DerA bCit t. hTaht ihs asse tasn t he –400 0.2 0.4 0.6 VSE0T.8 (V) 1.0 1.2 1.4 1.6–4 01520-039 control resolution of VSET to 0.4 dB/bit (0.04 dB/mV times Figure 40. POUT vs. VSET at 0.9 GHz for Dual-Mode Handset 10 mV). If finer resolution is required, the DAC output voltage Power Amplifier Application, −30°C, +25°C, and +85°C can be scaled using two resistors, as shown in Figure 39. This ENABLE AND POWER-ON converts the DAC maximum voltage of 2.55 V down to 1.6 V The AD8315 can be disabled by pulling the ENBL pin to and increases the control resolution to 0.25 dB/bit. ground. This reduces the supply current from the nominal level A filter capacitor (CFLT) must stabilize the loop. The choice of CFLT of 7.4 mA to 4 μA. The logic threshold for turning on the device depends to a large degree on the gain control dynamics of the is at 1.5 V with 2.7 V supply voltage. A plot of the enable glitch power amplifier, something that is frequently poorly characterized, is shown in Figure 23. Alternatively, the device can be completely so some trial and error can be necessary. disabled by pulling the supply voltage to ground. To minimize In this example, a 150 pF capacitor is used and a 1.5 kΩ series glitch in this mode, ENBL and VPOS must be tied together. If resistor is included. This adds a zero to the control loop and VPOS is applied before the device is enabled, a narrow 750 mV increases the phase margin, which helps to make the step response glitch results (see Figure 30). of the circuit more stable when the PA output power is low and In both situations, the voltage on VSET must be kept below the slope of the PA power control function is the steepest. 200 mV during power-on and power-off to prevent any unwanted transients on VAPC. Rev. D | Page 18 of 22

Data Sheet AD8315 INPUT COUPLING OPTIONS ANTENNA The internal 5 pF coupling capacitor of the AD8315, along with AD8315 the low frequency input impedance of 2.8 kΩ, give a high-pass RFIN CC input corner frequency of approximately 16 MHz. This sets the STRIPLINE RATTN minimum operating frequency. Figure 41, Figure 42, and Figure 43 CIN RIN show three options for input coupling. A broadband resistive match can be implemented by connecting a shunt resistor to ground at PA 01520-042 RFIN (see Figure 41). This 52.3 Ω resistor (other values can also Figure 43. Series Attention Input Coupling Option be used to select different overall input impedances) combines with Figure 43 shows a third method for coupling the input the input impedance of the AD8315 to give a broadband input signal into the AD8315. A series resistor, connected to the RF impedance of 50 Ω. While the input resistance and capacitance source, combines with the input impedance of the AD8315 to (CIN and RIN) of the AD8315 varies from device to device by resistively divide the input signal being applied to the input. This approximately ±20%, and over frequency (see Figure 12), the has the advantage of very little power being tapped off in RF dominance of the external shunt resistor means that the variation power transmission applications. in the overall input impedance is close to the tolerance of the USING THE CHIP SCALE PACKAGE external resistor. This method of matching is most useful in wideband applications or in multiband systems where there is On the underside of the chip scale package, there is an exposed more than one operating frequency. paddle. This paddle is internally connected to the chip ground. There is no thermal requirement to solder the paddle down to the A reactive match can also be implemented as shown in printed circuit board ground plane. However, soldering down Figure 42. This is not recommended at low frequencies as the paddle has been shown to increase the stability over frequency device tolerances dramatically vary the quality of the match of the AD8315 ACP response at low input power levels (that is, because of the large input resistance. For low frequencies, at around −45 dBm) in the DCS and PCS bands. Figure 41 or Figure 43 is recommended. EVALUATION BOARD In Figure 42, the matching components are drawn as generic reactances. Depending on the frequency, the input impedance Figure 44 shows the schematic of the AD8315 MSOP evaluation and the availability of standard value components, either a board. The layout and silkscreen of the component side are shown capacitor or an inductor is used. As in the previous case, the in Figure 45 and Figure 46. An evaluation board is also available input impedance at a particular frequency is plotted on a Smith for the LFCSP package (see the Ordering Guide for exact device Chart and matching components are chosen (shunt or series L, numbers). Apart from the slightly smaller device footprint, the shunt or series C) to move the impedance to the center of the chart. LFCSP evaluation board is identical to the MSOP board. The board is powered by a single supply in the 2.7 V to 5.5 V range. AD8315 The power supply is decoupled by a single 0.1 μF capacitor. RFIN CC Table 5 details the various configuration options of the R52S.H3UVNT CIN RIN evaluation board. 01520-040 J1 R1 R522.3Ω AD8315 0.1CµF1 TP1 Figure 41. Broadband Resistive Input Coupling Option RFIN 0Ω 1 RFIN VPOS 8 VPOS R3 VPOS 0Ω J2 AD8315 SW1 2 ENBL VAPC 7 VAPC J2 R4 C2 X1 RFIN CC VSET 3 VSET NC 6 TP2 (OPEN) (OPEN) X2 CIN RIN C4 4 FLTR COMM 5 (OPEN) 01520-041 LK1 NCV P=O NSO CONNECT LK2 Figure 42. Narrow-Band Reactive Input Coupling Option C3 0.1µF C5 R8 0.1µF R7 10kΩ 16.2kΩ AD8031 R6 17.8kΩ 10Rk5Ω 01520-043 Figure 44. Evaluation Board Schematic (MSOP) Rev. D | Page 19 of 22

AD8315 Data Sheet Table 5. Evaluation Board Configuration Options Component Function Default Condition TP1, TP2 Supply and Ground Vector Pins. Not Applicable SW1 Device Enable. When in Position A, the ENBL pin is connected to VPOS and the AD8315 is SW1 = A in operating mode. In Position B, the ENBL pin is grounded putting the device in power-down mode. R1, R2 Input Interface. The 52.3 Ω resistor in Position R2 combines with the AD8315 internal input R2 = 52.3 Ω (Size 0603) impedance to give a broadband input impedance of around 50 Ω. A reactive match can be R1 = 0 Ω (Size 0402) implemented by replacing R2 with an inductor and R1 (0 Ω) with a capacitor. Note that the AD8315 RF input is internally ac-coupled. R3, R4, C2 Output Interface. R4 and C2 can be used to check the response of VAPC to capacitive and resistive R4 = C2 = Open (Size 0603) loading. R3/R4 can be used to reduce the slope of VAPC. R3 = 0 Ω (Size 0603) C1 Power Supply Decoupling. The nominal supply decoupling consists of a 0.1 μF capacitor. C1 = 0.1 μF (Size 0603) C4 Filter Capacitor. The response time of VAPC can be modified by placing a capacitor between C4 = Open (Size 0603) FLTR (Pin 4) and ground. LK1, LK2 Measurement Mode. A quasimeasurement mode can be implemented by installing LK1 and LK2 LK1, LK2 = Installed (connecting an inverted VAPC to VSET) to yield the nominal relationship between RFIN and VSET. In this mode, a large capacitor (0.01 μF or greater) must be installed in C4. For operation in controller mode, both jumpers, LK1 and LK2, must be removed. The setpoint voltage is applied to VSET, RFIN is connected to the RF source (PA output or directional coupler), and VAPC is connected to the gain control pin of the PA. When used in controller mode, a capacitor must be installed in C4 for loop stability. For GSM/DCS handset power amplifiers, this capacitor must typically range from 150 pF to 300 pF. A quasimeasurement mode (where the AD8315 delivers an output voltage that is proportional to the log of the input signal) can be implemented, to establish the relationship between VSET and RFIN, by installing the two jumpers, LK1 and LK2. This mimics an AGC loop. To establish the transfer function of the 01520-044 lios gm aemaspu, rtehde, RthFa ti nisp,u tth me SuMst Abe c sownenpetc twohr illaeb tehleed v oVlStaEgTe onno wV SacEtTs Figure 45. Layout of Component Side (MSOP) as an output. This is the simplest method to validate operation of the evaluation board. When operated in this mode, a large EVALUATION BOARD REV A capacitor (0.01 μF or greater) must be installed in C4 (filter PWUP GND AD8315 capacitor) to ensure loop stability. A TP2 VAPC SW1 VPOS J2 RFIN B TP1 R3 R4 C2 J1 PWDN C1 R2 R1 Z1 C4 C5R7 J3 R5 R8 LK1 A1 LK2 R6 C3 08 - 006794 REV A VSET COMPONENT SIDE 01520-045 Figure 46. Silkscreen of Component Side (MSOP) Rev. D | Page 20 of 22

Data Sheet AD8315 OUTLINE DIMENSIONS 3.20 3.00 2.80 8 5 5.15 3.20 4.90 3.00 4.65 2.80 1 4 PIN 1 IDENTIFIER 0.65 BSC 0.95 15° MAX 0.85 1.10 MAX 0.75 0.80 0.15 0.40 6° 0.23 0.55 CO0P.0L50A.1N0ARICTOYMPLIANT0. 2T5O JEDEC STA0°NDARDS 0M.0O9-187-AA 0.40 10-07-2009-B Figure 47. 8-Lead Mini Small Outline Package [MSOP] (RM-8) Dimensions shown in millimeters 3.25 1.89 3.00 0.55 1.74 2.75 0.40 1.59 0.30 0.20 MIN 2.25 5 8 2.00 0.60 EXPOSED PAD 1.75 0.45 4 1 0.30 PIN 1 INDEX TOP VIEW BOTTOM VIEW PIN 1 AREA 0.50 BSC INDICATOR 0.80 FOR PROPER CONNECTION OF 0.75 0.05 MAX TTHHEE EPXINP COOSENDFI GPAUDR,A RTEIOFNE RA NTOD 0.70 0.02 NOM FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. 0.30 PKG-004467 SEPALTAINNGE 00..2138 0.203 REF 02-12-2014-A Figure 48. 8-Lead Lead Frame Chip Scale Package [LFCSP] 2 mm × 3 mm Body and 0.75 mm Package Height (CP-8-23) Dimensions shown in millimeters ORDERING GUIDE Model1 Temperature Range Package Description Package Option Ordering Quantity Branding AD8315ARMZ −30°C to +85°C 8-Lead MSOP, Tube RM-8 50 Q0S AD8315ARMZ-RL −30°C to +85°C 8-Lead MSOP, 13" Tape and Reel RM-8 3,000 Q0S AD8315ACPZ-REEL7 −30°C to +85°C 8-Lead LFCSP, 7" Tape and Reel CP-8-23 3,000 0J AD8315ACP-EVALZ LFCSP Evaluation Board 1 Z = RoHS Compliant Part. Rev. D | Page 21 of 22

AD8315 Data Sheet NOTES ©1999–2016 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D01520-0-8/16(D) Rev. D | Page 22 of 22