Radar Receive Path AFE: 6-Channel LNA/PGA/AAF with ADC Data Sheet AD8283 FEATURES FUNCTIONAL BLOCK DIAGRAM 61 cchhaannnneell so of fd LirNeAct, -PtoG-AA,D ACA F ZSEL AVDD18x AVDD33x PDWN MUXA DVDD18x DVDD33x VREF RBIAS Programmable gain amplifier (PGA) Includes low noise preamplifier (LNA) INA+ REFERENCE SPI-programmable gain = 16 dB to 34 dB in 6 dB steps INA– LNA PGA AAF Antialiasing filter (AAF) INB+ Programmable third-order low-pass elliptic filter (LPF) from INB– LNA PGA AAF 1 MHz to 12 MHz DSYNC INC+ Analog-to-digital converter (ADC) INC– LNA PGA AAF 12 bits of accuracy up to 72 MSPS IND+ MUX 1A2-DBCIT DRV D[0:11] SNR = 67 dB IND– LNA PGA AAF SFDR = 68 dB INE+ Low power, 170 mW per channel at 12 bits/72 MSPS INE– LNA PGA AAF Low noise, 3.5 nV/√Hz maximum of input referred INF+ voltage noise INF– LNA PGA AAF Power-down mode INADC+ INADC– 72-lead, 10 mm × 10 mm, LFCSP package Specified from −40°C to +105°C SPI Qualified for automotive applications AD8283 AAuPtPomLIoCtAivTe IrOadNaSr CS SCLK SDIO AUX CLK+CLK– 09795-001 Figure 1. Adaptive cruise control Collision avoidance Blind spot detection Self-parking Electronic bumper GENERAL DESCRIPTION The AD8283 is designed for low cost, low power, compact size, Fabricated in an advanced CMOS process, the AD8283 is flexibility, and ease of use. It contains six channels of a low noise available in a 10 mm × 10 mm, RoHS-compliant, 72-lead preamplifier (LNA) with a programmable gain amplifier (PGA) LFCSP. It is specified over the automotive temperature range and an antialiasing filter (AAF) plus one direct-to-ADC of −40°C to +105°C. channel, all integrated with a single 12-bit analog-to-digital Table 1. Related Devices converter (ADC). Part No. Description Each channel features a gain range of 16 dB to 34 dB in 6 dB AD8285 4-Channel LNA/PGA/AAF, pseudosimultaneous increments and an ADC with a conversion rate of up to 72 MSPS. channel sampling with ADC The combined input-referred noise voltage of the entire channel AD8284 4-Channel LNA/PGA/AAF, sequential channel is 3.5 nV/√Hz at maximum gain. The channel is optimized for sampling with ADC dynamic performance and low power in applications where a ADA8282 4-Channel LNA/PGA small package size is critical. Rev. C Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Tel: 781.329.4700 ©2011–2015 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com

AD8283 Data Sheet TABLE OF CONTENTS Features .....................................................................................1 Clock Jitter Considerations .................................................. 17 Applications...............................................................................1 SDIO Pin ............................................................................. 17 Functional Block Diagram .........................................................1 SCLK Pin ............................................................................. 17 General Description ..................................................................1 CS Pin .................................................................................. 17 Revision History ........................................................................2 RBIAS Pin............................................................................ 17 Specifications .............................................................................3 Voltage Reference ................................................................ 17 AC Specifications ...................................................................3 Power and Ground Recommendations ................................ 18 Digital Specifications .............................................................5 Exposed Paddle Thermal Heat Slug Recommendations ...... 18 Switching Specifications.........................................................6 Serial Peripheral Interface (SPI) .............................................. 19 Absolute Maximum Ratings ......................................................7 Hardware Interface .............................................................. 19 ESD Caution ..........................................................................7 Memory Map........................................................................... 21 Pin Configuration and Function Descriptions...........................8 Reading the Memory Map Table.......................................... 21 Typical Performance Characteristics .......................................10 Logic Levels ......................................................................... 21 Theory of Operation ................................................................14 Reserved Locations .............................................................. 21 Radar Receive Path AFE ......................................................14 Default Values...................................................................... 21 Channel Overview ...............................................................15 Application Diagrams.............................................................. 25 ADC.....................................................................................16 Outline Dimensions ................................................................ 27 Clock Input Considerations .................................................16 Ordering Guide ................................................................... 27 Clock Duty Cycle Considerations ........................................17 Automotive Products ........................................................... 27 REVISION HISTORY 8/15—Rev. B to Rev. C Changed AD951x/AD952x to AD9515/AD9520-0 ... Throughout Added Table 1; Renumbered Sequentially .................................1 10/14—Rev. A to Rev. B Changes to Addr. (Hex) 0x15, Table 8......................................23 Changes to Ordering Guide .....................................................27 11/13—Rev. 0 to Rev. A Changed Maximum f from 80 MSPS to 72 MSPS SAMPLE ................................................................................. Throughout Changed Clock Pulse Width High/Low (t /t ) at 72 MSPS EH EL from 6.25 ns to 6.94ns; Table 3...................................................6 Changes to Figure 25 ...............................................................14 Changes to Register Address 10 Bits[5:0] and Register Address 0x12, Bit 3; Table 8 .....................................................23 Updated Outline Dimensions ..................................................27 4/11—Revision 0: Initial Version Rev. C | Page 2 of 27

Data Sheet AD8283 SPECIFICATIONS AC SPECIFICATIONS AVDD18x = 1.8 V, AVDD33x = 3.3 V, DVDD18x = 1.8 V, DVDD33x = 3.3 V, 1.024 V internal ADC reference, f = 2.5 MHz, f = IN SAMPLE 72 MSPS, R = 50 Ω, LNA + PGA gain = 34 dB, LPF cutoff = f /4, full channel mode, 12-bit operation, temperature = −40°C to S SAMPLECH +105°C, unless otherwise noted. Table 2. AD8283W Parameter1 Conditions Min Typ Max Unit ANALOG CHANNEL CHARACTERISTICS LNA, PGA, and AAF channel Gain 16/22/28/34 dB Gain Range 18 dB Gain Error −1.25 +1.25 dB Input Voltage Range Channel gain =16 dB 0.25 V p-p Channel gain = 22 dB 0.125 Channel gain = 28 dB 0.0625 Channel gain = 34 dB 0.03125 Input Resistance 200 Ω input impedance selected 0.180 0.230 0.280 kΩ 200 kΩ input impedance selected 160 200 240 Input Capacitance 22 pF Input-Referred Voltage Noise Max gain at1 MHz 1.85 nV/√Hz Min gain at 1 MHz 6.03 nV/√Hz Noise Figure Max gain, R = 50 Ω, unterminated 7.1 dB S Max Gain, R=R = 50 Ω 12.7 dB S IN Output Offset Gain = 16 dB −60 +60 LSB Gain = 34 dB −250 +250 LSB AAF Low-Pass Filter Cutoff −3 dB, programmable 1.0 to 12.0 MHz AAF Low-Pass Filter Cutoff Tolerance After filter autotune −10 ±5 +10 % AAF Attenuation in Stop Band Third order elliptical filter 2× cutoff 30 dB 3× cutoff 40 dB Group Delay Variation Filter set at 2 MHz 400 ns Channel-to-Channel Phase Variation Frequencies up to −3 dB −5 ±0.5 +5 Degrees ¼ of −3 dB frequency −1 +1 Degrees Channel-to-Channel Gain Matching Frequencies up to −3 dB −0.5 ±0.1 +0.5 dB 1/4 of −3 dB frequency −0.25 +0.25 dB 1 dB Compression Relative to output 9.8 dBm Crosstalk −70 −55 dBc POWER SUPPLY AVDD18x 1.7 1.8 1.9 V AVDD33x 3.1 3.3 3.5 V DVDD18x 1.7 1.8 1.9 V DVDD33x 3.1 3.3 3.5 V I Full-channel mode 190 mA AVDD18 I Full-channel mode 190 mA AVDD33 I 22 mA DVDD18 I 2 mA DVDD33 Total Power Dissipation – per Full-channel mode, no signal, typical 170 mW channel supply voltage × maximum supply current; excludes output current Power-Down Dissipation 5 mW Power Supply Rejection Ratio (PSRR) Relative to input 1.6 mV/V Rev. C | Page 3 of 27

AD8283 Data Sheet AD8283W Parameter1 Conditions Min Typ Max Unit ADC Resolution 12 Bits Max Sample Rate 72 MSPS Signal-to-Noise Ratio (SNR) f = 1 MHz 68.5 dB IN Signal-to-Noise and Distortion 66 dB (SINAD) SNRFS 68 dB Differential Nonlinearity (DNL) Guaranteed no missing codes 1 LSB Integral Nonlinearity (INL) 10 LSB Effective Number of Bits (ENOB) 10.67 LSB ADC Output Characteristics Maximum Cap Load Per bit 20 pF I Peak Current with Cap Load Peak current per bit when driving a 40 mA DVDD33 20 pF load; can be programmed via the SPI port if required ADC REFERENCE Output Voltage Error VREF = 1.024 V ±25 mV Load Regulation At 1.0 mA, VREF = 1.024 V 2 mV Input Resistance 6 kΩ FULL CHANNEL CHARACTERISTICS LNA, PGA, AAF, and ADC SNRFS F = 1 MHz IN Gain = 16 dB 68 dB Gain = 22 dB 68 dB Gain = 28 dB 68 dB Gain = 34 dB 66 dB SINAD F = 1 MHz IN Gain = 16 dB 67 dB Gain = 22 dB 68 dB Gain = 28 dB 67 dB Gain = 34 dB 66 dB SFDR F = 1 MHz IN Gain = 16 dB 68 dB Gain = 22 dB 74 dB Gain = 28 dB 74 dB Gain = 34 dB 73 dB Harmonic Distortion Second Harmonic F =1 MHz at −10 dBFS, gain = 16 dB −70 dBc IN F =1 MHz at −10 dBFS, gain = 34 dB −70 dBc IN Third Harmonic F =1 MHz at −10 dBFS, gain = 16 dB −66 dBc IN F =1 MHz at −10 dBFS, gain = 34 dB −75 dBc IN IM3 Distortion F = 1 MHz, F = 1.1 MHz, −1 dBFS, −69 dBc IN1 IN2 gain = 34 dB Gain Response Time 600 ns Overdrive Recovery Time 200 ns 1 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions and how these tests were completed. Rev. C | Page 4 of 27

Data Sheet AD8283 DIGITAL SPECIFICATIONS AVDD18x = 1.8 V, AVDD33 = 3.3 V, DVDD18 = 1.8 V, DVDD33 = 3.3 V, 1.024 V internal ADC reference, f = 2.5 MHz, f = IN SAMPLE 72 MSPS, R = 50 Ω, LNA + PGA gain = 34 dB, LPF cutoff = f /4, full channel mode, 12-bit operation, temperature = −40°C to S SAMPLECH +105°C, unless otherwise noted. Table 3. Parameter1 Temperature Min Typ Max Unit CLOCK INPUTS (CLK+, CLK−) Logic Compliance CMOS/LVDS/LVPECL Differential Input Voltage2 Full 250 mV p-p Input Common-Mode Voltage Full 1.2 V Input Resistance (Differential) 25°C 20 kΩ Input Capacitance 25°C 1.5 pF LOGIC INPUTS (PDWN, SCLK, AUX, MUXA, ZSEL) Logic 1 Voltage Full 1.2 3.6 V Logic 0 Voltage Full 0.3 V Input Resistance 25°C 30 kΩ Input Capacitance 25°C 0.5 pF LOGIC INPUT (CS) Logic 1 Voltage Full 1.2 3.6 V Logic 0 Voltage Full 0.3 V Input Resistance 25°C 70 kΩ Input Capacitance 25°C 0.5 pF LOGIC INPUT (SDIO) Logic 1 Voltage Full 1.2 DVDD33x + 0.3 V Logic 0 Voltage Full 0 0.3 V Input Resistance 25°C 30 kΩ Input Capacitance 25°C 2 pF LOGIC OUTPUT (SDIO)3 Logic 1 Voltage (I = 800 μA) Full 3.0 V OH Logic 0 Voltage (I = 50 μA) Full 0.3 V OL LOGIC OUTPUT (D[11:0], DSYNC) Logic 1 Voltage (I = 2 mA) Full 3.0 V OH Logic 0 Voltage (I = 2 mA) Full 0.05 V OL 1 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions and how these tests were completed. 2 Specified for LVDS and LVPECL only. 3 Specified for 13 SDIO pins sharing the same connection. Rev. C | Page 5 of 27

AD8283 Data Sheet SWITCHING SPECIFICATIONS AVDD18x = 1.8 V, AVDD33x = 3.3 V, DVDD18x = 1.8 V, DVDD33x = 3.3 V, 1.024 V internal ADC reference, f = 2.5 MHz, f = IN SAMPLE 72 MSPS, R = 50 Ω, LNA + PGA gain = 34 dB, LPF cutoff = f /4, full channel mode, 12-bit operation, temperature = −40°C to S SAMPLECH +105°C, unless otherwise noted. Table 4. Parameter1 Temperature Min Typ Max Unit CLOCK Clock Rate Full 10 72 MSPS Clock Pulse Width High (t ) at 72 MSPS Full 6.94 ns EH Clock Pulse Width Low (t ) at 72 MSPS Full 6.94 ns EL Clock Pulse Width High (t ) at 40 MSPS Full 12.5 ns EH Clock Pulse Width Low (t ) at 40 MSPS Full 12.5 ns EL OUTPUT PARAMETERS Propagation Delay (t ) at 72 MSPS Full 1.5 2.5 5.0 ns PD Rise Time (t) Full 1.9 ns R Fall Time (t) Full 1.2 ns F Data Set-Up Time (t ) at 72 MSPS Full 9.0 10.0 11.0 ns DS Data Hold Time (t ) at 72 MSPS Full 1.5 4.0 5.0 ns DH Data Set-Up Time (t ) at 40 MSPS Full 21.5 22.5 23.5 ns DS Data Hold Time (t ) at 40 MSPS Full 1.5 4.0 5.0 ns DH Pipeline Latency Full 7 Clock cycles 1 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions and how these tests were completed. N N –1 INAx tEH tEL CLK– CLK+ tPD tDS tDH D[11:0] N – 7 N – 6 N – 5 N – 4 N – 3 N – 2 N – 1 N 09795-002 Figure 2. Timing Definitions for Switching Specifications Rev. C | Page 6 of 27

Data Sheet AD8283 ABSOLUTE MAXIMUM RATINGS Stresses at or above those listed under Absolute Maximum Table 5. Ratings may cause permanent damage to the product. This is a With Parameter Respect To Rating stress rating only; functional operation of the product at these Electrical or any other conditions above those indicated in the operational AVDD18x GND −0.3 V to +2.0 V section of this specification is not implied. Operation beyond AVDD33x GND −0.3 V to +3.5 V the maximum operating conditions for extended periods may affect product reliability. DVDD18x GND −0.3 V to +2.0 V DVDD33x GND −0.3 V to +3.5 V Analog Inputs GND −0.3 V to +3.5 V ESD CAUTION INx+, INx− Auxiliary Inputs GND −0.3 V to +2.0 V INADC+, INADC- Digital Outputs GND −0.3 V to +3.5 V D[11:0], DSYNC, SDIO CLK+, CLK− GND −0.3 V to +3.9 V PDWN, SCLK, CS, AUX, GND −0.3 V to +3.9 V MUXA, ZSEL RBIAS, VREF GND −0.3 V to +2.0 V Environmental Operating Temperature −40°C to +105°C Range (Ambient) Storage Temperature −65°C to +150°C Range (Ambient) Maximum Junction 150°C Temperature Lead Temperature 300°C (Soldering, 10 sec) Rev. C | Page 7 of 27

AD8283 Data Sheet PIN CONFIGURATION AND FUNCTION DESCRIPTIONS V V R R D D 3 3 3 3 D D CVDCC01234567891011VDC NDNNDDDDDDDDDDDDDN 210987654321098765 777666666666655555 NC 1 PIN 1 54 NC DSYNC 2 INDICATOR 53 TEST4 PDWN 3 52 DVDD18CLK DVDD18 4 51 CLK+ SCLK 5 50 CLK– SDIO 6 49 DVDD33CLK CS 7 48 AVDD33REF AUX 8 47 VREF MUXA 9 AD8283 46 RBIAS ZSEL 10 (TOP VIEW) 45 BAND TEST1 11 44 APOUT TEST2 12 43 ANOUT DVDD33SPI 13 42 TEST3 AVDD18 14 41 AVDD18ADC AVDD33A 15 40 AVDD18 INA– 16 39 INADC+ INA+ 17 38 INADC– NC 18 37 NC 901234567890123456 122222222223333333 NCNCDD33BINB–INB+DD33CINC–INC+DD33DIND–IND+DD33EINE–INE+DD33FINF–INF+NC V V V V V A A A A A N12..O TNTHCEE S= ENXOP OCOSENDNEPCADT.D DLOE NSOHOT UCLODN BNEE CTTIETDOT TOHAISN PAILNO.G/DIGITAL GROUND PLANE. 09795-003 Figure 3. Table 6. Pin Function Descriptions Pin No. Name Description 0 GND Ground. Exposed paddle on the bottom side; should be tied to the analog/digital ground plane. 1 NC No Connection. Pin can be tied to any potential. 2 DSYNC Data Out Synchronization. 3 PDWN Full Power-Down. Logic high overrides SPI and powers down the part, logic low allows selection through SPI. 4 DVDD18 1.8 V Digital Supply. 5 SCLK Serial Clock. 6 SDIO Serial Data Input/Output. 7 CS Chip Select Bar. 8 AUX Logic high forces to Channel ADC (INADC+/INADC−); AUX has a higher priority than MUXA. 9 MUXA Logic high forces to Channel A unless AUX is asserted. 10 ZSEL Input Impedance Select. Logic high overrides SPI and sets it to 200 kΩ; logic low allows selection through SPI. 11 TEST1 Pin should not be used; tie to ground. 12 TEST2 Pin should not be used; tie to ground. 13 DVDD33SPI 3.3 V Digital Supply, SPI Port. 14 AVDD18 1.8 V Analog Supply. 15 AVDD33A 3.3 V Analog Supply, Channel A. 16 INA− Negative LNA Analog Input for Channel A. 17 INA+ Positive LNA Analog Input for Channel A. 18 NC No Connect. Pin can be tied to any potential. 19 NC No Connect. Pin can be tied to any potential. 20 NC No Connect. Pin can be tied to any potential. 21 AVDD33B 3.3 V Analog Supply, Channel B. 22 INB− Negative LNA Analog Input for Channel B. 23 INB+ Positive LNA Analog Input for Channel B. 24 AVDD33C 3.3 V Analog Supply, Channel C. 25 INC− Negative LNA Analog Input for Channel C. 26 INC+ Positive LNA Analog Input for Channel C. Rev. C | Page 8 of 27

Data Sheet AD8283 Pin No. Name Description 27 AVDD33D 3.3 V Analog Supply, Channel D. 28 IND− Negative LNA Analog Input for Channel D. 29 IND+ Positive LNA Analog Input for Channel D. 30 AVDD33E 3.3 V Analog Supply, Channel E. 31 INE− Negative LNA Analog Input for Channel E. 32 INE+ Positive LNA Analog Input for Channel E. 33 AVDD33F 3.3 V Analog Supply, Channel F. 34 INF− Negative LNA Analog Input for Channel F. 35 INF+ Positive LNA Analog Input for Channel F. 36 NC No Connect, Pin can be tied to any potential. 37 NC No Connect. Pin can be tied to any potential. 38 INADC− Negative Analog Input for Alternate Channel F (ADC Only). 39 INADC+ Positive Analog Input for Alternate Channel F (ADC Only). 40 AVDD18 1.8 V Analog Supply. 41 AVDD18ADC 1.8 V Analog Supply, ADC. 42 TEST3 Pin should not be used; tie to ground. 43 ANOUT Analog Outputs (Debug Purposes Only). Pin should be floated. 44 APOUT Analog Outputs (Debug Purposes Only). Pin should be floated. 45 BAND Band Gap Voltage (Debug Purposes Only). Pin should be floated. 46 RBIAS External resistor to set the internal ADC core bias current. 47 VREF Voltage Reference Input/Output. 48 AVDD33REF 3.3 V Analog Supply, References. 49 DVDD33CLK 3.3 V Digital Supply, Clock. 50 CLK− Clock Input Complement. 51 CLK+ Clock Input True. 52 DVDD18CLK 1.8 V Digital Supply, Clock. 53 TEST4 Pin should not be used; tie to ground. 54 NC No Connect. Pin can be tied to any potential. 55 NC No Connect. Pin can be tied to any potential. 56 DVDD33DRV 3.3 V Digital Supply, Output Driver. 57 D11 ADC Data Out (MSB). 58 D10 ADC Data Out. 59 D9 ADC Data Out. 60 D8 ADC Data Out. 61 D7 ADC Data Out. 62 D6 ADC Data Out. 63 D5 ADC Data Out. 64 D4 ADC Data Out. 65 D3 ADC Data Out. 66 D2 ADC Data Out. 67 D1 ADC Data Out. 68 D0 ADC Data Out (LSB). 69 NC No Connect. Pin should be left open. 70 NC No Connect. Pin should be left open. 71 DVDD33DRV 3.3 V Supply, Output Driver. 72 NC No Connect. Pin can be tied to any potential. Rev. C | Page 9 of 27

AD8283 Data Sheet TYPICAL PERFORMANCE CHARACTERISTICS V = 3.3 V, 1.8 V, T = 25°C, F = 72 MSPS, R =200 kΩ, VREF = 1.0 V. S A S IN 50 40 38 40 36 34dB 34 30 28dB %) 32 22dB S ( 30 E 28 20 16dB VIC 26 N (dB) 10 OF DE 222024 GAI 0 GE 18 A 16 T –10 CEN 1124 –20 PER 108 6 –30 4 2 –400.1 1FREQUENCY (MHz)10 100 09795-014 033.5033.5833.6633.7433.8233.903(3L.9S8B3)4.0634.1434.2234.3034.3834.46 09795-033 Figure 4. Channel Gain vs. Frequency Figure 7. Gain Error Histogram (Gain = 34 dB) 1.0 20 34dB 19 28dB 0.8 22dB 18 16dB 17 0.6 %) 16 S ( 15 0.4 E 14 dB) VIC 13 R ( 0.2 DE 12 AIN ERRO–0.20 TAGE OF 110891 G N 7 –0.4 CE 6 R 5 E –0.6 P 4 3 –0.8 2 1 –1.0 0 –40 –15 TE1M0PERATURE3(5°C) 60 85 09795-038 00.010.020.030.040.050.060.070.080.090.100.110(.1d20B.1)30.140.150.160.170.180.190.200.210.220.230.240.25 09795-034 Figure 5. Gain Error vs. Temperature at All Gains Figure 8. Channel-to-Channel Gain Matching (Gain = 16 dB) 40 10 38 36 9 34 %) 32 %) 8 S ( 30 S ( E 28 E 7 VIC 26 VIC E 24 E 6 F D 22 F D O 20 O 5 GE 18 GE A 16 A 4 NT 14 NT CE 12 CE 3 R 10 R E E P 8 P 2 6 4 1 2 016.0016.0816.1616.2416.32 16.4 16(.d4B8)16.5616.6416.72 16.8 16.8816.96 09795-032 000.010.020.030.040.050.060.070.080.090.100.110(.1d20B.1)30.140.150.160.170.180.190.200.210.220.230.240.25 09795-035 Figure 6. Gain Error Histogram (Gain = 16 dB) Figure 9. Channel-to-Channel Gain Matching (Gain = 34 dB) Rev. C | Page 10 of 27

Data Sheet AD8283 12000 70 SNR 10000 65 SINAD S8000 S) 60 HIT BF OF D (d R 6000 A 55 E N B SI NUM4000 SNR/ 50 2000 45 0 40 –7 –6 –5 –4 –3 –2 –1CO0DE1 2 3 4 5 6 7 09795-015 16 22 GAIN (dB) 28 34 09795-017 Figure 10. Output Referred Noise Histogram (Gain = 16 dB) Figure 13. SNR vs. Gain 7000 20 6000 10 5000 0 S T R OF HI4000 N (dB) –10 MBE3000 GAI –20 U N 2000 –30 12MHz 8MHz 1000 –40 4MHz 2MHz 1MHz 0 –50 –7 –6 –5 –4 –3 –2 –1CO0DE1 2 3 4 5 6 7 09795-016 0.1 1FREQUENCY (Hz)10 100 09795-022 Figure 11. Output Referred Noise Histogram (Gain = 34 dB) Figure 14. Filter Response 15 200 180 160 34dB 10 140 NOISE (nV/√Hz) 5 16dB NOISE (nV/√Hz) 11028000 222d8BdB 22dB 60 16dB 28dB 40 34dB 20 0 0.1 FREQ1UENCY (MHz) 10 09795-030 00.1 FREQ1UENCY (MHz) 10 09795-031 Figure 12. Short Circuit Input-Referred Noise vs. Frequency Figure 15. Short-Circuit Output-Referred Noise vs. Frequency Rev. C | Page 11 of 27

AD8283 Data Sheet 1000 1.5 1MHz 2MHz 900 4MHz 8MHz 1.0 800 12MHz 700 0.5 ns) 600 E (V) AY ( 500 TUD 0 DEL 400 MPLI A –0.5 300 200 –1.0 100 00.1 1FREQUENCY (MHz)10 100 09795-019 –1.50 0.5 1.0 1.5 TIM2E.0 (µs) 2.5 3.0 3.5 4.0 09795-041 Figure 16. Group Delay vs. Frequency Figure 19. Overdrive Recovery –40 SECOND –1dBFS SECOND –10dBFS LEVEL –45 THIRD –1dBFS 560mV THIRD –10dBFS TRIGHOLDOFF –50 1.5µs Bc) –55 MEAN(C2) 7.177mV d µ:7.1773964m C ( m:7177m M:7.177m RMONI –60 3 SDO σMµ::E20A2N0m(C2) 220mV A –65 m:220m M:220m H σ:0 ANALOG –70 OUTPUT Fµ:R9E9Q7(.C7525)0949k7.8kHz 2 m:997.8k M:997.8k σ:0 –75 –800 1 2INPUT F3REQUENC4Y (MHz)5 6 7 09795-039 CH3 1V CH2 500mV Ω MA1CµHs21.255G60Sm/sV 800ps/pt 09795-024 Figure 17. Harmonic Distortion vs. Frequency Figure 20. Gain Step Response 500 200000 30 450 180000 400 160000 25 350 140000 EDANCE (Ω) 235000 110200000000 FIGURE (dB) 1250 34dB 50Ω TERMINATED IMP 125000 6800000000 NOISE 10 34dB UNTERMINATED 100 40000 5 50 20000 00.01 0.1 FREQUEN1CY (MHz) 10 1000 09795-040 00.1 FREQ1UENCY (MHz) 10 09795-042 Figure 18. RIN vs. Frequency Figure 21. Noise Figure vs. Frequency Rev. C | Page 12 of 27

Data Sheet AD8283 10 12 9 11 ES (%) 78 S (%) 109 C E VI C 8 F DE 6 DEVI 7 O 5 F E O 6 G E PERCENTA 234 ERCENTAG 345 P 2 1 1 0 –60F–5i6g–5u2–r4e8– 424–240–. 3C6–h32–a2n8–2n4–e2l0– O16–f1f2s–e8–t(4 LDS0iBs4t)r8ib1u21t6io20n2 4(G28a3i2n36 =40 14464 d85B2)5 660 09795-036 0–200–180–160–140–120–100–80–60–40–2(0LS0B)20 40 60 80100120140160180200 09795-037 Figure 23. Channel Offset Distribution (Gain = 34 dB) Rev. C | Page 13 of 27

AD8283 Data Sheet THEORY OF OPERATION RADAR RECEIVE PATH AFE AAF cutoff characteristics, and ADC sample rate and resolution. The primary application for the AD8283 is high-speed ramp, frequency modulated, continuous wave radar (HSR-FMCW The AD8283 includes a multiplexer (mux) in front of the ADC radar). Figure 25 shows a simplified block diagram of an HSR- as a cost saving alternative to having an ADC for each channel. FMCW radar system. The signal chain requires multiple The mux automatically switches between each active channel channels, each including a low noise amplifier (LNA), a after each ADC sample. The DSYNC output indicates when programmable gain amplifier (PGA), an antialiasing filter Channel A data is at the ADC output, and data for each active (AAF), and an analog-to-digital converter (ADC). The AD8283 channel follows sequentially with each clock cycle. provides all of these key components in a single 10 × 10 LFCSP The effective sample rate for each channel is reduced by a factor package. equal to the number of active channels. The ADC resolution of The performance of each component is designed to meet the 12 bits with up to 72 MSPS sampling satisfies the requirements demands of an HSR-FMCW radar system. Some examples of for most HSR-FMCW approaches. these performance metrics are the LNA noise, PGA gain range, REF. OSCILLATOR PA VCO CHIRP RAMP GENERATOR LNA PGA AAF LNA PGA AAF MUX 1A2-DBCIT DSP LNA PGA AAF ANTENNA AD8283 09795-004 Figure 24. Radar System Overview SDIO SCLK AD8283 SPI MUX DSYNC INTERFACE CONTROLLER 200Ω/ 200kΩ INx+ LNA PGA AAF MUX PIPAEDLCINE P3.A3RV ACLMLOESL D11:D0 INx– 22dB –6dB, THIRD-ORDER 12-BIT 1062dddBBB,, ELLIPTICAL FILTER 72MSPS 09795-005 Figure 25. Simplified Block Diagram of a Single Channel Rev. C | Page 14 of 27

Data Sheet AD8283 CHANNEL OVERVIEW The antialiasing filter uses a combination of poles and zeros to create a third-order elliptical filter. An elliptical filter is used to Each channel contains an LNA, a PGA, and an AAF in the achieve a sharp roll off after the cutoff frequency. The filter uses signal path. The LNA input impedance can be either 200 Ω or on-chip tuning to trim the capacitors to set the desired cutoff 200 kΩ. The PGA has selectable gains that result in channel frequency. This tuning method reduces variations in the cutoff gains ranging from 16 dB to 34 dB. The AAF has a three-pole frequency due to standard IC process tolerances of resistors elliptical response with a selectable cutoff frequency. The mux and capacitors. The default −3 dB low-pass filter cutoff is 1/3 or is synchronized with the ADC and automatically selects the 1/4 the ADC sample clock rate. The cutoff can be scaled to 0.7, next active channel after the ADC acquires a sample. 0.8, 0.9, 1, 1.1, 1.2, or 1.3 times this frequency through the SPI. The signal path is fully differential throughout to maximize Tuning is normally off to avoid changing the capacitor settings signal swing and reduce even-order distortion including the during critical times. The tuning circuit is enabled and disabled LNA, which is designed to be driven from a differential signal through the SPI. Initializing the tuning of the filter must be source. performed after initial power-up and after reprogramming the Low Noise Amplifier (LNA) filter cutoff scaling or ADC sample rate. Occasional retuning Good noise performance relies on a proprietary ultralow noise during an idle time is recommended to compensate for LNA at the beginning of the signal chain, which minimizes the temperature drift. noise contributions on the following PGA and AAF. The input A cut-off range of 1 MHz to 12 MHz is possible. An example impedance can be either 200 Ω or 200 kΩ and is selected through follows: the SPI port or by the ZSEL pin. • Four channels selected: A, B, C, and AUX The LNA supports differential output voltages as high as 4.0 V p-p • ADC clock: 30 MHz with positive and negative excursions of ±1.0 V from a common- • Per channel sample rate = 30/4 = 7.5 MSPS mode voltage of 1.5 V. With the output saturation level fixed, • Default tuned cutoff frequency = 7.5/4 = 1.88 MHz the channel gain sets the maximum input signal before saturation. Mux and Mux Controller Low value feedback resistors and the current-driving capability The mux is designed to automatically scan through each active of the output stage allow the LNA to achieve a low input- channel. The mux remains on each channel for one clock cycle, referred noise voltage of 3.5 nV/√Hz at a channel gain of 34 dB. then switches to the next active channel. The mux switching is The use of a fully differential topology and negative feedback synchronized to the ADC sampling so that the mux switching minimizes second-order distortion. Differential signaling and channel settling time do not interfere with ADC sampling. enables smaller swings at each output, further reducing third- As indicated in Table 9, Register Address 0C, Flex Mux Control, order distortion. Channel A, is usually the first converted input. The one Recommendation exceptions occurs when Channel AUX is the sole input (see Figure 26 for timing). Channel AUX is always forced to be the To achieve the best possible noise performance, it is important last converted input. Unselected codes put the respective to match the impedances seen by the positive and negative channels (LNA, PGA, and Filter) in power-down mode unless inputs. Matching the impedances ensures that any common- mode noise is rejected by the signal path. Register Address 0C, Bit 6, is set to 1. Figure 26 shows the timing of the clock input and data/DSYNC outputs. Antialiasing Filter (AAF) The filter that the signal reaches prior to the ADC is used to band limit the signal for antialiasing. Rev. C | Page 15 of 27

AD8283 Data Sheet N N + 1 INAx CLK– CLK+ D[11:0] XXXX OUTAN – 1 OUTB OUTC OUTD OUTE OUTF OUTAN OUTB t PD DSYNC t t DS DH NOTES 123... FDTOHSEYRRN AECB IIOSSV AAE LS CWEOVANEYFNSI GCAULLROIGACNTKEI ODCN YW CRILTEEHG LICSAHTTAEERNN NACEDYL DF ARR EUOSNMSL SE0ACSM SS PECLTHI NATGNON A1E0 CL1 H0A A( CONHRNA ECNLHN TAEONL N IATES,L B DA, IUCGX,I TD IAS, L ET DHAAENT DOA NF B LEEYNI NCAGHB ALPENRDNE)ES.LE NSTE LOENC TTEHDE, PINA RWAHLILCEHL C BAUSSE PDINSYSN.C IS NOT ACTIVE. 09795-006 Figure 26. Data and DSYNC Timing ADC 3.3V MINI-CIRCUITS® The AD8283 uses a pipelined ADC architecture. The quantized ADT1-1WT,1:1Z output from each stage is combined into a 12-bit result in the 0.1µF XFMR 0.1µF OUT CLK+ digital correction logic. The pipelined architecture permits the 50Ω 100Ω ADC VFAC3 0.1µF AD8283 first stage to operate on a new input sample and the remaining CLK– srtisaignegs etod goep oefr atthee o cnlo pcrke.c Tedhien ogu stapmutp sletas.g Sinagm bplloinckg aolcigcunrss t hone the 0.1µF SHCDSIHOMOD2TE8TS1K2:Y 09795-007 data, corrects errors, and passes the data to the output buffers. Figure 27. Transformer-Coupled Differential Clock CLOCK INPUT CONSIDERATIONS If a low jitter clock is available, another option is to ac-couple a differential PECL or LVDS signal to the sample clock input pins For optimum performance, the AD8283 sample clock inputs as shown in and Figure 28 and Figure 29. The AD9515/ (CLK+ and CLK−) should be clocked with a differential signal. AD9520-0 family of clock drivers offers excellent jitter This signal is typically ac-coupled into the CLK+ and CLK− pins performance. via a transformer or using capacitors. These pins are biased internally and require no additional bias. 3.3V 50Ω* AD9515/AD9520-0 Figure 27 shows the preferred method for clocking the AD8283. VFAC3 0.1µF 0.1µF A low jitter clock source, such as the Valpey Fisher oscillator OUT CLK CLK+ VFAC3-BHL-50MHz, is converted from single ended to 100Ω ADC PECL DRIVER AD8283 differential using an RF transformer. The back-to-back Schottky 0.1µF 0.1µF CLK CLK– diodes across the secondary transformer limit clock excursions 240Ω 240Ω ihnetlop st hper eAvDen8t2 t8h3e tloa ragpep vroolxtiamgea tsewlyin 0g.8s oVf tph-ep cdliofcfekr efrnotmial .f eTehdiisn g *50Ω RESISTOR IS OPTIONAL. 09795-008 through to other portions of the AD8283, and it preserves the Figure 28. Differential PECL Sample Clock fast rise and fall times of the signal, which are critical to low 3.3V jitter performance. 50Ω* AD9515/AD9520-0 VFAC3 0.1µF 0.1µF OUT CLK CLK+ ADC 100Ω LVDS DRIVER AD8283 0.1µF 0.1µF CLK CLK– *50Ω RESISTOR IS OPTIONAL. 09795-009 Figure 29. Differential LVDS Sample Clock Rev. C | Page 16 of 27

Data Sheet AD8283 In some applications, it is acceptable to drive the sample clock CLOCK JITTER CONSIDERATIONS inputs with a single-ended CMOS signal. In such applications, High speed, high resolution ADCs are sensitive to the quality of the CLK+ should be driven directly from a CMOS gate, and the clock input. The degradation in SNR at a given input frequency (f ) A CLK− pin should be bypassed to ground with a 0.1 μF capacitor due only to aperture jitter (t) can be calculated by J in parallel with a 39 kΩ resistor (see Figure 30). Although the SNR Degradation = 20 × log 10[1/2 × π × f × t] CLK+ input circuit supply is AVDD18, this input is designed to A J withstand input voltages of up to 3.3 V, making the selection of In this equation, the RMS aperture jitter represents the root mean the drive logic voltage very flexible. The AD9515/AD9520-0 square of all jitter sources, including the clock input, analog input family of parts can be used to provide 3.3 V inputs (see Figure 31). signal, and ADC aperture jitter. IF undersampling applications In this case, 39 kΩ is not needed. are particularly sensitive to jitter. 3.3V The clock input should be treated as an analog signal in cases AD9515/AD9520-0 VFAC3 0.1µF where aperture jitter may affect the dynamic range of the AD8283. OUT CLK OPTIONAL Power supplies for clock drivers should be separated from the 50Ω* 1.8V 100Ω 0.1µF CMOS DRIVER CLK+ ADC output driver supplies to avoid modulating the clock signal ADC with digital noise. Low jitter, crystal-controlled oscillators make CLK AD8283 0.1µF the best clock sources, such as the Valpey Fisher VFAC3 series. CLK– If the clock is generated from another type of source (by gating, 0.1µF 39kΩ *50Ω RESISTOR IS OPTIONAL. 09795-010 doirvigidininagl ,c olorc okt dhuerri mnge tthhoe dlass)t, istt eshp.o uld be retimed by the Figure 30. Single-Ended 1.8 V CMOS Sample Clock Refer to the AN-501 Application Note and the AN-756 3.3V Application Note for more in-depth information about how VFAC3 0.1µF AD9515/AD9520-0 jitter performance relates to ADCs (visit www.analog.com). OUT CLK OPTIONAL 50Ω* 3.3V 100Ω 0.1µF SDIO PIN CMOS DRIVER CLK+ ADC The SDIO pin is required to operate the SPI. It has an internal CLK AD8283 30 kΩ pull-down resistor that pulls this pin low and is only 1.8 V 0.1µF 0.1µF CLK– tolerant. If applications require that this pin be driven from a *50Ω RESISTOR IS OPTIONAL. 09795-011 3li.m3 iVt tlhoeg iccu lrerveenl,t i.n sert a 1 kΩ resistor in series with this pin to Figure 31. Single-Ended 3.3 V CMOS Sample Clock SCLK PIN CLOCK DUTY CYCLE CONSIDERATIONS The SCLK pin is required to operate the SPI port interface. It has Typical high speed ADCs use both clock edges to generate a an internal 30 kΩ pull-down resistor that pulls this pin low and is variety of internal timing signals. As a result, these ADCs may both 1.8 V and 3.3 V tolerant. be sensitive to the clock duty cycle. Commonly, a 5% tolerance is CS PIN required on the clock duty cycle to maintain dynamic performance The CS pin is required to operate the SPI port interface. It has an characteristics. The AD8283 contains a duty cycle stabilizer (DCS) that retimes the nonsampling edge, providing an internal clock internal 70 kΩ pull-up resistor that pulls this pin high and is both 1.8 V and 3.3 V tolerant. signal with a nominal 50% duty cycle. This allows a wide range of clock input duty cycles without affecting the performance of RBIAS PIN the AD8283. To set the internal core bias current of the ADC, place a resistor When the DCS is on, noise and distortion performance are nearly nominally equal to 10.0 kΩ to ground at the RBIAS pin. Using flat for a wide range of duty cycles. However, some applications other than the recommended 10.0 kΩ resistor for RBIAS may require the DCS function to be off. If so, keep in mind that degrades the performance of the device. Therefore, it is imperative the dynamic range performance can be affected when operated in that at least a 1.0% tolerance on this resistor be used to achieve this mode. See Table 9 for more details on using this feature. consistent performance. The duty cycle stabilizer uses a delay-locked loop (DLL) to VOLTAGE REFERENCE create the nonsampling edge. As a result, any changes to the A stable and accurate 0.5 V voltage reference is built into the sampling frequency require approximately eight clock cycles to AD8283. This is gained up internally by a factor of 2, setting allow the DLL to acquire and lock to the new rate. VREF to 1.0 V, which results in a full-scale differential input span of 2.0 V p-p for the ADC. VREF is set internally by default, but the VREF pin can be driven externally with a 1.0 V Rev. C | Page 17 of 27

AD8283 Data Sheet reference to achieve more accuracy. However, this device does A single PC board ground plane should be sufficient when using not support ADC full-scale ranges below 2.0 V p-p. the AD8283. With proper decoupling and smart partitioning of the PC board’s analog, digital, and clock sections, optimum When applying the decoupling capacitors to the VREF pin, use performance can be achieved easily. ceramic low-ESR capacitors. These capacitors should be close to the reference pin and on the same layer of the PCB as EXPOSED PADDLE THERMAL HEAT SLUG the AD8283. The VREF pin should have both a 0.1 µF capacitor RECOMMENDATIONS and a 1 µF capacitor connected in parallel to the analog ground. It is required that the exposed paddle on the underside of the These capacitor values are recommended for the ADC to device be connected to a quiet analog ground to achieve the properly settle and acquire the next valid sample. best electrical and thermal performance of the AD8283. An POWER AND GROUND RECOMMENDATIONS exposed continuous copper plane on the PCB should mate to When connecting power to the AD8283, it is recommended the AD8283 exposed paddle, Pin 0. The copper plane should have several vias to achieve the lowest possible resistive thermal that two separate 1.8 V supplies and two separate 3.3 V supplies path for heat dissipation to flow through the bottom of the PCB. be used: one for analog 1.8 V (AVDD18x) and digital 1.8 V These vias should be filled or plugged with nonconductive epoxy. (DVDD18x) and one for analog 3.3 V (AVDD33x) and digital 3.3 V (DVDD33x). If only one supply is available for both analog To maximize the coverage and adhesion between the device and and digital, for example, AVDD18x and DVDD18x, it should be PCB, partition the continuous copper pad by overlaying a silk- routed to the AVDD18x first and then tapped off and isolated screen or solder mask to divide this into several uniform sections. with a ferrite bead or a filter choke preceded by decoupling This ensures several tie points between the two during the reflow capacitors for the DVDD18x. The same is true for the analog process. Using one continuous plane with no partitions only and digital 3.3 V supplies. The user should employ several guarantees one tie point between the AD8283 and PCB. For decoupling capacitors on all supplies to cover both high and low more detailed information on packaging and for more PCB frequencies. These should be located close to the point of entry layout examples, see the AN-772 Application Note. at the PC board level and close to the parts, with minimal trace lengths. Rev. C | Page 18 of 27

Data Sheet AD8283 SERIAL PERIPHERAL INTERFACE (SPI) The AD8283 serial port interface allows the user to configure In addition to the operation modes, the SPI port can be the signal chain for specific functions or operations through a configured to operate in different manners. For applications structured register space provided inside the chip. This offers that do not require a control port, the CS line can be tied and the user added flexibility and customization depending on the held high. This places the remainder of the SPI pins in their application. Addresses are accessed via the serial port and can secondary mode as defined in the SDIO Pin and SCLK Pin be written to or read from via the port. Memory is organized sections. CS can also be tied low to enable 2-wire mode. When into bytes that can be further divided into fields, as documented CS is tied low, SCLK and SDIO are the only pins required for in the Memory Map section. Detailed operational information communication. Although the device is synchronized during can be found in the Analog Devices, Inc., AN-877 Application power-up, caution must be exercised when using this mode to Note, Interfacing to High Speed ADCs via SPI. ensure that the serial port remains synchronized with the CS There are three pins that define the serial port interface, or SPI. line. When operating in 2-wire mode, it is recommended to use They are the SCLK, SDIO, and CS pins. The SCLK (serial clock) a 1-, 2-, or 3-byte transfer exclusively. Without an active CS is used to synchronize the read and write data presented to the line, streaming mode can be entered but not exited. device. The SDIO (serial data input/output) is a dual-purpose In addition to word length, the instruction phase determines if pin that allows data to be sent to and read from the device’s the serial frame is a read or write operation, allowing the serial internal memory map registers. The CS (chip select bar) is an port to be used to both program the chip and read the contents active low control that enables or disables the read and write of the on-chip memory. If the instruction is a readback operation, cycles (see Table 7). performing a readback causes the serial data input/output (SDIO) pin to change direction from an input to an output at the Table 7. Serial Port Pins appropriate point in the serial frame. Pin Function SCLK Serial clock. The serial shift clock input. SCLK is used to Data can be sent in MSB- or LSB-first mode. MSB-first mode synchronize serial interface reads and writes. is the default at power-up and can be changed by adjusting the SDIO Serial data input/output. A dual-purpose pin. The typical configuration register. For more information about this and role for this pin is as an input or output, depending on other features, see the AN-877 Application Note, Interfacing to the instruction sent and the relative position in the High Speed ADCs via SPI. timing frame. CS Chip select bar (active low). This control gates the read HARDWARE INTERFACE and write cycles. The pins described in Table 7 constitute the physical interface between the user’s programming device and the serial port of The falling edge of the CS in conjunction with the rising edge of the AD8283. The SCLK and CS pins function as inputs when the SCLK determines the start of the framing sequence. During an using the SPI interface. The SDIO pin is bidirectional, functioning instruction phase, a 16-bit instruction is transmitted, followed by as an input during write phases and as an output during readback. one or more data bytes, which is determined by Bit Field W0 and This interface is flexible enough to be controlled by either serial Bit Field W1. An example of the serial timing and its definitions PROMS or PIC microcontrollers. This provides the user with can be found in Figure 32 and Table 8. an alternative method, other than a full SPI controller, for In normal operation, CS is used to signal to the device that SPI programming the device (see the AN-812 Application Note). commands are to be received and processed. When CS is brought If the user chooses not to use the SPI interface, these pins serve low, the device processes SCLK and SDIO to process instructions. a dual function and are associated with secondary functions Normally, CS remains low until the communication cycle is when the CS is strapped to AVDD during device power-up. See complete. However, if connected to a slow device, CS can be the SDIO Pin and SCLK Pin sections for details on which pin- brought high between bytes, allowing older microcontrollers strappable functions are supported on the SPI pins. enough time to transfer data into shift registers. CS can be stalled when transferring one, two, or three bytes of data. When W0 and W1 are set to 11, the device enters streaming mode and continues to process data, either reading or writing, until CS is taken high to end the communication cycle. This allows complete memory transfers without having to provide additional instructions. Regardless of the mode, if CS is taken high in the middle of any byte transfer, the SPI state machine is reset and the device waits for a new instruction. Rev. C | Page 19 of 27

AD8283 Data Sheet tS tDS tHI tCLK tH CS tDH tLO SCLK DON’T CARE DON’T CARE SDIO DON’T CARE R/W W1 W0 A12 A11 A10 A9 A8 A7 D5 D4 D3 D2 D1 D0 DON’T CARE 09795-012 Figure 32. Serial Timing Details Table 8. Serial Timing Definitions Parameter Minimum Timing (ns) Description t 5 Setup time between the data and the rising edge of SCLK DS t 2 Hold time between the data and the rising edge of SCLK DH t 40 Period of the clock CLK t 5 Setup time between CS and SCLK S t 2 Hold time between CS and SCLK H t 16 Minimum period that SCLK should be in a logic high state HI t 16 Minimum period that SCLK should be in a logic low state LO t 10 Minimum time for the SDIO pin to switch from an input to an output relative to the SCLK EN_SDIO falling edge (not shown in Figure 32). t 10 Minimum time for the SDIO pin to switch from an output to an input relative to the SCLK DIS_SDIO rising edge (not shown in Figure 32) Rev. C | Page 20 of 27

Data Sheet AD8283 MEMORY MAP READING THE MEMORY MAP TABLE LOGIC LEVELS Each row in the memory map table has eight address locations. An explanation of various registers follows: “bit is set” is The memory map is roughly divided into three sections: the synonymous with “bit is set to Logic 1” or “writing Logic 1 for chip configuration registers map (Address 0x00 and Address 0x01), the bit.” Similarly, “clear a bit” is synonymous with “bit is set to Logic 0” or “writing Logic 0 for the bit. the device index and transfer registers map (Address 0x04 to Address 0xFF), and the ADC channel functions registers map RESERVED LOCATIONS (Address 0x08 to Address 0x2C). Undefined memory locations should not be written to except The leftmost column of the memory map indicates the register when writing the default values suggested in this data sheet. address number, and the default value is shown in the second Addresses that have values marked as 0 should be considered rightmost column. The Bit 7 (MSB) column is the start of the reserved and have a 0 written into their registers during power-up. default hexadecimal value given. For example, Address 0x09, DEFAULT VALUES the clock register, has a default value of 0x01, meaning that Bit 7 = 0, Bit 6 = 0, Bit 5 = 0, Bit 4 = 0, Bit 3 = 0, Bit 2 = 0, Bit 1 = 0, After a reset, critical registers are automatically loaded with and Bit 0 = 1, or 0000 0001 in binary. This setting is the default default values. These values are indicated in Table 9, where an X refers to an undefined feature. for the duty cycle stabilizer in the on condition. By writing a 0 to Bit 0 of this address followed by an 0x01 to the SW transfer bit in Register 0xFF, the duty cycle stabilizer turns off. It is important to follow each writing sequence with a write to the SW transfer bit to update the SPI registers. Note that all registers except Register 0x00, Register 0x04, Register 0x05, and Register 0xFF are buffered with a master slave latch and require writing to the transfer bit. For more information on this and other functions, consult the AN-877 Application Note, Interfacing to High Speed ADCs via SPI. Rev. C | Page 21 of 27

AD8283 Data Sheet Table 9. AD8283 Memory Map Register Addr. Bit 7 Bit 0 Default Default Notes/ (Hex) Register Name (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 (LSB) Value Comments Chip Configuration Registers 00 CHIP_PORT_CONFIG 0 LSB first Soft 1 1 Soft LSB first 0 0x18 The nibbles 1 = on reset reset 1 = on should be 0 = off 1 = on 1 = on 0 = off mirrored so (default) 0 = off 0 = off (default) that LSB- or (default) (default) MSB-first mode is set correct regardless of shift mode. 01 CHIP_ID Chip ID Bits[7:0] Read The default is a (AD8283 = 0xA2, default) only unique chip ID, specific to the AD8283. This is a read-only register. Device Index and Transfer Registers 04 DEVICE_INDEX_2 X X X X X X Data Data 0x0F Bits are set to Channel Channel determine F E which on-chip 1 = on 1 = on device receives (default) (default) the next write 0 = off 0 = off command. 05 DEVICE_INDEX_1 X X X X Data Data Data Data 0x0F Bits are set to Channel Channel Channel Channel determine D C B A which on-chip 1 = on 1 = on 1 = on 1 = on device receives (default) (default) (default) (default) the next write 0 = off 0 = off 0 = off 0 = off command. FF DEVICE_UPDATE X X X X X X X SW 0x00 Synchronously transfer transfers data 1 = on from the 0 = off master shift (default) register to the slave. Channel Functions Registers 08 GLOBAL_MODES X X X X X X Internal power- 0x00 Determines the down mode power-down 00 = chip run mode (global). (default) 01 = full power- down 11 = reset 09 GLOBAL_CLOCK X X X X X X X Duty 0x01 Turns the cycle internal duty stabilizer cycle stabilizer 1 = on on and off (default) (global). 0 = off 0C FLEX_MUX_CONTROL X Power- X X Mux input active channels 0x00 Sets which mux down of 0000 = A input channel(s) unused 0001 = Aux are in use and channels 0010 = AB whether to 0 = PD 0011 = A Aux power down (power- unused 0100 = ABC down; channels. 0101 = AB Aux default) 0110 = ABCD 1 = power-on 0111 = ABC Aux 1000 = ABCDE 1001 = ABCD Aux 1010 = ABCDEF 1011 = ABCDE Aux Rev. C | Page 22 of 27

Data Sheet AD8283 Addr. Bit 7 Bit 0 Default Default Notes/ (Hex) Register Name (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 (LSB) Value Comments 0D FLEX_TEST_IO User test mode Reset PN Reset PN Output test mode—see Table 10 0x00 When this 00 = off (default) long short 0000 = off (default) register is set, 01 = on, single gen gen 0001 = midscale short the test data is alternate 1 = on 1 = on 0010 = +FS short placed on the 10 = on, single once 0 = off 0 = off 0011 = −FS short output pins in 11 = on, alternate (default) (default) 0100 = checkerboard output place of once 0101 = PN sequence long normal data. 0110 = PN sequence short (Local, except 0111 = one-/zero-word toggle for PN 1000 = user input sequence.) 1001 = 1-/0-bit toggle 1010 = 1× sync 1011 = one bit high 1100 = mixed bit frequency (format determined by the OUTPUT_MODE register) 0F FLEX_CHANNEL_INPUT Filter cutoff frequency control X X X X 0x30 Low pass filter 0000 = 1.3 × 1/4 × fSAMPLECH cutoff (global). 0001 = 1.2 × 1/4 × fSAMPLECH fSAMPLECH = ADC 0010 = 1.1 × 1/4 × fSAMPLECH sample rate/ 0011 = 1.0 × 1/4 × fSAMPLECH (default) number of 0100 = 0.9 × 1/4 × fSAMPLECH active 0101 = 0.8 × 1/4 × fSAMPLECH channels. 0110 = 0.7 × 1/4 × fSAMPLECH Note that the 0111 = N/A absolute range 1000 = 1.3 × 1/3 × fSAMPLECH is limited to 1001 = 1.2 × 1/3 × fSAMPLECH 1 MHz to 1010 = 1.1 × 1/3 × fSAMPLECH 12 MHz. 1011 = 1.0 × 1/3 × fSAMPLECH 1100 = 0.9 × 1/3 × fSAMPLECH 1101 = 0.8 × 1/3 × fSAMPLECH 1110 = 0.7 × 1/3 × fSAMPLECH 1111 = N/A 10 FLEX_OFFSET X X 6-bit LNA offset adjustment 0x20 LNA force 00 0000 for LNA bias high offset 01 1111 for LNA mid-high correction 10 0000 for LNA mid-low (default) (local). 11 1111 for LNA bias low 11 FLEX_GAIN_1 X X X X X 010 = 16 dB(default) 0x00 Total LNA + 011 = 22 dB PGA gain 100 = 28 dB adjustment 101 = 34 dB (local) 12 FLEX_BIAS_CURRENT X X X X X X LNA bias 0x09 LNA bias 00 = high current 01 = mid-high adjustment (default) (global). 10 = mid-low 11 = low 14 FLEX_OUTPUT_MODE X X X X X 1 = 0 = offset binary 0x00 Configures the output (default) outputs and invert 1 = twos comple- the format of (local) ment (global) the data. 15 FLEX_OUTPUT_ADJUST 0 = X X X Typical output rise Typical output drive 0x0F Used to adjust enable time and fall time, strength output rise and Data respectively 00 = 45 mA fall times and Bits 00 = 2.6 ns, 3.4 ns 01 = 30 mA select output [11:0] 01 = 1.1 ns, 1.6 ns 10 = 60 mA drive strength, 1 = 10 = 0.7 ns, 0.9 ns 11 = 60 mA limiting the disable 11 = 0.7 ns, 0.7 ns (default) noise added to Data (default) the channels Bits by output [11:0] switching. Rev. C | Page 23 of 27

AD8283 Data Sheet Addr. Bit 7 Bit 0 Default Default Notes/ (Hex) Register Name (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 (LSB) Value Comments 18 FLEX_VREF X 0 = X X X X 00 = 0.625 V 0x03 Select internal internal 01 = 0.750 V reference reference 10 = 0.875 V (recommended 1 = default) or ex- 11 = 1.024 V external (default) ternal reference reference (global); adjust internal refer- ence. 19 FLEX_USER_PATT1_LSB B7 B6 B5 B4 B3 B2 B1 B0 0x00 User-defined pattern, 1 LSB. 1A FLEX_USER_PATT1_ B15 B14 B13 B12 B11 B10 B9 B8 0x00 User-defined MSB pattern, 1 MSB. 1B FLEX_USER_PATT2_LSB B7 B6 B5 B4 B3 B2 B1 B0 0x00 User-defined pattern, 2 LSBs. 1C FLEX_USER_PATT2_ B15 B14 B13 B12 B11 B10 B9 B8 0x00 User-defined MSB pattern, 2 MSBs. 2B FLEX_FILTER X Enable X X 0x00 automatic low-pass tuning 1 = on (self- clearing) 2C CH_IN_IMP X X X X X X 0 = 0x00 Input imped- 200Ω ance adjust- (default) ment (global). 1 = 200kΩ Table 10. Flexible Output Test Modes Output Test Mode Subject to Data Bit Sequence Pattern Name Digital Output Word 1 Digital Output Word 2 Format Select 0000 Off (default) N/A N/A N/A 0001 Midscale short 1000 0000 0000 Same Yes 0010 +Full-scale short 1111 1111 1111 Same Yes 0011 −Full-scale short 0000 0000 0000 Same Yes 0100 Checkerboard output 1010 1010 1010 0101 0101 0101 No 0101 PN sequence long N/A N/A Yes 0110 PN sequence short N/A N/A Yes 0111 One-/zero-word toggle 1111 1111 1111 0000 0000 0000 No 1000 User input Register 0x19 to Register 0x1A Register 0x1B to Register 0x1C No 1001 1-/0-bit toggle 1010 1010 1010 N/A No 1010 1× sync 0000 0011 1111 N/A No 1011 One bit high 1000 0000 0000 N/A No 1100 Mixed bit frequency 1010 0011 0011 N/A No Rev. C | Page 24 of 27

Data Sheet AD8283 APPLICATION DIAGRAMS AVDD33REF DVDD33SPI DVDD18 AVDD18 3.3V 0.1µF 3.3V 0.1µF 1.8V 0.1µF 1.8V 0.1µF AVDD33A DVDD33CLK DVDD18CLK AVDD18 0.1µF 0.1µF 0.1µF 0.1µF AVDD33B DVDD33DRV AVDD18ADC 0.1µF 0.1µF 0.1µF AVDD33C DVDD33DRV 0.1µF 0.1µF AVDD33D 0.1µF 01234567891011 AVDD33E DDDDDDDDDDDD 0.1µF 210987654321098765 777666666666655555 AVDD33F 0.1µF NCDRVNCNCD0D1D2D3D4D5D6D7D8D9D10D11DRVNC 3 3 3 3 NC 1 NC DD DD NC 54 2 V V 53 DSYNC DSYNC D D TEST4 3 52 PDWN PDWN DVDD18CLK SCLK 10kΩ 456 DSCVDLKD18 CCLLKK+– 554109 CCLLKK+– SDIO SDIO DVDD33CLK 7 48 CS 8 CS AVDD33REF 47 AUX AUX VREF MUXA 9 MUXA AD8283 RBIAS 46 10kΩ 0.1µF 0.1µF ZSEL 111012 ZTTSEEESSLTT12 (TOP VIEW) AABNPAOONUUDTT 444543 1% 0.1µF INADC+ 13 DVDD33SPI TEST3 42 14 AVDD18 AVDD18ADC 41 INA– 0.1µF 15 AVDD33A AVDD18 40 16 INA– INADC+ 39 17 INA+ INADC– 38 18 NC 3B 3C 3D 3E 3F NC 37 D3 D3 D3 D3 D3 0.1µF INADC– INA+ 0.1µF NCNCAVDINB–INB+AVDINC–INC+AVDIND–IND+AVDINE–INE+AVDINF–INF+NC 901234567890123456 122222222223333333 0.1µF INF+ INB– 0.1µF INB+ 0.1µF 0.1µF INF– 0.1µF INE+ INC– 0.1µF 0.1µF INE– INC+ 0.1µF 0.1µF IND+ 0.1µF IND– N1.O ATLELS CAPACITORS FOR SUPPLIES AND REFERENCES SHOULD BE PLACED CLOSE TO THE PART. 09795-013 Figure 33. Differential Inputs Rev. C | Page 25 of 27

AD8283 Data Sheet AVDD33REF DVDD33SPI DVDD18 AVDD18 3.3V 0.1µF 3.3V 0.1µF 1.8V 0.1µF 1.8V 0.1µF AVDD33A DVDD33CLK DVDD18CLK AVDD18 0.1µF 0.1µF 0.1µF 0.1µF AVDD33B DVDD33DRV AVDD18ADC 0.1µF 0.1µF 0.1µF AVDD33C DVDD33DRV 0.1µF 0.1µF AVDD33D 0.1µF 01 012345678911 AVDD33E DDDDDDDDDDDD 0.1µF 210987654321098765 777666666666655555 AVDD33F 0.1µF NCDRVNCNCD0D1D2D3D4D5D6D7D8D9D10D11DRVNC 3 3 3 3 NC 1 NC DD DD NC 54 2 V V 53 DSYNC DSYNC D D TEST4 3 52 PDWN PDWN DVDD18CLK 4 51 SCLK 10kΩ 56 DSCVDLKD18 CCLLKK+– 5409 CCLLKK+– SDIO SDIO DVDD33CLK 7 48 CS CS AVDD33REF 8 47 AUX AUX VREF MUXA 9 MUXA AD8283 RBIAS 46 10kΩ 0.1µF 0.1µF ZSEL 111012 ZTTSEEESSLTT12 (TOP VIEW) AABNPAOONUUDTT 444543 1% 0.1µF INADC+ 13 DVDD33SPI TEST3 42 14 AVDD18 AVDD18ADC 41 15 AVDD33A AVDD18 40 16 INA– INADC+ 39 R 17 INA+ INADC– 38 0.1µF 18 NC 3B 3C 3D 3E 3F NC 37 D3 D3 D3 D3 D3 0.1µF INADC– INA 0.1µF NCNCAVDINB–INB+AVDINC–INC+AVDIND–IND+AVDINE–INE+AVDINF–INF+NC 901234567890123456 122222222223333333 0.1µF INF INB 0.1µF 0.1µF INE INC 0.1µF 0.1µF IND N12..O RATELELSS ICSATOPARC RIT (OINRxS– FINOPRU TSSU)P SPHLOIEUSL ADN MDA RTECFHE TRHEEN COEUST PSUHTO UIMLPDE BDEA NPCLAEC OEFD T CHLEO ISNEP UTTO DTRHIEV EPRA.RT. 09795-029 Figure 34. Single-Ended Inputs Rev. C | Page 26 of 27

Data Sheet AD8283 OUTLINE DIMENSIONS 10.10 0.60 0.30 10.00 SQ 0.60 0.42 0.23 9.90 0.42 0.24 0.18 PIN 1 0.24 5455 721 INDICATOR PIN 1 INDICATOR 9.85 0.50 9.75 SQ BSC 8.60 9.65 EXPOSED 8.50 SQ PAD 8.40 0.50 0.40 18 TOP VIEW 0.30 3367 BOTTOM VIEW 19 0.25 MIN 0.70 8.50 REF 12° MAX 0.65 0.90 0.85 0.60 FOR PROPER CONNECTION OF 0.05 MAX THE EXPOSED PAD, REFER TO 0.80 THE PIN CONFIGURATION AND 0.01 NOM FUNCTION DESCRIPTIONS SEPALTAINNGE COMPLIANT TO0 .J2E0D REECF SCTOAPNLD0A.A0NR8ADRSIT MYO-220-VNND-4 SECTION OF THIS DATA SHEET. 11-06-2013-C Figure 35. 72-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 10 mm × 10 mm Body, Very Thin Quad (CP-72-5) Dimensions shown in millimeters ORDERING GUIDE Model1, 2, 3 Temperature Range Package Description Package Option AD8283WBCPZ-RL −40°C to +105°C 72-Lead LFCSP_VQ, 13” Tape and Reel CP-72-5 AD8283WBCPZ −40°C to +105°C 72-Lead LFCSP_VQ, Waffle Pack CP-72-5 AD8283CP-EBZ Evaluation Board 1 Z = RoHS Compliant Part. 2 W = Qualified for Automotive Applications. 3 Compliant to JEDEC Standard MO-220-VNND-4. AUTOMOTIVE PRODUCTS The AD8283WBCPZ models are available with controlled manufacturing to support the quality and reliability requirements of automotive applications. Note that these automotive models may have specifications that differ from the commercial models; therefore, designers should review the Specifications section of this data sheet carefully. Only the automotive grade products shown are available for use in automotive applications. Contact your local Analog Devices account representative for specific product ordering information and to obtain the specific Automotive Reliability reports for this model. ©2011–2015 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D09795-0-8/15(C) Rev. C | Page 27 of 27