Single Supply, Rail-to-Rail Low Power, FET-Input Op Amp Data Sheet AD824 FEATURES PIN CONFIGURATION Single supply operation: 3 V to 30 V OUT A 1 14 OUT D Very low input bias current: 2 pA –IN A 2 13 –IN D Wide input voltage range +IN A 3 AD824 12 +IN D Rail-to-rail output swing TOP VIEW V+ 4 (Not to Scale) 11 V– Low supply current per amplifier: 500 µA +IN B 5 10 +IN C Wide bandwidth: 2 MHz SNloe wph raatsee: r2e vVe/µrssa l O–UINT BB 67 98 O–IUNT C C 00875-001 Figure 1. 14-Lead SOIC (R Suffix) APPLICATIONS Photo diode preamplifier Battery powered instrumentation Power supply control and protection Medical instrumentation Remote sensors Low voltage strain gage amplifiers DAC output amplifier GENERAL DESCRIPTION The AD824 is a quad, FET input, single supply amplifier, The FET input combined with laser trimming provides an input featuring rail-to-rail outputs. The combination of FET inputs that has extremely low bias currents with guaranteed offsets and rail-to-rail outputs makes the AD824 useful in a wide below 1 mV. This enables high accuracy designs even with high variety of low voltage applications where low input current is source impedances. Precision is combined with low noise, a primary consideration. making the AD824 ideal for use in battery powered medical equipment. The AD824 is guaranteed to operate from a 3 V single supply up to ±15 V dual supplies. AD824AR-3V parametric Applications for the AD824 include portable medical performance at 3 V is fully guaranteed. equipment, photo diode preamplifiers, and high impedance transducer amplifiers. Fabricated on Analog Devices, Inc., complementary bipolar process, the AD824 has a unique input stage that allows the The ability of the output to swing rail-to-rail enables designers input voltage to safely extend beyond the negative supply and to build multistage filters in single supply systems and maintain to the positive supply without any phase inversion or latch-up. high signal-to-noise ratios. The output voltage swings to within 15 mV of the supplies. The AD824 is specified over the extended industrial (−40°C to Capacitive loads to 350 pF can be handled without oscillation. +85°C) temperature range and is available in narrow 14-lead SOIC package. Rev. E Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Tel: 781.329.4700 ©2015 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com

AD824 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Input Characteristics .................................................................. 12 Applications ....................................................................................... 1 Output Characteristics............................................................... 12 Pin Configuration ............................................................................. 1 Applications Information .............................................................. 13 General Description ......................................................................... 1 Single Supply Voltage-to-Frequency Converter ..................... 13 Revision History ............................................................................... 2 Single Supply Programmable Gain Instrumentation Specifications ..................................................................................... 3 Amplifier ..................................................................................... 13 Electrical Specifications ............................................................... 3 3 V, Single Supply Stereo Headphone Driver ......................... 14 Absolute Maximum Ratings ............................................................ 6 Low Dropout Bipolar Bridge Driver ........................................ 14 Thermal Resistance ...................................................................... 6 A 3.3 V/5 V Precision Sample-and-Hold Amplifier .............. 15 Outline Dimensions ....................................................................... 16 ESD Caution .................................................................................. 6 Typical Performance Characteristics ............................................. 7 Ordering Guide .......................................................................... 16 Theory of Operation ...................................................................... 12 REVISION HISTORY 4/15—Rev. D to Rev. E Change to Figure 1 Caption ............................................................ 1 5/14—Rev. C to Rev. D Updated Format .................................................................. Universal Removed 16-Lead SOIC Package (Throughout) .......................... 1 Deleted Wafer Test Limits Section ................................................. 5 Deleted AD824 SPICE Macro-model Section ............................ 15 Changes to Ordering Guide .......................................................... 16 2/03—Rev. B to Rev. C Deleted N Package .............................................................. Universal Edits to General Description ........................................................... 1 Edits to Absolute Maximum Ratings ............................................. 5 Edits to Ordering Guide .................................................................. 5 Edits to Figure 4 .............................................................................. 12 Edits to Figure 8 .............................................................................. 13 Updated Outline Dimensions ....................................................... 16 1/02—Rev. A to Rev. B Edits to Electrical Specifications ................................................. 2, 3 Edits to Absolute Maximum Ratings ............................................. 5 Edits to Ordering Guide .................................................................. 5 Deleted Dice Characteristics ........................................................... 5 Rev. E | Page 2 of 16

Data Sheet AD824 SPECIFICATIONS ELECTRICAL SPECIFICATIONS At V = 5.0 V, V = 0 V, V = 0.2 V, T = 25°C; unless otherwise noted. S CM OUT A Table 1. Parameter Symbol Test Conditions/Comments Min Typ Max Unit INPUT CHARACTERISTICS Offset Voltage (AD824A) V 0.1 1.0 mV OS T to T 1.5 mV MIN MAX Input Bias Current I 2 12 pA B T to T 300 4000 pA MIN MAX Input Offset Current I 2 10 pA OS T to T 300 pA MIN MAX Input Voltage Range −0.2 +3.0 V Common-Mode Rejection Ratio CMRR V = 0 V to 2 V 66 80 dB CM V = 0 V to 3 V 60 74 dB CM T to T 60 dB MIN MAX Input Impedance 1013||3.3 Ω||pF Large Signal Voltage Gain A V = 0.2 V to 4.0 V VO O R = 2 kΩ 20 40 V/mV L R = 10 kΩ 50 100 V/mV L R = 100 kΩ 250 1000 V/mV L T to T , R = 100 kΩ 180 400 V/mV MIN MAX L Offset Voltage Drift ΔV /ΔT 2 µV/°C OS OUTPUT CHARACTERISTICS Output Voltage High V I = 20 µA 4.975 4.988 V OH SOURCE T to T 4.97 4.985 V MIN MAX I = 2.5 mA 4.80 4.85 V SOURCE T to T 4.75 4.82 V MIN MAX Output Voltage Low V I = 20 µA 15 25 mV OL SINK T to T 20 30 mV MIN MAX I = 2.5 mA 120 150 mV SINK T to T 140 200 mV MIN MAX Short Circuit Limit I Sink/source ±12 mA SC T to T ±10 mA MIN MAX Open-Loop Impedance Z f = 1 MHz, A = 1 100 Ω OUT V POWER SUPPLY Power Supply Rejection Ratio PSRR V = 2.7 V to 12 V 70 80 dB S T to T 66 dB MIN MAX Supply Current/Amplifier I T to T 500 600 µA SY MIN MAX DYNAMIC PERFORMANCE Slew Rate SR R = 10 kΩ, A = 1 2 V/µs L V Full-Power Bandwidth BW 1% distortion, V = 4 V p-p 150 kHz P O Settling Time t V = 0.2 V to 4.5 V, to 0.01% 2.5 µs S OUT Gain Bandwidth Product GBP 2 MHz Phase Margin φo No load 50 Degrees Channel Separation CS f = 1 kHz, R = 2 kΩ –123 dB L NOISE PERFORMANCE Voltage Noise e p-p 0.1 Hz to 10 Hz 2 µV p-p n Voltage Noise Density e f = 1 kHz 16 nV/√Hz n Current Noise Density i f = 1 kHz 0.8 fA/√Hz n Total Harmonic Distortion THD f = 10 kHz, R = ∞, A = +1 0.005 % L V Rev. E | Page 3 of 16

AD824 Data Sheet At V = ±15.0 V, V = 0 V, T = 25°C; unless otherwise noted. S OUT A Table 2. Parameter Symbol Test Conditions/Comments Min Typ Max Unit INPUT CHARACTERISTICS Offset Voltage (AD824A) V 0.5 2.5 mV OS T to T 0.6 4.0 mV MIN MAX Input Bias Current I V = 0 V 4 35 pA B CM T to T 500 4000 pA MIN MAX I V = −10 V 25 pA B CM Input Offset Current I 3 20 pA OS T to T 500 pA MIN MAX Input Voltage Range −15 +13 V Common-Mode Rejection Ratio CMRR V = −15 V to 13 V 70 80 dB CM T to T 66 dB MIN MAX Input Impedance 1013||3.3 Ω||pF Large Signal Voltage Gain A V = −10 V to +10 V; VO O R = 2 kΩ 12 50 V/mV L R = 10 kΩ 50 200 V/mV L R = 100 kΩ 300 2000 V/mV L T to T , R = 100 kΩ 200 1000 V/mV MIN MAX L Offset Voltage Drift ΔV /ΔT 2 µV/°C OS OUTPUT CHARACTERISTICS Output Voltage High V I = 20 µA 14.975 14.988 V OH SOURCE T to T 14.970 14.985 V MIN MAX I = 2.5 mA 14.80 14.85 V SOURCE T to T 14.75 14.82 V MIN MAX Output Voltage Low V I = 20 µA –14.985 –14.975 V OL SINK T to T –14.98 –14.97 V MIN MAX I = 2.5 mA –14.88 –14.85 V SINK T to T –14.86 –14.8 V MIN MAX Short Circuit Limit I Sink/source, T to T ±8 ±20 mA SC MIN MAX Open-Loop Impedance Z f = 1 MHz, A = 1 100 Ω OUT V POWER SUPPLY Power Supply Rejection Ratio PSRR V = 2.7 V to 15 V 70 80 dB S T to T 68 dB MIN MAX Supply Current/Amplifier I V = 0 V 560 625 µA SY O T to T 675 µA MIN MAX DYNAMIC PERFORMANCE Slew Rate SR R = 10 kΩ, A = 1 2 V/µs L V Full-Power Bandwidth BW 1% distortion, V = 20 V p-p 33 kHz P O Settling Time t V = 0 V to 10 V, to 0.01% 6 µs S OUT Gain Bandwidth Product GBP 2 MHz Phase Margin φo 50 Degrees Channel Separation CS f = 1 kHz, R = 2 kΩ –123 dB L NOISE PERFORMANCE Voltage Noise e p-p 0.1 Hz to 10 Hz 2 µV p-p n Voltage Noise Density e f = 1 kHz 16 nV/√Hz n Current Noise Density i f = 1 kHz 1.1 fA/√Hz n Total Harmonic Distortion THD f =10 kHz, V = 3 V rms, R = 10 kΩ 0.005 % O L Rev. E | Page 4 of 16

Data Sheet AD824 At V = 3.0 V, V = 0 V, V = 0.2 V, T = 25°C; unless otherwise noted. S CM OUT A Table 3. Parameter Symbol Test Conditions/Comments Min Typ Max Unit INPUT CHARACTERISTICS Offset Voltage (AD824A−3 V) V 0.2 1.0 mV OS T to T 1.5 mV MIN MAX Input Bias Current I 2 12 pA B T to T 250 4000 pA MIN MAX Input Offset Current I 2 10 pA OS T to T 250 pA MIN MAX Input Voltage Range 0 1 V Common-Mode Rejection Ratio CMRR V = 0 V to 1 V 58 74 dB CM T to T 56 dB MIN MAX Input Impedance 1013||3.3 Ω||pF Large Signal Voltage Gain A V = 0.2 V to 2.0 V; VO O R = 2 kΩ 10 20 V/mV L R = 10 kΩ 30 65 V/mV L R = 100 kΩ 180 500 V/mV L T to T , R = 100 kΩ 90 250 V/mV MIN MAX L Offset Voltage Drift ΔV /ΔT 2 µV/°C OS OUTPUT CHARACTERISTICS Output Voltage High V I = 20 µA 2.975 2.988 V OH SOURCE T to T 2.97 2.985 V MIN MAX I = 2.5 mA 2.8 2.85 V SOURCE T to T 2.75 2.82 V MIN MAX Output Voltage Low V I = 20 µA 15 25 mV OL SINK T to T 20 30 mV MIN MAX I = 2.5 mA 120 150 mV SINK T to T 140 200 mV MIN MAX Short Circuit Limit I Sink/source ±8 mA SC I Sink/source, T to T ±6 mA SC MIN MAX Open-Loop Impedance Z f = 1 MHz, A = 1 100 Ω OUT V POWER SUPPLY Power Supply Rejection Ratio PSRR V = 2.7 V to 12 V, 70 dB S T to T 66 dB MIN MAX Supply Current/Amplifier I V = 0.2 V, T to T 500 600 µA SY O MIN MAX DYNAMIC PERFORMANCE Slew Rate SR R =10 kΩ, A = 1 2 V/µs L V Full-Power Bandwidth BW 1% distortion, V = 2 V p-p 300 kHz P O Settling Time t V = 0.2 V to 2.5 V, to 0.01% 2 µs S OUT Gain Bandwidth Product GBP 2 MHz Phase Margin φo 50 Degrees Channel Separation CS f = 1 kHz, R = 2 kΩ –123 dB L NOISE PERFORMANCE Voltage Noise e p-p 0.1 Hz to 10 Hz 2 µV p-p n Voltage Noise Density e f = 1 kHz 16 nV/√Hz n Current Noise Density i 0.8 fA/√Hz n Total Harmonic Distortion THD f = 10 kHz, R = ∞, A = +1 0.01 % L V Rev. E | Page 5 of 16

AD824 Data Sheet ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE Table 4. Parameter1 Rating Table 5. Thermal Resistance Supply Voltage ±18 V Package Type θJA1 θJC Unit Input Voltage −VS − 0.2 V to +VS 14-Lead SOIC (R) 120 36 °C/W Differential Input Voltage ±30 V Output Short Circuit Duration to GND Indefinite 1 θJA is specified for the worst case conditions, that is, θJA is specified for device soldered in circuit board for SOIC package. Storage Temperature Range −65°C to +150°C Operating Temperature Range −40°C to +85°C Junction Temperature Range −65°C to +150°C ESD CAUTION Lead Temperature Range (Soldering 60 sec) 300°C 1 Absolute maximum ratings apply to packaged parts unless otherwise noted. Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. VCC I5 I6 R1 R2 Q18 Q29 R9 Q21Q27 Q4 Q6 C3 J1 J2 Q5 +IN Q19 Q20 Q7 R7 C4 R13 R15 C2 Q22 Q23 VOUT –IN Q24Q25 Q8 C1 Q2 Q3 Q31 R12 R14 R17 Q28 Q26 I1 I2 I3 I4 VEE 00875-002 Figure 2. Simplified Schematic of 1/4 AD824 Rev. E | Page 6 of 16

Data Sheet AD824 TYPICAL PERFORMANCE CHARACTERISTICS VS = ±15V VS = 5V 80 NO LOAD 80 NO LOAD 60 60 B) B) d d N ( 40 N ( 40 AI AI G 45 s) G 45 s) e e e e 20 90 egr 20 90 egr D D 135 E ( 135 E ( S S A A H H 0 180 P 0 180 P 100 1k 10k 100k 1M 10M 100 1k 10k 100k 1M 10M FREQUENCY (Hz) FREQUENCY (Hz) 100 100 90 90 10 10 0% 0% 50mV 1µs 00875-003 50mV 1µs 00875-005 Figure 3. Open-Loop Gain/Phase and Small Signal Response, VS = ±15 V, Figure 5. Open-Loop Gain/Phase and Small Signal Response, VS = 5 V, No Load No Load 80 CVSL == ±11050VpF 60 VCSL == 52V20pF 60 40 s) GAIN (dB) 2400 9405 egrees) GAIN (dB) 200 1914803505 PHASE (Degree D 135 E ( S A H 0 180 P –20 100 1k 10k 100k 1M 10M 1k 10k 100k 1M 10M FREQUENCY (Hz) FREQUENCY (Hz) 100 100 90 90 10 10 0% 50mV 1µs 00875-004 0% 50mV 1µs 00875-006 Figure 4. Open-Loop Gain/Phase and Small Signal Response, VS = ±15 V, Figure 6. Open-Loop Gain/Phase and Small Signal Response, VS = 5 V, CL = 100 pF CL = 220 pF Rev. E | Page 7 of 16

AD824 Data Sheet VS = 3V 60 NO LOAD 40 t 9.950µs s) GAIN (dB) 20 9140355 ASE (Degree 19000 H P 0 180 10 0% –20 5V 2µs 1k 10k 100k 1M 10M FREQUENCY (Hz) t 10.810µs 100 100 90 90 10 10 0% 50mV 1µs 00875-007 0% 5V 2µs 00875-009 Figure 7. Open-Loop Gain/Phase and Small Signal Response, VS = 3 V, Figure 9. Slew Rate, RL = 10 kΩ No Load 60 VCSL == 32V20pF 19000 VOUT 40 s) GAIN (dB) 20 9140355 HASE (Degree 01%0 5V 100µs 00875-010 P Figure 10. Phase Reversal with Inputs Exceeding Supply by 1 V 0 180 0.8 –20 0.7 1k 10k 100k 1M 10M FREQUENCY (Hz) 0.6 V) L ( 0.5 AI R TO 0.4 19000 UT SOURCE TP 0.3 U O 0.2 SINK 0.1 10 0% 50mV 1µs 00875-008 01µ 5µ 10µ L5O0µAD C1U0R0RµENT5 0(0Aµ) 1m 5m 10m 00875-011 Figure 8. Open-Loop Gain/Phase and Small Signal Response, VS = 3 V, Figure 11. Output Voltage to Supply Rail vs. Sink and Source Load Currents CL = 220 pF Rev. E | Page 8 of 16

Data Sheet AD824 14 COUNT = 60 12 10 S T 3V ≤ VS ≤ ±15V NI Hz) OF U 8 NSITY (nV/√6400 NUMBER 64 E D E OIS20 2 N 5 FRE1Q0UENCY1 5(kHz) 20 00875-012 0–2.5 –2.0 –1.5OF–F1S.0ET –V0O.5LTAG0E DR0.I5FT (µ1V.0/°C)1.5 2.0 2.5 00875-015 Figure 12. Voltage Noise Density Figure 15. TC VOS Distribution, −55°C to +125°C, VS = 5 V, 0 V 0.1 150 RL =∞ VS = 5V, 0V AV = +1 125 A) p 0.01 VS = +3V NT ( 100 E + N (%) VS = +5V T CURR 75 D E TH FFS 50 0.001 VS = ±15V T O U 25 P N I 0 0.000120 100 FREQUENCY (1Hkz) 10k 20k 00875-013 –25–60 –40 –20 0 TEM20PERA4T0URE6 (0°C) 80 100 120 140 00875-016 Figure 13. Total Harmonic Distortion Figure 16. Input Offset Current vs. Temperature 280 100k COUNT = 860 VS = 5V, 0V 240 10k A) 200 p NITS ENT ( 1k F U 160 RR BER O 120 AS CU 100 M BI NU UT 10 80 P N I 1 40 0–0.5 –0.4 –0.3 –0.O2FF–S0E.1T VO0LTAG0E.1 (mV0).2 0.3 0.4 0.5 00875-014 0.120 40 60TEMPERA8T0URE (°C1)00 120 140 00875-017 Figure 14. Input Offset Distribution, VS = 5 V, 0 V Figure 17. Input Bias Current vs. Temperature Rev. E | Page 9 of 16

AD824 Data Sheet 120 1k dB) 100 Hz) ON ( nV/√ JECTI 80 OISE ( 100 MODE RE 60 LTAGE N MON- 40 T VO 10 OM NPU C 20 I 010 100 1kFREQU1E0NkCY (Hz)100k 1M 10M 00875-018 11 10 F1R0E0QUENCY (1Hkz) 10k 100k 00875-021 Figure 18. Common-Mode Rejection vs. Frequency Figure 21. Input Voltage Noise Spectral Density vs. Frequency –40 120 B)100 d –60 N ( O TI 80 C E D (dB) –80 Y REJ 60 H L T PP U R S 40 E –100 W O P 20 –120100 1kFREQUENCY (Hz)10k 100k 00875-019 010 100 1kFREQU1E0NkCY (Hz)100k 1M 10M 00875-022 Figure 19. THD vs. Frequency, 3 V rms Figure 22. Power Supply Rejection vs. Frequency 100 100 30 80 80 25 OP GAIN (dB) 6400 ±15V 6400 RGIN (Degrees) VOLTAGE (V) 2105 OPEN-LO 20 3V, 0V 20 HASE MA OUTPUT 10 P 0 0 5 –2010 100 1kFREQU1E0NkCY (Hz)100k 1M 10M–20 00875-020 01k 3k I1N0PkUT FRE3Q0UkENCY 1(H0z0)k 300k 1M 00875-023 Figure 20. Open-Loop Gain and Phase vs. Frequency Figure 23. Large Signal Frequency Response Rev. E | Page 10 of 16

Data Sheet AD824 –80 –90 B)–100 d K ( TAL–110 5V 5µs SS 1 TO 4 100 O 90 R C–120 1 TO 2 1 TO 3 –130 10 –14010 100 FREQUE1NkCY (Hz) 10k 100k 00875-024 0% 00875-027 Figure 24. Crosstalk vs. Frequency Figure 27. Large Signal Response 10k 2750 VS = ±15V 2500 1k NCE (Ω)100 NT (µA)2250 DA RE2000 PE 10 UR VS = +3V, 0V M C OUTPUT I 1 SUPPLY 11570500 0.1 1250 0.0110 100 1kFREQU1E0NkCY (Hz)100k 1M 10M 00875-025 1000–60 –40 –20 0 TEM20PERA4T0URE6 (0°C) 80 100 120 140 00875-028 Figure 25. Output Impedance vs. Frequency, Gain = +1 Figure 28. Supply Current vs. Temperature 1k VS = ±15V VS = 3V, 0V V) m E ( G A LT100 O V N 20mV 500ns O ATI VOL – VS 100 R 90 U T SA 10 VS – VOH T U P T U O 10 0% 00875-026 10.01 0L.1OAD CURRENT (mA1) 10 00875-029 Figure 26. Small Signal Response, Unity Gain Follower, 10 kΩ||100 pF Load Figure 29. Output Saturation Voltage Rev. E | Page 11 of 16

AD824 Data Sheet THEORY OF OPERATION INPUT CHARACTERISTICS positive supply by more than 300 mV or if an input voltage will be applied to the AD824 when ±V = 0 V. The amplifier will be S In the AD824, n-channel JFETs are used to provide a low offset, damaged if left in that condition for more than 10 seconds. A low noise, high impedance input stage. Minimum input 1 kΩ resistor allows the amplifier to withstand up to 10 V of common-mode voltage extends from 0.2 V below −V to 1 V S continuous overvoltage and increases the input voltage noise by less than +V. Driving the input voltage closer to the positive S a negligible amount. rail causes a loss of amplifier bandwidth. Input voltages less than −V are a completely different story. The S The AD824 does not exhibit phase reversal for input voltages up amplifier can safely withstand input voltages 20 V below the to and including +V. Figure 30a shows the response of an S −V as long as the total voltage from the +V to the input termi- S S AD824 voltage follower to a 0 V to 5 V (+V) square wave input. S nal is less than 36 V. In addition, the input stage typically maintains The input and output are superimposed. The output tracks the picoamp level input currents across that input voltage range. input up to +V without phase reversal. The reduced bandwidth S OUTPUT CHARACTERISTICS above a 4 V input causes the rounding of the output waveform. For input voltages greater than +VS, a resistor in series with the The unique bipolar rail-to-rail output stage of the AD824 noninverting input prevents phase reversal at the expense of swings within 15 mV of the positive and negative supply greater input voltage noise. This is illustrated in Figure 30b. voltages. The approximate output saturation resistance of the AD824 is 100 Ω for both sourcing and sinking. This can be used 1V 2µs to estimate output saturation voltage when driving heavier 100 current loads. For instance, the saturation voltage is 0.5 V from 90 either supply with a 5 mA current load. For load resistances over 20 kΩ, the input error voltage of the AD824 is virtually unchanged until the output voltage is driven to 180 mV of either supply. 10 GND 0% If the output of the AD824 is overdriven to saturate either of the 1V output devices, the amplifier will recover within 2 μs of its input (a) returning to the amplifier’s linear operating region. Direct capacitive loads will interact with the amplifier’s effective 1V 1V 10µs output impedance to form an additional pole in the amplifier’s 100 +VS 90 feedback loop, which can cause excessive peaking on the pulse response or loss of stability. Worst case is when the amplifier is used as a unity gain follower. Figure 6 and Figure 8 show the pulse response of the AD824 as a unity gain follower driving 10 220 pF. Configurations with less loop gain, and as a result less GND 0% loop bandwidth, will be much less sensitive to capacitance load 1V effects. Noise gain is the inverse of the feedback attenuation (b) factor provided by the feedback network in use. 5V Figure 31 shows a method for extending capacitance load drive RP capability for a unity gain follower. With these component VIN values, the circuit drives 5,000 pF with a 10% overshoot. VOUT 00875-030 8+VS 0.01µF Figure 30. (a) Response with RP = 0; VIN from 0 V to +VS; 1/4 100Ω (b) VIN = −200 V to + VS + 200 mV; VOUT = 0 V to + VS; RP = 49.9 kΩ VIN AD824 0.01µF VOUT Because the input stage uses n-channel JFETs, input current 4 during normal operation is positive; the current flows out from –VS CL the input terminals. If the input voltage is driven more positive 20pF tdheavnic +e VjuSn −c t0io.4n Vs ,b tehceo imnpe ufot rcwurarredn bt iraesveedr.s Tesh disi ries citliluonst raast eindt einrn al 20kΩ 00875-031 Figure 10. Figure 31. Extending Unity Gain Follower Capacitive Load Capability Beyond 350 pF Use a current-limiting resistor in series with the input of the AD824 if there is a possibility of the input voltage exceeding the Rev. E | Page 12 of 16

Data Sheet AD824 APPLICATIONS INFORMATION SINGLE SUPPLY VOLTAGE-TO-FREQUENCY Table 6. AD824 In Amp Performance CONVERTER Parameter V = 3 V, 0 V V = ±5 V S S The circuit shown in Figure 32 uses the AD824 to drive a low CMRR 74 dB 80 dB power timer, which produces a stable pulse of width, t. The Common-Mode Voltage Range −0.2 V to +2 V −5.2 V to +4 V 1 positive going output pulse is integrated by R1 and C1 and used 3 dB BW as one input to the AD824, which is connected as a differential G = 10 180 kHz 180 kHz integrator. The other input (nonloading) is the unknown G = 100 18 kHz 18 kHz voltage, V . The AD824 output drives the timer trigger input, t IN SETTLING closing the overall feedback loop. 2 V Step (V = 0 V, 3 V) 2 μs S 10V 5 V (VS = ± 5 V) 5 μs U4 Noise @ f = 1 kHz REF02 C5 0.1µF 2 VREF = 5V G = 10 270 nV/√Hz 270 nV/√Hz 6 G = 100 2.2 μV/√Hz 2.2 μV/√Hz 3 5 R10SkCΩALE** C74MHOCSO4 C3 OUT2 0.1µF 4 U3B U3A 4 3 2 1 5µs OUT1 U2 100 CMOS 555 90 4991kR%Ω2 U1 0.0C11µF 116Rk3Ω* R4 V+8 2% 6 THR 3 491R9%1kΩ AD18/424 2 TR OUT 5 7 DIS CV 10 C6 0FVU LTLO S 2C.5AVLE0.01CµF2 3(N90P5pO%F) GN1D 0.1CµF4 0% 1V 00875-033 2% Figure 33. Pulse Response of In Amp to a 500 mV p-p Input Signal; VS = 5 V, 0 V; Gain = 10 NOTES fOUT = VIN/(VREF × t1), t1 = 1.1 × R3 × C6 = 25kHz fS AS SHOWN. R1 R2 R3 R4 R5 R6 **t1 *= == 1 13%03 %µMs,E 2FT0OATRL F fFIOLIULMTM, =,< <1250000kppHppzmm @//°° CCVI NTT CC= 2.0V 00875-032 VREF 90kΩ 9kΩ 1kΩ 1kΩ 9kΩ 90kΩ OPAHRMTT E#1K043 Figure 32. Single Supply Voltage-to-Frequency Converter G = 10 G = 100 G = 100 G = 10 Typical AD824 bias currents of 2 pA allow MΩ range source impedances with negligible dc errors. Linearity errors of 0.01% +VS full scale can be achieved with this circuit. This performance is 0.1µF 2 6 obtained with a 5 V single supply, which delivers less than 3 mA 1/4 1 1/4 7 to the entire circuit. RP AD824 AD824 SINGLE SUPPLY PROGRAMMABLE GAIN VIN1 1kΩ RP 3 5 11 VOUT 1kΩ INSTRUMENTATION AMPLIFIER VIN2 R6 (G = 10) VOUT = (VIN1 – VIN2)(1 + R 4 + R 5 ) + VREF The AD824 can be configured as a single supply instrumenta- R5 + R6 ttioo 5n Vam opr ldifuiearl tshuaptp ilsi easb ulep t too o ±p1e5r aVte. AfroDm82 s4in FgElTe siunpppultise bs idaos wn F(GO R= 1R01) =V ORU6T, R= 2(V =IN R15 – A VNIND2 )R(13 += R 4 R 4 ) + VREF 00875-034 currents of 2 pA minimize offset errors caused by high Figure 34. A Single Supply Programmable Instrumentation Amplifier unbalanced source impedances. An array of precision thin-film resistors sets the in amp gain to be either 10 or 100. These resistors are laser-trimmed to ratio match to 0.01% and have a maximum differential TC of 5 ppm/°C. Rev. E | Page 13 of 16

AD824 Data Sheet 3 V, SINGLE SUPPLY STEREO HEADPHONE DRIVER LOW DROPOUT BIPOLAR BRIDGE DRIVER The AD824 exhibits good current drive and THD + N The AD824 can be used for driving a 350 Ω Wheatstone bridge. performance, even at 3 V single supplies. At 1 kHz, total Figure 36 shows one half of the AD824 being used to buffer the harmonic distortion plus noise (THD + N) equals −62 dB AD589—a 1.235 V low power reference. The output of 4.5 V (0.079%) for a 300 mV p-p output signal. This is comparable can be used to drive an ADC front end. The other half of the to other single supply op amps that consume more power and AD824 is configured as a unity-gain inverter and generates the cannot run on 3 V power supplies. other bridge input of –4.5 V. Resistors R1 and R2 provide a constant current for bridge excitation. The AD620 low power In Figure 35, each channel’s input signal is coupled via a 1 µF instrumentation amplifier is used to condition the differential Mylar capacitor. Resistor dividers set the dc voltage at the output voltage of the bridge. The gain of the AD620 is pro- noninverting inputs so that the output voltage is midway grammed using an external resistor R and determined by: between the power supplies (1.5 V). The gain is 1.5. Each half of G the AD824 can then be used to drive a headphone channel. A 49.4kΩ G= +1 5 Hz high-pass filter is realized by the 500 µF capacitors and the R G headphones, which can be modeled as 32 Ω load resistors to ground. This ensures that all signals in the audio frequency range (20 Hz to 20 kHz) are delivered to the headphones. +VS 3V 49.9kΩ R1 +1.235V 20Ω 1/4 1µF 95.3kΩ 0.1µF 0.1µF AD589 AD824 TROEF AEDRCENCE INPUT MYLAR CHANNEL 1 26.4kΩ, 1% 1/4 +VS 47.5kΩ AD824 500µF 110%kΩ 350Ω 350Ω 3 7 95.3kΩ 4.99kΩ L 350Ω 350Ω RG AD824 6 10kΩ 5 HEADPHONES 110%kΩ 2 4 10kΩ 32Ω IMPEDANCE 110%kΩ –VS VREF 4.99kΩ R AD18/424 –4.5V +VS +5V R2 0.1µF 1µF CHANNEL 2 MY1µLFAR 47.5kΩ AD18/424 500µF 00875-035 Figure 36. Low D2r0oΩpo–uVtS BipolaGr –BNVrDSi0d.1gµeF Driver 1µF–5V 00875-036 Figure 35. 3 Volt Single Supply Stereo Headphone Driver Rev. E | Page 14 of 16

Data Sheet AD824 A 3.3 V/5 V PRECISION SAMPLE-AND-HOLD A design consideration in sample-and-hold circuits is voltage AMPLIFIER droop at the output caused by op amp bias and switch leakage currents. By choosing an JFET op amp and a low leakage CMOS In battery-powered applications, low supply voltage operational switch, this design minimizes droop rate error to better than amplifiers are required for low power consumption. Also, low 0.1 µV/µs in this circuit. Higher values of CH will yield a lower supply voltage applications limit the signal range in precision droop rate. For best performance, CH and C2 should be analog circuitry. Circuits like the sample-and-hold circuit polystyrene, polypropylene or Teflon capacitors. shown in Figure 37 illustrate techniques for designing precision analog circuitry in low supply voltage applications. To maintain These types of capacitors exhibit low leakage and low dielectric high signal-to-noise ratios (SNRs) in a low supply voltage absorption. Additionally, 1% metal film resistors were used application requires the use of rail-to-rail, input/output throughout the design. operational amplifiers. This design highlights the ability of the In the sample mode, SW1 and SW4 are closed, and the output is AD824 to operate rail-to-rail from a single 3 V/5 V supply, with V = −V . The purpose of SW4, which operates in parallel OUT IN the advantages of high input impedance. The AD824, a quad with SW1, is to reduce the pedestal, or hold step, error by JFET-input op amp, is well suited to sample-and-hold circuits injecting the same amount of charge into the noninverting due to its low input bias currents (3 pA, typical) and high input input of A3 that SW1 injects into the inverting input of A3. This impedances (3 × 1013 Ω, typical). The AD824 also exhibits very creates a common-mode voltage across the inputs of A3 and is low supply currents so the total supply current in this circuit is then rejected by the CMR of A3; otherwise, the charge injection less than 2.5 mA. from SW1 creates a differential voltage step error that appears at 3.3V/5V 3.3V/5V V . The pedestal error for this circuit is less than 2 mV over OUT R1 AD824 0.1µF the entire 0 V to 3.3 V/5 V signal range. Another method of 50kΩ 3 4 reducing pedestal error is to reduce the pulse amplitude applied A1 1 to the control pins. To control the ADG513, only 2.4 V are 2 R2 FALSE GROUND (FG) 50kΩ 11 required for the on state and 0.8 V for the off state. If possible, R4 2kΩ use an input control signal whose amplitude ranges from 0.8 V 3.3V/5V to 2.4 V instead of a full range 0 V to 3.3 V/5 V for minimum 13 ADG513 pedestal error. 15 14 R5 SW216 Other circuit features include an acquisition time of less than 2kΩ 10 11 3 µs to 1%; reducing CH and C2 will speed up the acquisition AD824 SW3 9 FG CH time further, but an increased pedestal error will result. Settling 5 500pF A2 7 2 3 time is less than 300 ns to 1%, and the sample-mode signal BW 6 SW1 1 is 80 kHz. 10 8 A3 + 7 6 9 AD824 –VOUT Tsuhpep AlieDs Gan5d13 f owra hsa cvhinogse nno fromr aitlsly a obpilietny aton dw norokr mwaitlhly 3 c lVos/5ed V SW4 8 AD824 C2 precision CMOS switches on a dielectrically isolated process. 12 FG 4 5 500pF SW2 is not required in this circuit; however, it was used in 14 SAMHPOLLED/ 13 A4 FG 00875-037 p arallel with SW3 to provide a lower RON analog switch. Figure 37. 3.3 V/5.5 V Precision Sample-and-Hold Circuit In many single supply applications, the use of a false ground generator is required. In this circuit, R1 and R2 divide the supply voltage symmetrically, creating the false ground voltage at one-half the supply. Amplifier A1 then buffers this voltage creating a low impedance output drive. The sample-and-hold circuit is configured in an inverting topology centered around this false ground level. Rev. E | Page 15 of 16

AD824 Data Sheet OUTLINE DIMENSIONS 8.75 (0.3445) 8.55 (0.3366) 4.00 (0.1575) 14 8 6.20 (0.2441) 3.80 (0.1496) 1 7 5.80 (0.2283) 1.27 (0.0500) 0.50 (0.0197) BSC 45° 1.75 (0.0689) 0.25 (0.0098) 0.25 (0.0098) 1.35 (0.0531) 8° 0.10 (0.0039) 0° COPLANARITY SEATING 0.10 0.51 (0.0201) PLANE 0.25 (0.0098) 1.27 (0.0500) 0.31 (0.0122) 0.17 (0.0067) 0.40 (0.0157) COMPLIANTTO JEDEC STANDARDS MS-012-AB C(RINEOFNPEATRRREOENNLCLTEIHN EOGSN EDLSIYM)AEANNRDSEI AORRNOESU NANORDEET DAIN-PO MPFRIFLO LMPIIMRLELIATIMTEEER TFSEO; RIRN ECUQHSU EDI VIINMA LEDENENSSTIIOGSN NFS.OR 060606-A Figure 38. 14-Lead Standard Small Outline Package [SOIC_N] Narrow Body (R-14) Dimensions shown in millimeters and (inches) ORDERING GUIDE Model1 Temperature Range Package Description Package Option AD824AR-14 −40°C to +85°C 14-Lead Standard Small Outline Package [SOIC_N] R-14 AD824AR-14-3V −40°C to +85°C 14-Lead Standard Small Outline Package [SOIC_N] R-14 AD824AR-14-3V-REEL −40°C to +85°C 14-Lead Standard Small Outline Package [SOIC_N] R-14 AD824AR-14-REEL −40°C to +85°C 14-Lead Standard Small Outline Package [SOIC_N] R-14 AD824AR-14-REEL7 −40°C to +85°C 14-Lead Standard Small Outline Package [SOIC_N] R-14 AD824ARZ-14 −40°C to +85°C 14-Lead Standard Small Outline Package [SOIC_N] R-14 AD824ARZ-14-3V −40°C to +85°C 14-Lead Standard Small Outline Package [SOIC_N] R-14 AD824ARZ-14-3V-RL −40°C to +85°C 14-Lead Standard Small Outline Package [SOIC_N] R-14 AD824ARZ-14-REEL −40°C to +85°C 14-Lead Standard Small Outline Package [SOIC_N] R-14 AD824ARZ-14-REEL7 −40°C to +85°C 14-Lead Standard Small Outline Package [SOIC_N] R-14 1 Z = RoHS Compliant Part. ©2015 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D00875-0-4/15(E) Rev. E | Page 16 of 16

Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: A nalog Devices Inc.: AD824ARZ-14 AD824AR-14 AD824AR-14-3V AD824AR-14-3V-REEL AD824AR-14-REEL AD824AR-14-REEL7 AD824ARZ-14-3V AD824ARZ-14-3V-RL AD824ARZ-14-REEL AD824ARZ-14-REEL7