40 μA Micropower Instrumentation Amplifier with Zero Crossover Distortion AD8236 FEATURES CONNECTION DIAGRAM Low power: 40 μA supply current (maximum) –IN 1 8 +VS Low input currents RG 2 7 VOUT 1 pA input bias current RG 3 6 REF 0.5 pA input offset current +IN 4 5 –VS HSpigahce C-MsaRvRin: g1 1M0S dOBP C MRR, G = 100 (NAToOtD Pto8 V 2SIE3cWa6le) 08000-001 Zero input crossover distortion Figure 1. Rail-to-rail input and output Gain set with single resistor Operates from 1.8 V to 5.5 V 5.0 4.5 V) APPLICATIONS E (4.0 G = 5 AG VS = 5V Medical instrumentation OLT3.5 VREF = 2.5V Low-side current sense E V3.0 D Portable devices MO2.5 N- O2.0 M M O1.5 UT C1.0 GVS = = 5 1.8V NP VREF = 0.9V I0.50 08000-002 –0.5 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 OUTPUTVOLTAGE(V) Figure 2. Wide Common-Mode Voltage Range vs. Output Voltage GENERAL DESCRIPTION The AD8236 is the lowest power instrumentation amplifier Table 1. Instrumentation Amplifiers by Category1 in the industry. It has rail-to-rail outputs and can operate on General Military Low High Speed voltages as low as 1.8 V. Its 40 μA maximum supply current Purpose Zero Drift Grade Power PGA makes it an excellent choice in battery-powered applications. AD8220 AD8230 AD620 AD8236 AD8250 The AD8236’s high input impedance, low input bias current of AD8221 AD8231 AD621 AD627 AD8251 1 pA, high CMRR of 110 dB (G = 100), small size, and low power AD8222 AD8290 AD624 AD623 AD8253 offer tremendous value. It has a wider common-mode voltage AD8228 AD8293G80 AD524 AD8223 range than typical three-op-amp instrumentation amplifiers, AD8295 AD8293G160 AD526 AD8226 making this a great solution for applications that operate on a AD8553 single 1.8 V or 3 V supply. An innovative input stage allows for AD8556 a wide rail-to-rail input voltage range without the crossover AD8557 distortion common in other designs. 1 See www.analog.com/inamps for the latest instrumentation amplifiers. The AD8236 is available in an 8-lead MSOP and is specified over the industrial temperature range of −40°C to +125°C. Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Tel: 781.329.4700 www.analog.com Trademarks and registered trademarks are the property of their respective owners. Fax: 781.461.3113 ©2009 Analog Devices, Inc. All rights reserved.

AD8236 TABLE OF CONTENTS Features .............................................................................................. 1  Layout .......................................................................................... 15  Applications ....................................................................................... 1  Reference Terminal .................................................................... 15  Connection Diagram ....................................................................... 1  Power Supply Regulation and Bypassing ................................ 15  General Description ......................................................................... 1  Input Bias Current Return Path ............................................... 16  Revision History ............................................................................... 2  Input Protection ......................................................................... 16  Specifications ..................................................................................... 3  RF Interference ........................................................................... 16  Absolute Maximum Ratings ............................................................ 7  Common-Mode Input Voltage Range ..................................... 17  Maximum Power Dissipation ..................................................... 7  Applications Information .............................................................. 18  ESD Caution .................................................................................. 7  AC-Coupled Instrumentation Amplifier ................................ 18  Pin Configuration and Function Descriptions ............................. 8  Low Power Heart Rate Monitor ............................................... 19  Typical Performance Characteristics ............................................. 9  Outline Dimensions ....................................................................... 20  Theory of Operation ...................................................................... 14  Ordering Guide .......................................................................... 20  Basic Operation .......................................................................... 14  Gain Selection ............................................................................. 14  REVISION HISTORY 5/09—Revision 0: Initial Version Rev. 0 | Page 2 of 20

AD8236 SPECIFICATIONS +V = 5 V, −V = 0 V (GND), V = 2.5 V, T = 25°C, G = 5, R = 100 kΩ to GND, unless otherwise noted. S S REF A L Table 2. Parameter Test Conditions Min Typ Max Unit COMMON-MODE REJECTION RATIO (CMRR) V = ±2.5 V, V = 0 V S REF CMRR DC V = −1.8 V to +1.8 V CM G = 5 86 94 dB G = 10 90 100 dB G = 100 100 110 dB G = 200 100 110 dB NOISE Voltage Noise Spectral Density, RTI f = 1 kHz, G = 5 76 nV/√Hz RTI, 0.1 Hz to 10 Hz G = 5 4 μV p-p G = 200 4 μV p-p Current Noise 15 fA/√Hz VOLTAGE OFFSET Input Offset, V 3.5 mV OS Average Temperature Coefficient (TC) −40°C to +125°C 2.5 μV/°C Offset RTI vs. Supply (PSR) V = 1.8 V to 5 V S G = 5 100 120 dB G = 10 110 126 dB G = 100 110 130 dB G = 200 110 130 dB INPUT CURRENT Input Bias Current 1 10 pA Overtemperature −40°C to +85°C 100 pA −40°C to +125°C 600 pA Input Offset Current 0.5 5 pA Overtemperature −40°C to +85°C 50 pA −40°C to +125°C 130 pA DYNAMIC RESPONSE Small Signal Bandwidth, –3 dB G = 5 23 kHz G = 10 9 kHz G = 100 0.8 kHz G = 200 0.4 kHz Settling Time 0.01% V = 4 V step OUT G = 5 444 μs G = 10 456 μs G = 100 992 μs G = 200 1816 μs Slew Rate G = 5 to 100 9 mV/μs Rev. 0 | Page 3 of 20

AD8236 Parameter Test Conditions Min Typ Max Unit GAIN Gain Range G = 5 + 420 kΩ/R 5 2001 V/V G Gain Error V = ±2.5 V, V = 0 V, V = −2 V to +2 V S REF OUT G = 5 0.005 0.05 % G = 10 0.03 0.2 % G = 100 0.06 0.2 % G = 200 0.15 0.3 % Nonlinearity R = 10 kΩ or 100 kΩ L G = 5 2 10 ppm G = 10 1.2 10 ppm G = 100 0.5 10 ppm G = 200 0.5 10 ppm Gain vs. Temperature −40°C to +125°C G = 5 0.25 1 ppm/°C G > 10 −50 ppm/°C INPUT Differential Impedance 440||1.6 GΩ||pF Common-Mode Impedance 110||6.2 GΩ||pF Input Voltage Range −40°C to +125°C 0 +V V S OUTPUT Output Voltage High, V R = 100 kΩ 4.98 4.99 V OH L −40°C to +125°C 4.98 V R L = 10 kΩ 4.9 4.95 V −40°C to +125°C 4.9 V Output Voltage Low, V R = 100 kΩ 2 5 mV OL L −40°C to +125°C 5 mV RL = 10 kΩ 10 25 mV −40°C to +125°C 30 mV Short-Circuit Limit, I ±55 mA SC REFERENCE INPUT R −IN, +IN = 0 V 210 kΩ IN I 20 nA IN Voltage Range −V +V V S S Gain to Output 1 V/V POWER SUPPLY Operating Range 1.8 5.5 V Quiescent Current 30 40 μA Overtemperature −40°C to +125°C 50 μA TEMPERATURE RANGE For Specified Performance −40 +125 °C 1 Although the specifications of the AD8236 list only low to midrange gains, gains can be set beyond 200. Rev. 0 | Page 4 of 20

AD8236 +V = 1.8 V, −V = 0 V (GND), V = 0.9 V, T = 25°C, G = 5, R = 100 kΩ to GND, unless otherwise noted. S S REF A L Table 3. Parameter Test Conditions Min Typ Max Unit COMMON-MODE REJECTION RATIO (CMRR) V = ±0.9 V, V = 0 V S REF CMRR DC V = −0.6 V to +0.6 V CM G = 5 86 94 dB G = 10 90 100 dB G = 100 100 110 dB G = 200 100 110 dB NOISE Voltage Noise Spectral Density, RTI f = 1 kHz, G = 5 76 nV/√Hz RTI, 0.1 Hz to 10 Hz G = 5 4 μV p-p G = 200 4 μV p-p Current Noise 15 fA/√Hz VOLTAGE OFFSET Input Offset, V 3.5 mV OS Average Temperature Coefficient (TC) −40°C to +125°C 2.5 μV/°C Offset RTI vs. Supply (PSR) V = 1.8 V to 5 V S G = 5 100 120 dB G = 10 110 126 dB G = 100 110 130 dB G = 200 110 130 dB INPUT CURRENT Input Bias Current 1 10 pA Overtemperature −40°C to +85°C 100 pA −40°C to +125°C 600 pA Input Offset Current 0.5 5 pA Overtemperature −40°C to +85°C 50 pA −40°C to +125°C 130 pA DYNAMIC RESPONSE Small Signal Bandwidth, –3 dB G = 5 23 kHz G = 10 9 kHz G = 100 0.8 kHz G = 200 0.4 kHz Settling Time 0.01% V = 1.4 V step OUT G = 5 143 μs G = 10 178 μs G = 100 1000 μs G = 200 1864 μs Slew Rate G = 5 to 100 11 mV/μs GAIN Gain Range G = 5 + 420 kΩ/R 5 2001 V/V G Gain Error V = ±0.9 V, V = 0 V, V = −0.6 V to +0.6 V S REF OUT G = 5 0.005 0.05 % G = 10 0.03 0.2 % G = 100 0.06 0.2 % G = 200 0.15 0.3 % Rev. 0 | Page 5 of 20

AD8236 Parameter Test Conditions Min Typ Max Unit Nonlinearity R = 10 kΩ or 100 kΩ L G = 5 1 10 ppm G = 10 1 10 ppm G = 100 0.5 10 ppm G = 200 0.4 10 ppm Gain vs. Temperature −40°C to +125°C G = 5 0.25 1 ppm/°C G > 10 −50 ppm/°C INPUT Differential Impedance 440||1.6 GΩ||pF Common-Mode Impedance 110||6.2 GΩ||pF Input Voltage Range −40°C to +125°C 0 +V V S OUTPUT Output Voltage High, V R = 100 kΩ 1.78 1.79 V OH L −40°C to +125°C 1.78 V RL = 10 kΩ 1.65 1.75 V −40°C to +125°C 1.65 V Output Voltage Low, V R = 100 kΩ 2 5 mV OL L −40°C to +125°C 5 mV RL = 10 kΩ 12 25 mV −40°C to +125°C 25 mV Short-Circuit Limit, I ±6 mA SC REFERENCE INPUT R −IN, +IN = 0 V 210 kΩ IN I 20 nA IN Voltage Range −V +V V S S Gain to Output 1 V/V POWER SUPPLY Operating Range 1.8 5.5 V Quiescent Current 33 40 μA Overtemperature −40°C to +125°C 50 μA TEMPERATURE RANGE For Specified Performance −40 +125 °C 1 Although the specifications of the AD8236 list only low to midrange gains, gains can be set beyond 200. Rev. 0 | Page 6 of 20

AD8236 ABSOLUTE MAXIMUM RATINGS Table 4. The difference between the total drive power and the load power is Parameter Rating the drive power dissipated in the package. Supply Voltage 6 V P = Quiescent Power + (Total Drive Power – Load Power) D Power Dissipation See Figure 3 Output Short-Circuit Current 55 mA P =(V ×I )+⎜⎛VS ×VOUT ⎟⎞–VOUT2 Input Voltage (Common Mode) ±VS D S S ⎜⎝ 2 RL ⎟⎠ RL Differential Input Voltage ±V S RMS output voltages should be considered. If R is referenced to L Storage Temperature Range −65°C to +125°C −V, as in single-supply operation, the total drive power is V × S S Operating Temperature Range −40°C to +125°C I . If the rms signal levels are indeterminate, consider the worst OUT Lead Temperature (Soldering, 10 sec) 300°C case, when V = V/4 for R to midsupply OUT S L Junction Temperature 140°C θJA (4-Layer JEDEC Standard Board) P =(V ×I )+(VS/4)2 8-Lead MSOP 135°C/W D S S R L Package Glass Transition Temperature In single-supply operation with R referenced to −V, worst case L S 8-Lead MSOP 140°C is V = V/2. OUT S ESD Human Body Model 2 kV Airflow increases heat dissipation, effectively reducing θJA. In Charge Device Model 1 kV addition, more metal directly in contact with the package leads Machine Model 200 V from metal traces, through holes, ground, and power planes reduces the θ . JA Stresses above those listed under Absolute Maximum Ratings Figure 3 shows the maximum safe power dissipation in the package may cause permanent damage to the device. This is a stress vs. the ambient temperature for the 8-lead MSOP on a 4-layer rating only; functional operation of the device at these or any JEDEC standard board. θ values are approximations. other conditions above those indicated in the operational JA section of this specification is not implied. Exposure to absolute 2.00 maximum rating conditions for extended periods may affect 1.75 device reliability. W) ON ( 1.50 MAXIMUM POWER DISSIPATION TI A The maximum safe power dissipation in the package of the SIP 1.25 S AD8236 is limited by the associated rise in junction temperature R DI 1.00 E (T) on the die. The plastic encapsulating the die locally reaches W theJ junction temperature. At approximately 140°C, which is the M PO 0.75 U glass transition temperature, the plastic changes its properties. M 0.50 XI Even temporarily exceeding this temperature limit may change A M 0.25 the stresses that the package exerts on the die, permanently shifting the parametric performance of the AD8236. 0 The still-air thermal properties of the package and PCB (θJA), –40 –20 0AMBIE2N0T TEM4P0ERATU60RE (°C)80 100 120 08000-045 the ambient temperature (TA), and the total power dissipated in Figure 3. Maximum Power Dissipation vs. Ambient Temperature the package (P ) determine the junction temperature of the die. D The junction temperature is calculated as ESD CAUTION T = T + (P × θ ) J A D JA The power dissipated in the package (P ) is the sum of the D quiescent power dissipation and the power dissipated in the package due to the load drive for all outputs. The quiescent power is the voltage between the supply pins (V) times the S quiescent current (I). Assuming the load (R) is referenced to S L midsupply, the total drive power is VS/2 × IOUT, some of which is dissipated in the package and some in the load (V × I ). OUT OUT Rev. 0 | Page 7 of 20

AD8236 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS –IN 1 8 +VS RG 2 AD8236 7 VOUT +RING 34 (NToOt Pto V SIEcWale) 65 R–VESF 08000-004 Figure 4. Pin Configuration Table 5. Pin Function Descriptions Pin No. Mnemonic Description 1 −IN Negative Input Terminal (True Differential Input) 2, 3 R Gain Setting Terminals (Place Resistor Across the R Pins) G G 4 +IN Positive Input Terminal (True Differential Input) 5 −V Negative Power Supply Terminal S 6 REF Reference Voltage Terminal (Drive This Terminal with a Low Impedance Voltage Source to Level-Shift the Output) 7 V Output Terminal OUT 8 +V Positive Power Supply Terminal S Rev. 0 | Page 8 of 20

AD8236 TYPICAL PERFORMANCE CHARACTERISTICS G = 5, +V = 5 V, V = 2.5 V, R = 100 kΩ tied to GND, T = 25°C, unless otherwise noted. S REF L A 700 GAIN = 5 600 TS 500 NI U OF 400 R E MB 300 U N 200 100 0 –40 –20 CMRR0 (µV/V) 20 40 08000-060 5µV/DIV 1s/DIV 08000-024 Figure 5. Typical Distribution of CMRR, G = 5 Figure 8. 0.1 Hz to 10 Hz RTI Voltage Noise GAIN = 200 800 S T NI 600 U F O R E B 400 M U N 200 0 5µV/DIV 1s/DIV 08000-025 –4000 –3000 –2000 –1000VOSI0 (µV)1000 2000 3000 400008000-061 Figure 6. Typical Distribution of Input Offset Voltage Figure 9. 0.1 Hz to 10 Hz RTI Voltage Noise 1k 140 120 GAIN = 200 100 GAIN = 100 √Hz) B) 80 ICNLTIEPRPNINAGL (nV/100 GAIN = 5 R(d E R S S 60 OI GAIN = 200 P N BANDWIDTH 40 LIMITED 20 GAIN = 10 10 08000-042 0 GAIN = 5 08000-035 1 10 100 1k 10k 0.1 1 10 100 1k 10k 100k FREQUENCY (Hz) FREQUNCY(Hz) Figure 7. Voltage Noise Spectral Density vs. Frequency Figure 10. Positive PSRR vs. Frequency, RTI, VS = ±0.9 V, ±2.5 V, VREF = 0 V Rev. 0 | Page 9 of 20

AD8236 120 15 GAIN = 100 100 10 GAIN = 10 80 GAIN = 200 5 PSRR (dB) 60 GAIN = 5 MRR (µV/V) 0 C 40 –5 20 –10 0 08000-040 –15 08000-014 0.1 1 10 100 1k 10k 100k –40 –20 0 20 40 60 80 100 120 FREQUENCY (Hz) TEMPERATURE (°C) Figure 11. Negative PSRR vs. Frequency, RTI, VS = ±0.9 V, ±2.5 V, VREF = 0 V Figure 14. Change in CMRR vs. Temperature, G = 5, Normalized at 25°C 120 60 50 GAIN = 200 100 40 GAIN = 100 30 80 GAIN = 10 B) B) 20 d d R ( 60 GAIN = 200 N ( 10 GAIN = 5 CMR GAIN = 100 GAI 0 40 –10 GAIN = 10 –20 20 00.1 1 10FREQU1E0N0CY (Hz)1GkAIN = 510k 10008000-023k ––430010 100 FR1kEQUENCY 1(H0kz) 100k 1M 08000-022 Figure 12. CMRR vs. Frequency, RTI Figure 15. Gain vs. Frequency, VS = 1.8 V, 5 V 120 6 100 5 80 4 CMRR (dB) 60 GAIN = 200GAIN = 100 V (V p-p)OUT3 40 2 20 1 0 GAIN = 5GAIN = 10 08000-051 0 08000-132 0.1 1 10 100 1k 10k 100k 1 10 100 1k 10k 100k FREQUENCY (Hz) FREQUENCY (Hz) Figure 13. CMRR vs. Frequency, 1 kΩ Source Imbalance, RTI Figure 16. Maximum Output Voltage vs. Frequency Rev. 0 | Page 10 of 20

AD8236 5.0 4.5 V) (4.98V, 4.737V) E ( 4.0 (0.01V, 4.24V) V) G m/DI RLOAD = 100kΩ TIED TO GND LTA 3.5 NEARITY (5pp RLOAD = 10kΩ TIED TO GND MON-MODE VO 322...050 LI M NON T CO 1.5 PU 1.0 (4.98V, 0.767V) N VS = 5V 08000-026 I 0.05 (0.01V, 0.27V) 0.5 1.0 1.5 OU2T.0PUT V2O.5LTAG3E. 0(V) 3.5 4.0 4.5 –0.5 0 0.5 1.0 1O.5UTP2.U0T V2O.5LTA3.G0E (3V.5) 4.0 4.5 5.0 5.5 08000-036 Figure 17. Gain Nonlinearity, G = 5 Figure 20. Input Common-Mode Voltage Range vs. Output Voltage, G = 5, VS = 5 V, VREF = 2.5 V 5.0 V) 4.5 (4.994V, 4.75V) V) GE ( 4.0 (0.01V, 4.25V) m/DI LTA 3.5 p O RITY (2p MODE V 32..05 A N- LINE RLOATDW =O 1 C0kUΩR VAENSD R10E0PkRΩE TSIEENDT TEOD :GND MMO 2.0 NON T CO 1.5 U 1.0 (4.994V, 0.076V) P VS = 5V 08000-028 IN 0.05 (0.01V, 0.026V) 0.5 1.0 1.5 OU2T.0PUT V2O.5LTAG3E. 0(V) 3.5 4.0 4.5 –0.5 0 0.5 1.0 1O.5UTP2U.0T V2O.5LTA3.G0E (3V.5) 4.0 4.5 5.0 5.5 08000-038 Figure 18. Gain Nonlinearity, G = 10 Figure 21. Input Common-Mode Voltage Range vs. Output Voltage, G = 200, VS = 5 V, VREF = 2.5 V 1.8 V) 1.6 (1.78V, 1.704V) V) GE ( 1.4 (0.0069V, 1.52V) pm/DI OLTA 1.2 p V TY (2 ODE 1.0 RI M A TWO CURVES REPRESENTED: N- 0.8 NONLINE RLOAD = 10kΩ AND 100kΩ TIED TO GND PUT COMMO 00..64 (1.78V, 0.274V) VS = 5V 08000-029 IN 0.02 (0.0069V, 0.09V) 0.5 1.0 1.5 OU2T.0PUT V2O.5LTAG3E. 0(V) 3.5 4.0 4.5 –0.2 0 0.2 0.4 O0U.6TPU0T. 8VOL1T.0AGE1 .(2V) 1.4 1.6 1.8 2.0 08000-037 Figure 19. Gain Nonlinearity, G = 200 Figure 22. Input Common-Mode Voltage Range vs. Output Voltage, G = 5, VS = 1.8 V, VREF = 0.9 V Rev. 0 | Page 11 of 20

AD8236 1.8 V) 1.6 (1.75V, 1.705V) GE ( 1.4 (0.03V, 1.533V) A T OL 1.2 V E D 1.0 V O DI N-M 0.8 2V/ O M M 0.6 444μs TO 0.01% O C PUT 0.4 (1.75V, 0.275V) IN 0.02–0.2 0 (0.00.32V, 00.1.403VO0)U.6TPU0T. 8VOL1T.0AGE1 .(2V) 1.4 1.6 1.8 2.0 08000-039 1ms/DIV 08000-047 Figure 23. Input Common-Mode Voltage Range vs. Output Voltage, Figure 26. Large Signal Pulse Response and Settling Time, G = 200, VS = 1.8 V, VREF = 0.9 V VS = ±2.5 V, VREF = 0 V, RL = 10 kΩ to VREF +VS –0.001 E V)AG–0.002 TAGE SWING (SUPPLY VOLT–0.003 +125°C +85°C +25°C –40°C mV/DIV UTPUT VOLERRED TO +0.003 700 143.2μs TO 0.01% OEF+0.002 R +125°C +85°C +25°C –40°C +0.–0V01S1.8 2.3 2.8SUPPLY3 .V3OLTAG3E.8 (V) 4.3 4.8 08000-054 1ms/DIV 08000-048 Figure 24. Output Voltage Swing vs. Supply Voltage, Figure 27. Large Signal Pulse Response and Settling Time, VS = ±0.9 V, ±2.5 V, VREF = 0 V, RL = 100 kΩ Tied to −VS VS = ±0.9 V, VREF = 0 V, RL = 10 kΩ to VREF +VS –0.1 E –40°C V)AG –0.2 +25°C G (LT +85°C NO +125°C AGE SWIUPPLY V –0.3 V/DIV TS m UTPUT VOLERRED TO +0.003 20 OEF +0.002 +125°C +85°C +25°C –40°C R +0.–0V01S1k 10k 100k03579-056 100µs/DIV 08000-117 RLOAD (Ω) Figure 25. Output Voltage Swing vs. Load Resistance, Figure 28. Small Signal Pulse Response, G = 5, VS = ±0.9 V, ±2.5 V, VREF = 0 V, RL = 100 kΩ Tied to −VS VS = ±2.5 V, VREF = 0 V, RL = 100 kΩ to VREF, CL = 100 pF Rev. 0 | Page 12 of 20

AD8236 500 400 s) µ 20mV/DIV TLING TIME ( 230000 T E S 100 08000-017 0 100µs/DIV 0 O1UTPUT VOLTAG2E STEP SIZE (3V) 4 08000-043 Figure 29. Small Signal Pulse Response, G = 5, CL = 100 pF, Figure 32. Settling Time vs. Output Voltage Step Size, VS = ±0.9 V, VREF = 0 V, RL = 100 kΩ to VREF VS = ±2.5 V, VREF = 0 V, RL = 10 kΩ Tied to VREF 40 38 36 A) 34 1.8V µ ( T DIV REN 32 mV/ UR 30 5V 0 C 2 LY 28 P P U 26 S 24 08000-113 2202 08000-034 1ms/DIV –40 –25 –10 5 20 35 50 65 80 95 110 125 TEMPERATURE(°C) Figure 30. Small Signal Pulse Response, G = 200, Figure 33. Total Supply Current vs. Temperature CL = 100 pF, VS = 2.5 V, VREF = 0 V, RL = 100 kΩ to VREF V DI V/ m 0 2 08000-013 1ms/DIV Figure 31. Small Signal Pulse Response, G = 200, CL = 100 pF, VS = 0.9 V, VREF = 0 V, RL = 100 kΩ to VREF Rev. 0 | Page 13 of 20

AD8236 THEORY OF OPERATION RG RG RG +VS –VS 2 3 8 5 ESD ESD PROTECTION PROTECTION ESD REF 6 PROTECTION 210kΩ 52.5kΩ 52.5kΩ 210kΩ OP AMP ESD A OPB AMP PROTECTION 7 VOUT ESD ESD PROTECTION PROTECTIOAND8236 08000-006 1 4 –IN +IN Figure 34. Simplified Schematic The AD8236 is a monolithic, 2-op-amp instrumentation GAIN SELECTION amplifier. It was designed for low power, portable applications Placing a resistor across the R terminals sets the gain of the G where size and low quiescent current are paramount. For example, AD8236, which can be calculated by referring to Table 6 or by it has a rail-to-rail input and output stage to offer more dynamic using the gain equation range when operating on low voltage batteries. Unlike traditional 420kΩ rail-to-rail input amplifiers that use a complementary differential R = pair stage and suffer from nonlinearity, the AD8236 uses a novel G G−5 architecture to internally boost the supply rail, allowing the Table 6. Gains Achieved Using 1% Resistors amplifier to operate rail to rail yet still deliver a low 0.5 ppm of 1% Standard Table Value of R (Ω) Calculated Gain nonlinearity. In addition, the 2-op-amp instrumentation amplifier G 422 k 6.0 architecture offers a wide operational common-mode voltage 210 k 7.0 range. Additional information is provided in the Common- 140 k 8.0 Mode Input Voltage Range section. Precision, laser-trimmed 105 k 9.0 resistors provide the AD8236 with a high CMRR of 86 dB 84.5 k 10.0 (minimum) at G = 5 and gain accuracy of 0.05% (maximum). 28 k 20.0 BASIC OPERATION 9.31 k 50.1 The AD8236 amplifies the difference between its positive input 4.42 k 100.0 (+IN) and its negative input (−IN). The REF pin allows the user 2.15 k 200.3 to level-shift the output signal. This is convenient when interfacing to a filter or analog-to-digital converter (ADC). The basic setup The AD8236 defaults to G = 5 when no gain resistor is used. is shown in Figure 35. Figure 37 shows an example configuration Gain accuracy is determined by the absolute tolerance of R . G for operating the AD8236 with dual supplies. The equation for The TC of the external gain resistor increases the gain drift of the AD8236 is as follows: the instrumentation amplifier. Gain error and gain drift are at a minimum when the gain resistor is not used. V = G × (VINP − VINM) + VREF OUT If no gain setting resistor is installed, the default gain, G, is 5. The Gain Selection section describes how to program the gain, G. 5V 0.1µF +IN VINP RG +VS GAINR ESSEITSTTIONGR RG AD8236 OUT VOUT REF VINM –IN –VS VREF 08000-136 Figure 35. Basic Setup Rev. 0 | Page 14 of 20

AD8236 LAYOUT INCORRECT CORRECT Careful board layout maximizes system performance. In applications that need to take advantage of the low input AD8236 AD8236 bias current of the AD8236, avoid placing metal under the REF REF input path to minimize leakage current. V V Grounding + The output voltage of the AD8236 is developed with respect to OP AMP tahcec uproatteen otuiatlp ount, tthhee rterfaecree nfrcoem te trhme iRnEalF, RpEinF .s Thoo uelnds ueirteh tehr eb me ost – 08000-137 connected to the AD8236 local ground (see Figure 37) or Figure 36. Driving the REF Pin connected to a voltage that is referenced to the AD8236 local POWER SUPPLY REGULATION AND BYPASSING ground (Figure 35). The AD8236 has high power supply rejection ration (PSRR). REFERENCE TERMINAL However, for optimal performance, a stable dc voltage should be The reference terminal, REF, is at one end of a 210 kΩ resistor used to power the instrumentation amplifier. Noise on the supply (see Figure 34). The output of the instrumentation amplifier pins can adversely affect performance. As in all linear circuits, is referenced to the voltage on the REF terminal; this is useful bypass capacitors must be used to decouple the amplifier. when the output signal needs to be offset to voltages other than A 0.1 μF capacitor should be placed close to each supply pin. common. For example, a voltage source can be tied to the REF A 10 μF tantalum capacitor can be used further away from the pin to level-shift the output so that the AD8236 can interface part (see Figure 37). In most cases, it can be shared by other with an ADC. The allowable reference voltage range is a function precision integrated circuits. of the gain, common-mode input, and supply voltages. The REF +VS pin should not exceed either +V or −V by more than 0.5 V. S S For best performance, especially in cases where the output is not 0.1µF 10µF measured with respect to the REF terminal, source impedance to the REF terminal should be kept low because parasitic resistance +IN can adversely affect CMRR and gain accuracy. Figure 36 AD8236 VOUT demonstrates how an op amp is configured to provide a low source impedance to the REF terminal when a midscale LOAD –IN REF reference voltage is desired. 0.1µF 10µF –VS 08000-138 Figure 37. Supply Decoupling, REF, and Output Referred to Ground Rev. 0 | Page 15 of 20

AD8236 +VS +VS AD8236 AD8236 REF REF –VS –VS TRANSFORMER TRANSFORMER +VS +VS C C AD8236 fHIGH-PASS=2π1RC R AD8236 REF REF R AC-COUPL–EVDS AC-COUPL–EVDS 08000-139 Figure 38. Creating an IBIAS Path INPUT BIAS CURRENT RETURN PATH RF INTERFERENCE The AD8236 input bias current is extremely small at less than RF rectification is often a problem in applications where there are 10 pA. Nonetheless, the input bias current must have a return large RF signals. The problem appears as a small dc offset voltage. path to common. When the source, such as a transformer, The AD8236, by its nature, has a 3.1 pF gate capacitance, CG, at each input. Matched series resistors form a natural low-pass filter cannot provide a return current path, one should be created (see Figure 38). that reduces rectification at high frequency (see Figure 39). The relationship between external, matched series resistors and the INPUT PROTECTION internal gate capacitance is expressed as All terminals of the AD8236 are protected against ESD. In 1 addition, the input structure allows for dc overload conditions FilterFreq = DIFF 2πRC a diode drop above the positive supply and a diode drop below G the negative supply. Voltages beyond a diode drop of the supplies 1 FilterFreq = cause the ESD diodes to conduct and enable current to flow CM 2πRC G through the diode. Therefore, an external resistor should be +VS used in series with each of the inputs to limit current for voltages above +V. In either scenario, the AD8236 safely S 0.1µF 10µF handles a continuous 6 mA current at room temperature. For applications where the AD8236 encounters extreme overload voltages, as in cardiac defibrillators, external series resistors and low leakage diode clamps, such as BAV199Ls, R +IN FJH1100s, or SP720s, should be used. CG AD8236 VOUT –VS R CG –IN –VS REF 0.1µF 10µF –VS 08000-140 Figure 39. RFI Filtering Without External Capacitors Rev. 0 | Page 16 of 20

AD8236 To eliminate high frequency common-mode signals while using COMMON-MODE INPUT VOLTAGE RANGE smaller source resistors, a low-pass RC network can be placed The common-mode input voltage range is a function of the at the input of the instrumentation amplifier (see Figure 40). input voltages, reference voltage, supplies, and the output of The filter limits the input signal bandwidth according to the Internal Op Amp A. Figure 34 shows the internal nodes of the following relationship: AD8236. Figure 20 to Figure 23 show the common-mode 1 voltage ranges for typical supply voltages and gains. FilterFreq = DIFF 2πR(2CD+CC+CG) If the supply voltages and reference voltage is not represented in Figure 20 to Figure 23, the following methodology can be used 1 FilterFreqCM =2πR(CC+CG) to calculate the acceptable common-mode voltage range: 1. Adhere to the input, output, and reference voltage ranges Mismatched C capacitors result in mismatched low-pass filters. C shown in Table 2 and Table 3. The imbalance causes the AD8236 to treat what would have been 2. Calculate the output of the internal op amp, A. The following a common-mode signal as a differential signal. To reduce the equation calculates this output: effect of mismatched external C capacitors, select a value of C C D greater than 10 times CC. This sets the differential filter frequency A= 5⎜⎛V −VDIFF ⎟⎞−52.5kΩV −VREF lower than the common-mode frequency. 4⎝ CM 2 ⎠ R DIFF 4 G +VS where: 0.1µF 10µF VDIFF is defined as the difference in input voltages, V = VINP − VINM. DIFF CC 1nF V is defined as the common mode voltage, CM R +IN V = (VINP + VINM)/2. CM 4.02kΩ CD 10nF AD8236 VOUT If no gain setting resistor, RG, is installed, set RG to infinity. R REF 3. Keep A within 10 mV of either supply rail. This is valid over 4.02kΩ –IN the −40°C to +125°C temperature range. CC 1nF 08000-141 −VS + 10 mV < A < +VS – 10 mV Figure 40. RFI Suppression Rev. 0 | Page 17 of 20

AD8236 APPLICATIONS INFORMATION AC-COUPLED INSTRUMENTATION AMPLIFIER +VS An integrator can be tied to the AD8236 in feedback to create a 0.1µF high-pass filter as shown in Figure 41. This circuit can be used to reject dc voltages and offsets. At low frequencies, the impedance of the capacitor, C, is high. Therefore, the gain of the integrator +IN fHIGH-PASS= 2π1RC is high. DC voltage at the output of the AD8236 is inverted and AD8236 gained by the integrator. The inverted signal is injected back into REF R the REF pin, nulling the output. In contrast, at high frequencies, –IN C the integrator has low gain because the impedance of C is low. Voltage changes at high frequencies are inverted but at a low +VS gain. The signal is injected into the REF pins, but it is not enough to 0.1µF null the output. At very high frequencies, the capacitor appears as a short. The op amp is at unity gain. High frequency signals are, AD8603 therefore, allowed to pass. When a signal exceeds f , the AD8236 outputs the high- +VS HIGH-PASS pass filtered input signal. 10µF VREF 08000-142 Figure 41. AC-Coupled Circuit Rev. 0 | Page 18 of 20

AD8236 LOW POWER HEART RATE MONITOR This circuit was designed and tested using the AD8609, low power, quad op amp. The fourth op amp is configured as a Schmitt The low power and small size of the AD8236 make it an trigger to indicate if the right arm or left arm electrodes fall off excellent choice for heart rate monitors. As shown in Figure 42, the body. Used in conjunction with the 953 kΩ resistors at the the AD8236 measures the biopotential signals from the body. inputs of the AD8236, the resistors pull the inputs apart when It rejects common-mode signals and serves as the primary gain the electrodes fall off the body. The Schmitt trigger sends an stage set at G = 5. The 4.7 μF capacitor and the 100 kΩ resistor active low signal to indicate a leads off condition. set the −3 dB cutoff of the high-pass filter that follows the instrumentation amplifier. It rejects any differential dc offsets The reference electrode (right leg) is set tied to ground. Likewise, that may develop from the half-cell overpotential of the electrode. the shield of the electrode cable is also tied to ground. Some portable heart rate monitors do not have a third electrode. In A secondary gain stage, set at G = 403, amplifies the ECG signal, such cases, the negative input of the AD8236 can be tied to GND. which is then sent into a second-order, low-pass, Bessel filter with −3 dB cutoff at 48 Hz. The 324 Ω resistor and 1 μF capacitor Note that this circuit is shown, solely, to demonstrate the capability serve as an antialiasing filter. The 1 μF capacitor also serves as a of the AD8236. Additional effort must be made to ensure charge reservoir for the ADC’s switched capacitor input stage. compliance with medical safety guidelines. +2.5V –2.5V 1kΩ 20kΩ +2.5V 5kΩ LEADS OFF DETECTION +2.5V INTERRUPT LEADS OFF 0.1µF AD8609 680nF 953kΩ +2.5V 0.1µF RA LA AD8236 24.9kΩ 4.02kΩ IN-AMP AD8609 324Ω 100kΩ AD8609 10-BIT ADC RL 953kΩ 0.1µF 1kΩ 402kΩ 220nF 0.1µF 1µF MCU + ADC 4.7µF –2.5V –2.5V –2.5V +2.5V 1kΩ AD8609 08000-143 –2.5V Figure 42. Example Low Power Heart Rate Monitor Schematic Rev. 0 | Page 19 of 20

AD8236 OUTLINE DIMENSIONS 3.20 3.00 2.80 8 5 5.15 3.20 4.90 3.00 4.65 2.80 1 4 PIN 1 0.65 BSC 0.95 0.85 1.10 MAX 0.75 0.80 0.15 0.38 0.23 8° 0.60 0.00 0.22 0.08 0° 0.40 COPLANARITY SEATING 0.10 PLANE COMPLIANT TO JEDEC STANDARDS MO-187-AA Figure 43. 8-Lead Mini Small Outline Package [MSOP] (RM-8) Dimensions shown in millimeters ORDERING GUIDE Model Temperature Range Package Description Package Option Branding AD8236ARMZ1 −40°C to +125°C 8-Lead MSOP RM-8 Y1W AD8236ARMZ-R71 −40°C to +125°C 8-Lead MSOP RM-8 Y1W AD8236ARMZ-RL1 −40°C to +125°C 8-Lead MSOP RM-8 Y1W 1 Z = RoHS Compliant Part. ©2009 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D08000-0-5/09(0) Rev. 0 | Page 20 of 20

Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: A nalog Devices Inc.: AD8236ARMZ AD8236ARMZ-R7 AD8236ARMZ-RL