Single-Supply, Rail-to-Rail Low Power FET-Input Op Amp Data Sheet AD822 FEATURES CONNECTION DIAGRAM True single-supply operation OUT1 1 8 V+ Output swings rail-to-rail Input voltage range extends below ground –IN1 2 7 OUT2 Single-supply capability from 5 V to 30 V +IN1 3 6 –IN2 HigDhu laola-sdu dprpivlye capability from ±2.5 V to ±15 V V– 4 AD822 5 +IN2 00874-001 Capacitive load drive of 350 pF, G = +1 Figure 1. 8-Lead PDIP (N Suffix); 8-Lead MSOP (RM Suffix); Minimum output current of 15 mA and 8-Lead SOIC_N (R Suffix) Excellent ac performance for low power 800 µA maximum quiescent current per amplifier Unity-gain bandwidth: 1.8 MHz Slew rate of 3 V/μs Good dc performance 800 µV maximum input offset voltage 2 µV/°C typical offset voltage drift 25 pA maximum input bias current Low noise 13 nV/√Hz at 10 kHz No phase inversion APPLICATIONS Battery-powered precision instrumentation Photodiode preamps Active filters 12-bit to 14-bit data acquisition systems Medical instrumentation Low power references and regulators GENERAL DESCRIPTION The AD822 is a dual precision, low power FET input op amp 100 that can operate from a single supply of 5 V to 30 V or from dual supplies of ±2.5 V to ±15 V. It has true single-supply capability Hz) with an input voltage range extending below the negative rail, V/√ n allowing the AD822 to accommodate input signals below ground E ( S while in the single-supply mode. Output voltage swing extends OI N to within 10 mV of each rail, providing the maximum output GE 10 A dynamic range. LT O V Offset voltage of 800 µV maximum, offset voltage drift of 2 µV/°C, UT P input bias currents below 25 pA, and low input voltage noise N I provide dc precision with source impedances up to a gigaohm. Tdihseto 1r.t8io Mn H(TzH uDni)t ya-t g1a0in k Hbazn, dawndid 3th V, /–µ9s3 s dleBw t orattael haraer mproonviicd ed 110 100FREQUENCY (Hz)1k 10k 00874-002 with a low supply current of 800 µA per amplifier. Figure 2. Input Voltage Noise vs. Frequency Rev. J Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Tel: 781.329.4700 ©1993–2015 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com

AD822 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Typical Performance Characteristics ........................................... 11 Applications ....................................................................................... 1 Applications Information .............................................................. 18 Connection Diagram ....................................................................... 1 Input Characteristics .................................................................. 18 General Description ......................................................................... 1 Output Characteristics............................................................... 18 Revision History ............................................................................... 2 Single-Supply Voltage to Frequency Converter ..................... 19 Specifications ..................................................................................... 4 Single-Supply Programmable Gain Instrumentation Absolute Maximum Ratings .......................................................... 10 Amplifier ..................................................................................... 20 Thermal Resistance .................................................................... 10 Low Dropout Bipolar Bridge Driver ........................................ 20 Maximum Power Dissipation ................................................... 10 Outline Dimensions ....................................................................... 21 ESD Caution ................................................................................ 10 Ordering Guide .......................................................................... 22 REVISION HISTORY 9/15—Rev. I to Rev. J 10/05—Rev. E to Rev. F Changes to Figure 12 ...................................................................... 12 Updated Format .................................................................. Universal Changes to Outline Dimensions .................................................. 24 1/10—Rev. H to Rev. I Updated Ordering Guide .............................................................. 24 Changes to Features Section and General Description Section . 1 Changes to Endnote 1, Table 1 ........................................................ 5 1/03—Rev. D to Rev. E Changes to Endnote 1, Table 2 ........................................................ 7 Edits to Specifications ....................................................................... 2 Changes to Endnote 1, Table 3 ........................................................ 9 Edits to Figure 10 ............................................................................ 16 Deleted Table 4; Renumbered Sequentially................................. 10 Updated Outline Dimensions ....................................................... 17 Changes to Table 5 .......................................................................... 12 Updated Outline Dimensions ....................................................... 21 10/02—Rev. C to Rev. D Changes to Ordering Guide .......................................................... 22 Edits to Features................................................................................. 1 Deleted 3 V, Single-Supply Stereo Headphone Driver Section . 22 Edits to Ordering Guide ................................................................... 6 Deleted Figure 50; Renumbered Sequentially............................. 22 Updated SOIC Package Outline ................................................... 17 8/08—Rev. G to Rev H. 8/02—Rev. B to Rev. C Changes to Features Section and General Description Section . 1 All Figures Updated ........................................................... Universal Changed V to V Throughout ................................................... 4 Edits to Features................................................................................. 1 O OUT Changes to Table 1 ............................................................................ 4 Updated All Package Outlines ...................................................... 17 Changes to Table 2 ............................................................................ 6 Changes to Table 3 ............................................................................ 8 7/01—Rev. A to Rev. B Changes to Table 5 .......................................................................... 12 All Figures Updated ........................................................... Universal Added Table 6; Renumbered Sequentially .................................. 12 CERDIP References Removed ....................................... 1, 6, and 18 Changes to Figure 13 Caption ....................................................... 14 Additions to Product Description ................................................... 1 Changes to Figure 29, Figure 31, and Figure 35 ......................... 17 8-Lead SOIC and 8-Lead MSOP Diagrams Added ...................... 1 Changes to Figure 36 ...................................................................... 18 Deletion of AD822S Column ........................................................... 2 Changed Application Notes Section to Applications Edits to Absolute Maximum Ratings and Ordering Guide ......... 6 Information Section ....................................................................... 20 Removed Metallization Photograph ............................................... 6 Changes to Figure 46 and Figure 47 ............................................. 21 Changes to Figure 49 ...................................................................... 22 7/93—Revision 0: Initial Version Changes to Figure 51 ...................................................................... 23 6/06—Rev. F to Rev. G Changes to Features .......................................................................... 1 Changes to Table 4 .......................................................................... 10 Changes to Table 5 .......................................................................... 12 Changes to Table 6 .......................................................................... 22 Rev. J | Page 2 of 24

Data Sheet AD822 The AD822 drives up to 350 pF of direct capacitive load as a follower and provides a minimum output current of 15 mA. 1V 1V 20µs This allows the amplifier to handle a wide range of load conditions. 100.... .... .... .... .... .... .... .... .... .... Its combination of ac and dc performance, plus the outstanding 5V 90 load drive capability, results in an exceptionally versatile amplifier . for the single-supply user. VOUT The AD822 is available in two performance grades. The A grade and B grade are rated over the industrial temperature range of −40°C to +85°C. 10 0%.... .... .... .... .... .... .... .... .... .... 0V The AD822 is offered in three varieties of 8-lead packages: PDIP, MSOP, and SOIC_N. (GND) 1V 00874-003 Figure 3. Gain of 2 Amplifier; VS = 5 V, 0 V, VIN = 2.5 V Sine Centered at 1.25 V, RL = 100 Ω Rev. J | Page 3 of 24

AD822 Data Sheet SPECIFICATIONS V = 0 V, 5 V at T = 25°C, V = 0 V, V = 0.2 V, unless otherwise noted. S A CM OUT Table 1. A Grade B Grade Parameter Test Conditions/Comments Min Typ Max Min Typ Max Unit DC PERFORMANCE Initial Offset 0.1 0.8 0.1 0.4 mV Maximum Offset Over Temperature 0.5 1.2 0.5 0.9 mV Offset Drift 2 2 µV/°C Input Bias Current V = 0 V to 4 V 2 25 2 10 pA CM At T 0.5 5 0.5 2.5 nA MAX Input Offset Current 2 20 2 10 pA At T 0.5 0.5 nA MAX Open-Loop Gain V = 0.2 V to 4 V OUT R = 100 kΩ 500 1000 500 1000 V/mV L T to T 400 400 V/mV MIN MAX R = 10 kΩ 80 150 80 150 V/mV L T to T 80 80 V/mV MIN MAX R = 1 kΩ 15 30 15 30 V/mV L T to T 10 10 V/mV MIN MAX NOISE/HARMONIC PERFORMANCE Input Voltage Noise f = 0.1 Hz to 10 Hz 2 2 µV p-p f = 10 Hz 25 25 nV/√Hz f = 100 Hz 21 21 nV/√Hz f = 1 kHz 16 16 nV/√Hz f = 10 kHz 13 13 nV/√Hz Input Current Noise f = 0.1 Hz to 10 Hz 18 18 fA p-p f = 1 kHz 0.8 0.8 fA/√Hz Harmonic Distortion R = 10 kΩ to 2.5 V L f = 10 kHz V = 0.25 V to 4.75 V −93 −93 dB OUT DYNAMIC PERFORMANCE Unity-Gain Frequency 1.8 1.8 MHz Full Power Response V p-p = 4.5 V 210 210 kHz OUT Slew Rate 3 3 V/µs Settling Time To 0.1% V = 0.2 V to 4.5 V 1.4 1.4 µs OUT To 0.01% V = 0.2 V to 4.5 V 1.8 1.8 µs OUT MATCHING CHARACTERISTICS Initial Offset 1.0 0.5 mV Maximum Offset Over Temperature 1.6 1.3 mV Offset Drift 3 3 µV/°C Input Bias Current 20 10 pA Crosstalk @ f = 1 kHz R = 5 kΩ −130 –130 dB L Crosstalk @ f = 100 kHz R = 5 kΩ −93 –93 dB L Rev. J | Page 4 of 24

Data Sheet AD822 A Grade B Grade Parameter Test Conditions/Comments Min Typ Max Min Typ Max Unit INPUT CHARACTERISTICS Input Voltage Range1, T to T −0.2 +4 −0.2 +4 V MIN MAX Common-Mode Rejection Ratio (CMRR) V = 0 V to 2 V 66 80 69 80 dB CM T to T V = 0 V to 2 V 66 66 dB MIN MAX CM Input Impedance Differential 1013||0.5 1013||0.5 Ω||pF Common Mode 1013||2.8 1013||2.8 Ω||pF OUTPUT CHARACTERISTICS Output Saturation Voltage2 V − V I = 20 µA 5 7 5 7 mV OL EE SINK T to T 10 10 mV MIN MAX V − V I = 20 µA 10 14 10 14 mV CC OH SOURCE T to T 20 20 mV MIN MAX V − V I = 2 mA 40 55 40 55 mV OL EE SINK T to T 80 80 mV MIN MAX V − V I = 2 mA 80 110 80 110 mV CC OH SOURCE T to T 160 160 mV MIN MAX V – V I = 15 mA 300 500 300 500 mV OL EE SINK T to T 1000 1000 mV MIN MAX V − V I = 15 mA 800 1500 800 1500 mV CC OH SOURCE T to T 1900 1900 mV MIN MAX Operating Output Current 15 15 mA T to T 12 12 mA MIN MAX Capacitive Load Drive 350 350 pF POWER SUPPLY Quiescent Current, T to T 1.24 1.6 1.24 1.6 mA MIN MAX Power Supply Rejection V+ = 5 V to 15 V 66 80 70 80 dB T to T 66 70 dB MIN MAX 1 This is a functional specification. Amplifier bandwidth decreases when the input common-mode voltage is driven in the range (V+ − 1 V) to V+. Common-mode error voltage is typically less than 5 mV with the common-mode voltage set at 1 V below the positive supply. 2 VOL − VEE is defined as the difference between the lowest possible output voltage (VOL) and the negative voltage supply rail (VEE). VCC − VOH is defined as the difference between the highest possible output voltage (VOH) and the positive supply voltage (VCC). Rev. J | Page 5 of 24

AD822 Data Sheet V = ±5 V at T = 25°C, V = 0 V, V = 0 V, unless otherwise noted. S A CM OUT Table 2. A Grade B Grade Parameter Test Conditions/Comments Min Typ Max Min Typ Max Unit DC PERFORMANCE Initial Offset 0.1 0.8 0.1 0.4 mV Maximum Offset Over Temperature 0.5 1.5 0.5 1 mV Offset Drift 2 2 µV/°C Input Bias Current V = −5 V to +4 V 2 25 2 10 pA CM At T 0.5 5 0.5 2.5 nA MAX Input Offset Current 2 20 2 10 pA At T 0.5 0.5 nA MAX Open-Loop Gain V = −4 V to +4 V OUT R = 100 kΩ 400 1000 400 1000 V/mV L T to T 400 400 V/mV MIN MAX R = 10 kΩ 80 150 80 150 V/mV L T to T 80 80 V/mV MIN MAX R = 1 kΩ 20 30 20 30 V/mV L T to T 10 10 V/mV MIN MAX NOISE/HARMONIC PERFORMANCE Input Voltage Noise f = 0.1 Hz to 10 Hz 2 2 µV p-p f = 10 Hz 25 25 nV/√Hz f = 100 Hz 21 21 nV/√Hz f = 1 kHz 16 16 nV/√Hz f = 10 kHz 13 13 nV/√Hz Input Current Noise f = 0.1 Hz to 10 Hz 18 18 fA p-p f = 1 kHz 0.8 0.8 fA/√Hz Harmonic Distortion R = 10 kΩ L f = 10 kHz V = ±4.5 V −93 −93 dB OUT DYNAMIC PERFORMANCE Unity-Gain Frequency 1.9 1.9 MHz Full Power Response V p-p = 9 V 105 105 kHz OUT Slew Rate 3 3 V/µs Settling Time to 0.1% V = 0 V to ±4.5 V 1.4 1.4 µs OUT to 0.01% V = 0 V to ±4.5 V 1.8 1.8 µs OUT MATCHING CHARACTERISTICS Initial Offset 1.0 0.5 mV Maximum Offset Over Temperature 3 2 mV Offset Drift 3 3 µV/°C Input Bias Current 25 10 pA Crosstalk @ f = 1 kHz R = 5 kΩ −130 −130 dB L Crosstalk @ f = 100 kHz R = 5 kΩ −93 −93 dB L INPUT CHARACTERISTICS Input Voltage Range1, T to T −5.2 +4 −5.2 +4 V MIN MAX Common-Mode Rejection Ratio (CMRR) V = −5 V to +2 V 66 80 69 80 dB CM T to T V = −5 V to +2 V 66 66 dB MIN MAX CM Input Impedance Differential 1013||0.5 1013||0.5 Ω||pF Common Mode 1013||2.8 1013||2.8 Ω||pF Rev. J | Page 6 of 24

Data Sheet AD822 A Grade B Grade Parameter Test Conditions/Comments Min Typ Max Min Typ Max Unit OUTPUT CHARACTERISTICS Output Saturation Voltage2 V − V I = 20 µA 5 7 5 7 mV OL EE SINK T to T 10 10 mV MIN MAX V − V I = 20 µA 10 14 10 14 mV CC OH SOURCE T to T 20 20 mV MIN MAX V − V I = 2 mA 40 55 40 55 mV OL EE SINK T to T 80 80 mV MIN MAX V − V I = 2 mA 80 110 80 110 mV CC OH SOURCE T to T 160 160 mV MIN MAX V − V I = 15 mA 300 500 300 500 mV OL EE SINK T to T 1000 1000 mV MIN MAX V − V I = 15 mA 800 1500 800 1500 mV CC OH SOURCE T to T 1900 1900 mV MIN MAX Operating Output Current 15 15 mA T to T 12 12 mA MIN MAX Capacitive Load Drive 350 350 pF POWER SUPPLY Quiescent Current, T to T 1.3 1.6 1.3 1.6 mA MIN MAX Power Supply Rejection V = ±5 V to ±15 V 66 80 70 80 dB SY T to T 66 70 dB MIN MAX 1 This is a functional specification. Amplifier bandwidth decreases when the input common-mode voltage is driven in the range (V+ − 1 V) to V+. Common-mode error voltage is typically less than 5 mV with the common-mode voltage set at 1 V below the positive supply. 2 VOL − VEE is defined as the difference between the lowest possible output voltage (VOL) and the negative voltage supply rail (VEE). VCC − VOH is defined as the difference between the highest possible output voltage (VOH) and the positive supply voltage (VCC). Rev. J | Page 7 of 24

AD822 Data Sheet V = ±15 V at T = 25°C, V = 0 V, V = 0 V, unless otherwise noted. S A CM OUT Table 3. A Grade B Grade Parameter Test Conditions/Comments Min Typ Max Min Typ Max Unit DC PERFORMANCE Initial Offset 0.4 2 0.3 1.5 mV Maximum Offset Over Temperature 0.5 3 0.5 2.5 mV Offset Drift 2 2 µV/°C Input Bias Current V = 0 V 2 25 2 12 pA CM V = −10 V 40 40 pA CM At T V = 0 V 0.5 5 0.5 2.5 nA MAX CM Input Offset Current 2 20 2 12 pA At T 0.5 0.5 nA MAX Open-Loop Gain V = −10 V to +10 V OUT R = 100 kΩ 500 2000 500 2000 V/mV L T to T 500 500 V/mV MIN MAX R = 10 kΩ 100 500 100 500 V/mV L T to T 100 100 V/mV MIN MAX R = 1 kΩ 30 45 30 45 V/mV L T to T 20 20 V/mV MIN MAX NOISE/HARMONIC PERFORMANCE Input Voltage Noise f = 0.1 Hz to 10 Hz 2 2 µV p-p f = 10 Hz 25 25 nV/√Hz f = 100 Hz 21 21 nV/√Hz f = 1 kHz 16 16 nV/√Hz f = 10 kHz 13 13 nV/√Hz Input Current Noise f = 0.1 Hz to 10 Hz 18 18 fA p-p f = 1 kHz 0.8 0.8 fA/√Hz Harmonic Distortion R = 10 kΩ L f = 10 kHz V = ±10 V −85 −85 dB OUT DYNAMIC PERFORMANCE Unity-Gain Frequency 1.9 1.9 MHz Full Power Response V p-p = 20 V 45 45 kHz OUT Slew Rate 3 3 V/µs Settling Time to 0.1% V = 0 V to ±10 V 4.1 4.1 µs OUT to 0.01% V = 0 V to ±10 V 4.5 4.5 µs OUT MATCHING CHARACTERISTICS Initial Offset 3 2 mV Maximum Offset Over Temperature 4 2.5 mV Offset Drift 3 3 µV/°C Input Bias Current 25 12 pA Crosstalk @ f = 1 kHz R = 5 kΩ −130 −130 dB L Crosstalk @ f = 100 kHz R = 5 kΩ −93 −93 dB L INPUT CHARACTERISTICS Input Voltage Range1, T to T −15.2 +14 −15.2 +14 V MIN MAX Common-Mode Rejection Ratio (CMRR) V = −15 V to +12 V 70 80 74 90 dB CM T to T V = −15 V to +12 V 70 74 dB MIN MAX CM Input Impedance Differential 1013||0.5 1013||0.5 Ω||pF Common Mode 1013||2.8 1013||2.8 Ω||pF Rev. J | Page 8 of 24

Data Sheet AD822 A Grade B Grade Parameter Test Conditions/Comments Min Typ Max Min Typ Max Unit OUTPUT CHARACTERISTICS Output Saturation Voltage2 V − V I = 20 µA 5 7 5 7 mV OL EE SINK T to T 10 10 mV MIN MAX V − V I = 20 µA 10 14 10 14 mV CC OH SOURCE T to T 20 20 mV MIN MAX V − V I = 2 mA 40 55 40 55 mV OL EE SINK T to T 80 80 mV MIN MAX V − V I = 2 mA 80 110 80 110 mV CC OH SOURCE T to T 160 160 mV MIN MAX V − V I = 15 mA 300 500 300 500 mV OL EE SINK T to T 1000 1000 mV MIN MAX V − V I = 15 mA 800 1500 800 1500 mV CC OH SOURCE T to T 1900 1900 mV MIN MAX Operating Output Current 20 20 mA T to T 15 15 mA MIN MAX Capacitive Load Drive 350 350 pF POWER SUPPLY Quiescent Current, T to T 1.4 1.8 1.4 1.8 mA MIN MAX Power Supply Rejection V = ±5 V to ±15 V 70 80 70 80 dB SY T to T 70 70 dB MIN MAX 1 This is a functional specification. Amplifier bandwidth decreases when the input common-mode voltage is driven in the range (V+ − 1 V) to V+. Common-mode error voltage is typically less than 5 mV with the common-mode voltage set at 1 V below the positive supply. 2 VOL − VEE is defined as the difference between the lowest possible output voltage (VOL) and the negative voltage supply rail (VEE). VCC − VOH is defined as the difference between the highest possible output voltage (VOH) and the positive supply voltage (VCC). Rev. J | Page 9 of 24

AD822 Data Sheet ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE Table 4. Parameter Rating θ is specified for the worst case conditions, that is, a device JA Supply Voltage ±18 V soldered in a circuit board for surface-mount packages. Internal Power Dissipation Table 5. Thermal Resistance 8-Lead PDIP (N) Observe derating curves Package Type θ Unit 8-Lead SOIC_N (R) Observe derating curves JA 8-lead PDIP (N) 90 °C/W 8-Lead MSOP (RM) Observe derating curves 8-lead SOIC_N (R) 160 °C/W Input Voltage1 ((V+) + 0.2 V) to ((V−) − 20 V) 8-lead MSOP (RM) 190 °C/W Output Short-Circuit Duration Indefinite Differential Input Voltage ±30 V MAXIMUM POWER DISSIPATION Storage Temperature Range (N) –65°C to +125°C The maximum power that can be safely dissipated by the AD822 is Storage Temperature Range (R, RM) –65°C to +150°C limited by the associated rise in junction temperature. For plastic Operating Temperature Range packages, the maximum safe junction temperature is 145°C. If A Grade and B Grade –40°C to +85°C these maximums are exceeded momentarily, proper circuit Lead Temperature 260°C operation is restored as soon as the die temperature is reduced. (Soldering, 60 sec) Leaving the device in the overheated condition for an extended period can result in device burnout. To ensure proper operation, it 1 See the Input Characteristics section. is important to observe the derating curves shown in Figure 27. Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a While the AD822 is internally short-circuit protected, this may not stress rating only; functional operation of the product at these be sufficient to guarantee that the maximum junction temperature or any other conditions above those indicated in the operational is not exceeded under all conditions. With power supplies ±12 V or section of this specification is not implied. Operation beyond less at an ambient temperature of 25°C or less, if the output node is the maximum operating conditions for extended periods may shorted to a supply rail, then the amplifier is not destroyed, even if affect product reliability. this condition persists for an extended period. ESD CAUTION Rev. J | Page 10 of 24

Data Sheet AD822 TYPICAL PERFORMANCE CHARACTERISTICS 70 5 VS = 0V, 5V 60 A) NITS50 ENT (p NUMBER OF U432000 PUT BIAS CURR 0 VS = ±5V VS = 0V, +5VAND ±5V N I 10 –00.5 –0.4 –0.3 –0.2OFF–0S.E1T VO0LTAG0E.1 (mV0).2 0.3 0.4 0.5 00874-004 –5–5 –4 –3 C–O2MMO–N1-MOD0E VOL1TAGE2 (V) 3 4 5 00874-007 Figure 4. Typical Distribution of Offset Voltage (390 Units) Figure 7. Input Bias Current vs. Common-Mode Voltage; VS = 5 V, 0 V, and VS = ±5 V 16 1k 14 VS = ±5V VS = ±15V 12 A)100 p T ( 10 N E N R N BI 8 CUR 10 % I S A 6 BI T U P 4 N 1 I 2 0–12 –10 –8 –O6FFS–E4T VO–L2TAGE0 DRIF2T (µV4/°C) 6 8 10 00874-005 0.1–16 –12 –8COMM–O4N-MOD0E VOLT4AGE (V)8 12 16 00874-008 Figure 5. Typical Distribution of Offset Voltage Drift (100 Units) Figure 8. Input Bias Current vs. Common-Mode Voltage; VS = ±15 V 50 100k 45 10k 40 A) F UNITS3350 RRENT (p 1k ER O25 S CU100 MB20 BIA NU15 UT 10 P N 10 I 1 5 00 1 2 I3NPUT 4BIAS C5URRE6NT (p7A) 8 9 10 00874-006 0.120 40 60TEMPER8A0TURE (°C1)00 120 140 00874-009 Figure 6. Typical Distribution of Input Bias Current (213 Units) Figure 9. Input Bias Current vs. Temperature; VS = 5 V, VCM = 0 V Rev. J | Page 11 of 24

AD822 Data Sheet 10M 40 OP GAIN (V/V) 1M VS = 0V, +5V VS = ±15V R VOLTAGE (µV) 200 RLP =O S20 RkΩAIL RL = 2kΩ NPEOGS RRAAIILL O O OPEN-L100k VS = 0V, +3V INPUT ERR–20 RPAOISL NEG RAIL RL = 100kΩ NEG RAIL 10k100 1LkOAD RESISTANCE 1(Ω0k) 100k 00874-010 –400 OUT60PUT VOLTA1G20E FROM SU18P0PLY RAILS2 4(0mV) 300 00874-013 Figure 10. Open-Loop Gain vs. Load Resistance Figure 13. Input Error Voltage with Output Voltage Within 300 mV of Either Supply Rail for Various Resistive Loads; VS = ±5 V 10M 1k RL = 100kΩ VS = ±15V √Hz) V) V/ OP GAIN (V/ 1M RL = 10kΩ VS V=S 0 =V ,± +155VV GE NOISE (n100 LO VS = 0V, +5V TA OPEN-100k VS = ±15V UT VOL 10 RL = 600Ω NP I VS = 0V, +5V 10k–60 –40 –20 0 TE2M0PER4A0TURE6 0(°C)80 100 120 140 00874-011 11 10 FREQU1E0N0CY (Hz) 1k 10k 00874-014 Figure 11. Open-Loop Gain vs. Temperature Figure 14. Input Voltage Noise vs. Frequency 300 –40 RL = 10kΩ 200 –50 ACL = –1 V) m GE ( 100 RL = 10kΩ –60 R VOLTA 0 RL = 100kΩ D (dB) –70 VS = 0V, +3V; VOUT = 2.5V p-p RO TH –80 ER VS = ±15V; VOUT = 20V p-p T –100 U –90 INP RL = 600Ω VS = ±5V; VOUT = 9V p-p –200 –100 VS = 0V, +5V; VOUT = 4.5V p-p –300–16 –12 –8 OU–T4PUT VO0LTAGE4 (V) 8 12 16 00874-012 –110100 1kFREQUENCY (Hz)10k 100k 00874-015 Figure 12. Input Error Voltage vs. Output Voltage for Resistive Loads Figure 15. THD vs. Frequency Rev. J | Page 12 of 24

Data Sheet AD822 100 100 90 80 80 80 dB) 70 VS = ±15V OOP GAIN (dB) 6400 GAIN PHASE 6400 ARGIN (Degrees) DE REJECTION ( 465000 VS = 0V, +3V VS = 0V, +5V L M O OPEN- 20 20 PHASE MMON-M 3200 O 0 0 C RL = 2kΩ 10 –2010CL = 1001p0F0 1kFREQU1E0NkCY (Hz1)00k 1M 10M–20 00874-016 010 100 1kFREQU1E0NkCY (Hz)100k 1M 10M 00874-019 Figure 16. Open-Loop Gain and Phase Margin vs. Frequency Figure 19. Common-Mode Rejection vs. Frequency 1k 5 ACL = +1 VS = ±15V V) m 100 GE ( 4 NREAGILATIVE PROAISLITIVE Ω) A ANCE ( 10 R VOLT 3 D O E R P R PUT IM 1 ODE E 2 +25°C T M OU0.1 MMON- 1 –55°C +125°C O –55°C C +125°C 0.01100 1k F1R0kEQUENCY1 0(H0kz) 1M 10M 00874-017 0–1 COMMON-M0ODE VOLTAGE1 FROM SUPPL2Y RAILS (V) 3 00874-020 Figure 17. Output Impedance vs. Frequency Figure 20. Absolute Common-Mode Error vs. Common-Mode Voltage from Supply Rails (VS − VCM) 16 1000 S 12 V) T m O ±VOL 8 1% TAGE (100 T L 0 4 O OM 0.01% N V VS – VOH FR 0 0.1% ERROR TIO OUTPUT SWING –1––248 1% 0.01% OUTPUT SATURA 10 VOL – VS –160 1 SET2TLING TIME3 (µs) 4 5 00874-018 00.001 0.01 LOA0D.1 CURRENT 1(mA) 10 100 00874-021 Figure 18. Output Swing and Error vs. Settling Time Figure 21. Output Saturation Voltage vs. Load Current Rev. J | Page 13 of 24

AD822 Data Sheet 1000 100 URATION VOLTAGE (mV)100 IIIISSSSOIOINNUUKKRR ==CC EE11 0m==m A11A0mmAA UPPLY REJECTION (dB)968754000000 +PSRR UT SAT 10 ISOURCE = 10µA WER S30 –PSRR TP ISINK = 10µA PO20 U O 10 1–60 –40 –20 0 TE2M0PER4A0TURE6 0(°C)80 100 120 140 00874-022 010 100 1kFREQU1E0NkCY (Hz1)00k 1M 10M 00874-025 Figure 22. Output Saturation Voltage vs. Temperature Figure 25. Power Supply Rejection vs. Frequency 80 30 mA) 70 VS = ±15V 25 RL = 2kΩ NT LIMIT ( 6500 –OUT GE (V) 20 VS = ±15V RE VS = ±15V TA RCUIT CUR 4300 VS = 0V, +5VVS = 0V, +3V +– UTPUT VOL 1150 T-CI 20 – O OR + VS = 0V, +5V SH 10 VS = 0V, +5V VS = 0V, +3V + 5 VS = 0V, +3V 0–60 –40 –20 0 TE2M0PER4A0TURE6 0(°C)80 100 120 140 00874-023 010k 100kFREQUENCY (Hz)1M 10M 00874-026 Figure 23. Short-Circuit Current Limit vs. Temperature Figure 26. Large Signal Frequency Response 1600 2.4 T = +125°C 2.2 1400 T = +25°C W)2.0 8-LEAD PDIP A)1200 N (1.8 T (µ T = –55°C TIO1.6 8-LEAD SOIC EN1000 PA R SI1.4 R S ENT CU 800 WER DI11..02 C 600 O S P0.8 QUIE 400 OTAL 0.6 8-LEAD MSOP T0.4 200 0.2 00 4 8 TO1T2ALSU1P6PLYV2O0LTAG2E4(V) 28 32 36 00874-024 0–60 –40 A–2M0BIENT 0TEMPER2A0TURE (4°0C) 60 80 00874-027 Figure 24. Quiescent Current vs. Supply Voltage vs. Temperature Figure 27. Maximum Power Dissipation vs. Temperature for Packages Rev. J | Page 14 of 24

Data Sheet AD822 –70 5V 5µs –80 100 90 –90 B) d K (–100 L A T S S–110 O R C –120 10 0% ––114300300 1k 3k FR1E0QkUENC3Y0 (kHz) 100k 300k 1M 00874-028 Figure 32. Large Signal Response Unity-Gain Follower; VS = ±15 V, R00874-032L = 10 kΩ Figure 28. Crosstalk vs. Frequency 10mV 500ns V+ 0.01µF 100 8 90 + 1/2 VIN AD822 – RL 100pF VOUT 4 0.01µF 00874-029 Figure 29. Unity-Gain Follower 10 0% 00874-033 5V 10µs Figure 33. Small Signal Response Unity-Gain Follower; VS = ±15 V, RL = 10 kΩ 100 90 1V 2µs 100 90 10 0% 00874-030 10 Figure 30. 20 V p-p, 25 kHz Sine Wave Input; Unity-Gain Follower; VS = ±15 V, GND 0% RL = 600 ΩV OUT 00874-034 V+ Figure 34. VS = 5 V, 0 V; Unity-Gain Follower Response to 0 V to 4 V Step 20kΩ 2.2kΩ 0.1µF 1µF V+ 0.01µF 2 – 8 – 6 8 20V p-p AD18/222 1 7 AD18/222 VIN + 1/2 3 + 5kΩ 5kΩ + 5 –AD822 RL 100pF VOUT VIN CROSSTALK = 20 log1V0OVUINT V– 0.1µF 1µF 00874-031 4 Figure 35. Unity -Gain Follower 00874-035 Figure 31. Crosstalk Test Circuit Rev. J | Page 15 of 24

AD822 Data Sheet 10kΩ 20kΩ VIN V+ VOUT 10mV 2µs 0.01µF 100 8 90 – 1/2 AD822 + RL 100pF 4 00874-036 Figure 36. Gain of 2 Inverter 10 GND 0% 1V 2µs 00874-039 Figure 39. VS = 5 V, 0 V; Gain of 2 Inverter Response to 20 mV Step, 100 Centered 20 mV Below Ground, RL = 10 kΩ 90 1V 2µs 100 90 10 GND 0% 00874-037 10 Figure 37. VS = 5 V, 0 V; Unity-Gain Follower Response to 0 V to 5 V Step GND 0% 00874-040 10mV 2µs Figure 40. VS = 5 V, 0 V; Gain of 2 Inverter Response to 2.5 V Step, Centered −1.25 V Below Ground, RL = 10 kΩ 100 90 500mV 10µs 100 90 10 GND 0% 00874-038 10 Figure 38. VS = 5 V, 0 V; Unity-Gain Follower Response to 40 mV Step, GND 0% Centered 40 mV above Ground, RL = 10 kΩ 00874-041 Figure 41. VS = 3 V, 0 V; Gain of 2 Inverter, VIN = 1.25 V, 25 kHz, Sine Wave Centered at −0.75 V, RL = 600 Ω Rev. J | Page 16 of 24

Data Sheet AD822 1V 10µs 100.... .... .... .... .... .... .... .... .... .... 90 10 GND 0%.... .... .... .... .... .... .... .... .... .... 1V (a) 1V 1V 10µs +Vs 100.... .... .... .... ... ... .... .... .... .... 90 10 GND 0%.... .... .... .... .... .... .... .... .... .... 1V (b) 5V RP VIN VOUT 00874-042 Figure 42. (a) Response with RP = 0; VIN from 0 V to +VS (b) VIN = 0 V to +VS + 200 mV VOUT = 0 V to +VS RP = 49.9 kΩ Rev. J | Page 17 of 24

AD822 Data Sheet APPLICATIONS INFORMATION INPUT CHARACTERISTICS 100k WHENEVERJOHNSONNOISEISGREATERTHAN AMPLIFIERNOISE,AMPLIFIERNOISECANBE In the AD822, N-channel JFETs are used to provide a low offset, 10k CONSIDEREDNEGLIGIBLEFORAPPLICATION. low noise, high impedance input stage. Minimum input common- V) 1kHz µ mode voltage extends from 0.2 V below −VS to 1 V less than +VS. SE ( 1k Driving the input voltage closer to the positive rail causes a loss OI RESISTOR JOHNSON N of amplifier bandwidth (as can be seen by comparing the large AGE 100 NOISE signal responses shown in Figure 34 and Figure 37) and increased LT O common-mode voltage error as illustrated in Figure 20. T V 10 U The AD822 does not exhibit phase reversal for input voltages up NP 10Hz I to and including +V. Figure 42 shows the response of an AD822 1 S AMPLIFIER-GENERATED voltage follower to a 0 V to 5 V (+VS) square wave input. The NOISE iunpp tuot +aVndS woiuthtpouutt aprhea ssue preevreimrspalo. sTehde. rTehdeu coeudt pbuatn dtrwacidktsh t ahbeo ivnep au t 0.110k 100k S1OMURCE IM10PMEDANC1E0 0(ΩM) 1G 10G 00874-043 4 V input causes the rounding of the output waveform. For input Figure 43. Total Noise vs. Source Impedance voltages greater than +V, a resistor in series with the AD822 S OUTPUT CHARACTERISTICS noninverting input prevents phase reversal, at the expense of greater input voltage noise. This is illustrated in Figure 42. The AD822 unique bipolar rail-to-rail output stage swings within 5 mV of the negative supply and 10 mV of the positive supply with Because the input stage uses N-channel JFETs, input current no external resistive load. The approximate output saturation during normal operation is negative; the current flows out from resistance of the AD822 is 40 Ω sourcing and 20 Ω sinking, which the input terminals. If the input voltage is driven more positive can be used to estimate output saturation voltage when driving than +V − 0.4 V, then the input current reverses direction as S heavier current loads. For instance, when sourcing 5 mA, the internal device junctions become forward biased. This is illustrated saturation voltage to the positive supply rail is 200 mV; when in Figure 7. sinking 5 mA, the saturation voltage to the negative rail is 100 mV. A current-limiting resistor should be used in series with the input The open-loop gain characteristic of the amplifier changes as a of the AD822 if there is a possibility of the input voltage exceeding function of resistive load, as shown in Figure 10 to Figure 13. For the positive supply by more than 300 mV, or if an input voltage is load resistances over 20 kΩ, the AD822 input error voltage is applied to the AD822 when +V or −V = 0 V. The amplifier is S S virtually unchanged until the output voltage is driven to 180 mV of damaged if left in that condition for more than 10 seconds. A 1 kΩ either supply. resistor allows the amplifier to withstand up to 10 V of continuous overvoltage and increases the input voltage noise by a negligible If the AD822 output is overdriven so that either of the output amount. devices are saturated, the amplifier recovers within 2 μs of the input returning to the linear operating region of the amplifier. Input voltages less than −V are different. The amplifier can safely S withstand input voltages 20 V below the negative supply voltage Direct capacitive loads interact with the effective output if the total voltage from the positive supply to the input terminal impedance of the amplifier to form an additional pole in the is less than 36 V. In addition, the input stage typically maintains amplifier feedback loop, which can cause excessive peaking on picoampere (pA) level input currents across that input the pulse response or loss of stability. The worst case occurs voltage range. when the amplifier is used as a unity-gain follower. Figure 44 shows the AD822 pulse response as a unity-gain follower The AD822 is designed for 13 nV/√Hz wideband input voltage driving 350 pF. This amount of overshoot indicates approximately noise and maintains low noise performance to low frequencies 20° of phase margin—the system is stable, but nearing the edge. (refer to Figure 14). This noise performance, along with the AD822 Configurations with less loop gain, and as a result less loop low input current and current noise, means that the AD822 bandwidth, are much less sensitive to capacitance load effects. contributes negligible noise for applications with source resistances greater than 10 kΩ and signal bandwidths greater than 1 kHz. This is illustrated in Figure 43. Rev. J | Page 18 of 24

Data Sheet AD822 SINGLE-SUPPLY VOLTAGE TO FREQUENCY 20mV 2µs CONVERTER 100.... .... .... .... .... .... .... .... .... .... The circuit shown in Figure 47 uses the AD822 to drive a low 90 power timer that produces a stable pulse of width t. The positive 1 going output pulse is integrated by R1 and C1 and used as one input to the AD822 that is connected as a differential integrator. The other input (nonloading) is the unknown voltage, V . The IN AD822 output drives the timer trigger input, closing the overall 10 feedback loop. .... .... .... .... .... .... .... .... .... .... 0% 10V Figure 44. Small Signal Response of AD822 as 00874-044 C0.51µF 2 6VRREEUFF 4=0 25V Unity-Gain Follower Driving 350 pF CMOS OUT2 3 5 RSCALE 74HCO4 C3 Figure 45 is a plot of noise gain vs. capacitive load that results in 4 10kΩ 4U3B 3 2U3A 1 0.1µF OUT1 a 20° phase margin for the AD822. Noise gain is the inverse of U2 R2 the feedback attenuation factor provided by the feedback 499kΩ 0.01µF, 2% CMOS 555 1% R3 4 8 network in use. U1 C1 116kΩ R V+ 6 5 R1 + 1/2 2 THR OUT 3 499kΩ AD822B TR VIN 1% – 7 DIS CV 5 GND C2 4 0.01µF 1 C4 2% 0.01µF RFR1 0VTO 2.5V 1+ FULL SCALE GAIN 3 N1.O fOTUETS = VIN/(VREF ×t1), t1 = 1.1 ×R3 ×C6. E = 25kHzfSAS SHOWN. NOIS 2 234... RRt13S= C= A3 L13E%µ F= M F1EO0T%RA Lf2O 0FUTIT LF =MI L 2<M05k 0<Hp1zp0 @0mp/ pV°CmIN T/ °=CC 2. T.0CV.. 00874-047 Figure 47. Single-Supply Voltage to Frequency Converter Typical AD822 bias currents of 2 pA allow MΩ range source 1 300 1k 3k 10k 30k impedances with negligible dc errors. Linearity errors on the CAPACITIVE LOAD FOR 20° PHASE MARGIN (pF) order of 0.01% full scale can be achieved with this circuit. This performance is obtained with a 5 V single supply that delivers less than 1 mA to the entire circuit. RF CL R1 00874-045 Figure 45. Noise Gain vs. Capacitive Load Tolerance Figure 46 shows a method for extending capacitance load drive capability for a unity-gain follower. With these component values, the circuit drives 5000 pF with a 10% overshoot. V+ 0.01µF 8 + VIN 1/2 100Ω AD822 VOUT – 4 0.01µF CL V– 20kΩ 20pF 00874-046 Figure 46. Extending Unity-Gain Follower Capacitive Load Capability Beyond 350 pF Rev. J | Page 19 of 24

AD822 Data Sheet SINGLE-SUPPLY PROGRAMMABLE GAIN R1 R2 R3 R4 R5 R6 OHMTEK INSTRUMENTATION AMPLIFIER + 90kΩ 9kΩ 1kΩ 1kΩ 9kΩ 90kΩ PART # 1043 The AD822 can be configured as a single-supply instrumentation VREF– amplifier that is able to operate from single supplies down to 3 V or dual supplies up to ±15 V. Using only one AD822 rather than three G = 10 G = 100 G = 100 G = 10 separate op amps, this circuit is cost and power efficient. The 2 pA V+ bias currents of the AD822 FET inputs minimize offset errors 0.1µF 2 caused by high, unbalanced source impedances. – 6 – An array of precision thin film resistors sets the in-amp gain to RP AD18/222 1 AD18/222 7 + be either 10 or 100. These resistors are laser trimmed to ratio VIN1 1kΩ 3+ 5 + 4 –VOUT match to 0.01% and have a maximum differential temperature RP 1kΩ coefficient of 5 ppm/°C. VIN2 ( R6 ) (G = 10) VOUT = (VIN1 – VIN2) 1+R4 + R5 +VREF PTaarbalme 6e.t Ienrs- A mp Performance VS = 3 V, 0 V VS = ±5 V (G = 100) VOUT = (VIN1 – VIN2)(1+R5R +4 R6)+VREF 00874-049 CMRR 74 dB 80 dB Figure 49. A Single-Supply Programmable Instrumentation Amplifier Common-Mode Voltage Range −0.2 V to +2 V −5.2 V to +4 V LOW DROPOUT BIPOLAR BRIDGE DRIVER 3 dB BW G = 10 180 kHz 180 kHz The AD822 can be used for driving a 350 Ω Wheatstone bridge. G = 100 18 kHz 18 kHz Figure 50 shows one half of the AD822 being used to buffer the t AD589, a 1.235 V low power reference. The output of 4.5 V can SETTLING 2 V Step 2 µs be used to drive an analog-to-digital converter (ADC) front end. 5 V Step 5 µs The other half of the AD822 is configured as a unity-gain inverter Noise @ f = 1 kHz and generates the other bridge input of −4.5 V. Resistor R1 and G = 10 270 nV/√Hz 270 nV/√Hz Resistor R2 provide a constant current for bridge excitation. The G = 100 2.2 µV/√Hz 2.2 µV/√Hz AD620 low power instrumentation amplifier is used to condition I (Total) 1.10 mA 1.15 mA the differential output voltage of the bridge. The gain of the AD620 SUPPLY is programmed using an external resistor (RG) and determined by 49.9kΩ 5µs G= +1 R 100.... .... .... .... ... ... .... .... .... .... G 90 V+ 49.9kΩ 8 R1 +1.235V 3 + 20Ω +AD589 A D1/8222 1 TOA/D CONVERTER REFERENCE INPUT – 2 – 25.4kΩ1% +VS 10 0% .... .... .... .... .... .... .... .... .... .... 10kΩ1% 350Ω 350Ω 2 – 7 1V 00874-048 350Ω 350Ω RG +AD6250 6 Figure 48. Pulse Response of In-Amp to a 500 mV p-p Input Signal; 10kΩ1% 3 4 VS = 5 V, 0 V; Gain = 0 VREF 6 – –VS 10kΩ1% A D1/8222 7 –4.5V V+ + + +5V 5 + R2 0.1μF 1μF 4 20Ω GND V– V–0.1μF+ + 1μF –5V 00874-051 Figure 50. Low Dropout Bipolar Bridge Driver Rev. J | Page 20 of 24

Data Sheet AD822 OUTLINE DIMENSIONS 0.400 (10.16) 0.365 (9.27) 0.355 (9.02) 8 5 0.280 (7.11) 0.250 (6.35) 1 4 0.240 (6.10) 0.325 (8.26) 0.310 (7.87) 0.100 (2.54) 0.300 (7.62) BSC 0.060 (1.52) 0.195 (4.95) 0.210 (5.33) MAX 0.130 (3.30) MAX 0.115 (2.92) 0.015 0.150 (3.81) (0.38) 0.015 (0.38) 0.130 (3.30) MIN GAUGE 0.115 (2.92) SEATING PLANE 0.014 (0.36) PLANE 0.010 (0.25) 0.022 (0.56) 0.008 (0.20) 0.005 (0.13) 0.430 (10.92) 0.018 (0.46) MIN MAX 0.014 (0.36) 0.070 (1.78) 0.060 (1.52) 0.045 (1.14) COMPLIANTTO JEDEC STANDARDS MS-001 CONTROLLING DIMENSIONSARE IN INCHES; MILLIMETER DIMENSIONS (RCINEOFRPEANRREERENN LCTEEHA EODSNSEL MSY)AAAYNR BDEE AR CROOEU NNNFODIGETUDAR-POEPFDRFOA INSPC RWHIAH ETOEQL UFEIO VORAR LU EHSNAETL ISFN FLDOEEARSDIGSN.. 070606-A Figure 51. 8-Lead Plastic Dual In-Line Package [PDIP] Narrow Body (N-8) Dimensions shown in inches and (millimeters) 5.00(0.1968) 4.80(0.1890) 8 5 4.00(0.1574) 6.20(0.2441) 3.80(0.1497) 1 4 5.80(0.2284) 1.27(0.0500) 0.50(0.0196) BSC 1.75(0.0688) 0.25(0.0099) 45° 0.25(0.0098) 1.35(0.0532) 8° 0.10(0.0040) 0° COPLANARITY 0.51(0.0201) 0.10 SEATING 0.31(0.0122) 0.25(0.0098) 01..2407((00..00510507)) PLANE 0.17(0.0067) COMPLIANTTOJEDECSTANDARDSMS-012-AA R(CINEOFNPEATRRREOENNLCLTEIHNEOGSNDELISYM)AEANNRDSEIAORRNOESUNANORDETEDAIN-POMPFRIFLOLMPIMIRLELIATIMTEEERTFSEO;RIRNECUQHSUEDIVIINMAELDENENSSTIIOGSNNFS.OR 012407-A Figure 52. 8-Lead Standard Small Outline Package [SOIC_N] Narrow Body (R-8) Dimensions shown in millimeters and (inches) Rev. J | Page 21 of 24

AD822 Data Sheet 3.20 3.00 2.80 8 5 5.15 3.20 4.90 3.00 4.65 2.80 1 4 PIN1 IDENTIFIER 0.65BSC 0.95 15°MAX 0.85 1.10MAX 0.75 0.80 0.15 0.40 6° 0.23 0.55 CO0P.0L5ANARITY 0.25 0° 0.09 0.40 0.10 COMPLIANTTOJEDECSTANDARDSMO-187-AA 100709-B Figure 53. 8-Lead Mini Small Outline Package [MSOP] (RM-8) Dimensions shown in millimeters ORDERING GUIDE Model1 Temperature Range Package Description Package Option Branding AD822AN −40°C to +85°C 8-Lead PDIP N-8 AD822ANZ −40°C to +85°C 8-Lead PDIP N-8 AD822AR −40°C to +85°C 8-Lead SOIC_N R-8 AD822AR-REEL −40°C to +85°C 8-Lead SOIC_N R-8 AD822AR-REEL7 −40°C to +85°C 8-Lead SOIC_N R-8 AD822ARZ −40°C to +85°C 8-Lead SOIC_N R-8 AD822ARZ-REEL −40°C to +85°C 8-Lead SOIC_N R-8 AD822ARZ-REEL7 −40°C to +85°C 8-Lead SOIC_N R-8 AD822ARMZ −40°C to +85°C 8-Lead MSOP RM-8 #B4A AD822ARMZ-REEL −40°C to +85°C 8-Lead MSOP RM-8 #B4A AD822BR −40°C to +85°C 8-Lead SOIC_N R-8 AD822BR-REEL −40°C to +85°C 8-Lead SOIC_N R-8 AD822BR-REEL7 −40°C to +85°C 8-Lead SOIC_N R-8 AD822BRZ −40°C to +85°C 8-Lead SOIC_N R-8 AD822BRZ-REEL −40°C to +85°C 8-Lead SOIC_N R-8 AD822BRZ-REEL7 −40°C to +85°C 8-Lead SOIC_N R-8 1 Z = RoHS Compliant Part, # denotes RoHS-compliant product may be top or bottom marked. SPICE model is available at www.analog.com. Rev. J | Page 22 of 24

Data Sheet AD822 NOTES Rev. J | Page 23 of 24

AD822 Data Sheet NOTES ©1993–2015 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D00874-0-9/15(J) Rev. J | Page 24 of 24