JFET Input Instrumentation Amplifier with Rail-to-Rail Output in MSOP Package AD8220 FEATURES PIN CONFIGURATION Low input currents AD8220 10 pA maximum input bias current (B grade) –IN 1 8 +VS 0.6 pA maximum input offset current (B grade) RG 2 7 VOUT High CMRR RG 3 6 REF 100 dB CMRR (minimum), G = 10 (B grade) +IN 4 5 –VS Exc8e0l ldeBn tC aMcR sRp e(mcifiniciamtiuomns) taon d5 kloHwz ,p Go w= e1r ( B grade) (NToOtPtoVSIEcaWle) 03579-005 Figure 1. 1.5 MHz bandwidth (G = 1) 14 nV/√Hz input noise (1 kHz) Slew rate: 2 V/μs 750 μA quiescent supply current (maximum) Versatile 10n MRaSiOl-tPo p-raacilk oaugtep ut NT (A) 1n IBIAS E Input voltage range to below negative supply rail RR 100p U 4 kV ESD protection C S 4.5 V to 36 V single supply A 10p BI ±2.25 V to ±18 V dual supply UT IOS P 1p Gain set with single resistor (G = 1 to 1000) N I Qualified for automotive applications 0.1p APPLICATIONS 03579-059 –50 –25 0 25 50 75 100 125 150 Medical instrumentation TEMPERATURE(°C) Precision data acquisition Figure 2. Input Bias Current and Offset Current vs. Temperature Transducer interfaces GENERAL DESCRIPTION The AD8220 is the first single-supply, JFET input instrumentation Gain is set from 1 to 1000 with a single resistor. Increasing the amplifier available in an MSOP package. Designed to meet the gain increases the common-mode rejection. Measurements that needs of high performance, portable instrumentation, the AD8220 need higher CMRR when reading small signals benefit when has a minimum common-mode rejection ratio (CMRR) of 86 dB the AD8220 is set for large gains. at dc and a minimum CMRR of 80 dB at 5 kHz for G = 1. Maxi- A reference pin allows the user to offset the output voltage. This mum input bias current is 10 pA and typically remains below feature is useful when interfacing with analog-to-digital converters. 300 pA over the entire industrial temperature range. Despite the The AD8220 is available in an MSOP that takes roughly half the JFET inputs, the AD8220 typically has a noise corner of only 10 Hz. board area of an SOIC. Performance for the A and B grade is With the proliferation of mixed-signal processing, the number specified over the industrial temperature range of −40°C to +85°C, of power supplies required in each system has grown. The AD8220 and the W grade is specified over the automotive temperature is designed to alleviate this problem. The AD8220 can operate range of −40°C to +125°C. on a ±18 V dual supply, as well as on a single +5 V supply. Its rail-to-rail output stage maximizes dynamic range on the low voltage supplies common in portable applications. Its ability to run on a single 5 V supply eliminates the need to use higher voltage, dual supplies. The AD8220 draws a maximum of 750 μA of quiescent current, making it ideal for battery powered devices. Rev. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Tel: 781.329.4700 www.analog.com Trademarks and registered trademarks are the property of their respective owners. Fax: 781.461.3113 ©2006–2010 Analog Devices, Inc. All rights reserved.

AD8220 TABLE OF CONTENTS Features .............................................................................................. 1  Power Supply Regulation and Bypassing ................................ 21  Applications ....................................................................................... 1  Input Bias Current Return Path ............................................... 21  Pin Configuration ............................................................................. 1  Input Protection ......................................................................... 21  General Description ......................................................................... 1  RF Interference ........................................................................... 22  Revision History ............................................................................... 2  Common-Mode Input Voltage Range ..................................... 22  Specifications ..................................................................................... 3  Driving an ADC ......................................................................... 22  Absolute Maximum Ratings ............................................................ 8  Applications Information .............................................................. 23  ESD Caution .................................................................................. 8  AC-Coupled Instrumentation Amplifier ................................ 23  Pin Configuration and Function Descriptions ............................. 9  Differential Output .................................................................... 23  Typical Performance Characteristics ........................................... 10  Electrocardiogram Signal Conditioning ................................. 25  Theory of Operation ...................................................................... 19  Outline Dimensions ....................................................................... 26  Gain Selection ............................................................................. 20  Ordering Guide .......................................................................... 26  Layout ........................................................................................... 20  Automotive Products ................................................................. 26  Reference Terminal .................................................................... 21  REVISION HISTORY 5/10—Rev. A to Rev. B 5/07—Rev. 0 to Rev. A Added W Grade .................................................................. Universal Changes to Table 1 ............................................................................. 3 Changes to Features Section and General Description Section . 1 Changes to Table 2 ............................................................................. 5 Changes to Specifications Section and Table 1 ............................. 3 Changes to Table 3 ............................................................................. 8 Changes to Table 2 ............................................................................ 5 Changes to Figure 6 and Figure 7 ................................................. 10 Updated Outline Dimensions ....................................................... 26 Changes to Figure 23 and Figure 24............................................. 13 Changes to Ordering Guide .......................................................... 26 Changes to Theory of Operation .................................................. 19 Added Automotive Products Section .......................................... 26 Changes to Layout .......................................................................... 20 Changes to Ordering Guide .......................................................... 26 4/06—Revision 0: Initial Version Rev. B | Page 2 of 28

AD8220 SPECIFICATIONS V+ = 15 V, V− = −15 V, V = 0 V, T = 25°C, T = −40°C to +85°C for A and B grades. T = −40°C to +125°C for W grade, S S REF A OPR OPR G = 1, R = 2 kΩ1, unless otherwise noted. L Table 1. A Grade B Grade W Grade Parameter Test Conditions Min Typ Max Min Typ Max Min Typ Max Unit COMMON-MODE T for A, B grades, A REJECTION RATIO (CMRR) T for W grade OPR CMRR DC to 60 Hz with V = ±10 V CM 1 kΩ Source Imbalance G = 1 78 86 77 dB G = 10 94 100 92 dB G = 100 94 100 92 dB G = 1000 94 100 92 dB CMRR at 5 kHz V = ±10 V CM G = 1 74 80 72 dB G = 10 84 90 80 dB G = 100 84 90 80 dB G = 1000 84 90 80 dB NOISE RTI noise = √(e 2 + (e /G)2), T ni no A Voltage Noise, 1 kHz Input Voltage Noise, e V +, V − = 0 V 14 14 17 14 nV/√Hz ni IN IN Output Voltage Noise, e V +, V − = 0 V 90 90 100 90 nV/√Hz no IN IN RTI, 0.1 Hz to 10 Hz G = 1 5 5 5 μV p-p G = 1000 0.8 0.8 0.8 μV p-p Current Noise f = 1 kHz 1 1 1 fA/√Hz VOLTAGE OFFSET V = V + V /G OS OSI OSO Input Offset, V T −250 +250 −125 +125 −250 +250 μV OSI A Average TC T −10 +10 −5 +5 −10 +10 μV/°C OPR Output Offset, V T −750 +750 −500 +500 −750 +750 μV OSO A Average TC T −10 +10 −5 +5 −10 +10 μV/°C OPR Offset RTI vs. Supply V = ±5 V to ±15 V, S (PSR) T for A, B grades, A T for W grade OPR G = 1 86 86 80 dB G = 10 96 100 92 dB G = 100 96 100 92 dB G = 1000 96 100 92 dB INPUT CURRENT Input Bias Current T 25 10 25 pA A Over Temperature T 0.3 0.3 100 nA OPR Input Offset Current T 2 0.6 2 pA A Over Temperature T 0.005 0.005 10 nA OPR DYNAMIC RESPONSE Small Signal Bandwidth, T A −3 dB G = 1 1500 1500 1500 kHz G = 10 800 800 800 kHz G = 100 120 120 120 kHz G = 1000 14 14 14 kHz Rev. B | Page 3 of 28

AD8220 A Grade B Grade W Grade Parameter Test Conditions Min Typ Max Min Typ Max Min Typ Max Unit Settling Time 0.01% 10 V step, T A G = 1 5 5 5 μs G = 10 4.3 4.3 4.3 μs G = 100 8.1 8.1 8.1 μs G = 1000 58 58 58 μs Settling Time 0.001% 10 V step, T A G = 1 6 6 6 μs G = 10 4.6 4.6 4.6 μs G = 100 9.6 9.6 9.6 μs G = 1000 74 74 74 μs Slew Rate G = 1 to 100 T 2 2 2 V/μs A GAIN G = 1 + (49.4 kΩ/R), G T for A, B grades, A T for W grade OPR Gain Range 1 1000 1 1000 1 1000 V/V Gain Error V = ±10 V OUT G = 1 −0.06 +0.06 −0.04 +0.04 −0.1 +0.1 % G = 10 −0.3 +0.3 −0.2 +0.2 −0.8 +0.8 % G = 100 −0.3 +0.3 −0.2 +0.2 −0.8 +0.8 % G = 1000 −0.3 +0.3 −0.2 +0.2 −0.8 +0.8 % Gain Nonlinearity VOUT = −10 V to +10 V, T A G = 1 R = 10 kΩ 10 15 10 15 10 15 ppm L G = 10 R = 10 kΩ 5 10 5 10 5 10 ppm L G = 100 R = 10 kΩ 30 60 30 60 30 60 ppm L G = 1000 R = 10 kΩ 400 500 400 500 400 500 ppm L G = 1 R = 2 kΩ 10 15 10 15 10 15 ppm L G = 10 R = 2 kΩ 10 15 10 15 10 15 ppm L G = 100 R = 2 kΩ 50 75 50 75 50 75 ppm L Gain vs. Temperature G = 1 3 10 2 5 3 10 ppm/°C G > 10 −50 −50 −50 ppm/°C INPUT Impedance (Pin to T 104||5 104||5 104||5 GΩ||pF A Ground)2 Input Operating Voltage V = ±2.25 V to ±18 V −V − +V − −V − +V − −V − +V − 2 V S S S S S S S Range3 for dual supplies 0.1 2 0.1 2 0.1 Over Temperature T −V − +V − −V − +V − −V − +V − V OPR S S S S S S 0.1 2.1 0.1 2.1 0.1 2.2 OUTPUT Output Swing R = 10 kΩ, T −14.7 +14.7 −14.7 +14.7 −14.7 +14.7 V L A Over Temperature T −14.6 +14.6 −14.6 +14.6 −14.3 +14.3 V OPR Short-Circuit Current T 15 15 15 mA A REFERENCE INPUT T kΩ A R 40 40 40 μA IN I V +, V − = 0 V 70 70 70 V IN IN IN Voltage Range −V +V −V +V +V V/V S S S S S Gain to Output T 1 ± 1 ± 1 ± V/V A 0.0001 0.0001 0.0001 Rev. B | Page 4 of 28

AD8220 A Grade B Grade W Grade Parameter Test Conditions Min Typ Max Min Typ Max Min Typ Max Unit POWER SUPPLY V Operating Range ±2.254 ±18 ±2.254 ±18 ±2.254 ±18 μA Quiescent Current T 750 750 750 μA A Over Temperature T 850 850 1000 μA OPR TEMPERATURE RANGE For Specified T −40 +85 −40 +85 −40 +125 °C OPR Performance 1 When the output sinks more than 4 mA, use a 47 pF capacitor in parallel with the load to prevent ringing. Otherwise, use a larger load, such as 10 kΩ. 2 Differential and common-mode input impedance can be calculated from the pin impedance: ZDIFF = 2(ZPIN); ZCM = ZPIN/2. 3 The AD8220 can operate up to a diode drop below the negative supply but the bias current increases sharply. The input voltage range reflects the maximum allowable voltage where the input bias current is within the specification. 4 At this supply voltage, ensure that the input common-mode voltage is within the input voltage range specification. V + = 5 V, V− = 0 V, V = 2.5 V, T = 25°C, T = −40°C to +85°C for A and B grades. T = −40°C to +125°C for W grade, G = 1, S S REF A OPR OPR R = 2 kΩ1, unless otherwise noted. L Table 2. A Grade B Grade W Grade Parameter Test Conditions Min Typ Max Min Typ Max Min Typ Max Unit COMMON-MODE REJECTION T for A, B grades, A RATIO (CMRR) T for W grade OPR CMRR DC to 60 Hz with V = 0 to 2.5 V CM 1 kΩ Source Imbalance G = 1 78 86 77 dB G = 10 94 100 92 dB G = 100 94 100 92 dB G = 1000 94 100 92 dB CMRR at 5 kHz V = 0 to 2.5 V CM G = 1 74 80 72 dB G = 10 84 90 80 dB G = 100 84 90 80 dB G = 1000 84 90 80 dB NOISE RTI noise = √(e 2 + ni (e /G)2), T no A Voltage Noise, 1 kHz V = ±2.5 V S Input Voltage Noise, e V +, V − = 0 V, V = 14 14 17 14 nV/√Hz ni IN IN REF 0 V Output Voltage Noise, e V +, V − = 0 V, V = 90 90 100 90 nV/√Hz no IN IN REF 0 V RTI, 0.1 Hz to 10 Hz G = 1 5 5 5 μV p-p G = 1000 0.8 0.8 0.8 μV p-p Current Noise f = 1 kHz 1 1 1 fA/√Hz VOLTAGE OFFSET V = V + V /G OS OSI OSO Input Offset, V T −300 +300 −200 +200 −300 +300 μV OSI A Average TC T −10 +10 −5 +5 −10 10 μV/°C OPR Output Offset, V T −800 +800 −600 +600 −800 +800 μV OSO A Average TC T −10 +10 −5 +5 −10 +10 μV/°C OPR Offset RTI vs. Supply (PSR) T for A, B grades, A T for W grade OPR G = 1 86 86 80 dB G = 10 96 100 92 dB G = 100 96 100 92 dB G = 1000 96 100 92 dB Rev. B | Page 5 of 28

AD8220 A Grade B Grade W Grade Parameter Test Conditions Min Typ Max Min Typ Max Min Typ Max Unit INPUT CURRENT Input Bias Current T 25 10 25 pA A Over Temperature T 0.3 0.3 100 nA OPR Input Offset Current T 2 0.6 2 pA A Over Temperature T 0.005 0.005 10 nA OPR DYNAMIC RESPONSE T A Small Signal Bandwidth, −3 dB G = 1 1500 1500 1500 kHz G = 10 800 800 800 kHz G = 100 120 120 120 kHz G = 1000 14 14 14 kHz Settling Time 0.01% T A G = 1 3 V step 2.5 2.5 2.5 μs G = 10 4 V step 2.5 2.5 2.5 μs G = 100 4 V step 7.5 7.5 7.5 μs G = 1000 4 V step 30 30 30 μs Settling Time 0.001% T A G = 1 3 V step 3.5 3.5 3.5 μs G = 10 4 V step 3.5 3.5 3.5 μs G = 100 4 V step 8.5 8.5 8.5 μs G = 1000 4 V step 37 37 37 μs Slew Rate G = 1 to 100 TA 2 2 2 V/μs GAIN G = 1 + (49.4 kΩ/R ), G T for A, B grades, A T for W grade OPR Gain Range 1 1000 1 1000 1 1000 V/V Gain Error V = 0.3 V to 2.9 V for OUT G = 1, V = 0.3 V to OUT 3.8 V for G > 1 G = 1 −0.06 +0.06 −0.04 +0.04 −0.1 +0.1 % G = 10 −0.3 +0.3 −0.2 +0.2 −0.8 +0.8 % G = 100 −0.3 +0.3 −0.2 +0.2 −0.8 +0.8 % G = 1000 −0.3 +0.3 −0.2 +0.2 −0.8 +0.8 % Nonlinearity V = 0.3 V to 2.9 V for OUT G = 1, V = 0.3 V to OUT 3.8 V for G > 1, T A G = 1 R = 10 kΩ 35 50 35 50 50 ppm L G = 10 R = 10 kΩ 35 50 35 50 50 ppm L G = 100 R = 10 kΩ 50 75 50 75 75 ppm L G = 1000 R = 10 kΩ 650 750 650 750 750 ppm L G = 1 RL = 2 kΩ 35 50 35 50 50 ppm G = 10 RL = 2 kΩ 35 50 35 50 50 ppm G = 100 RL = 2 kΩ 50 75 50 75 75 ppm Gain vs. Temperature G = 1 3 10 2 5 3 10 ppm/°C G > 10 −50 −50 −50 ppm/°C INPUT Impedance (Pin to T 104||6 104||6 104||6 GΩ||pF A Ground)2 Input Voltage Range3 T −0.1 +V − −0.1 +V − V A S S 2 2 Over Temperature T −0.1 +V − −0.1 +V − −0.1 +V − V OPR S S S 2.1 2.1 2.2 Rev. B | Page 6 of 28

AD8220 A Grade B Grade W Grade Parameter Test Conditions Min Typ Max Min Typ Max Min Typ Max Unit OUTPUT Output Swing R = 10 kΩ 0.15 4.85 0.15 4.85 0.15 4.85 V L Over Temperature T 0.2 4.80 0.2 4.80 0.3 4.70 V OPR Short-Circuit Current 15 15 15 mA REFERENCE INPUT TA R 40 40 40 kΩ IN IIN VIN+, VIN− = 0 V 70 70 70 μA Voltage Range −V +V −V +V −V +V V S S S S S S Gain to Output TA 1 ± 1 ± 1 ± V/V 0.0001 0.0001 0.0001 POWER SUPPLY Operating Range 4.5 36 4.5 36 4.5 36 V Quiescent Current T 750 750 750 μA A Over Temperature T 850 850 1000 μA OPR TEMPERATURE RANGE T , For Specified T −40 +85 −40 +85 −40 +125 °C OPR OPR Performance 1 When the output sinks more than 4 mA, use a 47 pF capacitor in parallel with the load to prevent ringing. Otherwise, use a larger load, such as 10 kΩ. 2 Differential and common-mode impedance can be calculated from the pin impedance: ZDIFF = 2(ZPIN); ZCM = ZPIN/2. 3 The AD8220 can operate up to a diode drop below the negative supply but the bias current increases sharply. The input voltage range reflects the maximum allowable voltage where the input bias current is within the specification. Rev. B | Page 7 of 28

AD8220 ABSOLUTE MAXIMUM RATINGS Table 3. Stresses above those listed under Absolute Maximum Ratings Parameter Rating may cause permanent damage to the device. This is a stress Supply Voltage ±18 V rating only; functional operation of the device at these or any Power Dissipation See Figure 3 other conditions above those indicated in the operational Output Short-Circuit Current Indefinite1 section of this specification is not implied. Exposure to absolute Input Voltage (Common Mode) ±Vs maximum rating conditions for extended periods may affect Differential Input Voltage ±Vs device reliability. Storage Temperature Range −65°C to +125°C Figure 3 shows the maximum safe power dissipation in the Operating Temperature Range2 −40°C to +125°C package vs. the ambient temperature for the MSOP on a 4-layer Lead Temperature (Soldering 10 sec) 300°C JEDEC standard board. θ values are approximations. JA Junction Temperature 140°C θ (4-Layer JEDEC Standard Board) 135°C/W JA 2.00 Package Glass Transition Temperature 140°C ESD (Human Body Model) 4 kV 1.75 W) EESSDD ((CMhaacrhgien eD Mevoicdee lM) odel) 10 .4kV k V TION ( 1.50 A 1 Assumes the load is referenced to midsupply. SSIP 1.25 2 Temperature for specified performance is −40°C to +85°C. For performance DI R 1.00 to 125°C, see the Typical Performance Characteristics section. E W PO 0.75 M U M 0.50 XI A M 0.250 03579-045 –40 –20 0 20 40 60 80 100 120 AMBIENTTEMPERATURE(°C) Figure 3. Maximum Power Dissipation vs. Ambient Temperature ESD CAUTION Rev. B | Page 8 of 28

AD8220 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS AD8220 –IN 1 8 +VS RG 2 7 VOUT RG 3 6 REF +IN 4 5 –VS (NToOtPtoVSIEcaWle) 03579-005 Figure 4. Pin Configuration Table 4. Pin Function Descriptions Pin No. Mnemonic Description 1 −IN Negative Input Terminal (True Differential Input) 2, 3 R Gain Setting Terminals (Place Resistor Across the R Pins) G G 4 +IN Positive Input Terminal (True Differential Input) 5 −V Negative Power Supply Terminal S 6 REF Reference Voltage Terminal (Drive This Terminal with a Low Impedance Voltage Source to Level-Shift the Output) 7 V Output Terminal OUT 8 +V Positive Power Supply Terminal S Rev. B | Page 9 of 28

AD8220 TYPICAL PERFORMANCE CHARACTERISTICS 1200 1600 1400 1000 1200 NUMBER OF UNITS 864000000 NUMBER OF UNITS 1086000000 400 200 0 –40 –20 0 20 40 03579-060 2000 0 1 2 3 4 5 03579-063 CMRR(µV/V) IBIAS(pA) Figure 5. Typical Distribution of CMRR (G = 1) Figure 8. Typical Distribution of Input Bias Current 1200 1000 1000 TS 800 TS 800 NI NI U U F F R O 600 R O 600 E E B B M M NU 400 NU 400 200 200 0 03579-061 0 03579-064 –200 –100 0 100 200 –0.2 –0.1 0 0.1 0.2 VOSI (µV) IOS(pA) Figure 6. Typical Distribution of Input Offset Voltage Figure 9. Typical Distribution of Input Offset Current 1000 1000 Hz) GAIN = 100 BANDWIDTH ROLL-OFF S 800 nV/ 100 NIT TI ( GAIN = 1 U R R OF 600 OISE GAIN = 10 E N B E UM 400 AG 10 GAIN = 100/GAIN = 1000 N T L O V GAIN = 1000 BANDWIDTH ROLL-OFF 200 0 03579-062 1 03579-042 –1000 –500 0 500 1000 1 10 100 1k 10k 100k VOSO (µV) FREQUENCY (Hz) Figure 7. Typical Distribution of Output Offset Voltage Figure 10. Voltage Spectral Density vs. Frequency Rev. B | Page 10 of 28

AD8220 XX 150 130 GAIN=1000 GAIN=100 BANDWIDTH 110 LIMITED X) dB) 90 GAIN=10 X ( R ( X R X S 70 GAIN=1 P 50 30 XX 5µV/DIV 1s/DIV 03579-024 10 03579-035 XX XX 1 10 100 1k 10k 100k 1M XXX(X) FREQUENCY(Hz) Figure 11. 0.1 Hz to 10 Hz RTI Voltage Noise (G = 1) Figure 14. Positive PSRR vs. Frequency, RTI XX 150 130 110 GAIN=1000 X (X) R (dB) 90 GAIN=1 X R X S 70 P GAIN=10 50 GAIN=100 30 XX 1µV/DIV 1s/DIV 03579-025 10 03579-040 XX XX 1 10 100 1k 10k 100k 1M XXX(X) FREQUENCY(Hz) Figure 12. 0.1 Hz to 10 Hz RTI Voltage Noise (G = 1000) Figure 15. Negative PSRR vs. Frequency, RTI 8 0.3 INPUT OFFSET 7 9 CURRENT±15 INPUT OFFSET 0.2 CURRENT±5 A) V) 65 RENT (pA) 7 00.1 RRENT (p Δ V (µOSI 43 UT BIAS CUR 35 –5.1–V15.1V ––00..21 T OFFSET CU 2 INP INPUTBIAS CIUNRPRUETNBTIA±S15 –0.3 NPU 1 CURRENT±5 I 01 03579-009 –1 ––00..54 0.1 1 TIM1E0(s) 100 1k –16 –12 –8COMM–O4N-MOD0EVOLT4AGE(V)8 12 16 03579-050 Figure 13. Change in Input Offset Voltage vs. Warmup Time Figure 16. Input Bias Current and Input Offset Current vs. Common-Mode Voltage Rev. B | Page 11 of 28

AD8220 160 10n 140 GAIN=1000 NT (A) 1n IBIAS 120 E RR 100p B) U d BIAS C 10p CMRR ( 100 GAIN=100 BALNIMDWITEIDDTH UT IOS 80 GAIN=10 GAIN=1 P 1p N I 0.1p 60 –50 –25 0 25 50 75 100 125 15003579-059 401 10 100 1k 10k 100k03579-051 TEMPERATURE(°C) FREQUENCY(Hz) Figure 17. Input Bias Current and Offset Current vs. Temperature, Figure 20. CMRR vs. Frequency, 1 kΩ Source Imbalance VS = ±15 V, VREF = 0 V 10 8 10n 6 1n 4 CURRENT (A) 10100pp IBIAS IOS Δ CMRR (μV/V) –220 1p –4 –6 0.1p –50 –25 0 25 50 75 100 125 15003579-065 –1–08–50 –30 –10 10 30 50 70 90 110 13003579-034 TEMPERATURE(°C) TEMPERATURE(°C) Figure 18. Input Bias Current and Offset Current vs. Temperature, Figure 21. Change in CMRR vs. Temperature, G = 1 VS = +5 V, VREF = 2.5 V 160 70 60 GAIN=1000 GAIN=1000 140 50 40 120 GAIN=100 GAIN=100 30 MRR (dB) 100 GAIN=10 BALNIMDIWTEIDDTH AIN (dB) 2100 GAIN=10 C GAIN=1 G 0 80 GAIN=1 –10 60 –20 40 03579-023 ––4300 03579-022 10 100 1k 10k 100k 100 1k 10k 100k 1M 10M FREQUENCY(Hz) FREQUENCY(Hz) Figure 19. CMRR vs. Frequency Figure 22. Gain vs. Frequency Rev. B | Page 12 of 28

AD8220 m/DIV) pm/DIV) RLOAD=2kΩ p p p 0 XXX ARITY (5 RLOAD = 2kΩ XXX RITY (50 RLOAD=10kΩ NLINE LINEA O N N RLOAD = 10kΩ NO VS = ±15V 03579-026 VS=±15V 03579-029 –10 –8 –6 –4 –2 0 2 4 6 8 10 –10 –8 –6 –4 –2 0 2 4 6 8 10 OUTPUT VOLTAGE (V) OUTPUTVOLTAGE(V) Figure 23. Gain Nonlinearity, G = 1 Figure 26. Gain Nonlinearity, G = 1000 18 +13V E (V) 12 ±15VSUPPLIES G V) A ppm/DI RLOAD = 2kΩ E VOLT 6 –14.8V,+5.5V +3V +14.9V,+5.5V XXX RITY (5 N-MOD 0 –4.8V,+0.6V ±5VSUPPLIES +4.95V,+0.6V NONLINEA RLOAD = 10kΩ UT COMMO –6 –14.8V–4,.–88V.3,V–3.3V –5.3V +4.95+V1,4–.93V.3,V–8.3V NP –12 VS = ±15V 03579-027 I –18 –15.3V 03579-037 –10 –8 –6 –4 –2 0 2 4 6 8 10 –16 –12 –8 –4 0 4 8 12 16 OUTPUT VOLTAGE (V) OUTPUTVOLTAGE(V) Figure 24. Gain Nonlinearity, G = 10 Figure 27. Input Common-Mode Voltage Range vs. Output Voltage, G = 1, VREF = 0 V 4 E (V) 3 +3V V) AG DI T m/ OL XXX EARITY (50pp RLOAD=10kΩ RLOAD=2kΩ MON-MODE V 21 +0.1V,+1.7+V5VSVIRNEGFL=E+S2.U5PVPL+Y4.,9V,+1.7V LIN OM +0.1V,+0.5V +4.9V,+0.5V N C NO UT 0 P VS=±15V 03579-028 IN –1 –0.3V 03579-036 –10 –8 –6 –4 –2 0 2 4 6 8 10 –1 0 1 2 3 4 5 6 OUTPUTVOLTAGE(V) OUTPUTVOLTAGE(V) Figure 25. Gain Nonlinearity, G = 100 Figure 28. Input Common-Mode Voltage Range vs. Output Voltage, G = 1, VS = +5 V, VREF = 2.5 V Rev. B | Page 13 of 28

AD8220 18 VS+ +13V –1 MODE VOLTAGE (V) 1260 –14.9–V±4,1.+95V5V.,4S+VU0.P4VPLIES +3V +4.9+V1,4+.09.V5,V+5.4V TAGE SWING (V)SUPPLY VOLTAGE –––234 –40°C+25°C ++18255°°CC NPUT COMMON- –1–26 –14.8–V4,.–99VV,–4.1V ±5VS–U5.P3PVLIES +4.9V,+–144..19VV,–9V OUTPUT VOLREFERRED TO +++432 +125°C +85°C +25°C –40°C I –18 –15.3V 03579-039 V+S–1 03579-053 –16 –12 –8 –4 0 4 8 12 16 2 4 6 8 10 12 14 16 18 OUTPUTVOLTAGE(V) DUAL SUPPLY VOLTAGE (±V) Figure 29. Input Common-Mode Voltage Range vs. Output Voltage, Figure 32. Output Voltage Swing vs. Supply Voltage, RLOAD = 2 kΩ, G = 10, G = 100, VREF = 0 V VREF = 0 V 4 VS+ –0.2 V) +3V +125°C GE ( 3 V)AGE –0.4 +85°C +25°C –40°C TA G (LT L NO DE VO 2 E SWIPLY V O +0.1V,+1.7V +4.9V,+1.7V GP M AU T COMMON- 1 +5VSVIRNEGFL=E+S2.U5PVPLY, UTPUT VOLTERRED TO S PU 0 OEF +0.4 +125°C +85°C +25°C –40°C N R I –1–1 0 +0.1V,1–0.5V 2 –0.3V 3 +4.94V,–0.5V5 603579-038 +V0S.2–2 4 6 8 10 12 14 16 1803579-054 OUTPUTVOLTAGE(V) DUAL SUPPLY VOLTAGE (±V) Figure 30. Input Common-Mode Voltage Range vs. Output Voltage, Figure 33. Output Voltage Swing vs. Supply Voltage, RLOAD = 10 kΩ, G = 10, G = 100, VS = +5 V, VREF = 2.5 V VREF = 0 V VS+ 15 –1 –40°C +125°C 10 –40°C MIT (V) –2 +25°C WING (V) 5 +25°C +85°C E LI NOTES +85°C E S +125°C AG 1. THE AD8220 CAN OPERATE UP TO A VBE BELOW AG 0 OLT TWHILEL N IENGCARTEIAVSEE S SUHPAPRLPYL, YB.UT THE BIAS CURRENT OLT V V UT UT –5 +125°C INP +1 –40°C +25°C +85°C +125°C OUTP +85°C VS–1– 03579-052 ––1150 +25°C–40°C 03579-055 2 4 6 8 10 12 14 16 18 100 1k 10k SUPPLY VOLTAGE (V) RLOAD (Ω) Figure 31. Input Voltage Limit vs. Supply Voltage, G = 1, VREF =0 V Figure 34. Output Voltage Swing vs. Load Resistance VS = ±15 V, VREF = 0 V Rev. B | Page 14 of 28

AD8220 5 XX –40°C 47pF +85°C NOLOAD 100pF V) 4 +25°C G ( +125°C N WI S 3 GE X) OLTA XXX ( V 2 T U P T U O 1 +125°C +25°C +85°C 0 –40°C 03579-056 XX 20mV/DIV 5µs/DIV 03579-018 100 1k 10k XX XX RLOAD (Ω) XXX(X) Figure 35. Output Voltage Swing vs. Load Resistance VS = +5 V, VREF = 2.5 V Figure 38. Small Signal Pulse Response for Various Capacitive Loads, VS = ±15 V, VREF = 0 V VS+ XX –1 –40°C 47pF S NOLOAD 100pF G (V)TAGE –2 +125°C +85°C +25°C WINVOL –3 SY –4 VOLTAGE TO SUPPL +4 XXX (X) T D PURE +3 TR UE OEF +2 +125°C +85°C +25°C R V+S–1 –40°C 03579-057 XX 20mV/DIV 5µs/DIV 03579-019 0 2 4 6 8 10 12 14 16 XX XX IOUT(mA) XXX(X) Figure 36. Output Voltage Swing vs. Output Current, VS = ±15 V, VREF = 0 V Figure 39. Small Signal Pulse Response for Various Capacitive Loads, VS = 5 V, VREF = 2.5 V VS+ 35 GAIN=10,100,1000 WING (V)VOLTAGES –1 +125°C +85°C +25°C NG (V p-p) 3205 GAIN=1 SY –2 WI VOLTAGE TO SUPPL +2 OLTAGE S 2105 T D V OUTPUREFERRE +1 +125°C +85°C +25°C OUTPUT 105 VS– –40°C 03579-058 0 03579-021 0 2 4 6 8 10 12 14 16 100 1k 10k 100k 1M 10M IOUT(mA) FREQUENCY(Hz) Figure 37. Output Voltage Swing vs. Output Current, VS = 5 V, VREF = 2.5 V Figure 40. Output Voltage Swing vs. Large Signal Frequency Response Rev. B | Page 15 of 28

AD8220 XX XX 5V/DIV 5V/DIV X) X) X ( X ( X X X X 5µsTO0.01% 58μsTO0.01% 0.002%/DIV 6µsTO0.001% 0.002%/DIV 74μsTO0.001% XX 20µs/DIV 03579-046 XX 200µs/DIV 03579-049 XX XX XX XX XXX(X) XXX(X) Figure 41. Large Signal Pulse Response and Settle Time, G = 1, Figure 44. Large Signal Pulse Response and Settle Time, G = 1000, RLOAD = 10 kΩ, VS = ±15 V, VREF = 0 V RLOAD = 10 kΩ, VS = ±15 V, VREF = 0 V XX 5V/DIV XX (X) XXX X 4.3μsTO0.01% 0.002%/DIV 4.6μsTO0.001% 20mV/DIV XX 20µs/DIV 03579-047 03579-016 XX XX 4µs/DIV XXX(X) XXX Figure 42. Large Signal Pulse Response and Settle Time, G = 10, Figure 45. Small Signal Pulse Response, G = 1, RLOAD = 2 kΩ, CLOAD = 100 pF, RLOAD = 10 kΩ, VS = ±15 V, VREF = 0 V VS = ±15 V, VREF = 0 V XX 5V/DIV XX (X) XXX X 8.1μsTO0.01% 0.002%/DIV 9.6μsTO0.001% 20mV/DIV XX 20µs/DIV 03579-048 03579-014 XX XX 4µs/DIV XXX(X) XXX Figure 43. Large Signal Pulse Response and Settle Time, G = 100, Figure 46. Small Signal Pulse Response, G = 10, RLOAD = 2 kΩ, CLOAD = 100 pF, RLOAD = 10 kΩ, VS = ±15 V, VREF = 0 V VS = ±15 V, VREF = 0 V Rev. B | Page 16 of 28

AD8220 X X X X X X 20mV/DIV 20mV/DIV 03579-012 03579-015 4µs/DIV 4µs/DIV XXX XXX Figure 47 Small Signal Pulse Response, G = 100, RLOAD = 2 kΩ, CLOAD = 100 pF, Figure 50. Small Signal Pulse Response, G = 10, RLOAD = 2 kΩ, CLOAD = 100 pF, VS = ±15 V, VREF =0 V VS = 5 V, VREF = 2.5 V X X X X X X 20mV/DIV 20mV/DIV 03579-010 03579-013 40µs/DIV 4µs/DIV XXX XXX Figure 48. Small Signal Pulse Response, G = 1000, RLOAD = 2 kΩ, Figure 51. Small Signal Pulse Response, G = 100, RLOAD = 2 kΩ, CLOAD = 100 pF, CLOAD = 100 pF, VS = ±15 V, VREF = 0 V VS = 5 V, VREF = 2.5 V X X X X X X 20mV/DIV 20mV/DIV 03579-017 03579-011 4µs/DIV 40µs/DIV XXX XXX Figure 49. Small Signal Pulse Response, G = 1, RLOAD = 2 kΩ, CLOAD = 100 pF, Figure 52. Small Signal Pulse Response, G = 1000, RLOAD = 2 kΩ, VS = 5 V, VREF = 2.5 V CLOAD = 100 pF, VS = 5 V, VREF = 2.5 V Rev. B | Page 17 of 28

AD8220 15 100 E (µs) 10 E (µs) SETTLEDTO0.001% M SETTLEDTO0.001% M TI TI G G 10 N N LI LI SETTLEDTO0.01% T T T T E 5 SETTLEDTO0.01% E S S 0 03579-043 1 03579-041 0 5 10 15 20 1 10 100 1000 OUTPUTVOLTAGESTEPSIZE(V) GAIN(V/V) Figure 53. Settling Time vs. Output Voltage Step Size (G = 1) ±15 V, VREF = 0 V Figure 54. Settling Time vs. Gain for a 10 V Step, VS = ±15 V, VREF = 0 V Rev. B | Page 18 of 28

AD8220 THEORY OF OPERATION +VS +VS +VS +VS NODE A RG NODE B 20kΩ R2 NODE F R1 24.7kΩ +VS 24.7kΩ –VS –VS 20kΩ OUTPUT A3 20kΩ +VS +VS NODE C NODE D NODE E +VS –VS +IN J1 Q1 C1 C2 Q2 J2 –IN 20kΩ REF –VS VPINCH A1 A2 VPINCH –VS –VS I VB I –VS 03579-006 Figure 55. Simplified Schematic The AD8220 is a JFET input, monolithic instrumentation amplifier The AD8220 has extremely low load-induced nonlinearity. All based on the classic 3-op amp topology (see Figure 55). Input amplifiers that comprise the AD8220 have rail-to-rail output Transistor J1 and Input Transistor J2 are biased at a fixed current so capability for enhanced dynamic range. The input of the AD8220 that any input signal forces the output voltages of A1 and A2 to can amplify signals with wide common-mode voltages even change accordingly; the input signal creates a current through R slightly lower than the negative supply rail. The AD8220 operates G that flows in R1 and R2 such that the outputs of A1 and A2 provide over a wide supply voltage range. It can operate from either a the correct, gained signal. Topologically, J1, A1, and R1 and J2, A2, single +4.5 V to +36 V supply or a dual ±2.25 V to ±18 V. The and R2 can be viewed as precision current feedback amplifiers that transfer function of the AD8220 is have a gain bandwidth of 1.5 MHz. The common-mode voltage 49.4kΩ and amplified differential signal from A1 and A2 are applied to a G1 R difference amplifier that rejects the common-mode voltage but G amplifies the differential signal. The difference amplifier employs Users can easily and accurately set the gain using a single, 20 kΩ laser-trimmed resistors that result in an in-amp with gain standard resistor. Because the input amplifiers employ a current error less than 0.04%. New trim techniques were developed to feedback architecture, the AD8220 gain-bandwidth product ensure that CMRR exceeds 86 dB (G = 1). increases with gain, resulting in a system that does not suffer as much bandwidth loss as voltage feedback architectures at higher Using JFET transistors, the AD8220 offers an extremely high gains. A unique pinout enables the AD8220 to meet a CMRR input impedance, extremely low bias currents of 10 pA specification of 80 dB through 5 kHz (G = 1). The balanced maximum, a low offset current of 0.6 pA maximum, and no pinout, shown in Figure 56, reduces parasitics that adversely input bias current noise. In addition, input offset is less than affect CMRR performance. In addition, the new pinout 125 μV and drift is less than 5 μV/°C. Ease of use and robustness simplifies board layout because associated traces are grouped were considered. A common problem for instrumentation amplifiers is that at high gains, when the input is overdriven,1 together. For example, the gain setting resistor pins are adjacent to the inputs, and the reference pin is next to the output. an excessive milliampere input bias current can result and the output can undergo phase reversal. The AD8220 has none of AD8220 these problems; its input bias current is limited to less than –IN 1 8 +VS 10 μA, and the output does not phase reverse under overdrive RG 2 7 VOUT fault conditions. RG 3 6 REF 1 Overdriving the input at high gains refers to when the input signal is within +IN 4 5 –VS teohxveae mrsduprpilvepi,ln yag tv taoh lgteaa iginnep sou fbt 1su 0ts 0itnh, cdeer aitvmhinepg ali mtfiheper l caifamienrpn cloiaftine onru owttpi touhut 1ttp0hu eVt g o1a0ni0n ± eV1d.5 s Vig cnoanl.s Ftiotur tes (NToOtPtoVSIEcaWle) 03579-005 Figure 56. Pin Configuration Rev. B | Page 19 of 28

AD8220 GAIN SELECTION gain setting resistor to the R pins should be kept as short as G possible to minimize parasitic inductance. An example layout is Placing a resistor across the R terminals sets the AD8220 gain, G shown in Figure 57 and Figure 58. To ensure the most accurate which can be calculated by referring to Table 5 or by using the output, the trace from the REF pin should either be connected to gain equation the AD8220 local ground (see Figure 59) or connected to a 49.4kΩ voltage that is referenced to the AD8220 local ground. RG G1 Common-Mode Rejection Ratio (CMRR) Table 5. Gains Achieved Using 1% Resistors The AD8220 has high CMRR over frequency giving it greater 1% Standard Table Value of RG (Ω) Calculated Gain immunity to disturbances, such as line noise and its associated 49.9 k 1.990 harmonics, in contrast to typical in-amps whose CMRR falls off 12.4 k 4.984 around 200 Hz. These in-amps often need common-mode 5.49 k 9.998 filters at the inputs to compensate for this shortcoming. The 2.61 k 19.93 AD8220 is able to reject CMRR over a greater frequency range, 1.00 k 50.40 reducing the need for input common-mode filtering. 499 100.0 A well-implemented layout helps to maintain the high CMRR 249 199.4 over frequency of the AD8220. Input source impedance and 100 495.0 capacitance should be closely matched. In addition, source 49.9 991.0 resistance and capacitance should be placed as close to the inputs as possible. The AD8220 defaults to G = 1 when no gain resistor is used. Grounding Gain accuracy is determined by the absolute tolerance of R . G The TC of the external gain resistor increases the gain drift of The output voltage of the AD8220 is developed with respect to the instrumentation amplifier. Gain error and gain drift are kept the potential on the reference terminal. Care should be taken to to a minimum when the gain resistor is not used. tie REF to the appropriate local ground (see Figure 59). LAYOUT In mixed-signal environments, low level analog signals need to be isolated from the noisy digital environment. Many ADCs Careful board layout maximizes system performance. In have separate analog and digital ground pins. Although it is applications that need to take advantage of the low input bias convenient to tie both grounds to a single ground plane, the current of the AD8220, avoid placing metal under the input path current traveling through the ground wires and PC board can to minimize leakage current. To maintain high CMRR over cause a large error. Therefore, separate analog and digital frequency, lay out the input traces symmetrically and lay out the ground returns should be used to minimize the current flow traces of the R resistor symmetrically. Ensure that the traces G from sensitive points to the system ground. maintain resistive and capacitive balance; this holds for additional PCB metal layers under the input and R pins. Traces from the G 03579-101 03579-102 Figure 57. Example Layout—Top Layer of the AD8220 Evaluation Board Figure 58. Example Layout—Bottom Layer of the AD8220 Evaluation Board Rev. B | Page 20 of 28

AD8220 REFERENCE TERMINAL INPUT BIAS CURRENT RETURN PATH The reference terminal, REF, is at one end of a 20 kΩ resistor The AD8220 input bias current is extremely small at less than (see Figure 55). The output of the instrumentation amplifier is 10 pA. Nonetheless, the input bias current must have a return referenced to the voltage on the REF terminal; this is useful path to common. When the source, such as a transformer, when the output signal needs to be offset to voltages other than cannot provide a return current path, one should be created common. For example, a voltage source can be tied to the REF (see Figure 60). pin to level-shift the output so that the AD8220 can interface +VS with an ADC. The allowable reference voltage range is a function of the gain, common-mode input, and supply voltages. The REF pin should not exceed either +V or −V by more than 0.5 V. S S For best performance, especially in cases where the output is AD8220 not measured with respect to the REF terminal, source impedance REF to the REF terminal should be kept low, because parasitic resistance can adversely affect CMRR and gain accuracy. POWER SUPPLY REGULATION AND BYPASSING –VS The AD8220 has high PSRR. However, for optimal TRANSFORMER performance, a stable dc voltage should be used to power the instrumentation amplifier. Noise on the supply pins can adversely affect performance. As in all linear circuits, bypass +VS capacitors must be used to decouple the amplifier. C A 0.1 μF capacitor should be placed close to each supply pin. A 10 μF tantalum capacitor can be used further away from the 1 R part (see Figure 59). In most cases, it can be shared by other fHIGH-PASS=2πRC AD8220 precision integrated circuits. C REF +VS R 0.1µF 10µF AC-COUPL–EVDS 03579-002 +IN Figure 60. Creating an IBIAS Path INPUT PROTECTION AD8220 VOUT All terminals of the AD8220 are protected against ESD. LOAD (ESD protection is guaranteed to 4 kV, human body model.) In –IN REF addition, the input structure allows for dc overload conditions a diode drop above the positive supply and a diode drop below the negative supply. Voltages beyond a diode drop of the supplies 0.1µF 10µF cause the ESD diodes to conduct and enable current to flow –VS 03579-001 tuhsreodu ignh s tehriee ds iwoditeh. eTahcehr eoffo trhee, ainnp euxttse rton alilm reist icstuorrr esnhto fuolrd be Figure 59. Supply Decoupling, REF and Output Referred to Ground voltages above +Vs. In either scenario, the AD8220 safely handles a continuous 6 mA current at room temperature. For applications where the AD8220 encounters extreme overload voltages, as in cardiac defibrillators, external series resistors and low leakage diode clamps, such as BAV199Ls, FJH1100s, or SP720s, should be used. Rev. B | Page 21 of 28

AD8220 RF INTERFERENCE +15V RF rectification is often a problem in applications where there are 0.1µF 10µF large RF signals. The problem appears as a small dc offset voltage. The AD8220 by its nature has a 5 pF gate capacitance, C , at its CC 1nF G inputs. Matched series resistors form a natural low-pass filter that R +IN 4.02kΩ reduces rectification at high frequency (see Figure 61). The VOUT relationship between external, matched series resistors and the CD 10nF AD8220 R REF internal gate capacitance is expressed as follows: 4.02kΩ –IN FilterFreq  1 CC 1nF DIFF 2πRC G 0.1µF 10µF FilterFreqCM 2πR1C –15V 03579-003 G Figure 62. RFI Suppression +15V COMMON-MODE INPUT VOLTAGE RANGE The common-mode input voltage range is a function of the 0.1µF 10µF input range and the outputs of Internal Amplifier A1, Internal Amplifier A2, and Internal Amplifier A3, the reference voltage, and the gain. Figure 27 to Figure 30 show common-mode voltage ranges for various supply voltages and gains. R +IN CG DRIVING AN ADC –VS AD8220 VOUT An instrumentation amplifier is often used in front of an ADC R to provide CMRR and additional conditioning, such as a voltage CG –IN –VS REF level shift and gain (see Figure 63). In this example, a 2.7 nF capacitor and a 1 kΩ resistor create an antialiasing filter for the AD7685. The 2.7 nF capacitor also serves to store and deliver the necessary charge to the switched capacitor input of the 0.1µF 10µF –15V 03579-030 AloDadC f.r Tomhe t1h ek Ωam sperliifeise rr.e Hsisotwore vreerd, ulacregse t hsoeu brucred iemnp oefd tahnec 2e. 7in n F Figure 61. RFI Filtering Without External Capacitors front of the ADC can degrade THD. The example shown in Figure 63 is for sub-60 kHz applications. For higher bandwidth applications where THD is important, To eliminate high frequency common-mode signals while using the series resistor needs to be small. At worst, a small series smaller source resistors, a low-pass RC network can be placed at resistor can load the AD8220, potentially causing the output to the input of the instrumentation amplifier (see Figure 62). The overshoot or ring. In such cases, a buffer amplifier, such as the filter limits the input signal bandwidth according to the following AD8615, should be used after the AD8220 to drive the ADC. relationship: +5V 1 FilterFreq  DIFF 2πR(2CDCCCG) 10µF 0.1µF ADR435 1 +5V 4.7µF FilterFreq  CM 2πR(CCCG) +IN 1kΩ Mismatched CC capacitors result in mismatched low-pass filters. ±50mV 1.07kΩ AD8220 AD7685 REF 2.7nF The imbalance causes the AD8220 to treat what would have –IN been a common-mode signal as a differential signal. To reduce +2.5V CthDe gerfefeactet ro tfh manis 1m0a tticmheeds CexCt.e Trnhaisl sCeCt sc tahpea cdiitfofersr,e snetlieacl tf ialt vear lue of 03579-033 Figure 63. Driving an ADC in a Low Frequency Application frequency lower than the common-mode frequency. Rev. B | Page 22 of 28

AD8220 APPLICATIONS INFORMATION AC-COUPLED INSTRUMENTATION AMPLIFIER DIFFERENTIAL OUTPUT Measuring small signals that are in the noise or offset of the In certain applications, it is necessary to create a differential amplifier can be a challenge. Figure 64 shows a circuit that signal. New high resolution ADCs often require a differential can improve the resolution of small ac signals. The large gain input. In other cases, transmission over a long distance can reduces the referred input noise of the amplifier to 14 nV/√Hz. require differential processing for better immunity to Therefore, smaller signals can be measured because the noise interference. floor is lower. DC offsets that would have been gained by 100 Figure 65 shows how to configure the AD8220 to output a are eliminated from the AD8220 output by the integrator differential signal. An OP1177 op amp is used to create a feedback network. differential voltage. Errors from the op amp are common to At low frequencies, the OP1177 forces the AD8220 output to both outputs and are thus common mode. Likewise, errors from 0 V. Once a signal exceeds f , the AD8220 outputs the using mismatched resistors cause a common-mode dc offset HIGH-PASS amplified input signal. error. Such errors are rejected in differential signal processing by differential input ADCs or instrumentation amplifiers. +VS When using this circuit to drive a differential ADC, V can be REF 0.1µF set using a resistor divider from the reference of the ADC to make the output ratiometric with the ADC as shown in Figure 66. +IN fHIGH-PASS=2π1RC R AD8220 499Ω REF R 15.8kΩ –IN C 1µF +VS 0.1µF 0.1µF –VS OP1177 +VS –VS 0.1µF VREF 10µF 10µF –VS 03579-004 Figure 64. AC-Coupled Circuit Rev. B | Page 23 of 28

AD8220 +15V AMPLITUDE 0.1µF +5V –5V TIME +IN VOUTA=+VIN+VREF 2 AD8220 ±5V AMPLITUDE REF +5.0V –IN 4.99kΩ +2.5V +0V TIME 0.1µF +5V –15V 4.99kΩ –15V OP1177 +15V VRAEMFPL++IT25U..50DVVE 0.1µF 0.1µF 2.5V +0V 10µF TIME VOUTB=–2VIN+VREF 03579-008 Figure 65. Differential Output with Level Shift +15V 0.1µF TIME +IN VOUTA=+VIN+VREF 2 ±5V AD8220 TO0VTO+5VADC +5VFROMREFERENCE REF +5VFROMREFERENCE –IN 4.99kΩ V2R.5EVF 4.99kΩ +AIN REF 0.1µF –AIN 4.99kΩ 10nF –15V –15V OP1177 +15V +5V 4.99kΩ 0.1µF 10µF 0.1µF TO0VTO+5VADC VOUTB=–2VIN+VREF 03579-031 Figure 66. Configuring the AD8220 to Output A Ratiometric, Differential Signal Rev. B | Page 24 of 28

AD8220 ELECTROCARDIOGRAM SIGNAL CONDITIONING In addition, the AD8220 JFET inputs have ultralow input bias current and no current noise, making it useful for ECG The AD8220 makes an excellent input amplifier for next applications where there are often large impedances. The MSOP generation ECGs. Its small size, high CMRR over frequency, and the optimal pinout of the AD8220 allow smaller footprints rail-to-rail output, and JFET inputs are well suited for this and more efficient layout, paving the way for next-generation application. Potentials measured on the skin range from 0.2 mV portable ECGs. to 2 mV. The AD8220 solves many of the typical challenges of Figure 67 shows an example ECG schematic. Following the measuring these body surface potentials. The high CMRR of AD8220 is a 0.033 Hz high-pass filter, formed by the 4.7 μF the AD8220 helps reject common-mode signals that come in capacitor and the 1 MΩ resistor, which removes the dc offset the form of line noise or high frequency EMI from equipment that develops between the electrodes. An additional gain of 50, in the operating room. Its rail-to-rail output offers a wide provided by the AD8618, makes use of the 0 V to 5 V input dynamic range allowing for higher gains than would be possible range of the ADC. An active, fifth-order, low-pass Bessel filter using other instrumentation amplifiers. JFET inputs offer a removes signals greater than approximately 160 Hz. An OP2177 large input capacitance of 5 pF. A natural RC filter is formed buffers, inverts, and gains the common-mode voltage taken at reducing high frequency noise when series input resistors are the midpoint of the AD8220 gain setting resistors. This right- used in front of the AD8220 (see the RF Interference section). leg drive circuit helps cancel common-mode signals by inverting the common-mode signal and driving it back into the body. A 499 kΩ series resistor at the output of the OP2177 limits the current driven into the body. G=+50 LOW-PASSFIFTHORDERFILTERAT157Hz INSTRUMENTATION +5V AMGP=LI+F1I4ER 2.5V 1.18kΩ 57.6kΩ 14kΩ 14kΩ 19.3kΩ 33nF 14.5kΩ 68nF 2.2pF AD8220 HIGH-PASSFILTER0.033Hz 47nF AD8618 AD8618 A B 15kΩ 10kΩ +5V +5V +5V +5V +5V 500Ω AD7685 24.9kΩ 19.3kΩ 14.5kΩ ADC 10kΩ10pF –5V +5V24.9kΩ 4.12kΩ –5V 4.72µ2F0pF 1MΩ AD8618 AD8618 1.15kΩ 2.7nF R+E5VF 4.7µF 2.2pF +5V 33nF 4.99kΩ 22nF REFERENCE ADR435 –5V OP2177 2.5V 2.5V 2.5V 2.5V C –5V OPAMPS 68pF 12.7kΩ 866kΩ +5V 499kΩ OP2177 –5V 03579-032 Figure 67. Example ECG Schematic Rev. B | Page 25 of 28

AD8220 OUTLINE DIMENSIONS 3.20 3.00 2.80 8 5 5.15 3.20 4.90 3.00 4.65 2.80 1 4 PIN1 IDENTIFIER 0.65BSC 0.95 15°MAX 0.85 1.10MAX 0.75 0.80 0.15 0.40 6° 0.23 0.55 CO0P.0L5ANARITY 0.25 0° 0.09 0.40 0.10 COMPLIANTTOJEDECSTANDARDSMO-187-AA 100709-B Figure 68. 8-Lead Mini Small Outline Package [MSOP] (RM-8) Dimensions shown in millimeters ORDERING GUIDE Model1, 2 Temperature Range3 Package Description Package Option Branding AD8220ARMZ −40°C to +85°C 8-Lead MSOP RM-8 H01 AD8220ARMZ-RL −40°C to +85°C 8-Lead MSOP, 13" Tape and Reel RM-8 H01 AD8220ARMZ-R7 −40°C to +85°C 8-Lead MSOP, 7" Tape and Reel RM-8 H01 AD8220BRMZ −40°C to +85°C 8-Lead MSOP RM-8 H0P AD8220BRMZ-RL −40°C to +85°C 8-Lead MSOP, 13" Tape and Reel RM-8 H0P AD8220BRMZ-R7 −40°C to +85°C 8-Lead MSOP, 7" Tape and Reel RM-8 H0P AD8220WARMZ −40°C to +125°C 8-Lead MSOP RM-8 Y2D AD8220WARMZ-RL −40°C to +125°C 8-Lead MSOP, 13" Tape and Reel RM-8 Y2D AD8220WARMZ-R7 −40°C to +125°C 8-Lead MSOP, 7" Tape and Reel RM-8 Y2D 1 Z = RoHS Compliant Part. 2 W = Qualified for Automotive Applications. 3 See the Typical Performance Characteristics section for expected operation from 85°C to 125°C. AUTOMOTIVE PRODUCTS The AD8220W models are available with controlled manufacturing to support the quality and reliability requirements of automotive applications. Note that these automotive models may have specifications that differ from the commercial models; therefore, designers should review the Specifications section of this data sheet carefully. Only the automotive grade products shown are available for use in automotive applications. Contact your local Analog Devices account representative for specific product ordering information and to obtain the specific Automotive Reliability reports for these models. Rev. B | Page 26 of 28

AD8220 NOTES Rev. B | Page 27 of 28

AD8220 NOTES ©2006–2010 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D03579-0-5/10(B) Rev. B | Page 28 of 28

Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: A nalog Devices Inc.: AD8220ARMZ AD8220ARMZ-R7 AD8220BRMZ AD8220WARMZ AD8220BRMZ-R7 AD8220BRMZ-RL AD8220WARMZ-R7 AD8220WARMZ-RL AD8220TRMZ-EP AD8220TRMZ-EP-R7