350 MHz Single-Supply (5 V) Triple 2:1 Multiplexers AD8188/AD8189 FEATURES FUNCTIONAL BLOCK DIAGRAM Fully buffered inputs and outputs IN0A 1 24 VCC Fast channel-to-channel switching: 4 ns DGND 2 LOGIC 23 OE Single-supply operation (5 V) IN1A 3 22 SEL A/B High speed VREF 4 SELECTENABLE 21 VCC 350 MHz bandwidth (−3 dB) @ 200 mV p-p IN2A 5 0 20 OUT0 300 MHz bandwidth (−3 dB) @ 2 V p-p VCC 6 19 VEE Slew rate: 1000 V/μs VEE 7 1 18 OUT1 Fast settling time: 7 ns to 0.1% IN2B 8 17 VCC Low current: 19 mA/20 mA VEE 9 2 16 OUT2 Excellent video specifications: load resistor (R) = 150 Ω IN1B 10 15 VEE L DDiiffffeerreennttiiaall pgahians ee rerrorro: r0: .00.50%5° INV0EBE 1112 AD8188/AD8189 1143 VDCVCCC 06239-001 Low glitch Figure 1. All hostile crosstalk −84 dB @ 5 MHz −52 dB @ 100 MHz High off isolation: −95 dB @ 5 MHz Low cost Fast, high impedance disable feature for connecting multiple outputs Logic-shifted outputs APPLICATIONS Switching RGB in LCD and plasma displays RGB video switchers and routers GENERAL DESCRIPTION The AD8188 (G = 1) and AD8189 (G = 2) are high speed, 4.0 6.0 single-supply, triple 2-to-1 multiplexers. They offer −3 dB small 3.5 5.5 signal bandwidth of 350 MHz and −3 dB large signal bandwidth 3.0 5.0 of 300 MHz, along with a slew rate in excess of 1000 V/μs. With −ar8e4 w deBll osfu aitlel dh ofosrti lme acnroys hstiaglhk sapnede d− 9ap5p dlBic aotfifo insso.l aTthioen , the parts AGE (V) 22..05 INPUT 44..05 TAGE (V) T L differential gain and differential phase error of 0.05% and 0.05° OL 1.5 3.5 VO respectively, along with 0.1 dB flatness to 70 MHz, make the T V 1.0 3.0 UT U P P T AD8188 and AD8189 ideal for professional and component IN 0.5 OUTPUT 2.5 OU video multiplexing. The parts offer 4 ns switching time, making 0 2.0 them an excellent choice for switching video signals, while –0.5 1.5 consuming less than 20 mA on a single 5 V supply (100 mW). –1.0 1.0 Bouottphu dtse vinicteos a h havigeh a i hmigphed sapneceed sdtaistaeb. Tleh fiesa atullroew tsh taht es ebtus itlhdein g of 0 5 10TIME (ns)15 20 25 06239-002 larger input arrays while minimizing off-channel output Figure 2. AD8189 Video Amplitude Pulse Response, loading. The devices are offered in a 24-lead TSSOP. VOUT = 1.4 V p-p, RL = 150 Ω Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Tel: 781.329.4700 www.analog.com Trademarks and registered trademarks are the property of their respective owners. Fax: 781.461.3113 ©2006 Analog Devices, Inc. All rights reserved.

AD8188/AD8189 TABLE OF CONTENTS Features..............................................................................................1 Full Power Bandwidth vs. −3 dB Large Signal Bandwidth...14 Applications.......................................................................................1 Single-Supply Considerations...................................................14 Functional Block Diagram..............................................................1 AC-Coupled Inputs....................................................................16 General Description.........................................................................1 Tolerance to Capacitive Load....................................................16 Revision History...............................................................................2 Secondary Supplies and Supply Bypassing.............................16 Specifications.....................................................................................3 Split-Supply Operation..............................................................16 Absolute Maximum Ratings............................................................5 Applications.....................................................................................17 Thermal Resistance......................................................................5 Single-Supply Operation...........................................................17 Maximum Power Dissipation.....................................................5 AC-Coupling...............................................................................17 ESD Caution..................................................................................5 DC Restore..................................................................................19 Pin Configuration and Function Descriptions.............................6 High Speed Design Considerations.........................................20 Typical Performance Characteristics.............................................7 Evaluation Board............................................................................21 Theory of Operation......................................................................14 Schematics...................................................................................23 High Impedance Disable...........................................................14 Outline Dimensions.......................................................................24 Off Isolation................................................................................14 Ordering Guide..........................................................................24 REVISION HISTORY 10/06—Revision 0: Initial Version Rev. 0 | Page 2 of 24

AD8188/AD8189 SPECIFICATIONS T = 25°C. For the AD8188, V = 5 V, R = 1 kΩ to 2.5 V. For the AD8189, V = 5 V, V = 2.5 V, R = 150 Ω to 2.5 V; unless otherwise noted. A S L S REF L Table 1. AD8188/AD8189 Parameter Conditions Min Typ Max Unit DYNAMIC PERFORMANCE −3 dB Bandwidth (Small Signal) V = 200 mV p-p 350 MHz OUT −3 dB Bandwidth (Large Signal) V = 2 V p-p 300 MHz OUT 0.1 dB Flatness V = 200 mV p-p 70 MHz OUT Slew Rate (10% to 90% Rise Time) V = 2 V p-p, R = 150 Ω 1000 V/μs OUT L Settling Time to 0.1% V = 1 V Step, R = 150 Ω 6/7.5 ns IN L NOISE/DISTORTION PERFORMANCE Differential Gain 3.58 MHz, R = 150 Ω 0.05 % L Differential Phase 3.58 MHz, R = 150 Ω 0.05 Degrees L All Hostile Crosstalk 5 MHz −84/−78 dB 100 MHz −52/−48 dB Channel-to-Channel Crosstalk, RTI 5 MHz −90/−85 dB Off Isolation 5 MHz −84/−95 dB Input Voltage Noise f = 100 kHz to 100 MHz 7/9 nV/√Hz DC PERFORMANCE Voltage Gain Error No load 0.1 ±0.3/±0.6 % Voltage Gain Error Matching Channel A to Channel B 0.04 ±0.2/±0.2 % VREF Gain Error 1 kΩ load 0.04 ±0.6 % Input Offset Voltage 0.2/0.5 ±6.5/±7.0 mV TMIN to TMAX ±8.0 mV Input Offset Voltage Matching Channel A to Channel B 0.2 ±5.0/±5.5 mV Input Offset Drift 10/5 μV/°C Input Bias Current 1.5 4/4 μA V Bias Current (AD8189 Only) 1.0 μA REF INPUT CHARACTERISTICS Input Resistance @ 100 kHz 1.8/1.3 MΩ Input Capacitance 0.9/1.0 pF Input Voltage Range (About Midsupply) IN0A, IN0B, IN1A, IN1B, IN2A, IN2B ±1.2 V V +0.9/−1.2 V REF OUTPUT CHARACTERISTICS Output Voltage Swing R = 1 kΩ 3.1/2.8 3.2/3.0 V p-p L R = 150 Ω 2.8/2.5 3.0/2.7 V p-p L Short-Circuit Current 85 mA Output Resistance Enabled @ 100 kHz 0.2/0.35 Ω Disabled @ 100 kHz 1000/600 kΩ Output Capacitance Disabled 1.5/2.0 pF POWER SUPPLY Operating Range 3.5 5.5 V Power Supply Rejection Ratio +PSRR, V = 4.5 V to 5.5 V, V = 0 V −72/−61 dB CC EE −PSRR, V = −0.5 V to +0.5 V, V = 5.0 V −76/−72 dB EE CC Quiescent Current All channels on 18.5/19.5 21.5/22.5 mA All channels off 3.5/4.5 4.5/5.5 mA T to T , all channels on 15 23 mA MIN MAX SWITCHING CHARACTERISTICS Channel-to-Channel Switching Time 50% logic to 50% output settling, INxA = +1 V, 3.6/4 ns INxB = −1 V Enable-to-Channel On Time 50% logic to 50% output settling, input = 1 V 4/3.8 ns Rev. 0 | Page 3 of 24

AD8188/AD8189 AD8188/AD8189 Parameter Conditions Min Typ Max Unit Disable-to-Channel Off Time 50% logic to 50% output settling, input = 1 V 17/5 ns Channel Switching Transient (Glitch) All channels grounded 21/45 mV Output Enable Transient (Glitch) All channels grounded 64/118 mV DIGITAL INPUTS Logic 1 Voltage SEL A/B, OE 1.6 V Logic 0 Voltage SEL A/B, OE 0.6 V Logic 1 Input Current SEL A/B, OE = 2.0 V 45 nA Logic 0 Input Current SEL A/B, OE = 0.5 V 2 μA Rev. 0 | Page 4 of 24

AD8188/AD8189 ABSOLUTE MAXIMUM RATINGS MAXIMUM POWER DISSIPATION Table 2. Parameter1 Rating The maximum safe junction temperature for plastic encapsulated Supply Voltage 5.5 V devices is determined by the glass transition temperature of the DV to D 5.5 V plastic, approximately 150°C. Temporarily exceeding this limit CC GND DV to V 8.0 V may cause a shift in parametric performance due to a change in CC EE V to D 8.0 V the stresses exerted on the die by the package. Exceeding a CC GND IN0A, IN0B, IN1A, IN1B, IN2A, IN2B, V V ≤ V ≤ V junction temperature of 175°C for an extended period can REF EE IN CC SEL A/B, OE DGND ≤ VIN ≤ VCC result in device failure. Output Short-Circuit Operation Indefinite While the AD8188/AD8189 is internally short circuit protected, Operating Temperature Range –40°C to +85°C this may not be sufficient to guarantee that the maximum junction Storage Temperature Range –65°C to +150°C temperature (150°C) is not exceeded under all conditions. To Lead Temperature Range (Soldering, 10 sec) 300°C ensure proper operation, it is necessary to observe the 1 Specification is for device in free air (TA = 25°C). maximum power derating curves shown in Figure 3. Stresses above those listed under Absolute Maximum Ratings 2.5 may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any W) N ( 2.0 other conditions above those indicated in the operational O TI section of this specification is not implied. Exposure to absolute PA SI 1.5 maximum rating conditions for extended periods may affect S DI device reliability. R E W PO 1.0 THERMAL RESISTANCE M U M θJA is specified for the worst-case conditions, that is, a device AXI 0.5 M soldered in a circuit board for surface-mount packages. 0 TPaacbklea g3e. TTyhperem al Resistance θJA2 θJC Unit –50 –40 –30 –20 –A1M0BIE0NT 1T0EM2P0ER3A0TU4R0E (°5C0) 60 70 80 90 06239-003 24-Lead TSSOP1 85 20 °C/W Figure 3. Maximum Power Dissipation vs. Temperature 1 Maximum internal power dissipation (PD) should be derated for ambient ESD CAUTION temperature (TA) such that PD < (150°C TA)/θJA. 2 θJA is on a 4-layer board (2s 2p). Rev. 0 | Page 5 of 24

AD8188/AD8189 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS IN0A 1 24 VCC DGND 2 23 OE IN1A 3 22 SEL A/B VREF 4 AD8188/ 21 VCC IN2A 5 AD8189 20 OUT0 VCC 6 TOP VIEW 19 VEE VEE 7 (Not to Scale) 18 OUT1 IN2B 8 17 VCC VEE 9 16 OUT2 IN1B 10 15 VEE INV0EBE 1112 1143 VDCVCCC 06239-004 Figure 4. AD8188/AD8189 Pin Configuration Table 4. Pin Function Descriptions Pin No. Mnemonic Description 1 IN0A Input, High-Z . Routed to OUT0 when A is selected. IN 2 D Ground Reference for Digital Control Circuitry. GND 3 IN1A Input, High-Z . Routed to OUT1 when A is selected. IN 4 V AD8188: Bypass point for internal reference. Does not affect dc level of output. REF AD8189: Input to reference buffers for all channels. Can be used to offset the outputs. 5 IN2A Input, High-Z . Routed to OUT2 when A is selected. IN 6, 13, 17, 21, 24 V Positive Analog Supply. Nominally 5 V higher than V . CC EE 7, 9, 11, 15, 19 V Negative Analog Supply. EE 8 IN2B Input, High-Z . Routed to OUT2 when B is selected. IN 10 IN1B Input, High-Z . Routed to OUT1 when B is selected. IN 12 IN0B Input, High-Z . Routed to OUT0 when B is selected. IN 14 DV Positive Supply for Digital Control Circuitry. Referenced to D CC GND. 16 OUT2 Output. Can connect to IN2A, IN2B, or disable. 18 OUT1 Output. Can connect to IN1A, IN1B, or disable. 20 OUT0 Output. Can connect to IN0A, IN0B, or disable. 22 SEL A/B Logic high selects the three A inputs. Logic low selects the three B inputs. 23 OE Output Enable. Logic high enables the three outputs. Table 5. Truth Table SEL A/B OE OUT 0 0 High-Z 1 0 High-Z 1 1 INxA 0 1 INxB Rev. 0 | Page 6 of 24

AD8188/AD8189 TYPICAL PERFORMANCE CHARACTERISTICS 3 0.6 1 0.5 976Ω 2 DUT 0.5 GAIN 0 0.4 50Ω 52.3Ω 1 0.4 B) GAIN (dB) –––3210 FLATNESS GAIN 0000...321 FLATNESS (dB) NORMALIZED GAIN (dB) ––––4321 FLATNESS 0000...321 RMALIZED FLATNESS (d –4 –0.1 NO –5 –0.1 –5 –0.2 –6 –0.3 –6 –0.2 0.1 1 FR1E0QUENCY (1M0H0z) 1k 10k 06239-005 0.1 1 FR1E0QUENCY (1M0H0z) 1k 10k 06239-008 Figure 5. AD8188 Frequency Response, VOUT = 200 mV p-p, RL = 1 kΩ Figure 8. AD8189 Frequency Response, VOUT = 200 mV p-p, RL = 150 Ω 1 1 0 0 –1 B) –1 –2 N (d N (dB) –3 ED GAI –2 GAI –4 LIZ –3 A M –5 R O –4 N –6 150Ω 976Ω DUT –7 50Ω 52.3Ω –5 –8 –6 0.1 1 FREQUE1N0CY (MHz) 100 1k 06239-006 0.1 1 FREQUE1N0CY (MHz) 100 1k 06239-009 Figure 6. AD8188 Frequency Response, VOUT = 2 V p-p, RL = 1 kΩ Figure 9. AD8189 Frequency Response, VOUT = 2 V p-p, RL = 150 Ω 1 1 +85°C –40°C +25°C 0 +25°C 0 –1 –40°C B) –1 +85°C d N ( B) –2 GAI –2 N (d ED GAI –3 ALIZ –3 M R –4 O –4 N 150Ω 976Ω DUT –5 –5 50Ω 52.3Ω –6 –6 0.1 1 FREQUE1N0CY (MHz) 100 1k 06239-007 0.1 1 FREQUE1N0CY (MHz) 100 1k 06239-010 Figure 7. AD8188 Large Signal Bandwidth vs. Temperature, Figure 10. AD8189 Large Signal Bandwidth vs. Temperature, VOUT = 2 V p-p, RL = 1 kΩ VOUT = 2 V p-p, RL = 150 Ω Rev. 0 | Page 7 of 24

AD8188/AD8189 0 0 –10 –10 –20 –20 –30 –30 B) –40 B) –40 d d LK ( –50 LK ( –50 A A ST –60 ST –60 S S O O R –70 R –70 C C –80 –80 –90 –90 –100 –100 –110 –110 0.1 1 FREQUE1N0CY (MHz) 100 1k 06239-011 0.1 1 FREQUE1N0CY (MHz) 100 1k 06239-014 Figure 11. AD8188 All Hostile Crosstalk vs. Frequency Figure 14. AD8189 All Hostile Crosstalk vs. Frequency (Drive All INxA, Listen to Output with INxB Selected) (Drive All INxA, Listen to Output with INxB Selected) 0 0 –10 –10 –20 –20 –30 –30 B) –40 B) –40 d d LK ( –50 LK ( –50 A A –60 ST –60 ST S S –70 O O R –70 R C C –80 –80 –90 –90 –100 –100 –110 –110 –120 0.1 1 FREQUE1N0CY (MHz) 100 1k 06239-012 0.1 1 FREQUE1N0CY (MHz) 100 1k 06239-015 Figure 12. AD8188 Adjacent Channel Crosstalk vs. Frequency Figure 15. AD8189 Adjacent Channel Crosstalk vs. Frequency (Drive One INxA, Listen to an Adjacent Output with INxB Selected) (Drive One INxA, Listen to an Adjacent Output with INxB Selected) 0 0 –10 –10 –20 –20 –30 dB) –30 dB) –40 ON ( –40 ON ( –50 TI TI A –50 A –60 L L O O F IS –60 F IS –70 F F –80 O –70 O –90 –80 –100 –90 –110 –100 –120 1 10FREQUENCY (MHz1)00 1k 06239-013 1 10FREQUENCY (MHz1)00 1k 06239-016 Figure 13. AD8188 Off Isolation vs. Frequency Figure 16. AD8189 Off Isolation vs. Frequency (Drive Inputs with OE Tied Low) (Drive Inputs with OE Tied Low) Rev. 0 | Page 8 of 24

AD8188/AD8189 0 0 –10 –10 –20 –20 –30 –30 c) c) B B d –40 d –40 N ( N ( O O TI –50 TI –50 R R THIRD TO –60 TO –60 DIS THIRD DIS –70 –70 SECOND SECOND –80 –80 –90 –90 –100 –100 1 FREQUE1N0CY (MHz) 100 06239-017 1 FREQUE1N0CY (MHz) 100 06239-020 Figure 17. AD8188 THD vs. Frequency, VOUT = 2 V p-p, RL = 150 Ω Figure 20. AD8189 THD vs. Frequency, VOUT = 2 V p-p, RL = 150 Ω 0 0 –10 –10 –20 –20 –30 –30 c) –PSRR c) B –40 B –PSRR d d R ( R ( –40 R –50 R S S P P –50 –60 +PSRR –60 –70 +PSRR –80 –70 –90 –80 0.01 0.1 FREQUEN1CY (MHz) 10 100 06239-018 0.01 0.1 FREQUEN1CY (MHz) 10 100 06239-021 Figure 18. AD8188 PSRR vs. Frequency, RL = 150 Ω Figure 21. AD8189 PSRR vs. Frequency, RL = 150 Ω 20 20 18 18 16 16 14 14 Hz) 12 Hz) 12 V/ V/ E (n 10 E (n 10 S S OI 8 OI 8 N N 6 6 4 4 2 2 0 0 0.01 0.1 1FREQUE1N0CY (MHz1)00 1k 10k 06239-019 0.01 0.1 1FREQUE1N0CY (MHz1)00 1k 10k 06239-022 Figure 19. AD8188 Input Voltage Noise vs. Frequency Figure 22. AD8189 Input Voltage Noise vs. Frequency Rev. 0 | Page 9 of 24

AD8188/AD8189 10k 10k 1k 1k Ω) Ω) E (k 100 E (k 100 C C N N A A D D PE 10 PE 10 M M I I 1 1 0.1 0.1 0.1 1 FREQUE1N0CY (MHz) 100 1k 06239-023 0.1 1 FREQUE1N0CY (MHz) 100 1k 06239-026 Figure 23. AD8188 Input Impedance vs. Frequency Figure 26. AD8189 Input Impedance vs. Frequency 1k 1k 100 100 Ω) Ω) E ( E ( C C AN 10 AN 10 D D E E P P M M I I 1 1 0.1 0.1 0.1 1 FREQUE1N0CY (MHz) 100 1k 06239-024 0.1 1 FREQUE1N0CY (MHz) 100 1k 06239-027 Figure 24. AD8188 Enabled Output Impedance vs. Frequency Figure 27. AD8189 Enabled Output Impedance vs. Frequency 10k 10k 1k 1k Ω) Ω) E (k 100 E (k 100 C C N N A A D D PE 10 PE 10 M M I I 1 1 0.1 0.1 0.1 1 FREQUE1N0CY (MHz) 100 1k 06239-025 0.1 1 FREQUE1N0CY (MHz) 100 1k 06239-028 Figure 25. AD8188 Disabled Output Impedance vs. Frequency Figure 28. AD8189 Disabled Output Impedance vs. Frequency Rev. 0 | Page 10 of 24

AD8188/AD8189 2.8 3.3 2.8 3.2 2.7 2.7 3.1 INPUT 2.6 2.6 INPUT 3.0 GE (V) 22..54 AGE (V) GE (V) 22..45 22..98 AGE (V) A T A T T L T L L 2.3 2.8 O L 2.3 2.7 O O V O V T V 2.2 UT T V 2.2 OUTPUT 2.6 UT U P U P P OUTPUT T P T IN 2.1 OU IN 2.1 2.5 OU 2.0 2.0 2.4 1.9 1.9 2.3 1.8 2.3 1.8 2.2 0 5 10TIME (ns)15 20 25 06239-029 0 5 10TIME (ns)15 20 25 06239-032 Figure 29. AD8188 Small Signal Pulse Response, Figure 32. AD8189 Small Signal Pulse Response, VOUT = 200 mV p-p, RL = 1 kΩ VOUT = 200 mV p-p, RL = 150 kΩ 3.0 5.0 4.0 6.0 INPUT 3.5 5.5 2.5 4.5 3.0 5.0 2.0 4.0 INPUT GE (V) 1.5 3.5 AGE (V) GE (V) 22..05 44..50 AGE (V) A T A T T L T L L 1.0 3.0 O L 1.5 3.5 O O V O OUTPUT V T V OUTPUT UT T V 1.0 3.0 UT U 0.5 2.5 P U P P T P T IN OU IN 0.5 2.5 OU 0 2.0 0 2.0 –0.5 1.5 –0.5 1.5 –1.0 1.0 –1.0 1.0 0 5 10TIME (ns)15 20 25 06239-030 0 5 10TIME (ns)15 20 25 06239-033 Figure 30. AD8188 Video Amplitude Pulse Response, Figure 33. AD8189 Video Amplitude Pulse Response, VOUT = 700 mV p-p, RL = 1 kΩ VOUT = 1.4 V p-p, RL = 150 kΩ 4.0 7.0 4.0 6.0 INPUT 3.5 6.5 3.5 5.5 INPUT 3.0 6.0 3.0 5.0 2.5 5.5 2.5 4.5 E (V) 2.0 5.0 GE (V) E (V) 2.0 OUTPUT 4.0 GE (V) G 1.5 4.5 A G 1.5 3.5 A A T A T T L T L L 1.0 4.0 O L 1.0 3.0 O T VO 0.5 OUTPUT 3.5 UT V T VO 0.5 2.5 UT V U P U P NP 0 3.0 UT NP 0 2.0 UT I O I O –0.5 2.5 –0.5 1.5 –1.0 2.0 –1.0 1.0 –1.5 1.5 –1.5 0.5 –2.0 1.0 –2.0 0 0 5 10TIME (ns)15 20 25 06239-031 0 5 10TIME (ns)15 20 25 06239-034 Figure 31. AD8188 Large Signal Pulse Response, Figure 34. AD8189 Large Signal Pulse Response, VOUT = 2 V p-p, RL = 1 kΩ VOUT = 2 V p-p, RL = 150 kΩ Rev. 0 | Page 11 of 24

AD8188/AD8189 DIV) tSETTLED DIV) tSETTLED V/ V/ m m 1 1 T ( T ( U U P P T T U U O O t0 TIME (2ns/DIV) 06239-035 t0 TIME (2ns/DIV) 06239-038 Figure 35. AD8188 Settling Time (0.1%), VOUT = 2 V Step, RL = 1 kΩ Figure 38. AD8189 Settling Time (0.1%), VOUT = 2 V Step, RL = 150 Ω 2.3 6.0 2.0 5.5 1.8 5.5 1.5 5.0 V) SEL A/B V) E ( 1.3 5.0 E ( 1.0 4.5 MPLITUD 00..38 44..50 UDE (V) MPLITUD 0.5 SEL A/B 4.0 UDE (V) ULSE A –0.3 OUTPUT 3.5 AMPLIT ULSE A –0.50 OUTPUT 33..50 AMPLIT P –0.8 3.0 T P T CT A/B –1.3 2.5 OUTPU CT A/B –1.0 2.5 OUTPU E E –1.5 2.0 L –1.8 2.0 L E E S S –2.3 1.5 –2.0 1.5 –2.8 1.0 –2.5 1.0 0 5 10TIME (ns)15 20 25 06239-036 0 5 10TIME (ns)15 20 25 06239-039 Figure 36. AD8188 Channel-to-Channel Switching Time, Figure 39. AD8189 Channel-to-Channel Switching Time, VOUT = 2 V p-p, INxA = 3.5 V, INxB = 1.5 V VOUT = 2 V p-p, INxA = 3.0 V, INxB = 2.0 V 2.0 3.0 2.0 3.0 V) 1.5 2.9 V) 1.5 2.9 E ( E ( UD SEL A/B V) UD SEL A/B V) MPLIT 1.0 2.8 UDE ( MPLIT 1.0 2.8 UDE ( ULSE A 0.5 2.7 AMPLIT ULSE A 0.5 2.7 AMPLIT P T P T A/B 0 2.6 TPU A/B 0 2.6 TPU CT OU CT OU E E L OUTPUT L OUTPUT E –0.5 2.5 E –0.5 2.5 S S –1.0 2.4 –1.0 2.4 0 5 10 15 20TIM2E5 (ns)30 35 40 45 50 06239-037 0 5 10 15 20TIM2E5 (ns)30 35 40 45 50 06239-040 Figure 37. AD8188 Channel Switching Transient (Glitch), Figure 40. AD8189 Channel Switching Transient (Glitch), INxA = INxB = 0 V INxA = INxB = VREF = 0 V Rev. 0 | Page 12 of 24

AD8188/AD8189 2.0 5.5 2.0 6.0 OE 1.5 OE 5.0 1.5 5.5 ULSE AMPLITUDE (V) 10..005 OUTPUT 443...505 PUT AMPLITUDE (V) ULSE AMPLITUDE (V) –010...5005 OUTPUT 5443....0505 PUT AMPLITUDE (V) OE P –0.5 3.0 OUT OE P –1.0 3.0 OUT –1.0 2.5 –1.5 2.5 –1.5 2.0 –2.0 2.0 0 20 40 60 80TIM1E0 0(ns)120 140 160 180 200 06239-041 0 20 40 60 80TIM1E0 0(ns)120 140 160 180 200 06239-043 Figure 41. AD8188 Enable On/Off Time, VOUT = 0 V to 1 V Figure 43. AD8189 Enable On/Off Time, VOUT = 0 V to 1 V 1.5 3.0 2.0 3.0 2.9 1.5 2.9 OE PULSE AMPLITUDE (V) 10..05 OE 222...876 OUTPUT AMPLITUDE (V) OE PULSE AMPLITUDE (V) 01..050 OUOTEPUT 222...876 OUTPUT AMPLITUDE (V) OUTPUT 2.5 –0.5 2.5 0 2.4 –1.0 2.4 0 5 10 15 20TIM2E5 (ns)30 35 40 45 50 06239-042 0 5 10 15 20TIM2E5 (ns)30 35 40 45 50 06239-044 Figure 42. AD8188 Channel Enable/Disable Transient (Glitch) Figure 44. AD8189 Channel Enable/Disable Transient (Glitch) Rev. 0 | Page 13 of 24

AD8188/AD8189 THEORY OF OPERATION The AD8188 (G = 1) and AD8189 (G = 2) are single-supply, muxes. In this case, the proper load resistance for the off triple 2:1 multiplexers with TTL-compatible global input isolation calculation is the output impedance of an enabled switching and output-enable control. Optimized for selecting AD8188, typically less than a 1/10 Ω. between two RGB (red, green, blue) video sources, the devices FULL POWER BANDWIDTH VS. −3 dB LARGE have high peak slew rates, maintaining their bandwidth for SIGNAL BANDWIDTH large signals. Additionally, the multiplexers are compensated for Note that full power bandwidth for an undistorted sinusoidal high phase margin, minimizing overshoot for good pixel signal is often calculated using the peak slew rate from the equation resolution. The multiplexers also have respectable video specifications and are superior for switching NTSC or PAL PeakSlewRate FullPower Bandwidth= composite signals. 2π×SinusoidAmplitude The multiplexers are organized as three independent channels, The peak slew rate is not the same as the average slew rate. The each with two input transconductance stages and one output average slew rate is typically specified as the ratio transimpedance stage. The appropriate input transconductance stages are selected via one logic pin (SEL A/B) such that all ΔV OUT three outputs simultaneously switch input connections. The Δt unused input stages are disabled with a proprietary clamp measured between the 20% and 80% output levels of a circuit to provide excellent crosstalk isolation between on and sufficiently large output pulse. For a natural response, the peak off inputs while protecting the disabled devices from damaging slew rate can be 2.7 times larger than the average slew rate. reverse base-emitter voltage stress. No additional input Therefore, calculating a full power bandwidth with a specified buffering is necessary, resulting in low input capacitance and average slew rate gives a pessimistic result. See the Specifications high input impedance without additional signal degradation. section for the large-signal bandwidth and average slew rate for The transconductance stage is a high slew rate, class AB circuit both the AD8188 and AD8189 (large signal bandwidth is defined that sources signal current into a high impedance node. Each as the −3 dB point measured on a 2 V p-p output sine wave). output stage contains a compensation network and is buffered Figure 17 and Figure 20 contain plots for the second- and third- to the output by a complementary emitter-follower stage. order harmonic distortion. Specifying these three aspects of the Voltage feedback sets the gain with the AD8188 configured as a signal path’s large signal dynamics allows the user to predict unity gain follower, and the AD8189 configured as a gain-of-two system behavior for either pulse or sinusoid waveforms. amplifier with a feedback network. This architecture provides SINGLE-SUPPLY CONSIDERATIONS drive for a reverse-terminated video load (150 Ω) with low The AD8188 and AD8189 offer superior large signal dynamics. differential gain and phase errors, while consuming relatively The trade-off is that the input and output compliance is limited little power. Careful chip layout and biasing result in excellent to ~1.3 V from either rail when driving a 150 Ω load. The crosstalk isolation between channels. following sections address some challenges of designing video HIGH IMPEDANCE DISABLE systems within a single 5 V supply. The output-enable logic pin (OE) of the AD8188 and AD8189 The AD8188 controls whether the three outputs are enabled or disabled to a The AD8188 is internally wired as a unity-gain follower. Its high impedance state. The high impedance disable allows larger inputs and outputs can both swing to within ~1.3 V of either matrices to be built by busing the outputs together. rail. This affords the user 2.4 V of dynamic range at input and In the case of the AD8189 (G = 2), the reference buffers also output that should be enough for most video signals, whether disable to a state of high output impedance. This feature the inputs are ac- or dc-coupled. In both cases, the choice of output prevents the feedback network of a disabled channel from termination voltage determines the quiescent load current. loading the output, which is valuable when busing together the For improved supply rejection, the V pin should be tied to an outputs of several muxes. REF ac ground (the more quiet the supply, the better). Internally, the OFF ISOLATION V pin connects to one terminal of an on-chip capacitor. The REF The off isolation performance of the signal path is dependent capacitor’s other terminal connects to an internal node. The upon the value of the load resistor, R. For calculating off consequence of building this bypass capacitor on-chip is L isolation, the signal path can be modeled as a simple high-pass twofold. First, the VREF pin on the AD8188 draws no input bias network with an effective capacitance of 3 fF. Off isolation current. (Contrast this to the case of the AD8189, where the improves as the load resistance is decreased. In the case of the VREF pin typically draws 2 μA of input bias current.) Second, on AD8188, off isolation is specified with a 1 kΩ load. However, a the AD8188, the VREF pin can be tied to any voltage within the practical application would likely gang the outputs of multiple supply range. Rev. 0 | Page 14 of 24

AD8188/AD8189 AD8188 5V 5V 1.3V IN0A MUX SYSTEM VO_MAX = 3.7V IN0B OUT0 A0 OUT0 VOUT IN1A VO_MIN = 1.3V OUT1 1.3V IN1B GND IN2A OUT2 IN2B 5V “C_BYPASS” 5V VREF VREF 1.6V INTERNAL CAP VO_MAX = 3.4V BIAS REFERENCE VREF VO_MIN = 1.3V FigureD( F4IOR5E.R VC ERTEX FCA POMinNP NLCEEoC,n GTnINeODcNt, iVToCOnC Af, oANrNY AD “D QV8UE1EIE8).T8” ( DACiff GerRsO frUoNmD A06239-045D 8189) Figure 47. Output Compliance of Main A1m.3pVlifier ChanGnNeDl and Groun06239-047d Buffer The AD8189 • The signal at the V pin appears at each output. REF The AD8189 uses on-chip feedback resistors to realize the gain- Therefore, V should be tied to a well bypassed, low REF of-two function. To provide low crosstalk and a high output impedance source. Using superposition, it is shown that impedance when disabled, each set of 500 Ω feedback resistors V = 2 × V − V is terminated by a dedicated reference buffer. A reference buffer OUT IN REF is a high speed op amp configured as a unity-gain follower. The • To maximize the output dynamic range, the reference three reference buffers, one for each channel, share a single, voltage should be chosen with care. For example, consider high impedance input, the VREF pin (see Figure 46). VREF input amplifying a 700 mV video signal with a sync pulse bias current is typically less than 2 μA. 300 mV below black level. If the user decides to set V at REF 5V black level to preferentially run video signals on the faster A0 NPN transistor path, the AD8189 allows a reference 1× OUT0 voltage as low as 1.3 V + 300 mV = 1.6 V. If the AD8189 is 5V used, the sync pulse is amplified to 600 mV. Therefore, the B0 lower limit on V becomes 1.3 V + 600 mV = 1.9 V. For REF 500Ω routing RGB video, an advantageous configuration is to VFO VREF 5GVBUF 0 500Ω teimedp ltooy g +ro3u Vn da.n d −2 V supplies, in which case VREF can be If system considerations prevent running the multiplexer on 5V VF-1 split supplies, a false ground reference should be employed. A GBUF 1 low impedance reference can be synthesized with a second OUT1 500Ω 500Ω operational amplifier. Alternately, a well bypassed resistor VF-2 divider can be used. Refer to the Applications section for 5V GBUF 2 further explanation and more examples. 500Ω 500Ω OUT2 06239-046 5V Figure 46. Conceptual Diagram of a Single Multiplexer Channel, G = 2 10kΩ This configuration has a few implications for single-supply 100kΩ operation: 0.022µF VREF • On the AD8189, V cannot be tied to the most negative 100Ω REF OP21 analog supply, V . The limits on reference voltage are (see 1µF 1µF EE Figure 47): FROM 1992 ADI AMPLIFIER APPLICATIONS GUIDE V1.E3E V+ <1. 3V V <, 3 V.4R EVF ×o nV C0C V −/ 51 .V6 Vsu pplies GND 06239-048 REF Figure 48. Synthesis of a False Ground Reference Rev. 0 | Page 15 of 24

AD8188/AD8189 5V SECONDARY SUPPLIES AND SUPPLY BYPASSING The high current output transistors are given their own supply 10kΩ pins (Pin 15, Pin 17, Pin 19, and Pin 21) to reduce supply noise VREF on-chip and to improve output isolation. Because these secondary, high current supply pins are not connected on-chip 10kΩ 1µF to the primary analog supplies, V /V (Pin 6, Pin 7, Pin 9, CC EE Pin 11, Pin 13, and Pin 24), some care should be taken to ensure CAP MUST BE LARGE that the supply bypass capacitors are connected to the correct ETWRNITAOHNU SMGIHEINN TIMTO UC AMUB RBSROOEURNNBTCSE. 06239-049 pins. At a minimum, the primary supplies should be bypassed. Figure 49. Alternate Method for Synthesis of a False Ground Reference Pin 6 and Pin 7 can be a convenient place to accomplish this. Stacked power and ground planes are a convenient way to AC-COUPLED INPUTS bypass the high current supply pins (see Figure 51). Using ac-coupled inputs presents an interesting challenge for video systems operating from a single 5 V supply. In NTSC and IN0A 1 24 VCC PAL video systems, 700 mV is the approximate difference DGND 2 23 OE between the maximum signal voltage and black level. It is assumed that sync has been stripped. However, given the two IN1A 3 22 SEL A/B pathological cases shown in Figure 50, a dynamic range of twice the maximum signal swing is required if the inputs are to be VREF 4 21 VCC ac-coupled. A possible solution is to use a dc restore circuit IN2A 5 20 OUT0 before the mux. WHITE LINE WITH BLACK PIXEL VCC 6 MUX1 19 VEE 0.1µF 1µF +700mV VREF VEE 7 18 OUT1 VAVG VAVG VREF –700mV IN2B 8 MUX2 17 VCC BLACK LINE WITH WHITE PIXEL VEE 9 16 OUT2 +5V VINPUT = VREF + VSIGNAL IN1B 10 MUX3 15 VEE VSIGNAL VVSRREEETFF B ~ISY V ATAH VDEGC R VEOSLISTTAOGRES VEE 11 14 DVCC Figure 50. PatholoGgNiDcal Case for Input Dynamic Range 06239-050 IN0B 12 13 VCC 06239-051 Figure 51. Detail of Primary and Secondary Supplies TOLERANCE TO CAPACITIVE LOAD SPLIT-SUPPLY OPERATION Op amps are sensitive to reactive loads. A capacitive load at the Operating from split supplies (for example, [+3 V/−2 V] or output appears in parallel with an effective resistance (R ) of EFF ±2.5 V) simplifies the selection of the V voltage and load REF R = (R || r ) EFF L O resistor termination voltage. In this case, it is convenient to tie where RL is the discrete resistive load, and rO is the open loop VREF to ground. The logic inputs are internally level-shifted to output impedance, approximately 15 Ω for these muxes. allow the digital supplies and logic inputs to operate from 0 V and 5 V when powering the analog circuits from split supplies. The load pole (f ) at LOAD The maximum voltage difference between DV and V must CC EE 1 f = not exceed 8 V (see Figure 52). LOAD 2πR C EFF L DIGITAL SUPPLIES ANALOG SUPPLIES can seriously degrade phase margin and, therefore, stability. The (+5V) DVCC (+2.5V) VCC old workaround is to place a small series resistor directly at the 8V MAX output to isolate the load pole. While effective, this ruse also aTfhfeec AtsD th8e1 8d8c aanndd A teDrm81i8n9a tairoen b cuhilatr wacitther ais vtiacrsi aobfl ea c7o5m Ωp esynsstaetmio.n (0V) DGND (–2.5V) VEE 06239-052 Figure 52. Split-Supply Operation scheme that senses the output reactance and trades bandwidth for phase margin, ensuring faster settling and lower overshoot at higher capacitive loads. Rev. 0 | Page 16 of 24

AD8188/AD8189 APPLICATIONS SINGLE-SUPPLY OPERATION If the input is biased at 2.5 V dc, the input signal can potentially go 700 mV both above and below this point. The resulting 1.8 V The AD8188/AD8189 are targeted mainly for use in single- and 2.2 V are within the input signal range for single 5 V supply 5 V systems. For operating on these supplies, both V EE operation. Because the part is unity-gain, the outputs follow the and D should be tied to ground, and the control logic pins GND inputs, and there is adequate range at the output as well. should be referenced to ground. Normally, the DV supply CC When the AD8188 is operated from a single supply of 5 V and needs to be set to the same positive supply as the driving logic. ground, ac-coupling is often useful. This is particularly true when For dc-coupled, single-supply operation, it is necessary to set an the input signals are a typical RGB source from a PC. These appropriate input dc level that is within the specified range of the signals go all the way to ground at the most negative, outside of amplifier. For the unity-gain AD8188, the output dc level is the the AD8188 input range, when its negative supply is ground. same as the input, while for the gain-of-two AD8189, the V REF The closest that the input can go to ground is typically 1.3 V. input can be biased to obtain an appropriate output dc level. There are several basic methods for ac-coupling the inputs. Figure 53 shows a circuit that provides a gain-of-two and is They all consist of a series capacitor followed by a circuit for dc-coupled. The video input signals must have a dc bias from setting the dc operating point of the input and then the AD8188 their source of approximately 1.5 V. This same voltage is applied input. If a termination is provided, it should be located before to V of the AD8189. The result is that when the video signal REF the series coupling capacitor. is at 1.5 V, the output is also at the same voltage. This is close to The different circuits vary in the means used to establish the dc the lower dynamic range of both the input and the output. operating point after the coupling capacitor. A straightforward When the input goes most positive, which is 700 mV above the way to do this is to use a voltage divider for each input. black level for a standard video signal, it reaches a value of 2.2 V, However, because there are six inputs altogether, 12 resistors are and there is enough headroom for the signal. On the output required to set all of the dc operating points. This means many side, the magnitude of the signal changes by 1.4 V, making the components in a small space, but the circuit has the advantage maximum output voltage 2.2 V + 1.4 V = 3.6 V. This is just of having the lowest crosstalk among any of the inputs. This within the dynamic range of the output of the part. circuit is shown in Figure 54. AC-COUPLING A circuit that uses the minimum number of resistors can be AD8188 designed. First, create a node, V , which serves as the bias MID When a video signal is ac-coupled, the amount of dynamic voltage for all of the inputs. Then, a single resistor is used to range required to handle the signal can potentially be double connect from each input (inside the ac-coupling capacitor) and the amount required for dc-coupled operation. For the unity- VMID (see Figure 55). gain AD8188, there is still enough dynamic range to handle an ac-coupled, standard video signal with 700 mV p-p amplitude. 3V TO 5V 5V IN0A DVCC VCC REDA AD8189 IN1A GRNA OUT0 ×2 RED 0.7V MAX IN2A BLUA 3.0V 2.2V 5V 1.4V MAX 1.5V 3.48kΩ 1.5V ×2 OUT1 GRN 1.5V VREF TYPICAL OUTPUT LEVELS BLACK TYPICAL INPUT LEVELS 1.5kΩ BLACK (ALL 3 OUTPUTS) LEVEL (ALL 6 OUTPUTS) LEVEL REDB IN0B ×2 OUT2 BLU IN1B GRNB IN2B BLUB DGND VEE SEL A/B OE 06239-055 Figure 53. AD8189 DC-Coupled (Bypassing and Logic Not Shown) Rev. 0 | Page 17 of 24

AD8188/AD8189 5V 5V 5V 0.1µF 0.1µF 10µF 4.99kΩ RGB 75Ω 4.99kΩ SOURCE A IN0A DVCC VCC R AD8188 0.1µF 5V G 75Ω 4.99kΩ 4.99kΩ IN0B + OUT0 – B 0.1µF 5V 75Ω 4.99kΩ 4.99kΩ IN1A IN1B + OUT1 TO A/D, 5V – ETC. 75Ω 4.99kΩ 0.1µF 4.99kΩ IN2A 0.1µF 5V RGB 75Ω 4.99kΩ + OUT2 SOURCE B 4.99kΩ IN2B – R 0.1µF 5V HI = A SEL A/B G 75Ω 4.99kΩ LO = B 4.99kΩ B VREF 0.1µF DGND VEE OE HLOI = = E DNIASBALBELE 06239-053 Figure 54. AD8188 AC-Coupling Using Separate Voltage Dividers 5V 5V 0.1µF 0.1µF 10µF VMID RGB 75Ω SOURCE A 4.99kΩ IN0A DVCC VCC R AD8188 0.1µF VMID G 75Ω 4.99kΩ IN0B + OUT0 – B 0.1µF VMID 75Ω 4.99kΩ IN1A IN1B + OUT1 TO A/D, 75Ω 0.1µF VMID – ETC. 4.99kΩ IN2A RGB 75Ω 0.1µF VMID + OUT2 SOURCE B 4.99kΩ IN2B – R G 75Ω 0.1µF VMID LHOI == AB SEL A/B B 4.99kΩ VREF 5V 0.1µF DGND VEE OE VMID 100Ω HI = ENABLE LO = DISABLE 100Ω 0.1µF 10µF 06239-054 Figure 55. AD8188 AC-Coupling Using a Single VMID Reference The circuit in Figure 55 can increase the crosstalk between The second technique for minimizing crosstalk is to use large inputs, because each input signal creates a small signal on V resistor values to connect from the inputs to V . The major factor MID MID due to its nonzero impedance. There are several means to limiting the value of these resistors is offset caused by the input minimize this. First, make the impedance of the V divider bias current (I ) that must flow through these resistors to the MID B small. Small resistor values lower the dc resistance, and good AD8188 inputs. The typical I for an AD8188 input is 1.5 μA, B bypassing to ground minimizes the ac impedance. It is also which causes an offset voltage of 1.5 mV per 1 kΩ of resistance. possible to use a voltage regulator or another system supply voltage if it is the correct value. It should be close to the mid- supply voltage of the AD8188. Rev. 0 | Page 18 of 24

AD8188/AD8189 These two techniques can also be combined. Typically, crosstalk input capacitors of the AD8189. The input points of the between the RGB signals from the same source is less objectionable AD8189 are switched to a 1.5 V reference by the ADG786, than crosstalk between two different sources. The former can which works in the following manner: cause a color or luminance shift, but spatially, everything is • The SEL A/B signal selects the A or B input to the AD8189. It coherent. However, the crosstalk signals from two uncorrelated also selects the switch positions in the ADG786 such that the sources can create ghost images that are far more objectionable. same selected inputs are connected to V when EN is low. REF A technique for minimizing crosstalk between two different • During the horizontal interval, all of the RGB input signals are sources is to create two separate VMID circuits. Then, the inputs at a flat black level. A logic signal that is low during HSYNC is from each source can be connected to their own V node, MID applied to the EN of the ADG786. This closes the switches and minimizing crosstalk between sources. clamps the black level to 1.5 V. At all other times, the switches AD8189 are off and the node at the inputs to the AD8189 floats. When using the gain-of-two AD8189 in a simple ac-coupled There are two considerations for sizing the input coupling application, there is a dynamic range limitation at the output capacitors. One is the time constant during the H-pulse caused by its higher gain. At the output, the gain-of-two clamping. The other is the droop associated with the capacitor produces a signal swing of 1.4 V, but the ac-coupling doubles discharge due to the input bias current of the AD8189. For the this required amount to 2.8 V. The AD8189 outputs can only former, it is better to have a small capacitor, but for the latter, a swing from 1.4 V to 3.6 V on a 5 V supply, so there are only larger capacitor is better. 2.2 V of dynamic signal swing available at the output. The on resistance of the ADG786 and the coupling capacitor A standard means for reducing the dynamic range requirements form the time constant of the input clamp. The ADG786 on of an ac-coupled video signal is to use a dc restore. This circuit resistance is 5 Ω maximum. With a 0.1 μF capacitor, a time works to limit the dynamic range requirements by clamping the constant of 0.5 μs is created. Thus, a sync pulse of greater than black level of the video signal to a fixed level at the input to the 2.5 μs causes less than 1% error. This is not critical because the amplifier. This prevents the video content of the signal from black level from successive lines is very close and the voltage varying the black level, as happens in a simple ac-coupled circuit. changes little from line to line. DC RESTORE A rough approximation of the horizontal line time for a graphics After ac-coupling a video signal, it is necessary to use a dc system is 30 μs. This varies depending on the resolution and the restore to establish where the black level is. Usually, this appears vertical rate. The coupling capacitor needs to hold the voltage at the end of a video signal chain. This dc restore circuit needs relatively constant during this time, while the input bias current to have the required accuracy for the system. It compensates for of the AD8189 discharges it. all the offsets of the preceding stages. Therefore, if a dc restore The change in voltage is I times the line time divided by the B circuit is to be used only for dynamic range limiting, it does not capacitance. With an I of 2.5 μA, a line time of 30 μs, and a B require great dc accuracy. 0.1 μF coupling capacitor, the amount of droop is 0.75 mV. This A dc restore circuit using the AD8189 is shown in Figure 56. is roughly 0.1% of the full video amplitude and is not observable Two separate sources of RGB video are ac-coupled to the 0.1 μF in the video display. 5V 3V TO 5V 5V VDD 0.1µF IN0A DVCC VCC ADG786 REDA AD8189 S1A 0.1µF IN1A D1 S1B GRNA ×2 OUT0 RED 0.1µF IN2A BLUA 5V VREF 3.48kΩ 1.+5V D2 SS22AB VREF VREF ×2 OUT1 GRN 1.5kΩ 10µF 0.1µF D3 S3A REDB 0.1µF IN0B ×2 OUT2 BLU S3B 0.1µF IN1B GRNB GND VSS BLUB 0.1µF IN2B LOGIC DGND VEE SEL A/B OE HSYNC 2.4V MIN EN A0 A1 A2 0.8V MIN SEL A/B 06239-056 Figure 56. AD8189 AC-Coupled with DC Restore Rev. 0 | Page 19 of 24

AD8188/AD8189 HIGH SPEED DESIGN CONSIDERATIONS The AD8188/AD8189 are extremely high speed switching very close to the pins of the part with minimum extra circuit amplifiers for routing the highest resolution graphic signals. length in the path. It is also helpful to have a large V plane on CC Extra care is required in the circuit design and layout to ensure a circuit board layer that is closely spaced to the ground plane. that the full resolution of the video is realized. This creates a low inductance interplane capacitance, which is very helpful in supplying the fast transient currents that the part First, the board should have at least one layer of a solid ground demands during high resolution signal transitions. plane. Long signal paths should be referenced to a ground plane as controlled-impedance traces. All bypass capacitors should be Rev. 0 | Page 20 of 24

AD8188/AD8189 EVALUATION BOARD An evaluation board has been designed and is offered for The logic control signals can be statically set by adding or running the AD8188/AD8189 on a single supply. The inputs removing a jumper. If a fast signal is required to drive the logic and outputs are ac-coupled and terminated with 75 Ω resistors. pins, an SMA connector can be used to deliver the signal, and a For the AD8189, a potentiometer is provided to allow setting place for a termination resistor is provided. V at any value between V and ground. REF CC 06239-057 Figure 57. Component Side Board Layout 06239-058 Figure 58. Circuit Side Board Layout Rev. 0 | Page 21 of 24

AD8188/AD8189 06239-059 Figure 59. Component Side Silkscreen 06239-060 Figure 60. Circuit Side Silkscreen Rev. 0 | Page 22 of 24

AD8188/AD8189 SCHEMATICS VCC E EL A/B UT0 UT1 UT2 160-93260 O S O O O D D D D D N N N N N G G G G G A A A A A CC CC C180.1µF C190.1µF C200.1µF V R231kΩ V R241kΩ VCC W1 ANDGND R20*W2TBD AAGNDGND R10*TBD AGND R12*TBD AGND R14*TBD AGND AGND R19*TBD AG VCC R975Ω R1175Ω R1375Ω C1510µF GND C70.1µF AGND VCC C1610µF AGND 0F A C11µ 0. D 7F GN C11µ A 0. 4 2GND3GND AGND DUT 24VCC23OE22SEL A/B21VCC20OUT019VEE18OUT117VCC16OUT215VEE14DVCC13VCC D8188/D8189VCC VCC C120.1µF AGND 1GND IN0A DGND IN1A VREF IN2A VCC VEE IN2B VEE IN1B VEE IN0B AA GND 1 2 3 4 5 6 7 8 9 10 11 12 GND ES. A S REF RPO V 2Ω U R24.99k EST P T R VREF R154.99kΩ C140.01µF VREF R174.99kΩ VREF R184.99kΩ VREF R214.99kΩ ON BOARD FO C10.1µF D C40.1µF D C240.1µF AGND VCC C30.1µF AGND C60.1µF C80.1µF C90.1µF D ON EVALUATI N N E G G L R475Ω A R575Ω A VREF 6Ω STAL VCC R1VREF CW C1310µF R1AGND4.99k R6C575Ω0.1µFDAGND BR775ΩAGNDAGND BR375ΩAGNDAGND BR875ΩAGNDAGND 4, R19, AND R20 NOT INSED FOR AD8188. AGND IN2A AGN IN2 IN1 IN0 10, R12, R11 IS NOT U D D RR N N * A AG A AG REF N0 N1 V I I Figure 61. Single-Supply Evaluation Board Rev. 0 | Page 23 of 24

AD8188/AD8189 OUTLINE DIMENSIONS 7.90 7.80 7.70 24 13 4.50 4.40 4.30 6.40 BSC 1 12 PIN 1 0.65 1.20 BSC MAX 0.15 0.05 8° 0.75 0.30 SEATING 0.20 0° 0.60 0.19 PLANE 0.09 0.45 0.10 COPLANARITY COMPLIANT TO JEDEC STANDARDS MO-153-AD Figure 62. 24-Lead Thin Shrink Small Outline Package [TSSOP] [RU-24] Dimensions shown in millimeters ORDERING GUIDE Model Temperature Range Package Description Package Option AD8188ARUZ1 –40°C to +85°C 24-Lead Thin Shrink Small Outline Package [TSSOP] RU-24 AD8188ARUZ-RL1 –40°C to +85°C 24-Lead Thin Shrink Small Outline Package [TSSOP], 13" Reel RU-24 AD8188ARUZ-R71 –40°C to +85°C 24-Lead Thin Shrink Small Outline Package [TSSOP], 7" Reel RU-24 AD8189ARUZ1 –40°C to +85°C 24-Lead Thin Shrink Small Outline Package [TSSOP] RU-24 AD8189ARUZ-RL1 –40°C to +85°C 24-Lead Thin Shrink Small Outline Package [TSSOP], 13" Reel RU-24 AD8189ARUZ-R71 –40°C to +85°C 24-Lead Thin Shrink Small Outline Package [TSSOP], 7" Reel RU-24 AD8188Z-EVALZ1 Evaluation Board AD8189Z-EVALZ1 Evaluation Board 1 Z = Pb-free part. ©2006 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D06239-0-10/06(0) Rev. 0 | Page 24 of 24