a High Speed, Low Power Wide Supply Range Amplifier AD817 FEATURES CONNECTION DIAGRAM Low Cost 8-Pin Plastic Mini-DIP (N) and High Speed SOIC (R) Packages 50 MHz Unity Gain Bandwidth 350 V/(cid:109)s Slew Rate 45 ns Settling Time to 0.1% (10 V Step) NULL 1 AD817 8 NULL Flexible Power Supply Specified for Single (+5 V) and –IN 2 7 +VS Dual ((cid:54)5 V to (cid:54)15 V) Power Supplies +IN 3 6 OUTPUT Low Power: 7.5 mA max Supply Current High Output Drive Capability –VS 4 5 NC Drives Unlimited Capacitive Load TOP VIEW 50 mA Minimum Output Current NC = NO CONNECT Excellent Video Performance 70 MHz 0.1 dB Bandwidth (Gain = +1) The AD817 is fully specified for operation with a single +5 V 0.04% & 0.08(cid:56) Differential Gain & Phase Errors power supply and with dual supplies from – 5 V to – 15 V. This @ 3.58 MHz power supply flexibility, coupled with a very low supply current Available in 8-Pin SOIC and 8-Pin Plastic Mini-DIP of 7.5 mA and excellent ac characteristics under all power sup- ply conditions, make the AD817 the ideal choice for many de- manding yet power sensitive applications. PRODUCT DESCRIPTION The AD817 is a low cost, low power, single/dual supply, high In applications such as ADC buffers and line drivers the AD817 speed op amp which is ideally suited for a broad spectrum of simplifies the design task with its unique combination of a signal conditioning and data acquisition applications. This 50 mA minimum output current and the ability to drive breakthrough product also features high output current drive unlimited capacitive loads. capability and the ability to drive an unlimited capacitive load The AD817 is available in 8-pin plastic mini-DIP and SOIC while still maintaining excellent signal integrity. packages. The 50 MHz unity gain bandwidth, 350 V/m s slew rate and set- ORDERING GUIDE tling time of 45 ns (0.1%) make possible the processing of high speed signals common to video and imaging systems. Further- Temperature Package Package more, professional video performance is attained by offering dif- Model Range Description Option ferential gain & phase errors of 0.04% & 0.08(cid:176) @ 3.58 MHz and 0.1 dB flatness to 70 MHz (gain = +1). AD817AN –40(cid:176) C to +85(cid:176) C 8-Pin Plastic DIP N-8 AD817AR –40(cid:176) C to +85(cid:176) C 8-Pin Plastic SOIC R-8 1kW 3.3m F 5V 500ns +VS 100 0.01m F 90 100pF PUHLPSE VIN 1kW 7 LOAD GENERATOR 50W 2 AD817 6 VOUT TPE6PK2RT0OR1 BOFENETIX 3 4 0.01m F C10L00pF 10 0% 1000pF 3.3m F LOAD –VS AD817 Driving a Large Capacitive Load REV.B Information furnished by Analog Devices is believed to be accurate and © Analog Devices, Inc., 1995 reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or One Technology Way, P.O. Box 9106, Norwood. MA 02062-9106, U.S.A. otherwise under any patent or patent rights of Analog Devices. Tel: 617/329-4700 Fax: 617/326-8703

AD817–SPECIFICATIONS (@ T = +25(cid:56)C, unless otherwise noted) A AD817A Parameter Conditions V Min Typ Max Units S DYNAMIC PERFORMANCE Unity Gain Bandwidth – 5 V 30 35 MHz – 15 V 45 50 MHz 0, +5 V 25 29 MHz Bandwidth for 0.1 dB Flatness Gain = +1 – 5 V 18 30 MHz – 15 V 40 70 MHz 0, +5 V 10 20 MHz Full Power Bandwidth1 V = 5 V p-p OUT R = 500 W – 5 V 15.9 MHz LOAD V = 20 V p-p OUT R = 1 kW – 15 V 5.6 MHz LOAD Slew Rate R = 1 kW – 5 V 200 250 V/m s LOAD Gain = 1 – 15 V 300 350 V/m s 0, +5 V 150 200 V/m s Settling Time to 0.1% –2.5 V to +2.5 V – 5 V 45 ns 0 V–10 V Step, A = –1 – 15 V 45 ns V Settling Time to 0.01% –2.5 V to +2.5 V – 5 V 70 ns 0 V–10 V Step, A = –1 – 15 V 70 ns V Total Harmonic Distortion F = 1 MHz – 15 V 63 dB C Differential Gain Error NTSC – 15 V 0.04 0.08 % (R = 150 W ) Gain = +2 – 5 V 0.05 0.1 % LOAD 0, +5 V 0.11 % Differential Phase Error NTSC – 15 V 0.08 0.1 Degrees (R = 150 W ) Gain = +2 – 5 V 0.06 0.1 Degrees LOAD 0, +5 V 0.14 Degrees INPUT OFFSET VOLTAGE – 5 V to – 15 V 0.5 2 mV T to T 3 mV MIN MAX Offset Drift 10 m V/(cid:176) C INPUT BIAS CURRENT – 5 V, – 15 V 3.3 6.6 m A T 10 m A MIN T 4.4 m A MAX INPUT OFFSET CURRENT – 5 V, – 15 V 25 200 nA T to T 500 nA MIN MAX Offset Current Drift 0.3 nA/(cid:176) C OPEN LOOP GAIN V = – 2.5 V – 5 V OUT R = 500 W 2 4 V/mV LOAD T to T 1.5 V/mV MIN MAX R = 150 W 1.5 3 V/mV LOAD V = – 10 V – 15 V OUT R = 1 kW 4 6 V/mV LOAD T to T 2.5 5 V/mV MIN MAX V = – 7.5 V – 15 V OUT R = 150 W LOAD (50 mA Output) 2 4 V/mV COMMON-MODE REJECTION V = – 2.5 V – 5 78 100 dB CM V = – 12 V – 15 V 86 120 dB CM – 15 V 80 100 dB POWER SUPPLY REJECTION V = – 5 V to – 15 V 75 86 dB S T to T 72 dB MIN MAX INPUT VOLTAGE NOISE f = 10 kHz – 5 V, – 15 V 15 nV/(cid:214) Hz INPUT CURRENT NOISE f = 10 kHz – 5 V, – 15 V 1.5 pA/(cid:214) Hz –2– REV. B

AD817 AD817A Parameter Conditions V Min Typ Max Units S INPUT COMMON-MODE – 5 V +3.8 +4.3 V VOLTAGE RANGE –2.7 –3.4 V – 15 V +13 +14.3 V –12 –13.4 V 0, +5 V +3.8 +4.3 V +1.2 +0.9 V OUTPUT VOLTAGE SWING R = 500 W – 5 V 3.3 3.8 – V LOAD R = 150 W – 5 V 3.2 3.6 – V LOAD R = 1 kW – 15 V 13.3 13.7 – V LOAD R = 500 W – 15 V 12.8 13.4 – V LOAD R = 500 W 0, +5 V +1.5, LOAD +3.5 V Output Current – 15 V 50 mA – 5 V 50 mA 0, +5 V 30 mA Short-Circuit Current – 15 V 90 mA INPUT RESISTANCE 300 kW INPUT CAPACITANCE 1.5 pF OUTPUT RESISTANCE Open Loop 8 W POWER SUPPLY Operating Range Dual Supply – 2.5 – 18 V Single Supply +5 +36 V Quiescent Current – 5 V 7.0 7.5 mA T to T – 5 V 7.5 mA MIN MAX – 15 V 7.5 mA T to T – 15 V 7.0 7.5 mA MIN MAX NOTES 1Full power bandwidth = slew rate/2 p V . PEAK Specifications subject to change without notice. ABSOLUTE MAXIMUM RATINGS1 2.0 SupplyVoltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 18V InternalPowerDissipation2 atts 8-PIN MINI-DIP PACKAGE TJ = +150(cid:176)C W Plastic(N) . . . . . . . . . . . . . . . . . . . . . . See Derating Curves – SmallOutline(R) . . . . . . . . . . . . . . . . . See Derating Curves ON 1.5 TI IDnipffuetr eVnotlitaalgIen p(CutoVmomltoange M .o .d .e ). . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .– –6VVS SSIPA DI Output Short Circuit Duration . . . . . . . . See Derating Curves R 1.0 E Storage Temperature Range N, R . . . . . . . . .–65(cid:176) C to +125(cid:176) C OW Operating Temperature Range . . . . . . . . . . . . –40(cid:176) C to +85(cid:176) C M P 8-PIN SOIC PACKAGE Lead Temperature Range (Soldering10sec) . . . . . . . . +300(cid:176) C MU0.5 XI A NOTES M 1Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional 0 –50–40–30–20–10 0 10 20 30 40 50 60 70 80 90 operation of the device at these or any other conditions above those indicated in the AMBIENT TEMPERATURE – (cid:176)C operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2Specification is for device in free air: 8-pin plastic package: q = 100(cid:176)C/watt; JA Maximum Power Dissipation vs. Temperature 8-pin SOIC package: q = 160(cid:176)C/watt. JA CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily WARNING! accumulate on the human body and test equipment and can discharge without detection. Although the AD817 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. ESD SENSITIVE DEVICE REV. B –3–

AD817–Typical Characteristics 20 8.0 s olt A V m –E – 15 NT – 7.5 G E RAN +VCM URR +85(cid:176)C +25(cid:176)C ODE 10 LY C7.0 ON-M –VCM SUPP -40(cid:176)C M T M N T CO 5 ESCE6.5 NPU QUI I 0 6.0 0 5 10 15 20 0 5 10 15 20 SUPPLY VOLTAGE – – Volts SUPPLY VOLTAGE – – Volts Figure 1.Common-Mode Voltage Range vs. Supply Figure 4.Quiescent Supply Current vs. Supply Voltage for Various Temperatures 20 400 s olt V15 350 –– G s GE SWIN10 RL = 500W mATE – V/300 A R LT W O E T V RL = 150W SL U P 5 250 T U O 0 200 0 5 10 15 20 0 5 10 15 20 SUPPLY VOLTAGE – – Volts SUPPLY VOLTAGE – – Volts Figure 2.Output Voltage Swing vs. Supply Figure 5.Slew Rate vs. Supply Voltage 30 100 s m h p O s p-25 E – G – Volt20 VS = – 15V EDANC 10 N P VOLTAGE SWI1150 OP OUTPUT IM 1 OUTPUT 5 VS = – 5V OSED-LO0.1 L C 0 0.01 10 100 1k 10k 1k 10k 100k 1M 10M 100M LOAD RESISTANCE – W FREQUENCY – Hz Figure 3.Output Voltage Swing vs. Load Resistance Figure 6.Closed-Loop Output Impedance vs. Frequency –4– REV. B

AD817 7 100 +100 PHASE – 5V OR – 15V SUPPLIES 6 80 +80 s e mBIAS CURRENT – A45 N-LOOP GAIN – dB4600 GAIN – 5V GSAUIPNP –L1IE5VS SUPPLIES ++4600 ASE MARGIN – Degre T 3 E20 +20 H U P P P O N I 2 0 0 R = 1kW L 1 –20 –60 –40 –20 0 20 40 60 80 100 120 140 1k 10k 100k 1M 10M 100M 1G TEMPERATURE – (cid:176)C FREQUENCY – Hz Figure 7.Input Bias Current vs. Temperature Figure 10.Open-Loop Gain and Phase Margin vs. Frequency 130 7 – 15V 6 mA110 NT – SOURCE CURRENT V/mV5 RRE 90 N – – 5V U AI UIT C SINK CURRENT OP G4 RC 70 LO ORT CI OPEN-3 SH 50 2 30 1 –60 –40 –20 0 20 40 60 80 100 120 140 100 1k 10k TEMPERATURE – (cid:176)C LOAD RESISTANCE – Ohms Figure 8.Short Circuit Current vs. Temperature Figure 11.Open Loop Gain vs. Load Resistance 100 100 90 80 s80 80 egree PHASE MARGIN MHz 70 PSOUPSPITLIVYE MARGIN – D60 GAIN BANDWIDTH 60NDWIDTH – PSR – dB5600 NSUEGPPALTYIVE SE BA 40 A N PH40 40GAI 30 Y T NI 20 U 20 20 10 –60 –40 –20 0 20 40 60 80 100 120 140 100 1k 10k 100k 1M 10M 100M TEMPERATURE – (cid:176)C FREQUENCY – Hz Figure 9.Unity Gain Bandwidth and Phase Margin Figure 12.Power Supply Rejection vs. Frequency vs. Temperature REV. B –5–

AD817–Typical Characteristics 120 –40 VIN = 1V p-p GAIN = +2 –50 B 100 d N – –60 O B RTI R – d80 STO–70 M DI 2nd HARMONIC C C NI O–80 M 60 AR 3rd HARMONIC H –90 40 –100 1k 10k 100k 1M 10M 100 1k 10k 100k 1M 10M FREQUENCY – Hz FREQUENCY – Hz Figure 13.Common-Mode Rejection vs. Frequency Figure 16.Harmonic Distortion vs. Frequency 30 50 s p-p RL = 1kW V/ Hz40 TAGE – Volt20 E NOISE – n30 L G VO RL = 150W TA20 UT 10 OL TP T V U U O P10 N I 0 0 100k 1M 10M 100M 3 10 100 1k 10k 100k 1M 10M FREQUENCY – Hz FREQUENCY – Hz Figure 14.Large Signal Frequency Response Figure 17.Input Voltage Noise Spectral Density 10 380 0.1% 8 V 6 –O 360 T 4 OM 0 2 1% 0.01% mV/s R – NG F 0 ATE 340 PUT SWI––42 1% 0.01% SLEW R T U 320 O–6 0.1% –8 –100 20 40 60 80 100 120 140 160 300 –60 –40 –20 0 20 40 60 80 100 120 140 SETTLING TIME – ns TEMPERATURE – (cid:176)C Figure 15.Output Swing and Error vs. Settling Time Figure 18.Slew Rate vs. Temperature –6– REV. B

AD817 0.05 ent 1kW DIFF GAIN c er 0.04 N – P +VS 3.3m F AI G L 0.01m F A es 0.1 0.03 NTI gre RE 7 PHASE – De0.08 DIFF PHASE DIFFE HPO(SUPRSL )FSUEN (CLSTI)ON VIN 100W 23AD48170.061mVFOUT TPE6PK2RT0OR1 BOFENETIX TEPKR7TEARA2O4MNPIX L GENERATOR 50W TIA0.06 3.3m F RL N E R FE –VS DIF0.04– 5 – 10 – 15 SUPPLY VOLTAGE – Volts Figure 19.Differential Gain and Phase vs. Figure 22.Noninverting Amplifier Connection Supply Voltage 5 34 VIN 1kWCC 1kW VOUT V–– 51SV5V C34ppCFF 110F64.L1MMAdHHTBzzNESS 19000 5V 50ns 2 +5V 6pF 12MHz 1 N – dB 0 VS = – 15V AI G–1 –2 VS = – 5V 10 –3 0% –4 VS = +5V 5V –5 100k 1M 10M 100M FREQUENCY – Hz Figure 20.Closed-Loop Gain vs. Frequency, Figure 23.Noninverting Large Signal Pulse Gain = –1 Response, R = 1 kW L 5 4 1kW VS 0F.L1AdTBNESS 200mV 20ns 3 – 15V 70MHz 100 2 VIN 150VWOUT –+55VV 2167MMHHzz 90 dB 1 VS = – 15V N – 0 AI G–1 VS = – 5V –2 10 0% –3 VS = +5V –4 200mV –5 100k 1M 10M 100M FREQUENCY – Hz Figure 21.Closed-Loop Gain vs. Frequency, Figure 24.Noninverting Small Signal Pulse Gain = +1 Response, R = 1 kW L REV. B –7–

AD817–Typical Characteristics 5V 50ns 5V 50ns 100 100 90 90 10 10 0% 0% 5V 5V Figure 25.Noninverting Large Signal Pulse Figure 28.Inverting Large Signal Pulse Response, R = 150 W Response, R = 1 kW L L 200mV 20ns 200mV 50ns 100 100 90 90 10 10 0% 0% 200mV 200mV Figure 26.Noninverting Small Signal Pulse Figure 29.Inverting Small Signal Pulse Response, R = 150 W Response, R = 1 kW L L 1kW 3.3m F +VS 0.01m F HPUPLSE (LSIG) VIN 1RkIWN 7 O(SRS IGFU)NCTION 2AD817 6VOUT TPE6K2T0R1 OFENTIX TEK7TAR2O4NIX GENERATOR 50W PROBE PREAMP 3 4 0.01m F 3.3m F RL –VS Figure 27.Inverting Amplifier Connection –8– REV. B

AD817 DRIVING CAPACITIVE LOADS +VS The internal compensation of the AD817, together with its high output current drive, permit excellent large signal performance while driving extremely high capacitive loads. 1kW OUTPUT +VS 3.3m F CF –IN 0.01m F RIN HP VIN 1kW 7 GENPEURLSAETOR 2AD817 6VOUT TPE6K2T0R1 OFNETIX TEK7TAR2O4NIX +IN 50W PROBE PREAMP 3 4 0.01m F CL 3.3m F 1000pF –VS NULL 1 NULL 8 –VS Figure 31.Simplified Schematic Figure 30a.Inverting Amplifier Driving a 1000 pF Capacitive Load INPUT CONSIDERATIONS An input protection resistor (R in Figure 22) is required in cir- IN cuits where the input to the AD817 will be subjected to tran- 5V 500ns sient or continuous overload voltages exceeding the +6 V maximum differential limit. This resistor provides protection for 100 90 100pF the input transistors by limiting their maximum base current. For high performance circuits, it is recommended that a “bal- ancing” resistor be used to reduce the offset errors caused by bias current flowing through the input and feedback resistors. The balancing resistor equals the parallel combination of R IN and R and thus provides a matched impedance at each input F 10 1000pF terminal. The offset voltage error will then be reduced by more 0% than an order of magnitude. 5V GROUNDING & BYPASSING When designing high frequency circuits, some special precau- Figure 30b. Inverting Amplifier Pulse Response While tions are in order. Circuits must be built with short interconnect Driving Capacitive Loads leads. When wiring components, care should be taken to pro- vide a low resistance, low inductance path to ground. Sockets THEORY OF OPERATION should be avoided, since their increased interlead capacitance The AD817 is a low cost, wide band, high performance opera- can degrade circuit bandwidth. tional amplifier which effectively drives heavy capacitive or resis- Feedback resistors should be of low enough value (<1 kW ) to tive loads. It also provides a constant slew rate, bandwidth and assure that the time constant formed with the inherent stray settling time over its entire specified temperature range. capacitance at the amplifier’s summing junction will not limit The AD817 (Figure 31) consists of a degenerated NPN differ- performance. This parasitic capacitance, along with the parallel ential pair driving matched PNPs in a folded-cascode gain stage. resistance of R /R , form a pole in the loop transmission which The output buffer stage employs emitter followers in a class AB F IN may result in peaking. A small capacitance (1 pF–5 pF) may be amplifier which delivers the necessary current to the load while used in parallel with the feedback resistor to neutralize this effect. maintaining low levels of distortion. Power supply leads should be bypassed to ground as close as The capacitor, CF, in the output stage mitigates the effect of possible to the amplifier pins. Ceramic disc capacitors of 0.1 m F capacitive loads. At low frequencies, and with low capacitive are recommended. loads, the gain from the compensation node to the output is very close to unity. In this case, CF is bootstrapped and does not +VS contribute to the overall compensation capacitance of the device. As the capacitive load is increased, a pole is formed with the 2 7 output impedance of the output stage. This reduces the gain, AD817 6 and therefore, C is incompletely bootstrapped. Effectively, F 8 some fraction of C contributes to the overall compensation 3 1 F capacitance, reducing the unity gain bandwidth. As the load 4 10kW VOS ADJUST capacitance is further increased, the bandwidth continues to fall, maintaining the stability of the amplifier. –VS Figure 32. Offset Null Configuration REV. B –9–

AD817 OFFSET NULLING Measuring the rapid settling time of AD817 (45 ns to 0.1% and The input offset voltage of the AD817 is inherently very low. 70 ns to 0.01%–10 V step) requires applying an input pulse with However, if additional nulling is required, the circuit shown in a very fast edge and an extremely flat top. With the AD817 con- Figure 32 can be used. The null range of the AD817 in this con- figured in a gain of –1, a clamped false summing junction re- figuration is – 15 mV. sponds when the output error is within the sum of two diode voltages (ª1 volt). The signal is then amplified 20 times by a AD817 SETTLING TIME clamped amplifier whose output is connected directly to a sam- Settling time is comprised primarily of two regions. The first is pling oscilloscope. Figures 33 and 34 show the settling time of the slew time in which the amplifier is overdriven, where the the AD817, with a 10 volt step applied. output voltage rate of change is at its maximum. The second is the linear time period required for the amplifier to settle to s 0 olt within a specified percent of the final value. V –2 – G –4 N 10olts –6 SWI 8 – V –8 UT 6 WING –10OUTP 4 S 2 PUT O % E0.20 NG TIME TO % NAL VALUE000...1000550 0 OUT SETTLING TIME TOF FINAL VALU0000....001155050 0 50 100 150 200 250 300 350 400 TLIF FI0.15 ETO0.20 Figure 34. Settling Time in ns 0 V to –10 V S 0 50 100 150 200 250 300 350 400 Figure 33. Settling Time in ns 0 V to +10 V 2· HP2835 ERROR AMPLIFIER 1MW 15pF VERROR OUTPUT · 10 5 2H·P2835 3 AD829 6 100W SOEUTTTPLUINTG 2 4 0.47m F SHORT, DIRECT 7 CONNECTION TO 0.01m F 0.01m F TEKTRONIX TYPE 11402 OSCILLOSCOPE PREAMP ERROR 0.47m F INPUT SECTION SIGNAL OUTPUT –VS +VS 100W 1.9kW 0 TO – 10V NOTE: SPUOPWPELRY EDIL&1SA05GM NULL FSAULMSMEING UWSITEH C GIRRCOUUITN DB OPALARNDE MERCURY RELAY ADJUST NODE 7, 8 2 1kW 100W 500W 1kW GTETSNLIEG LRNEAAVTLEOLR 13 1, 14 CCA5O0BAWLXE 500W 5–18pF DUTEENSVDTIECRE TFEETK TPRROONBIEX TPO6201 50Hz 2 TEKTRONIX TYPE OUTPUT 50W AD817 6 10pF 1O1S4C0I2LLOSCOPE 3 7 SCOPE PROBE PREAMP INPUT 4 CAPACITANCE SECTION DIGITAL 2.2m F 0.01m F GROUND 2.2m F 0.01m F ANALOG +VS GROUND –VS Figure 35. Settling Time Test Circuit –10– REV. B

AD817 A HIGH PERFORMANCE ADC INPUT BUFFER +VS High performance analog to digital converters (ADCs) require input buffers with correspondingly high bandwidths and very low levels of distortion. Typical requirements include distortion R3 1kW 3.3m F levels of –60 dB to –70 dB for a 1 volt p-p signal and band- SELECT C1, R1, R2 & R3 widths of 10 MHz or more. In addition, an ADC buffer may FOR DESIRED LOW C2 0.01m F FREQUENCY CORNER. need to drive very large capacitive loads. 0.1m F R1 (R2 = R1 + R3) 9kW The circuit of Figure 36 is useful for driving high speed convert- ers such as the differential input of the AD733, 10-bit ADC. C1 2 7 COUT This circuit may be used with other converters with only minor 0.1m F AD817 6 VOUT modifications. Using the AD817 provides the user with the op- VIN 3 4 150RWL CL tion of either operating the buffer in differential mode or from a R2 200pF 10kW C3 single +5 volt supply. Operating from a +5 volt power supply 0.1m F helps to avoid overdriving the ADC—a common problem with buffers operating at higher supply voltages. Figure 37. Single Supply Amplifier Configuration SINGLE SUPPLY OPERATION Combining R3 with C2 forms a low-pass filter with a corner Another exciting feature of the AD817 is its ability to perform frequency of 1.5 kHz. This is needed to maintain amplifier well in a single supply configuration. The AD817 is ideally PSRR, since the supply is connected to V through the input IN suited for applications that require low power dissipation and divider. The values for R and C were chosen to demonstrate L L high output current and those which need to drive large capaci- the AD817’s exceptional output drive capability. In this con- tive loads, such as high speed buffering and instrumentation. figuration, the output is centered around 2.5 V. In order to eliminate the static dc current associated with this level, C3 was Referring to Figure 37, careful consideration should be given to inserted in series with R . the proper selection of component values. The choices for this L particular circuit are: R1+ R3//R2 combine with C1 to form a low frequency corner of approximately 300 Hz. 1kW +VS 0.1m F 1kW 7 2 50W AD817 6 26VINA VIN CCAOBALXE 3 4 0.1m F 500mVp-p MAX 52.5W –VS A1D0-7B7IT3 18MHz +VS ADC 0.1m F 3 7 1kW AD817 6 27 VINB 2 4 0.1m F +5V 100m F +VS –VS 25V ADREF43 COMMON 100m F 1kW RVEOFELRTAEGNCEE +2.5V 25V –5V –VS Figure 36. A Differential Input Buffer for High Bandwidth ADCs REV. B –11–

AD817 HIGH SPEED DAC BUFFER (10.24 V for a 1 kW resistor). Note that since the DAC gener- The wide bandwidth and fast settling time of the AD817 make ates a positive current to ground, the voltage at the amplifier it a very good output buffer for high speed current output D/A output will be negative. A 100 W series resistor between the converters like the AD668. As shown in Figure 38, the op amp noninverting amplifier input and ground minimizes the offset establishes a summing node at ground for the DAC output. The effects of op amp input bias currents. output voltage is determined by the amplifier’s feedback resistor +15V 5 9 10m F 6/ TO ANALOG 5– GROUND PLANE – b 0.1m F 7 0 1 MSB VCC 24 17 C 2 REFCOM 23 1V NOMINAL REFERENCE INPUT 3 REFIN1 22 10kW 4 REFIN2 21 1kW 5 AD668 IOUT 20 100W ANALOG DIGITAL INPUTS 6 RLOAD 19 AD817 OUTPUT 7 ACOM 18 ANALOG GROUND PLANE ANALOG 8 LCOM 17 SUPPLY 10m F GROUND 9 IBPO 16 0.1m F 10 V 15 –15V EE 11 THCOM 14 100pF 1kW 12 LSB VTH 13 +5V Figure 38. High Speed DAC Buffer OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 8-Pin Plastic Mini-DIP 8-Pin SOIC (N-8) (SO-8) 8 5 0.25 8 5 PIN 1 (6.35) 0.31 0.1574 (4.00) (7.87) 0.1497 (3.80) 1 4 PIN 1 1 4 0.2440 (6.20) 0.2284 (5.80) 0.30 (7.62) 0.39 (9.91) MAX REF 0.165–0.01 0(0.0.8395––00..2051) 00..11899608 ((45..8000)) 00..00109969 ((00..5205)) x 45(cid:176) (4.19–0.25) 0.0688 (1.75) 0.0098 (0.25) 0.0532 (1.35) (03.M.112I8N5) 0(4.1.587––00.0.736) 01(.0005(cid:176)1.(cid:176)218––00.0.0083) 0.0040 (0.10) 0(B.10.S52C070) 00..00119328 ((00..4395)) 00..00009785 ((00..2159)) 80(cid:176)(cid:176) 00..00510600 ((10..2471)) N U.S.A. 0(.00.1486––00..00083) (B20..S15C04) (0N0.O0.83M43) SPLEAANTEING TED I N RI P –12– REV. B

Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: A nalog Devices Inc.: AD817ANZ AD817ARZ AD817AR AD817AR-REEL AD817AR-REEL7 AD817ARZ-REEL AD817ARZ-REEL7