33 × 17, 3.2 Gbps Digital Crosspoint Switch AD8151 FEATURES APPLICATIONS Low cost High speed serial backplane routing to Sonet OC-48 33 × 17, fully differential, nonblocking array applications with FEC 3.2 Gbps per port NRZ data rate Fiber optic network switching Wide power supply range: +3.3 V, –3.3 V Fiber channel Low power LVDS 425 mA (outputs enabled) FUNCTIONAL BLOCK DIAGRAM 35 mA (outputs disabled) INP INN LV PECL- and LV ECL-compatible CS CMOS/TTL-level control inputs: 3 V to 5 V RE 33 33 Low jitter NDPOrorpoi tvhgiemersaai matz esbm itaneackrbksmlp erile naoqanuutetiip ordeunidrt ie mccutprlyere dnatn ce DA 75 OUTPUTADDRESSDECODER LFR7A1IA-R7TBNSCI×TKTH SLER7A1CA-7TBONCI×TNKHD INPUTDECODERS DIFFSM3EW3ARTI×TERC1NI7XHTIAL 1177 OOUUTTPN User-controlled voltage at the load WE AD8151 Minimize power dissipation Individual output disable for busing and reducing power UPDATE Double row latch RESET 02169-001 Buffered inputs Figure 1. 184-lead LQFP package . GENERAL DESCRIPTION The AD81511 is a member of the Xstream line of products, offering a breakthrough in digital switching and a large switch array (33 × 17) on very little power—typically less than 1.5 W. It also operates at data rates in excess of 3.2 Gbps per port, V making it suitable for Sonet OC-48 applications with DI V/ 8/10-bit forward-error correction (FEC). Furthermore, the m 0 5 price of the AD8151 makes it affordable enough to be used for 1 lower data rates. The AD8151’s flexible supply voltages allow the user to operate with either emitter-coupled logic (ECL) or positive emitter-coupled logic (PECL) data levels, and with 3.3 V for further power reduction. The control interface is CMOS- 02169-002 /TTL-compatible (3 V to 5 V). 70ps/DIV Figure 2. Eye Pattern, 3.2 Gbps, PRBS 23 Its fully differential signal path reduces jitter and crosstalk, while allowing the use of smaller, single-ended voltage swings. 1 Patent pending. The AD8151 is offered in a 184-lead LQFP package that operates over the extended commercial temperature range of 0°C to 85°C. Rev. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Tel: 781.329.4700 www.analog.com Trademarks and registered trademarks are the property of their respective owners. Fax: 781.461.3113 © 2005 Analog Devices, Inc. All rights reserved.

AD8151 TABLE OF CONTENTS Features..............................................................................................1 Control Interface............................................................................17 Applications.......................................................................................1 Control Pin Description............................................................17 Functional Block Diagram..............................................................1 Control Interface Translators....................................................18 General Description.........................................................................1 Circuit Description.........................................................................19 Revision History...............................................................................2 Applications.....................................................................................23 Specifications.....................................................................................3 Input and Output Busing..........................................................23 Absolute Maximum Ratings............................................................4 Evaluation Board........................................................................23 Maximum Power Dissipation.....................................................4 Power Supplies............................................................................24 ESD Caution..................................................................................4 Configuration Programming....................................................25 Pin Configuration and Function Descriptions.............................5 Software Installation..................................................................25 Typical Performance Characteristics.............................................9 Software Operation....................................................................26 Control Interface Truth Tables......................................................13 Outline Dimensions.......................................................................38 Control Interface Timing Diagrams............................................14 Ordering Guide..........................................................................38 Control Interface Programming Example..............................16 REVISION HISTORY 12/05—Rev. A to Rev. B Changes to Table 1............................................................................3 Changes to Figure 4..........................................................................5 Changes to Table 3............................................................................6 Changes to Table 4..........................................................................13 Changes to Figure 51......................................................................35 Changes to Ordering Guide..........................................................38 9/05—Rev. 0 to Rev. A Updated Format..............................................................Universal Change to Figure 51...................................................................34 Change to Ordering Guide........................................................37 4/01—Revision 0: Initial Version Rev. B | Page 2 of 40

AD8151 SPECIFICATIONS @ 25°C, V = 3.3 V to 5 V, V = 0 V, R = 50 Ω (see Figure 26), I = 16 mA, unless otherwise noted. CC EE L OUT Table 1. Parameter Conditions Min Typ Max Unit DYNAMIC PERFORMANCE Max Data Rate/Channel (NRZ) 2.5 3.2 Gbps Channel Jitter Data rate = 3.2 Gbps 52 ps p-p RMS Channel Jitter 8 ps Propagation Delay Input to output 650 ps Propagation Delay Match See Figure 23 ±50 ±100 ps Output Rise/Fall Time 20% to 80% 100 ps INPUT CHARACTERISTICS Input Voltage Swing Single-ended (see Figure 18) 200 1000 mV p-p Input Bias Current 2 μA Input Capacitance 2 pF Input VIN High VCC − 1.2 VCC V Input VIN Low VCC − 2.4 VCC − 1.4 V OUTPUT CHARACTERISTICS Output Voltage Swing Differential 800 mV p-p Output Voltage Range (See Figure 19) VCC − 1.8 VCC V Output Current 5 25 mA Output Capacitance 2 pF Output VOUT High VCC − 1.8 V Output V Low V V OUT CC POWER SUPPLY Operating Range PECL, V V = 0 V 3.0 5.25 V CC EE ECL, V V = 0 V –5.25 –3.0 V EE CC V 3 5 V DD V 0 V SS Quiescent Current V 2 mA DD V All outputs enabled, I = 16 mA 425 mA EE OUT T to T 450 mA MIN MAX All outputs disabled 35 mA THERMAL CHARACTERISTICS Operating Temperature Range 0 85 °C θJA 30 °C/W LOGIC INPUT CHARACTERISTICS V = 3 V dc to 5 V dc DD Input V High 1.9 V V IN DD Input V Low 0 0.9 V IN Rev. B | Page 3 of 40

AD8151 ABSOLUTE MAXIMUM RATINGS T = 25°C, unless otherwise noted. MAXIMUM POWER DISSIPATION A Table 2. The maximum power that can be safely dissipated by the Parameter Rating AD8151 is limited by the associated rise in junction Supply Voltage temperature. The maximum safe junction temperature for VDD − VEE 10.5 V plastic encapsulated devices is determined by the glass transition temperature of the plastic, approximately 150°C. VCC − VEE 5.5 V Temporarily exceeding this limit may cause a shift in VDD − VSS 5.5 V parametric performance due to a change in the stresses exerted VSS − VEE 5.5 V on the die by the package. Exceeding a junction temperature of VSS − VCC 5.5 V 175°C for an extended period can result in device failure. To VDD − VCC 5.5 V ensure proper operation, it is necessary to observe the Internal Power Dissipation maximum power derating curves shown in Figure 3. 184-Lead LQFP (ST-184) 4.2 W 6 Differential Input Voltage 2.0 V Storage Temperature Range –65°C to +125°C TJ = 150°C W) Lead Temperature (Soldering 10 sec) 300°C N ( 5 Junction Temperature, θJA 30°C/W TIO A P SI 4 S DI R Stresses above those listed under Absolute Maximum Ratings E W may cause permanent damage to the device. This is a stress O 3 P M rating only; functional operation of the device at these or any U M other conditions above those listed in the operational sections AXI 2 of this specification is not implied. Exposure to absolute M maximum rating conditions for extended periods may affect 1 02169-003 device reliability. –10 0 10 20 30 40 50 60 70 80 90 AMBIENT TEMPERATURE (°C) Figure 3. ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. Rev. B | Page 4 of 40

AD8151 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS VEEIN19NIN19PVEEIN18NIN18PVEEIN17NIN17PVEEIN16NIN16PVEEVCCVDDRESETCSREWEUPDATEA0A1A2A3A4D0D1D2D3D4D5D6VSSREFVREFEEVCCVEEIN15NIN15PVEEIN14NIN14PVEEIN13NIN13PVEE 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 8 8 8 8 7 7 7 7 7 7 7 7 7 7 6 6 6 6 6 6 6 6 6 6 5 5 5 5 5 5 5 5 5 5 4 4 4 4 4 4 4 4 4 4 3 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 VEE 1 PIN 1 138 VEE IN20P 2 INDICATOR 137 IN12N IN20N 3 136 IN12P VEE 4 135 VEE IN21P 5 134 IN11N IN21N 6 133 IN11P VEE 7 132 VEE IN22P 8 131 IN10N IN22N 9 130 IN10P VEE 10 129 VEE IN23P 11 128 IN09N IN23N 12 127 IN09P VEE 13 126 VEE IN24P 14 125 IN08N IN24N 15 124 IN08P VEE 16 123 VEE IN25P 17 122 IN07N IN25N 18 121 IN07P VEE 19 120 VEE IN26P 20 119 IN06N IN26N 21 AD8151 118 IN06P VEE 22 184L LQFP 117 VEE IN27P 23 TOP VIEW 116 IN05N IN27N 24 (Not to Scale) 115 IN05P VEE 25 114 VEE IN28P 26 113 IN04N IN28N 27 112 IN04P VEE 28 111 VEE IN29P 29 110 IN03N IN29N 30 109 IN03P VEE 31 108 VEE IN30P 32 107 IN02N IN30N 33 106 IN02P VEE 34 105 VEE IN31P 35 104 IN01N IN31N 36 103 IN01P VEE 37 102 VEE IN32P 38 101 IN00N IN32N 39 100 IN00P VEE 40 99 VEE VCC 41 98 VCC VEE 42 97 VEEA0 OUT16N 43 96 OUT00P OUT16P 44 95 OUT00N VEEA16 45 94 VEEA1 VEE 46 93 VEE 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 4 4 4 5 5 5 5 5 5 5 5 5 5 6 6 6 6 6 6 6 6 6 6 7 7 7 7 7 7 7 7 7 7 8 8 8 8 8 8 8 8 8 8 9 9 9 ENP5NP4NP3NP2NP1NP0NP9NP8NP7NP6NP5NP4NP3NP2NP E VEOUT15OUT15VA1EEOUT14OUT14VA1EEOUT13OUT13VA1EEOUT12OUT12VA1EEOUT11OUT11VA1EEOUT10OUT10VA1EEOUT09OUT09VAEEOUT08OUT08VAEEOUT07OUT07VAEEOUT06OUT06VAEEOUT05OUT05VAEEOUT04OUT04VAEEOUT03OUT03VAEEOUT02OUT02VAEEOUT01OUT01VE 02169-004 Figure 4. Pin Configuration Rev. B | Page 5 of 40

AD8151 Table 3. Pin Function Descriptions Pin No. Mnemonic Type Description 1, 4, 7, 10, 13, 16, 19, 22, 25, 28, 31, V Power Supply Most Negative PECL Supply (Common with Other Points Labeled EE 34, 37, 40, 42, 46, 47, 92, 93, 99, V ) EE 102, 105, 108, 111, 114, 117, 120, 123, 126, 129, 132, 135, 138, 139, 142, 145, 148, 172, 175, 178, 181, 184 2 IN20P PECL/ECL High Speed Input 3 IN20N PECL/ECL High Speed Input Complement 5 IN21P PECL/ECL High Speed Input 6 IN21N PECL/ECL High Speed Input Complement 8 IN22P PECL/ECL High Speed Input 9 IN22N PECL/ECL High Speed Input Complement 11 IN23P PECL/ECL High Speed Input 12 IN23N PECL/ECL High Speed Input Complement 14 IN24P PECL/ECL High Speed Input 15 IN24N PECL/ECL High Speed Input Complement 17 IN25P PECL/ECL High Speed Input 18 IN25N PECL/ECL High Speed Input Complement 20 IN26P PECL/ECL High Speed Input 21 IN26N PECL/ECL High Speed Input Complement 23 IN27P PECL/ECL High Speed Input 24 IN27N PECL/ECL High Speed Input Complement 26 IN28P PECL/ECL High Speed Input 27 IN28N PECL/ECL High Speed Input Complement 29 IN29P PECL/ECL High Speed Input 30 IN29N PECL/ECL High Speed Input Complement 32 IN30P PECL/ECL High Speed Input 33 IN30N PECL/ECL High Speed Input Complement 35 IN31P PECL/ECL High Speed Input 36 IN31N PECL/ECL High Speed Input Complement 38 IN32P PECL/ECL High Speed Input 39 IN32N PECL/ECL High Speed Input Complement 41, 98, 149, 171 V Power Supply Most Positive PECL Supply (Common with Other Points Labeled V ) CC CC 43 OUT16N PECL/ECL High Speed Output Complement 44 OUT16P PECL/ECL High Speed Output 45 V A16 Power Supply Most Negative PECL Supply (Unique to this Output) EE 48 OUT15N PECL/ECL High Speed Output Complement 49 OUT15P PECL/ECL High Speed Output 50 V A15 Power Supply Most Negative PECL Supply (Unique to this Output) EE 51 OUT14N PECL/ECL High Speed Output Complement 52 OUT14P PECL/ECL High Speed Output 53 V A14 Power Supply Most Negative PECL Supply (Unique to this Output) EE 54 OUT13N PECL/ECL High Speed Output Complement 55 OUT13P PECL/ECL High Speed Output 56 V A13 Power Supply Most Negative PECL Supply (Unique to this Output) EE 57 OUT12N PECL/ECL High Speed Output Complement 58 OUT12P PECL/ECL High Speed Output 59 V A12 Power Supply Most Negative PECL Supply (Unique to this Output) EE 60 OUT11N PECL/ECL High speed Output Complement 61 OUT11P PECL/ECL High speed Output 62 V A11 Power Supply Most Negative PECL Supply (Unique to this Output) EE 63 OUT10N PECL/ECL High Speed Output Complement Rev. B | Page 6 of 40

AD8151 Pin No. Mnemonic Type Description 64 OUT10P PECL/ECL High Speed Output 65 V A10 Power Supply Most Negative PECL Supply (Unique to this Output) EE 66 OUT09N PECL/ECL High Speed Output Complement 67 OUT09P PECL/ECL High Speed Output 68 V A9 Power Supply Most Negative PECL Supply (Unique to this Output) EE 69 OUT08N PECL/ECL High speed Output Complement 70 OUT08P PECL/ECL High Speed Output 71 V A8 Power Supply Most Negative PECL Supply (Unique to this Output) EE 72 OUT07N PECL/ECL High Speed Output Complement 73 OUT07P PECL/ECL High Speed Output 74 V A7 Power Supply Most Negative PECL Supply (Unique to this Output) EE 75 OUT06N PECL/ECL High Speed Output Complement 76 OUT06P PECL/ECL High Speed Output 77 V A6 Power Supply Most Negative PECL Supply (Unique to this Output) EE 78 OUT05N PECL/ECL High Speed Output Complement 79 OUT05P PECL/ECL High Speed Output 80 V A5 Power Supply Most Negative PECL Supply (Unique to this Output) EE 81 OUT04N PECL/ECL High Speed Output Complement 82 OUT04P PECL/ECL High Speed Output 83 V A4 Power Supply Most Negative PECL Supply (Unique to this Output) EE 84 OUT03N PECL/ECL High Speed Output Complement 85 OUT03P PECL/ECL High Speed Output 86 V A3 Power Supply Most Negative PECL Supply (Unique to this Output) EE 87 OUT02N PECL/ECL High Speed Output Complement 88 OUT02P PECL/ECL High Speed Output 89 V A2 Power Supply Most Negative PECL Supply (Unique to this Output) EE 90 OUT01N PECL/ECL High Speed Output Complement 91 OUT01 P PECL/ECL High Speed Output 94 V A1 Power Supply Most Negative PECL Supply (Unique to this Output) EE 95 OUT00N PECL/ECL High Speed Output Complement 96 OUT00P PECL/ECL High Speed Output 97 V A0 Power Supply Most Negative PECL Supply (Unique to this Output) EE 100 IN00P PECL/ECL High Speed Input 101 IN00N PECL/ECL High Speed Input Complement 103 IN01P PECL/ECL High Speed Input 104 IN01N PECL/ECL High Speed Input Complement 106 IN02P PECL/ECL High Speed Input 107 IN02N PECL/ECL High Speed Input Complement 109 IN03P PECL/ECL High Speed Input 110 IN03N PECL/ECL High Speed Input Complement 112 IN04P PECL/ECL High Speed Input 113 IN04N PECL/ECL High Speed Input Complement 115 IN05P PECL/ECL High Speed Input 116 IN05N PECL/ECL High Speed Input Complement 118 IN06P PECL/ECL High Speed Input 119 IN06N PECL/ECL High Speed Input Complement 121 IN07P PECL/ECL High Speed Input 122 IN07N PECL/ECL High Speed Input Complement 124 IN08P PECL/ECL High Speed Input 125 IN08N PECL/ECL High Speed Input Complement 127 IN09P PECL/ECL High Speed Input 128 IN09N PECL/ECL High Speed Input Complement Rev. B | Page 7 of 40

AD8151 Pin No. Mnemonic Type Description 130 IN10P PECL/ECL High Speed Input 131 IN10N PECL/ECL High Speed Input Complement 133 IN11P PECL/ECL High Speed Input 134 IN11N PECL/ECL High Speed Input Complement 136 IN12P PECL/ECL High Speed Input 137 IN12N PECL/ECL High Speed Input Complement 140 IN13P PECL/ECL High Speed Input 141 IN13N PECL/ECL High Speed Input Complement 143 IN14P PECL/ECL High Speed Input 144 IN14N PECL/ECL High Speed Input Complement 146 IN15P PECL/ECL High Speed Input 147 IN15N PECL/ECL High Speed Input Complement 150 V REF R Program Connection Point for Output Logic Pull-Down Programming Resistor EE (Must be Connected to V ) EE 151 REF R Program Connection Point for Output Logic Pull-Down Programming Resistor 152 V Power Supply Most Negative Control Logic Supply SS 153 D6 TTL Enable/Disable Output 154 D5 TTL Bit 32—MSB Input Select 155 D4 TTL Bit 16 156 D3 TTL Bit 8 157 D2 TTL Bit 4 158 D1 TTL Bit 2 159 D0 TTL Bit 1—LSB Input Select 160 A4 TTL Bit 16—MSB Output Select 161 A3 TTL Bit 8 162 A2 TTL Bit 4 163 A1 TTL Bit 2 164 A0 TTL Bit 1—LSB Output Select 165 UPDATE TTL Second Rank Program 166 WE TTL First Rank Program 167 RE TTL Enable Readback 168 CS TTL Enable Chip to Accept Programming 169 RESET TTL Disable All Outputs (Hi-Z) 170 V Power Supply Most Positive Control Logic Supply DD 173 IN16P PECL/ECL High Speed Input 174 IN16N PECL/ECL High Speed Input Complement 176 IN17P PECL/ECL High Speed Input 177 IN17N PECL/ECL High Speed Input Complement 179 IN18P PECL/ECL High Speed Input 180 IN18N PECL/ECL High Speed Input Complement 182 IN19P PECL/ECL High Speed Input 183 IN19N PECL/ECL High Speed Input Complement Rev. B | Page 8 of 40

AD8151 TYPICAL PERFORMANCE CHARACTERISTICS V V DI DI V/ V/ m m 0 0 5 5 1 1 02169-005 02169-008 100ps/DIV 70ps/DIV Figure 5. Eye Pattern 2.5 Gbps, PRBS 23 Figure 8. Eye Pattern 3.2 Gbps, PRBS 23 p-p = 43ps p-p = 53ps STD DEV = 8ps STD DEV = 8ps V V DI DI V/ V/ m m 0 0 5 5 1 1 02169-006 02169-009 20ps/DIV 20ps/DIV Figure 6. Jitter @ 2.5 Gbps, PRBS 23 Figure 9. Jitter @ 3.2 Gbps, PRBS 23 100 100 90 90 80 80 70 70 %) %) EYE WIDTH ( 654000 % EYE WIDTH =(CLOCKC PLEORCIKO DPE–R JIIOTDTER p-p) × 100 EYE HEIGHT ( 654000 % EYE HEIGHT =(VOVUOTU @T @ D A0T.5AG RbpAsTE) × 100 30 30 20 20 100 02169-007 100 02169-010 0.5 1.0 1.5 2.0 2.5 3.0 3.5 0.5 1.0 1.5 2.0 2.5 3.0 3.5 DATA RATE (Gbps) DATA RATE (Gbps) Figure 7. Eye Width vs. Data Rate, PRBS 23 Figure 10. Eye Height vs. Data Rate, PRBS 23 Rev. B | Page 9 of 40

AD8151 100 100 90 90 80 80 70 70 ER (ps) 6500 PEAK-PEAK ER (ps) 6500 3.2Gbps JITTER JITT 40 JITTER JITT 40 30 30 2.5Gbps JITTER 20 20 100 STANDARD DEVIATION 02169-011 100 3.2Gbps STD DEV 2.5Gbps STD DEV 02169-014 1.0 1.5 2.0 2.5 3.0 3.5 0 10 20 30 40 50 60 70 80 90 DATA RATE (Gbps) TEMPERATURE (°C) Figure 11. Jitter vs. Data Rate, PRBS 23 Figure 14. Jitter vs. Temperature, PRBS 23 p-p = 38ps STD DEV = 7.7ps V V DI DI V/ V/ m m 150 150 02169-012 pS-TpD = D 3E2Vp s= 4.7ps 02169-015 100ps/DIV 75ps/DIV Figure 12. Crosstalk, 2.5 Gbps, PRBS 23, Attack Signal Is Off Figure 15. Crosstalk, 3.2 Gbps, PRBS 23, Attack Signal Is Off p-p = 70ps STD DEV = 8ps V V DI DI V/ V/ m m 150 150 02169-013 pS-TpD = D 7E0Vp s= 9ps 02169-016 100ps/DIV 75ps/DIV Figure 13. Crosstalk, 2.5 Gbps, PRBS 23, Attack Signal Is On Figure 16. Crosstalk, 3.2 Gbps, PRBS 23, Attack Signal Is On Rev. B | Page 10 of 40

AD8151 p-p = 43ps p-p = 43ps STD DEV = 8ps STD DEV = 8ps V V DI DI V/ V/ m m 0 0 5 5 1 1 02169-017 02169-020 1.4ns/DIV 1.1ns/DIV Figure 17. Response, 2.5 Gbps, Figure 20. Response, 3.2 Gbps, 32-Bit Pattern 1111 1111 0000 0000 0101 0101 0011 0011 32-Bit Pattern 1111 1111 0000 0000 0101 0101 0011 0011 100 100 90 90 80 80 ps) ps) 3.2Gbps R ( 70 R ( 70 E E TT 60 TT 60 JI JI AK 50 2.5Gbps JITTER AK 50 E E P P 2.5Gbps O- 40 O- 40 T T AK- 30 AK- 30 PE 3.2Gbps JITTER PE 20 20 100 02169-018 100 02169-021 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 –5.0 –4.8 –4.6 –4.4 –4.2 –4.0 –3.8 –3.6 –3.4 –3.2 –3.0 INPUT AMPLITUDE (V) VEE (V) Figure 18. Jitter vs. Single-Ended Input Amplitude, PRBS 23 Figure 21. Jitter vs. Supply, PRBS 23 100 100 90 90 80 80 s) s) p p ER ( 70 2.5Gbps ER ( 70 3.2Gbps TT 60 TT 60 AK JI 50 3.2Gbps AK JI 50 E E 2.5Gbps P P O- 40 O- 40 T T AK- 30 AK- 30 E E P P 20 20 100 02169-019 100 02169-022 –1.6 –1.4 –1.2 –1.0 –0.8 –0.6 –0.4 –0.2 0 0.2 0.4 0.6 –1.4 –1.2 –1.0 –0.8 –0.6 –0.4 –0.2 0 0.2 VIH (V) VOH (V) Figure 19. Jitter vs. VIH, PRBS 23 Figure 22. Jitter vs. VOH, PRBS 23, Output Amplitude = 0.4 V Single-Ended Rev. B | Page 11 of 40

AD8151 100 200 90 150 80 s) 100 p 70 Y ( CY 60 ELA 50 N D FREQUE 5400 AGATION –500 P 30 O PR–100 20 100 02169-023 ––210500 02169-025 550 570 590 610 630 650 670 690 710 730 –100 –80 –60 –40 –20 0 20 40 60 80 100 PROPAGATION DELAY (ps) NORMALIZED TEMPERATURE (°C) Figure 23. Variation in Channel-to-Channel Delay, All 561 Points Figure 25. Propagation Delay, Normalized at 25°C vs. Temperature 100 VCC VCC VTT 90 PRBS 49.9Ω HIGH SPEED GENERATOR 1.65kΩ AD8151 SAMPLING 80 OSCILLOSCOPE ps) DATA OUT –6dB P P R ( 70 50Ω TTE 60 2.5Gbps 105Ω IN OUT JI DATA OUT –6dB N N K 50Ω A 50 TO-PE 40 3.2Gbps 1.65kΩ VEE 49.9Ω AK- 30 VEE VTT PE 21000 02169-024 VVRCISNCE =T = =0 0. 81VV.,5 V4pkE-pΩE ,E= IXO–CU3.TE3 P=VT ,1 V6ATmST A N=,O –V1TO.EH6DV =, –V0D.D8 V=, 5VVO,L V =SS– 1=. 20VV 02169-026 5 10 15 20 25 OUTPUT CURRENT (mA) Figure 24. Jitter vs. IOUT, PRBS 23 Figure 26. Test Circuit Rev. B | Page 12 of 40

AD8151 CONTROL INTERFACE TRUTH TABLES Table 4. Basic Control Functions Control Pins1 RESET CS WE RE UPDATE Function 0 X X X X Global Reset. Reset all second rank enable bits to zero (disable all outputs). 1 1 X X X Control Disable. Ignore all logic (but the signal matrix still functions as programmed). D [6:0] are high impedance. 1 0 0 1 1 Single Output Preprogram. Write input configuration data from Data Bus D [6:0] into first rank of latches for the output selected by the Output Address Bus A [4:0]. 1 0 1 0 1 Single Output Readback. Readback input configuration data from second rank of latches onto Data Bus D [6:0] for the single output selected by the Output Address Bus A [4:0]. 1 0 1 1 0 Global Update. Copy input configuration data from all 17 first rank latches into second rank of latches, updating signal matrix connections for all outputs. 1 0 0 1 0 Transparent Write and Update. It is possible to write data directly onto rank two. This simplifies logic when synchronous signal matrix updating is not necessary. 1 X means don’t care. Table 5. Address/Data Examples Output Address Pins Enable Input Address Pins MSB–LSB1 MSB–LSB Bit1 A4 A3 A2 A1 A0 D6/E D5 D4 D3 D2 D1 D0 Function 0 0 0 0 0 X 0 0 0 0 0 0 Lower Address/Data Range. Connect Output 00 (A[4:0] = 00000) to Input 00 (D[5:0] = 000000). 1 0 0 0 0 X 1 0 0 0 0 0 Upper Address/Data Range. Connect Output 16 (A[4:0] = 10000) to Input 32 (D[5:0] = 100000). Binary Output Number 2 1 Binary Input Number Enable Output. Connect Selected Output (A[4:0] = 0 to 16) to Designated Input (D[5:0] = 0 to 32) and Enable Output (D6 = 1). Binary Output Number2 0 X X X X X X Disable Output. Disable Specified Output (D6 = 0). 1 0 0 0 1 X Binary Input Number Broadcast Connection. Connect all 17 outputs to same designated input and set all 17 enable bits to D6. Readback is not possible with the broadcast address. 1 0 0 1 0 X 1 0 0 0 0 1 Reserved. Any address or data code greater or equal to these are reserved for future expansion or factory testing. 1 X means don’t care. 2 The binary output number can also be the broadcast connection designator, 10001. Rev. B | Page 13 of 40

AD8151 CONTROL INTERFACE TIMING DIAGRAMS CS INPUTS WE INPUTS A[4:0] INPUTS D[6:0] INPUTS tCSW tCHW tASW t tAHW WP tDSW tDHW 02169-027 Figure 27. First Rank Write Cycle Table 6. First Rank Write Cycle Parameter Mnemonic Description Conditions Min Typ Max Unit Setup Time t Chip select to write enable T = 25°C 0 ns CSW A t Address to write enable V = 5 V 0 ns ASW DD t Data to write enable V = 3.3 V 15 ns DSW CC Hold Time t Chip select from write enable 0 ns CHW t Address from write enable 0 ns AHW t Data from write enable 0 ns DHW Enable Pulse t Width of write enable pulse 15 ns WP CS INPUTS UPDATE INPUTS ENABLING OUT[0:16][N:P] DATA FROM RANK 1 OUTPUTS TOGGLE OUT[0:16][N:P] PREVIOUS RANK 2 DATA DATA FROM RANK 1 OUTPUTS DISABLING OUT[0:16][N:P] DATA FROM RANK 2 OUTPUTS tCSU t tCHU UW t UOE t UOD tUOT 02169-028 Figure 28. Second Rank Update Cycle Table 7. Second Rank Update Cycle Parameter Mnemonic Function Conditions Min Typ Max Unit Setup Time t Chip select to update T = 25°C 0 ns CSU A Hold Time t Chip select from update V = 5 V ns CHU DD Output Enable Times t Update to output enable V = 3.3 V 25 40 ns UOE CC Output Toggle Times t Update to output reprogram 25 40 ns UOT Output Disable Times t Update to output disabled 25 30 ns UOD Update Pulse t Width of update pulse 15 ns UW Rev. B | Page 14 of 40

AD8151 CS INPUTS UPDATE INPUTS WE INPUTS ENABLING OUT[0:16][N:P] INPUT {DATA 1} INPUT {DATA 2} OUTPUTS DISABLING OUT[0:16][N:P] INPUT {DATA 0} INPUT {DATA 1} OUTPUTS tCSU t tCHU UW tUOT tWOT tUOE tWOD tWHU 02169-029 Figure 29. First Rank Write Cycle and Second Rank Update Cycle Table 8. First Rank Write Cycle and Second Rank Update Cycle Parameter Mnemonic Function Conditions Min Typ Max Unit Setup Time t Chip select to update T = 25°C 0 ns CSU A Hold Time t Chip select from update V = 5 V 0 ns CHU DD Output Enable Times t Update to output enable V = 3.3 V 25 40 ns UOE CC t Write enable to output enable 25 40 ns WOE Output Toggle Times t Update to output reprogram 25 30 ns UOT t Write enable to output reprogram 25 30 ns WOT Output Disable Times t 1 Update to output disabled 25 30 ns UODD t Write enable to output disabled 25 30 ns WOD Setup Time t Write enable to update 10 ns WHU Update Pulse t Width of update pulse 15 ns UW 1 Not shown. CS INPUTS RE INPUTS A[4:0] ADDR 1 ADDR 2 INPUTS D[6:0] DATA DATA OUTPUTS {ADDR 1} {ADDR 2} tCSR tRDE tAA tCHR t RHA tRDD 02169-030 Figure 30. Second Rank Readback Cycle Table 9. Second Rank Readback Cycle Parameter Mnemonic Function Conditions Min Typ Max Unit Setup Time t Chip select to read enable T = 25°C 0 ns CSR A Hold Time t Chip select from read enable V = 5 V 0 ns CHR DD Read Enable t Address from read enable V = 3.3 V 5 ns RHA CC Enable Time t Data from read enable 10 kΩ 15 ns RDE Access Time t Data from address 20 pF on D[6:0] 15 ns AA Release Time t Data from read enable Bus 15 30 ns RDD Rev. B | Page 15 of 40

AD8151 RESET INPUTS DISABLING OUT[0:16][N:P] OUTPUTS t TOD tTW 02169-031 Figure 31. Asynchronous Reset Table 10. Asynchronous Reset Parameter Mnemonic Function Conditions Min Typ Max Unit Disable Time t Output disable from reset T = 25°C 25 30 ns TOD A Width of Reset Pulse t V = 5 V 15 ns TW DD V = 3.3 V CC CONTROL INTERFACE PROGRAMMING EXAMPLE The following conservative pattern connects all outputs to Input 7, except Output 16, which is connected to Input 32. The vector clock period t is 15 ns. It is possible to accelerate the execution of this pattern by deleting Vectors 1, 4, 7, and 9. 0 Table 11. Basic Test Pattern Vector No. RESET CS WE RE UPDATE A[4:0] D[6:0] Comments 0 0 1 1 1 1 xxxxx xxxxxxx Disable all outputs 1 1 1 1 1 1 xxxxx xxxxxxx 2 1 0 1 1 1 10001 1000111 All outputs connected to Input 7 3 1 0 0 1 1 10001 1000111 Write to first rank 4 1 0 1 1 1 10001 1000111 5 1 0 1 1 1 10000 1100000 Connects Output 16 to Input 32 6 1 0 0 1 1 10000 1100000 Write to first rank 7 1 0 1 1 1 10000 1100000 8 1 0 1 1 0 xxxxx xxxxxxx Transfer to second rank 9 1 0 1 1 1 xxxxx xxxxxxx 10 1 1 1 1 1 xxxxx xxxxxxx Disable interface Rev. B | Page 16 of 40

AD8151 CONTROL INTERFACE 7 TO 17× 33 To facilitate multiple chip address decoding, there is a chip- UPDATE RESET SMWATITRCIXH select pin. All logic signals except the reset pulse are ignored 7 7 7 7 33 0 0 unless the chip select pin is active. The chip select pin disables 7 7 7 7 33 only the control logic interface and does not change the 1 1 D[0:6] 7 7 7 7 33 operation of the signal matrix. The chip select pin does not 2 2 power down any of the latches, so any data programmed in the latches is preserved. 7 7 7 7 33 16 16 RANK 1 RANK 2 All control pins are level-sensitive, not edge-triggered. 1 OF 33 17 ROWS OF 7-BIT DECODERS LATCHES CONTROL PIN DESCRIPTION WE A[4:0] Inputs Output address pins. The binary encoded address applied to these 5 input pins determines which one of the 17 outputs is being programmed (or being read back). The most significant bit (MSB) is A4. 1 OF 17 AD[E0:C4O]DERS RE 02169-031 DIn[p6u:t0 c] oInnpfiguutsra/Otiount pduattas pins. In write mode, the binary Figure 32. Control Interface (Simplified Schematic) encoded data applied to the D pins [6:0] determines which of 33 inputs is to be connected to the output specified with the The AD8151 control interface receives and stores the desired A pins [4:0]. The MSB is D5 and the least significant bit (LSB) is connection matrix for the 33 input and 17 output signal pairs. D0. Bit D6 is the enable bit, setting the specified output signal The interface consists of 17 rows of double-rank 7-bit latches, pair to an enabled state if D6 is logic high or disabled to a high 1 row for each output. The 7-bit data-word stored in each of impedance state if D6 is logic low. In readback mode, the these latches indicates to which (if any) of the 33 inputs the D pins [6:0] are low impedance outputs, indicating the data- output is connected. word stored in the second rank for the output specified with the One output at a time can be preprogrammed by addressing the A pins [4:0]. The readback drivers are designed to drive high output and writing the desired connection data into the first impedances only, so external drivers connected to the D rank of latches. This process can be repeated until each of the pins [6:0] should be disabled during readback mode. desired output changes has been preprogrammed. All output WE Input connections can then be programmed at once by passing the data from the first rank of latches into the second rank. The First Rank Write Enable. Forcing this pin to logic low allows the output connections always reflect the data programmed into the data on the D pins [6:0] to be stored in the first rank latch for second rank of latches and do not change until the first rank of the output specified by the A pins [4:0]. The WE pin must be data is passed into the second rank. returned to a logic high state after a write cycle to avoid overwriting the first rank data. If necessary for system verification, the data in the second rank of latches can be read back from the control interface. UPDATE Input Second Rank Write Enable. Forcing this pin to logic low allows At any time, a reset pulse can be applied to the control interface the data stored in all 17 first rank latches to be transferred to the to globally reset the appropriate second rank data bits, disabling second rank latches. The signal connection matrix is repro- all 17 signal output pairs. This feature can be used to avoid grammed when the second rank data is changed. This is a output bus contention on system startup. The contents of the global pin, transferring all 17 rows of data at once. It is not first rank remain unchanged. necessary to program the address pins. It should be noted that The control interface pins are connected via logic-level trans- after the initial power-up of the device, the first rank data is lators. These translators allow programming and readback of undefined. It may be desirable to preprogram all 17 outputs the control interface using logic levels different from those in before performing the first update cycle. the signal matrix. Rev. B | Page 17 of 40

AD8151 RE Input It is useful to momentarily hold RESET at a logic low state when Second Rank Read-Enable. Forcing this pin to logic low enables powering up the AD8151 in a system that has multiple output the output drivers on the bidirectional D pins [6:0], entering signal pairs connected together. Failure to do this can result in the readback mode of operation. By selecting an output address several signal outputs contending after power-up. The RESET with the A pins [4:0] and forcing RE to logic low, the 7-bit pin is not gated by the state of the chip-select pin, CS. It should data stored in the second rank latch for that output address is be noted that the RESET pin does not program the first rank, written to the D pins [6:0]. Data should not be written to the which contains undefined data after power-up. D pins [6:0] externally while in readback mode. CONTROL INTERFACE TRANSLATORS The RE and WE pins are not exclusive, and can be used at the The AD8151 control interface has two supply pins, V and V . DD SS same time, but data should not be written to the D pins [6:0] The potential between the positive logic supply, V , and the DD from external sources while in readback mode. negative logic supply, V , must be at least 3 V and no more than SS 5 V. Regardless of supply, the logic threshold is approximately CS Input 1.6 V above V , allowing the interface to be used with most SS Chip-Select. This pin must be forced to logic low to program or CMOS and TTL logic drivers. The signal matrix supplies, V CC receive data from the logic interface, with the exception of the and V , can be set independently of the voltage on V and V , EE DD SS RESET pin, described in the next section. This pin has no with the constraints that (V − V ) ≤ 10 V. These constraints DD EE effect on the signal pairs and does not alter any of the stored allow operation of the control interface on 3 V or 5 V, while the control data. signal matrix is operated on 3.3 V or 5 V PECL or –3.3 V or –5 V ECL. RESET Input Global Output Disable Pin. Forcing the RESET pin to logic low resets the enable bit, D6, in all 17 second rank latches, regardless of the state of any of the other pins. This has the effect of immediately disabling the 17 output signal pairs in the matrix. Rev. B | Page 18 of 40

AD8151 CIRCUIT DESCRIPTION The AD8151 is a high speed 33 × 17 differential crosspoint VCC VCC VCC– 2V switch designed for data rates up to 3.2 Gbps per channel. The AD8151 supports PECL-compatible input and output levels ZO ZOR1 R1 when operated from a 5 V supply (V = 5 V, V = GND), or INxxN INxxN CC EE ECL-compatible levels when operated from a –5 V supply ZO ZO INxxP INxxP (VCC = GND, VEE = –5 V). To save power, the AD8151 can run ZO ZO R2 R2 ECL SOURCE ECL SOURCE from a +3.3 V supply to interface with low voltage PECL circuits or a –3.3 V supply to interface with low voltage ECL VTT = VCC– 2V VEE (a) (b) circuits. The AD8151 utilizes differential current-mode outputs with an individual disable control, which facilitates busing the VCC outputs of multiple AD8151s together to assemble larger switch arrays. This feature also reduces system crosstalk and can ZO greatly reduce power dissipation in a large switch array. A single INxxN external resistor programs the current for all enabled output ZO 2ZO INxxP stages, allowing user control over output levels with different RL RL ECL SOURCE output termination schemes and transmission line characteristic impedances. VEE (c) 02169-034 High Speed Data Inputs (INxxP, INxxN) Figure 34. AD8151 Input Termination from ECL/PECL Sources: (a) Parallel Termination Using VTT Supply, (b) Thevenin Equivalent Termination, The AD8151 has 33 pairs of differential voltage-mode inputs. and (c) Differential Termination The common-mode input range extends from the positive supply voltage (V ) down to include standard ECL or PECL If the AD8151 is driven from a current-mode output stage such CC input levels (V – 2 V). The minimum differential input as another AD8151, the input termination should be chosen to CC voltage is 200 mV. Unused inputs may be connected directly to accommodate that type of source, as explained in the following any level within the allowed common-mode input range. A section. simplified schematic of the input circuit is shown in Figure 33. High speed Data Outputs (OUTyyP, OUTyyN) VCC The AD8151 has 17 pairs of differential current-mode outputs. The output circuit, shown in Figure 35, is an open-collector NPN current switch with resistor-programmable tail current and output compliance extending from the positive supply INxxP INxxN voltage (V ) down to standard ECL or PECL output levels CC (V − 2 V). The outputs can be disabled individually to permit CC outputs from multiple AD8151s to be connected directly. Since VEE 02169-033 the output currents of multiple enabled output stages sum when Figure 33. Simplified Input Circuit directly connected, care should be taken to ensure that the output compliance limit is not exceeded at any time by disabling To maintain signal fidelity at the high data rates supported by the active output driver before enabling an inactive driver. the AD8151, the input transmission lines should be terminated as close to the input pins as possible. The preferred input VCC termination structure depends primarily on the application and OUTyyP OUTyyN the output circuit of the data source. Standard ECL components VCC– 2V have open emitter outputs that require pull-down resistors. Three input termination networks suitable for this type of source are shown in Figure 34. The characteristic impedance of the transmission line is shown as Z . The resistors, R1 and R2, O in the Thevenin termination are chosen to synthesize a V TT source with an output resistance of Z and an open-circuit DISABLE IOUT O output voltage equal to V – 2 V. The load resistors (RL) in the CC dfoifllfoewreenrtsi aolf t tehrem EinCaLti osonu srcchee. me are needed to bias the emitter VEE VEE 02169-035 Figure 35. Simplified Output Circuit Rev. B | Page 19 of 40

AD8151 To ensure proper operation, all outputs (including unused In this case, the output levels are output) must be pulled high using external pull-up networks to V = V – (¼)I R OH COM OUT L a level within the output compliance range. If outputs from V = V – (¾)I R OL COM OUT L multiple AD8151s are wired together, a single pull-up network V = V – V = (½)I R SWING OH OL OUT L can be used for each output bus. The pull-up network should be chosen to keep the output voltage levels within the output Output Current Set Pin (REF) compliance range at all times. Recommended pull-up networks A simplified schematic of the reference circuit is shown in to produce PECL/ECL 100 kΩ and 10 kΩ compatible outputs Figure 38. A single external resistor connected between the REF are shown in Figure 36. Alternatively, a separate supply can be pin and V determines the output current for all output stages. EE used to provide VCOM, making RCOM and DCOM unnecessary. This feature allows a choice of pull-up networks and trans- mission line characteristic impedances while still achieving a VCC VCC nominal output swing of 800 mV. At low data rates, substantial RCOM DCOM power savings can be achieved by using lower output swings AD8151 VCOM AD8151 VCOM and higher load resistances. RL RL RL RL OUTyyN OUTyyN OUTyyP OUTyyP 02169-036 AD8151 IOUT/20 VCC Figure 36. Output Pull-Up Networks for PECL/ECL: a) 100 kΩ and b) 10kΩ The output levels are 1.2V REF VVOOHL == VVCCOOMM – IOUTRL RSVEETE 02169-038 VSWING = VOH − VOL = IOUTRL Figure 38. Simplified Reference Circuit V = V – I R (100 kΩ mode) COM CC OUT COM V = V – V(D ) (10 kΩ mode) The nominal output current is given by the following: COM CC COM ⎛1.2V⎞ The common-mode adjustment element (RCOM or DCOM) can be IOUT=20⎜⎝ RSET ⎟⎠ omitted if the input range of the receiver includes the positive supply voltage. The bypass capacitors reduce common-mode The minimum set resistor is R = 960 Ω resulting in SET, MIN perturbations by providing an ac short from the common nodes I = 25 mA. The maximum set resistor is R = 4.8 kΩ OUT, MAX SET, MAX (VCOM) to ground. When busing together the outputs of resulting in IOUT, MIN = 5 mA. Nominal 800 mV differential multiple AD8151s or when running at high data rates, double output swing can be achieved in a 50 Ω load using R = 1.5 kΩ SET termination of its outputs is recommended to mitigate the (I = 16 mA), or in a doubly terminated 75 Ω load using OUT impact of reflections due to open transmission line stubs and R = 1.13 kΩ (I = 21.3 mA). To minimize stray capacitance SET OUT the lumped capacitance of the AD8151 output pins. A possible and avoid the pickup of unwanted signals, the external set connection is shown in Figure 37; the bypass capacitors provide resistor should be located close to the REF pin. Bypassing the an ac short from the common nodes of the termination resistors set resistor is not recommended. to ground. To maintain signal fidelity at high data rates, the Power Supplies stubs connecting the output pins to the output transmission lines or load resistors should be as short as possible. There are several options for the power supply voltages for the AD8151, as there are two separate sections of the chip that VCC require power supplies. These are the control logic and the high RCOM speed data paths. Depending on the system architecture, the AD8151 RL VCOM RL voltage levels of these supplies can vary. OUTyyN Logic Supplies OUTyyP AD8151 ZO ZO The control (programming) logic is CMOS and is designed to interface with any of the standard single-ended logic families OUTyyN (CMOS or TTL). Its supply voltage pins are V (Pin 170, logic OUTyyP DD positive) and V (Pin 152, logic ground). In all cases the logic SS ZO ZO ground should be connected to the system digital ground. V DD RL RL should be supplied at between 3.3 V to 5 V to match the supply voltage of the logic family that is used to drive the logic inputs. RECEIVER 02169-037 cVitDoDr s. hTohuel dab bseo lbuytpe amssaexdi mtou gmro vuonltda gwei tfhro am 0 .V1 μF t oce Vram iisc 5 c.5ap Va.- Figure 37. Double Termination of AD8151 Outputs DD SS Rev. B | Page 20 of 40

AD8151 Data Path Supplies POWER DISSIPATION The data path supplies have more options for their voltage levels. For analysis, the power dissipation of the AD8151 can be The choices here affect several other areas, such as power divided into three separate parts. These are the control logic, dissipation, bypassing, and common-mode levels of the inputs the data path circuits, and the (ECL or PECL) outputs, which and outputs. The more positive voltage supply for the data paths are part of the data path circuits but can be dealt with is V (Pin 41, Pin 98, Pin 149, and Pin 171). The more negative separately. The control logic is CMOS technology and does not CC supply is V , which appears on many pins that are not listed here. dissipate a significant amount of power. This power is, of EE The maximum allowable voltage across these supplies is 5.5 V. course, greater when the logic supply is 5 V rather than 3 V, but The first choice in the data path power supplies is to decide overall it is not a significant amount of power and can be whether to run the device as ECL or PECL. For ECL operation, ignored for thermal analysis. V is at ground potential, while V is at a negative supply CC EE between –3.3 V to –5 V. This makes the common-mode voltage VDD VCC of the inputs and outputs a negative voltage (see Figure 39). AD8151 ROUT IOUT +3.3V TO +5V CONTROL DATA LOGIC PATHS 0.1μF GND IL, ODGAITCA PATH VOUTLOW– VEE VDD VCC AD8151 VSS VEE CONTROL DATA GND GND 02169-041 LOGIC PATHS Figure 41. Major Power Consumption Paths The data path circuits operate between the supplies V and VSS VEE CC V . As described in the power supply section, this voltage can EE 0.1μF GND (ONE FOR EVERY TWO VEE PINS) range from 3.3 V to 5 V. The current consumed by this section –3.3V TO–5V 02169-039 idsi scsoipnasttaionnt, bsyo aobpoeurat t3in5g p aetr cae lnotw. Terh veo pltoawgee rc adnis sdiepcarteeads ein p tohwe er Figure 39. Power Supplies and Bypassing for ECL Operation data path outputs is affected by several factors. The first is whether the outputs are enabled or disabled. The worst case The proper way to run the device is to dc-couple the data paths occurs when all of the outputs are enabled. The current to other ECL logic devices that use ground as the most positive consumed by the data path logic can be approximated by supply and use a negative voltage for V . However, if the part is EE to be ac-coupled, it is not necessary to have the input/output I = 35 mA + [I /20 mA × 3 mA)] × (no. of outputs enabled) CC OUT common mode at the same level as the other system circuits, but it is probably more convenient to use the same supply rails This equation states that a minimum ICC of 35 mA always flows. for all devices. For PECL operation, VEE is at ground potential ICC increases by a factor that is proportional to both the number and V is a positive voltage from 3.3 V to 5 V. Thus, the of enabled outputs and the programmed output current. CC common mode of the inputs and outputs is at a positive voltage. The power dissipated in this circuit section is simply the voltage These can then be dc-coupled to other PECL operated devices. of this section (V – V ) times the current. To calculate the If the data paths are ac-coupled, then the common-mode levels CC EE worst case, assume that V – V is 5.0 V, all outputs are do not matter (see Figure 40). CC EE enabled, and the programmed output current is 25 mA. The +3.3V TO +5V +3.3V TO +5V power dissipated by the data path logic is 0.1μF 0.1μF P = 5.0 V {35 mA + [4.5 mA + (25 mA/20 mA × 3 mA)] × 17} = 876 mW (ONE FOR EACH VCC PIN, VDD VCC 4 REQUIRED) The power dissipated by the output current depends on several AD8151 factors. These are the programmed output current, the voltage drop from a logic low output to V , and the number of enabled CONTROL DATA EE LOGIC PATHS outputs. A simplifying assumption is that one of each (enabled) differential output pair is low and draws the full output current GNVDSS GNVDEE 02169-040 (caonmdp dleismsiepnattaersy m oousttp ouft tohf et hpeo wpaeirr fios rh tihgaht aonudtp durta)w, ws hinilsei gtnhief i- Figure 40. Power Supplies and Bypassing for PECL Operation cant current. Rev. B | Page 21 of 40

AD8151 Thus, the power dissipation of the high output can be ignored and There should be no thermal-relief pattern when connecting the the output power dissipation for each output can be assumed to vias to the inner layers for these V pins. Additional vias in EE occur in a single static low output that sinks the full output pro- parallel and close to the pin leads can provide an even lower grammed current. The voltage across which this current flows can thermal resistive path. If possible, use 2 oz copper foil to also vary, depending on the output circuit design and the supplies provide better heat removal than 1 oz copper foil. The AD8151 that are used for the data path circuitry. In general, however, there package has a specified thermal impedance θ of 30°C/W. This JA is a voltage difference between a logic low signal and V . This is is the worst case still-air value that can be expected when the EE the drop across which the output current flows. For a worst case, circuit board does not significantly enhance the heat removal this voltage can be as high as 3.5 V. Thus, for all outputs enabled from the package. By using the concept described earlier or by and the programmed output current set to 25 mA, the power using forced-air circulation, the thermal impedance can be dissipated by the outputs is lowered. P = 3.5 V (25 mA) × 17 = 1.49 W For an extreme worst case analysis, the junction temperature increase above the ambient can be calculated assuming 2 W of Heat Sinking power dissipation and a θ of 30°C/W to yield a 60°C rise above JA Depending on several factors in its operation, the AD8151 can the ambient. There are many techniques described earlier that dissipate upwards of 2 W or more. The part is designed to can mitigate this situation. Most actual circuits do not result in operate without the need for an explicit external heat sink. this high an increase of the junction temperature above the However, the package design offers enhanced heat removal via ambient. some of the package pins to the PC board traces. The V pins EE on the input sides of the package (Pin 1 to Pin 46 and Pin 93 to Pin 138) have finger extensions inside the package that connect to the paddle upon which the IC chip is mounted. These pins provide a lower thermal resistance from the IC to the V pins EE than other pins that just have a bond wire. As a result, these pins can be used to enhance the heat removal process from the IC to the circuit board and ultimately to the ambient. The V EE pins described earlier should be connected to a large area of circuit board trace material to take the most advantage of their lower thermal resistance. If there is a large area available on an inner layer that is at V potential, then vias can be provided EE from the package pin traces to this layer. Rev. B | Page 22 of 40

AD8151 APPLICATIONS INPUT AND OUTPUT BUSING Unlike some other high speed digital components, the AD8151 does not have on-chip terminations. While this location would Although the AD8151 is a digital part, in any application that be closer to the actual end of the transmission line for some runs at high speed, analog design details have to be given very architectures, this concept can limit system design options. In careful consideration. At high data rates, the design of the signal particular, it is not possible to bus more than two inputs or channels have a strong influence on data integrity and its outputs on the same transmission line and it is also not possible associated jitter and ultimately bit error rate (BER). to change the value of these terminations to use for different While it might be considered very helpful to have a suggested impedance transmission lines. The AD8151, with the added circuit board layout for any particular system configuration, this ability to disable its outputs, is much more versatile in these is not something that can be practically realized. Systems come types of architectures. in all shapes, sizes, speeds, performance criteria, and cost con- If the external traces are kept to a bare minimum, then the straints. Therefore, some general design guidelines are pre- output presents a mostly lumped capacitive load of about 2 pF. sented that can be used for all systems and judiciously modified A single stub of 2 pF does not adversely affect signal integrity to where appropriate. a large extent for most transmission lines, but the more of these High speed signals travel best, that is, they maintain their stubs, the greater their adverse influence. integrity when they are carried by a uniform transmission line One way to mitigate this effect is to locally reduce the capa- that is properly terminated at either end. Any abrupt mis- citance of the main transmission line near the point of stub matches in impedance or improper termination creates intersection. Some practical means for doing this are to narrow reflections that add to or subtract from parts of the desired the PC board traces in the region of the stub and/or to remove signal. Small amounts of this effect are unavoidable, but too some of the ground plane(s) near this intersection. The effect of much distorts the signal to the point that the channel these techniques is to locally lower the capacitance of the main BER increases. It is difficult to fully quantify these effects transmission line at these points, while the added capacitance of because they are influenced by many factors in the overall the AD8151 outputs compensate for this reduction in capaci- system design. tance. The overall intent is to create as uniform a transmission A constant-impedance transmission line is characterized by line as possible. having a uniform cross-section profile over its entire length. In In selecting the location of the termination resistors, it is particular, there should be no stubs, which are branches that important to keep in mind that, as their name implies, they intersect the main run of the transmission line. These can have should be placed at either end of the line. There should be an electrical appearance that is approximated by a lumped minimal or no projection of the transmission line beyond the element, such as a capacitor, or if long enough, by another point where it connects to the termination resistors. transmission line. If stubs are unavoidable in a design, their effect can be minimized by making them as short as possible EVALUATION BOARD and as high an impedance as possible. An evaluation board has been designed and is available to Figure 37 shows a differential transmission line that connects rapidly test the main features of the AD8151. This board allows two differential outputs from the AD8151 to a generic receiver. the user to analyze the analog performance of the AD8151 A more generalized system can have more outputs bused and channels and easily control the configuration of the board with more receivers on the same bus, but the same concepts apply. a PC. The board has limited numbers of differential input/ The inputs of the AD8151 can also be considered as a receiver. output pairs. Each differential pair of microstrips is connected The transmission lines that bus the devices together are shown to either top mount or side launch SMA connectors. The top with terminations at each end. mount SMA connectors are drilled and stubbed for superior performance. The FR4 type board contains a total of nine The individual outputs of the AD8151 are stubs that intersect outputs (all even numbered outputs) and 20 inputs (0, 2, 4, 6, 8, the main transmission line. Ideally, their current source outputs 10, 12, 13, 14, 15, 16, 17, 18, 20, 22, 24, 26, 28, 30, 32). It is would be infinite impedance, and they would have no effect on important to note that the shells of the SMA connectors are signals that propagate along the transmission line. In reality, attached to V . This makes only ECL or negative level swings CC each external pin of the AD8151 projects into the package and possible during testing. has a bond wire connected to the chip inside. On-chip wiring then connects to the collectors of the output transistors and to ESD protection diodes. Rev. B | Page 23 of 40

AD8151 POWER SUPPLIES There are additional higher value capacitors elsewhere on the board for bypassing at lower frequencies. The location of these The AD8151 is designed to work with standard ECL logic capacitors is not as critical. levels. This means that V is at ground and V is at a negative CC EE supply. The shells of the I/O SMA connectors are at VCC Input and Output Considerations potential. Thus, when operating in the standard ECL Each input contains a 100 Ω differential termination. Although configuration, test equipment can be directly connected to the differential termination eases board layout due to its compact board, since the test equipment also has its connector shells at nature, it can cause problems with the driving generator. A typical ground potential. pulse or pattern generator wants to see 50 Ω to ground (or to –2 V Operating in PECL mode requires V to be at a positive in some cases). High speed probing of the input has shown that if CC voltage while V is at ground. Since this generates a positive this type of termination is not present, input amplitudes can be EE voltage at the shells of the I/O connectors, it can cause problems slightly off. The dc input levels can be even more affected. when directly connecting to test equipment. Some equipment, Depending on the generator used, these levels can be off as much as such as battery-operated oscilloscopes, can be floated from 800 mV in either direction. A correction for this problem is to ground, but care should be taken with line-powered equipment attach a 6 dB attenuator to each P and N input. Because the to avoid creating a dangerous situation. Refer to the manual of AD8151 has a large common-mode voltage range on its input the test equipment that is being used. stage, it is not significantly affected by dc level errors. The voltage difference from VCC to VEE can range from 3 V to On this evaluation board, all unused inputs are tied to VCC 5 V. Power savings can be realized by operating at a lower (GND). All outputs, whether attached to connectors or not, are voltage without any compromise in performance. tied to VTT through a 49.9 Ω resistor. The AD8151 device is on the component side of the board, while input terminations and A separate connection is provided for VTT, the termination output back terminations are on the circuit side. The input potential of the outputs. This can be at a voltage as high as VCC, signals from the circuit side transit through via holes to the but power savings can be realized if VTT is at a voltage that is DUT’s pads. The component-side output signals connect to via somewhat lower. holes and to circuit-side 49.9 Ω termination resistors. As a practical matter, current on the evaluation board flows Board Construction from the V supply through the termination resistors into the TT For this board, FR4 material was chosen over more exotic board multiple outputs of the AD8151 and to the V supply. When EE materials. Tests show exotic materials are unnecessary. This is a running in ECL mode, V should be at a negative supply. TT 4-layer board, so power is bused on both external and internal Most power supplies do not allow a simultaneous ground layers. Test structures show microstrip performance is unaf- connection to V and a negative supply at V , because it fected by the dc bias levels on the plane beneath it. CC TT would force the source current to originate from a negative The board manufacturing process should ensure a controlled supply, which wants to flow to the more-negative V . In this EE impedance board. The board stack consists of a 5-mil-thick case, the source current does not then return to the ground layer between external and internal layers. This allows the use of terminal of the V supply. Thus, V should be referenced to TT TT an 8-mil-wide microstrip trace running from the SMA con- V when running in ECL mode or a true bipolar supply should EE nector to the DUT’s pads. The narrow trace eliminates the need be used. to reduce the trace width as the DUT’s pads are approached and The digital supply is provided to the AD8151 by the V and helps to control the microstrip trace impedance. The thin 5-mil DD V pins. V should always be at ground potential to make it dielectric also reduces crosstalk by confining the electromag- SS SS compatible with standard CMOS or TTL logic. V can range netic fields between the trace and the plane below. DD from 3 V to 5 V, and should be matched to the supply voltage of the logic used to control the AD8151. However, since PCs use 5 V logic on their parallel port, V should be 5 V when using a DD PC to program the AD8151. Bypassing Most of the board’s bypass capacitors are opposite the DUT on the solder side and are connected between V and V . This is CC EE where they are most effective. For low inductance, use 0.01 μF ceramic chip capacitors. Rev. B | Page 24 of 40

AD8151 CONFIGURATION PROGRAMMING After running the software, the user is prompted to identify which of three software drivers is used with the PC parallel The board is configurable by one of two methods. For ease of port. The default is LPT1, which is most commonly used. use, custom software is provided that controls the AD8151 However, some laptops commonly use the PRN driver. It is also programming via the parallel port of a PC. This requires a possible that some systems are configured with the LPT2 driver. standard printer cable that has a DB-25 connector at one end If it is not known which driver is used, it is best to select LPT1 (parallel-port or printer-port interface) and a Centronix and proceed to the next screen, which displays the buttons that connector at the other, which connects to P2 of the AD8151 allow the connection of inputs to outputs of the AD8151. All of evaluation board. The programming with this setup is serial, so the outputs should be in the output off state after the program it is not the fastest way to configure the AD8151 matrix. starts running. Any of the active buttons can be selected by However, the user interface makes it very convenient to use this clicking the mouse, which sends out a burst of programming programming method. data. If a high speed programming interface is desired, the AD8151 After the software driver has been selected, the user can address and data buses are directly available on P3. The source generate a steady stream of programming signals out of the of the program signals can be a piece of test equipment such as parallel port by holding down the left or right arrow key on the the Tektronix HFS-9000 digital test generator or other hardware keyboard. The clock test point on the AD8151 evaluation board that generates programming signals. When using the PC inter- can be monitored with an oscilloscope for any activity (a user- face, the jumper at W1 should be installed and no connections supplied printer cable must be connected). If there is a square- should be made to P3. When using the P3 interface, no jumper wave present, the proper software driver is selected for the PC’s is installed at W1. There are locations for termination resistors parallel port. for the address and data signals, if needed. SOFTWARE INSTALLATION If there is no signal present, select another driver by clicking Parallel Port on the File menu. Select a different software The software to operate the AD8151 is provided on two 3.5" driver and carry out the test described previously until signal floppy disks. To install the software on a PC: activity is present at the clock test point. 1. Insert Disk 1 into the floppy disk drive. 2. Run the setup.exe program. This program routinely installs the software. 3. Insert Disk 2 when prompted. 4. Select a program directory when prompted. Rev. B | Page 25 of 40

AD8151 SOFTWARE OPERATION This sends out the proper program data and returns to the main screen with a full column of buttons selected under the chosen Click any button in the matrix to program the input to output input. connection. This sends the proper programming sequence out the PC parallel port. Since only one input can be programmed The Off column can be used to disable the desired output. To to a given output at one time, clicking a button in a horizontal disable all outputs, click Global Reset. This button selects a full row cancels the other selection that is already selected in that column of Off buttons. row. However, any number of outputs can share the same input. Two scratch pad memories (Memory 1 and Memory 2) are A shortcut for programming all outputs to the same input is to provided to conveniently save a particular configuration. use the broadcast feature. Click Broadcast Connection and a However, these registers are erased when the program is screen appears that prompts the user to select which input terminated. For long term storage of configurations, the disk should be connected to all outputs. Type in an integer from 0 to storage memory should be used. The Save and Load selections 32 and then click OK. can be accessed from the File menu. AD8151 02169-042 Figure 42. Evaluation Board Controller Rev. B | Page 26 of 40

AD8151 02169-043 Figure 43. Component Side Rev. B | Page 27 of 40

AD8151 02169-044 Figure 44. Circuit Side Rev. B | Page 28 of 40

AD8151 02169-045 Figure 45. Silkscreen Top Rev. B | Page 29 of 40

AD8151 02169-046 Figure 46. Solder Mask Top Rev. B | Page 30 of 40

AD8151 02169-047 Figure 47. Silkscreen Bottom Rev. B | Page 31 of 40

AD8151 02169-048 Figure 48. Solder Mask Bottom Rev. B | Page 32 of 40

AD8151 02169-049 Figure 49. INT1 (VEE) Rev. B | Page 33 of 40

AD8151 02169-050 Figure 50. INT2 (VCC) Rev. B | Page 34 of 40

AD8151 CE VEE VCVEVCC VEEVCC 0.0C1μ1F2 C0.801μF C6 0.01CμF5VCC VEE 0V.EE01VμFCC REFVREFEE VEEVCCC0.901μF C7 VCC VEE C 0.01μF R203 VEEVCC 0.0C1μ2F9VC0C.01VCμEEF4IN19NIN19P IN18NIN18P IN17NIN17P IN16NIN16P VCVDDVERESETEC0CS.1031REμFWEUPDATEA0A1A2A3A4D0D1D20D3.0C1D4μ1F4VD5D1DD6.5kVΩSS IN15NIN15P IN14NIN14P IN13NIN13PC0V.EE1001VμFCCC0.3001μF 184183182181180179178177176175174173172171170169168167166165164163162161160159158157156155154153152151150149148147146145144143142141140139 0.C0311μF VEE 1 PIN 1 138 VEE VCC IINN2200NP 32 INDICATOR 113376 IINN1122NP VEE 4 135 VEE IN21P 5 134 IN11N IN21N 6 133 IN11P VEE 7 132 VEE VCC IINN2222NP 98 113301 IINN1100NP 0.C0312μF VEE 10 129 VEE IN23P 11 128 IN09N IN23N 12 127 IN09P VEE 13 126 VEE IN24P 14 125 IN08N IN24N 15 124 IN08P VEE 16 123 VEE IN25P 17 122 IN07N IN25N 18 121 IN07P VEE 19 120 VEE IN26P 20 119 IN06N IN26N 21 AD8151 118 IN06P VEE 22 184L LQFP 117 VEE IN27P 23 TOP VIEW 116 IN05N IN27N 24 (Not to Scale) 115 IN05P VEE 25 114 VEE IN28P 26 113 IN04N IN28N 27 112 IN04P VEE 28 111 VEE IN29P 29 110 IN03N IN29N 30 109 IN03P VEE 31 108 VEE IN30P 32 107 IN02N IN30N 33 106 IN02P VEE 34 105 VEE IN31P 35 104 IN01N IN31N 36 103 IN01P VEE 37 102 VEE C11 IN32P 38 101 IN00N C60 0.01μF IN32N 39 100 IN00P 0.01μF VEE VEE 40 99 VEE VEE VCC 41 98 VCC VEE 42 97 VEEA0 VCC OOUUTT1166NP 4434 9956 OOUUTT0000PN 0.C0115μF VEEA16 45 94 VEEA1 VEE 46 93 VEE 47484950515253545556575859606162636465666768697071727374757677787980818283848586878889909192 VEEOUT15NOUT15PVA15EEOUT14NOUT14PA14VEEOUT13NOUT13PA13VEEOUT12NOUT12PVA12EEOUT11NOUT11PVA11EEOUT10NOUT10PVA10EEOUT09NOUT09PA9VEEOUT08NOUT08PVA8EEOUT07NOUT07PA7VEEOUT06NOUT06PA6VEEOUT05NOUT05PA5VEEOUT04NOUT04PVA4EEOUT03NOUT03PVA3EEOUT02NOUT02PVA2EEOUT01NOUT01PVEE 02169-051 Figure 51. Bypassing Schematic Rev. B | Page 35 of 40

AD8151 VCC VCC VCC VCC VCC VCC 1.65Rk1Ω9 IN00P 1.65Rk4Ω0 IN06P 1.65Rk5Ω8 IN12P 1.6R5k8Ω9 IN18P 1.65Rk9Ω4 IN24P 1.6R51k1Ω6 IN30P OUT08P R491.690Ω P87 OUT00P R491.291Ω P103 P4 P16 P28 P40 P52 P64 VTT VTT R20 R39 R57 R90 R93 R117 105Ω 105Ω 105Ω 105Ω 105Ω 105Ω OUT08N R162 OUT00N R122 P5 P17 P29 P41 P53 P65 49.9Ω 49.9Ω P86 P102 R21 IN00N R38 IN06N R56 IN12N R91 IN18N R92 IN24N R118 IN30N 1.65kΩ 1.65kΩ 1.65kΩ 1.65kΩ 1.65kΩ 1.65kΩ R165 R125 VEE VEE VEE VEE VEE VEE OUT09P 49.9Ω OUT01P 49.9Ω VCC VTT VTT R59 OUT09N R4196.93Ω OUT01N 4R91.297Ω 1.65kΩ IN13P P30 P31 R10650Ω OUT10P R491.795Ω P83 OUT02P 4R91.390Ω P99 R61 IN13N VTT VTT 1.65kΩ OUT10N R173 OUT02N R132 VEE 49.9Ω P82 49.9Ω P98 VCC VCC VCC VCC VCC VCC R170 R135 R28 R44 R62 R85 R98 R112 OUT11P 49.9Ω OUT03P 49.9Ω 1.65kΩ IN02P 1.65kΩ IN08P 1.65kΩ IN14P 1.65kΩ IN20P 1.65kΩ IN26P 1.65kΩ IN32P VTT VTT P8 R27 P20 R45 P32 R63 P44 R84 P56 R99 P68 R111 OUT11N R172 OUT03N R133 105Ω 105Ω 105Ω 105Ω 105Ω 105Ω 49.9Ω 49.9Ω P9 P21 P33 P45 P57 P69 R26 IN02N R46 IN08N R64 IN14N R83 IN20N R100 IN26N R110 IN32N 1.65kΩ 1.65kΩ 1.65kΩ 1.65kΩ 1.65kΩ 1.65kΩ P79 P95 R185 R140 VEE VEE VEE VEE VEE VEE OUT12P 49.9Ω OUT04P 49.9Ω VCC VTT VTT OUT12N R183 OUT04N R142 R65 49.9Ω 49.9Ω 1.65kΩ IN15P P78 P94 P34 R66 R180 R145 105Ω OUT13P 49.9Ω OUT05P 49.9Ω P35 VTT VTT R67 IN15N 1.65kΩ OUT13N R182 OUT05N R143 49.9Ω 49.9Ω VEE VCC VCC VCC VCC VCC P75 P91 R195 R150 R34 R50 R68 R79 R104 OUT14P 49.9Ω OUT06P 49.9Ω 1.65kΩ IN04P 1.65kΩ IN10P 1.65kΩ IN16P 1.65kΩ IN22P 1.65kΩ IN28P VTT VTT P12 R33 P24 R51 P36 R69 P48 R78 P60 R105 OUT14N R4199.93Ω OUT06N 4R91.95Ω2 105Ω 105Ω 105Ω 105Ω 105Ω P74 P90 P13 P25 P37 P49 P61 1.65Rk3Ω2 IN04N 1.6R5k5Ω2 IN10N 1.6R5k7Ω0 IN16N 1.65Rk7Ω7 IN22N 1.6R51k0Ω6 IN28N OUT15P 4R91.990Ω OUT07P R491.595Ω VEE VEE VEE VEE VEE VTT VTT VCC OUT15N R192 OUT07N R153 VCC 49.9Ω 49.9Ω R71 1.65kΩ IN17P P C16 P38 1R0752Ω IINN0019,, IINN0131,, IINN0159,, IINN0271,, OUT16P 4R92.90Ω0 P71 VTT 0.01μF VCC P39 IN23, IN25, IN27, IN29, IN31 VTT C82 R73 IN17N N 0.01μF 1.65kΩ OUT16N 4R91.99Ω8 VTT VCC VEE P70 VTT 0.C018μ3F VCC 02169-052 Figure 52. Evaluation Board Input/Output Schematic Rev. B | Page 36 of 40

AD8151 CLK A1 1 2 CLK P2 6 DATA P2 5 DATA3 A1744HC514A16 12 OD0UT_EN VQCC0 1290 12 OD0UT_EN VQCC0 1290 VDD VDD 794HAC1148 3 18 3 18 A1 74HC14 74HC14 D1 Q1 D1 Q1 11 10 4 17 4 17 VSS P2 25 VSS 5 D2 Q2 16 5 D2 Q2 16 74HC14 6 DD34 74AH2C74QQ34 15 6 DD34 74HAC374 QQ34 15 13 A1 12 VDD 7 D5 Q5 14 7 D5 Q5 14 74HC14 8 13 8 13 VSS 109 DDG67ND CQQLK67 1121 VVDSDS 190 DDG67ND CQQLK67 1121 17904HAC4132 8 A4 12 11 13 R7 49Ω 160A4 R12 74HC132 VSS 49Ω 153D6 R8 VSS 49Ω 161A3 R13 VSS 4R99Ω 162A2 VSS 49Ω R14 154D5 VSS 49Ω 155D4 R10 VSS 49Ω 163A1 R15 VSS 49Ω 156D3 R11 VSS 49Ω 164A0 R16 20Rk1Ω VSS VSS 49Ω 157D2 VDD 1 A4 A4 VSS 4R91Ω7 158D1 W1 3 4 R18 VSS 2 5 6 VSS 49Ω 159D0 74HC132 74HC132 READ P2 7 RESET P2 3 WRITE P2 8 UPDATE P2 4 CHIP_SELECT P2 2 TP5 WRITE P3 13 TP6 RESET P3 7 READ P3 11 TP4 D0 P3 27 TP20 A4 P3 25 TP9 A3 P3 23 TP10 A2 P3 21 TP11 A1 P3 19 TP12 A0 P3 17 TP13 D6 P3 39 TP14 D5 P3 37 TP15 D4 P3 35 TP16 D3 P3 33 TP17 D2 P3 31 TP18 D1 P3 29 TP19 TP7 UPDATE P3 15 TP8 CHIP_SELECT P3 9 VDD P3 5 VDD R2 VSS P3 14 VSS 49kΩ CHIP_SELECT P3 8 VSS R3 168 PP33 1228 VSS 49kΩ U16P5DATE VTT P1 6 VTT PPPPP33333 2122248620 VVSSSS 49Rk5Ω49RRk64Ω W1R166ER69SITEET VCC PP11 12 ++ C1C10013μμFF VVVTCCTCC AA11V,,D 44D PPIINN 17V4 ID SISD T TIEIEDD TV TODOD V VSDS.D.VDD PP33 4308 VSS 49kΩ R16E7AD VEE PP11 34 VVEEEE C86 C87 C88 C89 0.1μF 0.1μF 0.1μF 0.1μF P3 36 VDD P1 7 VDD P3 34 + C2 PP33 3302 VSS P1 5 10μF VSS VSS VSS VSS VSS P3 16 P104 PP33 160 P105 02169-053 Figure 53. Evaluation Board Logic Controls Rev. B | Page 37 of 40

AD8151 OUTLINE DIMENSIONS 22.20 0.75 22.00 SQ 1.60 0.60 MAX 21.80 0.45 184 139 1 138 PIN 1 20.20 20.00 SQ TOP VIEW 19.80 (PINS DOWN) 1.45 0.20 1.40 0.09 1.35 7° 3.5° 46 93 0.15 0° 47 92 0.05 SPELAANTIENG 0C.O08P LMAANXARITY VIEW A B0.S4C0 0.23 LEAD PITCH 0.18 VIEW A 0.13 ROTATED 90° CCW Figure 54. 184-Lead Low Profile Quad Flat Package [LQFP] (ST-184) Dimensions shown in millimeters ORDERING GUIDE Model Temperature Range Package Description Package Option AD8151AST 0°C to 85°C 184-Lead LQFP ST-184 AD8151ASTZ1 0°C to 85°C 184-Lead LQFP ST-184 AD8151-EVAL Evaluation Board 1 Z = Pb-free part. Rev. B | Page 38 of 40

AD8151 NOTES Rev. B | Page 39 of 40

AD8151 NOTES © 2005 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. C02169-0-12/05(B) Rev. B | Page 40 of 40