Triple Differential Driver for Wideband Video Data Sheet AD8146/AD8147/AD8148 FEATURES FUNCTIONAL BLOCK DIAGRAMS Triple high speed fully differential driver B B AM BM 700 MHz, −3 dB, 2 V p-p bandwidth (AD8146/AD8148) VS+ –IN +IN VS– VOC VOC 600 MHz, −3 dB, 2 V p-p bandwidth (AD8147) 24 23 22 21 20 19 200 MHz, 0.1 dB, 2 V p-p bandwidth OPD 1 AD8146 18 VOCMC 3000 V/μs slew rate VS– 2 17 VS+ Fixed gain (AD8146/AD8147: G = 2, AD8148: G = 4) –IN A 3 16 –IN C Differential or single-ended input to differential output +IN A 4 15 +IN C Can be used as differential-to-differential receiver B VS– 5 A C 14 VS– Drives one or two 100 Ω UTP cables –OUT A 6 13 –OUT C Adjustable output common-mode voltage (AD8146) 7 8 9 10 11 12 IntOeruntpalu cto bmalmanocne- merordoer −fe5e0d dbBa c@k 5n0e tMwHozr k +OUT A VS+ +OUT B –OUT B VS+ +OUT C 09327-001 On-chip, sync-on common-mode encoding (AD8147/AD8148) Figure 1. Output pull-down feature for line isolation C) Low power: 57 mA @ 5 V for 3 drivers (AD8146) N Y WAvidaiela sbulpep inly a v somltaagll e4 r manmg e×: 4+ 5m Vm t oLF ±C5S VP VS+ –IN G +IN G (SVS– VSYNC HSYNC 24 23 22 21 20 19 OPD 1 18 SYNC LEVEL APPLICATIONS AD8147/ AD8148 QXGA or 1080p video transmission VS– 2 17 VS+ (SYNC) KVM networking –IN R 3 ×2 16 –IN B Video over unshielded twisted pair (UTP) +IN R 4 15 +IN B Differential signal multiplexing VS– 5 A B C 14 VS– –OUT R 6 13 –OUT B 7 8 9 10 11 12 +OUT R VS+ +OUT G –OUT G VS+ +OUT B 09327-002 Figure 2. GENERAL DESCRIPTION The AD8146/AD8147/AD8148 are high speed triple, differential or of 700 MHz and fast slew rates. They have an internal common- single-ended input to differential output drivers. The AD8146 mode feedback feature that provides output amplitude and and AD8147 have a fixed gain of 2, and the AD8148 has a fixed phase matching that is balanced to −60 dB at 50 MHz, suppressing gain of 4. They are all specifically designed for the highest even-order harmonics and minimizing radiated resolution component video signals but can be used for any electromagnetic interference (EMI). type of analog signals or high speed data transmission over The common-mode voltage of each AD8146 output can be set either Category 5 UTP cable or differential printed circuit to any level, allowing transmission of signals over the common- board (PCB) transmission lines. mode voltages. The AD8147 and AD8148 encode the vertical These drivers can be used with the AD8145 triple differential- and horizontal sync signals on the common-mode voltages of to-singled-ended receiver, and the AD8117 crosspoint switch to the outputs. All outputs can be independently set to low voltage produce a video distribution system capable of supporting states to be used with series diodes for line isolation, allowing UXGA or 1080p signals. easy differential multiplexing over the same twisted pair cable. Manufactured on the Analog Devices, Inc. second generation The AD8146/AD8147/AD8148 are available in a 24-lead LFCSP XFCB bipolar process, the drivers have large signal bandwidths and operate over a temperature range of −40°C to +85°C. Rev. B Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Tel: 781.329.4700 ©2007–2014 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com

AD8146/AD8147/AD8148 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1  Input Common-Mode Voltage Range in Single-Supply Applications ....................................................................................... 1  Applications ................................................................................ 15  Functional Block Diagrams ............................................................. 1  Output Common-Mode Control ............................................. 15  General Description ......................................................................... 1  Sync-On Common-Mode ......................................................... 15  Revision History ............................................................................... 2  Applications ..................................................................................... 16  Specifications ..................................................................................... 3  Driving RGB Video Signals Over Category-5 UTP Cable .... 16  Absolute Maximum Ratings ............................................................ 7  Video Sync-On Common-Mode .............................................. 16  Thermal Resistance ...................................................................... 7  Driving Two UTP Cables With One Driver ........................... 18  ESD Caution .................................................................................. 7  Using the AD8146 as a Receiver ............................................... 18  Pin Configurations and Function Descriptions ........................... 8  Output Pull-Down (OPD) ........................................................ 19  Typical Performance Characteristics ........................................... 10  Layout and Power Supply Decoupling Considerations ......... 19  Theory of Operation ...................................................................... 14  Driving a Capacitive Load ......................................................... 19  Definition of Terms .................................................................... 14  Adding Pre-Emphasis to the AD8148 ...................................... 20  Analyzing an Application Circuit ............................................. 14  Exposed Paddle (EP).................................................................. 21  Closed-Loop Gain ...................................................................... 14  Outline Dimensions ....................................................................... 22  Calculating the Input Impedance ............................................. 15  Ordering Guide .......................................................................... 22  REVISION HISTORY 3/14—Rev. A to Rev. B Changed LFCSP_VQ to LFCSP_WQ (Throughout) ................... 7 Updated Outline Dimensions ....................................................... 22 Changes to Ordering Guide .......................................................... 22 8/10—Rev. 0 to Rev. A Changes to Table 1 ............................................................................ 3 Changes to Table 2 ............................................................................ 5 Changes to Pin Configurations and Function Descriptions Section ................................................................................................ 8 Changes to Adding Pre-Emphasis to the AD8148 Section ....... 20 Updated Outline Dimensions ....................................................... 22 5/07—Revision 0: Initial Version Rev. B | Page 2 of 24

Data Sheet AD8146/AD8147/AD8148 SPECIFICATIONS V = ±5V, V = 0 V (AD8146); SYNC LEVEL = 0 V (AD8147/AD8148); T = 25°C; R, = 200 Ω, unless otherwise noted. S OCM L dm T to T = −40°C to +85°C. MIN MAX Table 1. Parameter Conditions Min Typ Max Unit DIFFERENTIAL INPUT AC Dynamic Performance −3 dB Small Signal Bandwidth V = 0.2 V p-p, O AD8146/AD8148 900 MHz AD8147 780 MHz −3 dB Large Signal Bandwidth V = 2 V p-p, O AD8146/AD8148 700 MHz AD8147 600 MHz Bandwidth for 0.1 dB Flatness V = 2 V p-p, O AD8146/AD8147 200 MHz AD8148 235 MHz Slew Rate V = 2 V p-p, 25% to 75% 3000 V/µs O Isolation Between Amplifiers f = 10 MHz AD8146/AD8147 −86 dB AD8148 −80 dB DIFFERENTIAL INPUT DC Input Common-Mode Voltage Range −5 to +5 V Input Resistance Differential 1.0 kΩ Single-ended input AD8146/AD8147 750 Ω AD8148 833 Ω Input Capacitance Differential 2 pF DC CMRR ΔV /ΔV , ΔV = ±1 V OUT, dm IN, cm IN, cm AD8146/AD8147/AD8148 −53/−49/−55 dB DIFFERENTIAL OUTPUT Differential Signal Gain ΔV /ΔV ; ΔV = ±1 V OUT, dm IN, dm IN, dm AD8146/AD8147 1.94 2.00 V/V ΔV /ΔV ; ΔV = ±1 V OUT, dm IN, dm IN, dm AD8148 3.8 4.0 V/V Output Voltage Swing Each single-ended output AD8146/AD8147/AD8148 −3/−2.25/−3.42 +3.4/+3.4/+3.5 V Output Offset Voltage −19 +19 mV Output Offset Drift T to T ±8 µV/°C MIN MAX Output Balance Error ΔV /ΔV , ΔV = 2 V p-p OUT, cm IN, dm OUT, dm f = 50 MHz AD8146/AD8147 −52 dB AD8148 −49 dB DC AD8146/AD8148 −41 dB AD8147 −44 dB Output Voltage Noise (RTO) f = 1 MHz AD8146/AD8147 25 nV/√Hz AD8148 42 nV/√Hz Output Short-Circuit Current Short to GND, source/sink +87/−67 mA Rev. B | Page 3 of 24

AD8146/AD8147/AD8148 Data Sheet Parameter Conditions Min Typ Max Unit V DYNAMIC PERFORMANCE (AD8146 ONLY) OCM −3 dB Bandwidth ΔV = 100 mV p-p 340 MHz OCM Slew Rate V = −1 V to +1 V, 25% to 75% 800 V/µs OCM DC Gain ΔV = ±1 V 0.98 1.00 V/V OCM V INPUT CHARACTERISTICS (AD8146 ONLY) OCM Input Voltage Range ±3 V Input Resistance 12.5 kΩ Input Offset Voltage −36 +36 mV DC CMRR ΔV /ΔV , ΔV = ±1 V −48 dB OUT, dm OCM OCM SYNC DYNAMIC PERFORMANCE (AD8147/ AD8148 ONLY) Slew Rate V = −1 V to +1 V; 25% to 75% 1000 V/µs OUT, cm H AND V INPUTS (AD8147/AD8148 SYNC SYNC ONLY) Low-to-High Threshold 1.5 to1.7 V High-to-Low Threshold 1.5 to1.7 V SYNC LEVEL INPUT (AD8147/AD8148 ONLY) Setting to 0.5 V Pulse Levels 0.5 V Gain to Red Common-Mode Output ΔV /ΔV , AD8147/AD8148 0.93/0.96 1.10/1.05 V/V O, cm SYNC LEVEL Gain to Green Common-Mode Output ΔV /ΔV , AD8147/AD8148 1.91/1.93 2.15/2.08 V/V O, cm SYNC LEVEL Gain to Blue Common-Mode Output ΔV /ΔV , AD8147/AD8148 −1.10/−1.05 −0.93/−0.96 V/V O, cm SYNC LEVEL POWER SUPPLY Operating Range +4.5 ±5.5 V Quiescent Current, Positive Supply AD8146/AD8147/AD8148 58/61.5/62.5 mA Disabled AD8146 6 mA AD8147/AD8148 21.5 mA Quiescent Current, Negative Supply AD8146/AD8147/AD8148 −58/−60.5/−62 mA Disabled −37 mA PSRR ΔV /ΔV; ΔV = ±1 V OUT, dm S S AD8146/AD8147/AD8148 −66/−52/−55 dB OUTPUT PULL-DOWN OPD Input Low Voltage 1.1 V OPD Input High Voltage 2.1 V OPD Input Bias Current 520 µA OPD Assert Time 1 µs OPD Deassert Time 10 ns Output Voltage When OPD Asserted Each output, OPD input @ V+ −3.8 V S Rev. B | Page 4 of 24

Data Sheet AD8146/AD8147/AD8148 V = +5 V or ±2.5 V; V = midsupply (AD8146); SYNC LEVEL = 0 V (AD8147/AD8148); T = 25°C; R = 200 Ω, unless otherwise noted. S OCM L, dm T to T = −40°C to +85°C. MIN MAX Table 2. Parameter Conditions Min Typ Max Unit DIFFERENTIAL INPUT AC Dynamic Performance −3 dB Small Signal Bandwidth V = 0.2 V p-p, O AD8146 870 MHz AD8147/AD8148 680 MHz −3 dB Large Signal Bandwidth V = 2 V p-p, O AD8147 590 MHz AD8146/AD8148 620 MHz Bandwidth for 0.1 dB Flatness V = 2 V p-p, O AD8146/AD8147 165 MHz AD8148 200 MHz DIFFERENTIAL INPUT DC Input Common-Mode Voltage Range 0 to 5 V Input Resistance Differential 1.0 kΩ Single-ended input AD8146/AD8147 750 Ω AD8148 833 Ω Input Capacitance Differential 2 pF DC CMRR ΔV /ΔV ; ΔV = ±1 V, OUT, dm IN, cm IN, cm AD8146/AD8147/AD8148 −49/−45/−49 dB DIFFERENTIAL OUTPUT Differential Signal Gain ΔV /ΔV ; ΔV = ±1 V, OUT, dm IN, dm IN, dm AD8146/AD8147 1.94 2.00 V/V ΔV /ΔV ; ΔV = ±1 V OUT, dm IN, dm IN, dm AD8148 3.80 4.00 V/V Output Voltage Swing Each single-ended output, V = ±2.5 V −1.17 +1.24 V S Output Offset Voltage −17 +17 mV Output Offset Drift T to T ±8 µV/°C MIN MAX Output Balance Error ΔV /ΔV , ΔV = 2 V p-p, OUT, cm IN, dm OUT, dm f = 50 MHz −53 dB AD8146/AD8147 −49 dB AD8148 DC AD8146/AD8148 −41 dB AD8147 −44 dB Output Voltage Noise (RTO) f = 1 MHz AD8146/AD8147 25 nV/√Hz AD8148 42 nV/√Hz Output Short-Circuit Current Short to GND, source/sink +63/−48 mA V DYNAMIC PERFORMANCE (AD8146 OCM ONLY) −3 dB Bandwidth ΔV = 100 mV p-p 310 MHz OCM Slew Rate V = −1 V to +1 V, 25% to 75% 800 V/µs OCM DC Gain ΔV = ±1 V 0.98 1.00 V/V OCM Rev. B | Page 5 of 24

AD8146/AD8147/AD8148 Data Sheet Parameter Conditions Min Typ Max Unit V INPUT CHARACTERISTICS (AD8146 OCM ONLY) Input Voltage Range ±1.2 V Input Resistance 12.5 kΩ Input Offset Voltage −36 +36 mV DC CMRR ΔV /ΔV ; ΔV = ±1 V −42 dB O, dm OCM OCM SYNC DYNAMIC PERFORMANCE (AD8147/ AD8148 ONLY) Slew Rate V = −1 V to +1 V; 25% to 75% 800 V/µs OUT, cm H AND V INPUTS (AD8147/AD8148 SYNC SYNC ONLY) Low-to-High Threshold 1.3 to 1.5 V High-to-Low Threshold 1.3 to 1.5 V SYNC LEVEL INPUT (AD8147/AD8148 ONLY) Setting to 0.5 V Pulse Levels 0.5 V Gain to Red Common-Mode Output ΔV /ΔV , AD8147/AD8148 0.88/0.92 1.07/1.04 V/V O, cm SYNC LEVEL Gain to Green Common-Mode Output ΔV /ΔV , AD8147/AD8148 1.83/1.85 2.08/2.00 V/V O, cm SYNC LEVEL Gain to Blue Common-Mode Output ΔV /ΔV , AD8147/AD8148 −1.07/−1.04 −0.88/−0.92 V/V O, cm SYNC LEVEL POWER SUPPLY Operating Range +4.5 ±5.5 V Quiescent Current Positive Supply AD8146/AD8147/AD8148 50/55.5/ 54 mA Disable AD8146 4 mA AD8147/AD8148 12 mA Quiescent Current Negative Supply AD8146/AD8147/AD8148 −50/−55/−53 mA Disabled AD8146/AD8147/ AD8148 −14/−18.2/−15 mA PSRR ΔV /ΔV; ΔV = ±1 V, OUT, dm S S AD8146/AD8147/AD8148 −70/−52/-60 dB OUTPUT PULL-DOWN OPD Input Low Voltage 1.0 V OPD Input High Voltage 2.0 V OPD Input Bias Current 160 µA OPD Assert Time 600 ns OPD Deassert Time 10 ns Output Voltage When OPD Asserted Each output, OPD input @ V+ −1.6 V S Rev. B | Page 6 of 24

Data Sheet AD8146/AD8147/AD8148 ABSOLUTE MAXIMUM RATINGS mode feedback loops. The internal resistor tap used in the Table 3. common-mode feedback loop places a 4 kΩ differential load on Parameter Rating the output. Differential feedback, network resistor values are Supply Voltage 11 V given in the Theory of Operation section and Applications All V ±V OCM S section. RMS output voltages should be considered when Power Dissipation See Figure 3 dealing with ac signals. Input Common-Mode Voltage ±V S Airflow reduces θ . In addition, more metal directly in contact Storage Temperature Range −65°C to +125°C JA with the package leads from metal traces, through holes, Operating Temperature Range −40°C to +85°C ground, and power planes reduces the θ . The exposed paddle Lead Temperature (Soldering, 10 sec) 300°C JA on the underside of the package must be soldered to a pad on Junction Temperature 150°C the PCB surface that is thermally connected to a ground plane Stresses above those listed under Absolute Maximum Ratings to achieve the specified θ . JA may cause permanent damage to the device. This is a stress Figure 3 shows the maximum safe power dissipation in the rating only and functional operation of the device at these or package vs. the ambient temperature for the 24-lead LFCSP any other conditions above those indicated in the operational (57°C/W) package on a JEDEC standard 4-layer board with the section of this specification is not implied. Exposure to absolute underside paddle soldered to a pad that is thermally connected maximum rating conditions for extended periods may affect to a ground plane. θ values are approximations. JA device reliability. 3.5 THERMAL RESISTANCE W) 3.0 θJA is specified for the worst-case conditions, that is, θJA is N ( specified for the device soldered in a circuit board in still air. TIO 2.5 A P Table 4. Thermal Resistance with the Underside Pad DISSI 2.0 Connected to the Plane R E Package Type/PCB Type θ Unit W 1.5 JA O P 24-Lead LFCSP_WQ/4-Layer 57 °C/W M U 1.0 M Maximum Power Dissipation XI A M 0.5 The maximum safe power dissipation in the AD8146/ AD8147/AD8148 package is limited by the associated rise in 0 jwuhniccthio ins ttheme gplearsast utrraen (sTitJi)o onn t etmhep deirea.t uArte a, pthpero pxliamstaicte clyh a1n5g0e°sC i,t s –40 –20 AMB0IENT TE2M0PERATU4R0E (°C) 60 80 09327-021 Figure 3. Maximum Power Dissipation vs. Temperature for a 4-Layer Board properties. Even temporarily exceeding this temperature limit can change the stresses that the package exerts on the die, permanently shifting the parametric performance of the ESD CAUTION AD8146/AD8147/AD8148. Exceeding a junction temperature of 175°C for an extended time can result in changes in the silicon devices, potentially causing failure. The power dissipated in the package (P ) is the sum of the D quiescent power dissipation and the power dissipated in the package due to the load drive for all outputs. The quiescent power is the voltage between the supply pins (VS) times the quiescent current (I). The load current consists of differential S and common-mode currents flowing to the loads, as well as currents flowing through the internal differential and common- Rev. B | Page 7 of 24

AD8146/AD8147/AD8148 Data Sheet PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS AB BB MM V+S NI– NI+V–SVCOVCO 432109 222221 PIN 1 OPD 1 INDICATOR 18VOCMC VS– 2 17VS+ –IN A 3 AD8146 16–IN C +IN A 4 TOP VIEW 15+IN C VS– 5 (Not to Scale) 14VS– –OUT A 6 13–OUT C 789012 111 A TUO+V+SB TUO+B TUO–V+SCT UO+ 09327-004 NOTES 1. THE EXPOSED PADDLE ON THE UNDERSIDE OF THE CHIP MUST BE CONNECTED TO A GROUND PLANE. Figure 4. AD8146 Pin Configuration Table 5. AD8146 Pin Function Descriptions Pin No. Mnemonic Description 1 OPD Output Pull-Down. 2, 5, 14, 21 V Negative Power Supply Voltage. S− 3 −IN A Inverting Input, Amplifier A. 4 +IN A Noninverting Input, Amplifier A. 6 −OUT A Negative Output, Amplifier A. 7 +OUT A Positive Output, Amplifier A. 8, 11, 17, 24 V Positive Power Supply Voltage. S+ 9 +OUT B Positive Output, Amplifier B. 10 −OUT B Negative Output, Amplifier B. 12 +OUT C Positive Output, Amplifier C. 13 −OUT C Negative Output, Amplifier C. 15 +IN C Noninverting Input, Amplifier C. 16 −IN C Inverting Input, Amplifier C. 18 V C The voltage applied to this pin controls output common-mode voltage, Amplifier C. OCM 19 V B The voltage applied to this pin controls output common-mode voltage, Amplifier B. OCM 20 V A The voltage applied to this pin controls output common-mode voltage, Amplifier A. OCM 22 +IN B Noninverting Input, Amplifier B. 23 −IN B Inverting Input, Amplifier B. Exposed Paddle GND Signal Ground Reference. Rev. B | Page 8 of 24

Data Sheet AD8146/AD8147/AD8148 )C N Y V+SG NI–GN +IS( V–SVCNYSHCNYS 432109 222221 PIN 1 OPD 1 INDICATOR 18SYNC LEVEL VS– 2 AD8147/ 17VS+ (SYNC) –IN R 3 16–IN B AD8148 +IN R 4 15+IN B VS– 5 (NToOt Pto V SIEcaWle) 14VS– –OUT R 6 13–OUT B 789012 111 R TUO+V+SG TUO+G TUO–V+SB TUO+ 09327-005 NOTES 1. THE EXPOSED PADDLE ON THE UNDERSIDE OF THE CHIP MUST BE CONNECTED TO A GROUND PLANE. Figure 5. AD8147/AD8148 Pin Configuration Table 6. AD8147/AD8148 Pin Function Descriptions Pin No. Mnemonic Description 1 OPD Output Pull-Down. 2, 5, 14 V Negative Power Supply Voltage. S− 3 −IN R Inverting Input, Red Amplifier. 4 +IN R Noninverting Input, Red Amplifier. 6 −OUT R Negative Output, Red Amplifier. 7 +OUT R Positive Output, Red Amplifier. 8, 11, 24 V Positive Power Supply Voltage. S+ 9 +OUT G Positive Output, Green Amplifier. 10 −OUT G Negative Output, Green Amplifier. 12 +OUT B Positive Output, Blue Amplifier. 13 −OUT B Negative Output, Blue Amplifier. 15 +IN B Noninverting Input, Blue Amplifier. 16 −IN B Inverting Input, Blue Amplifier. 17 V (SYNC) Positive Power Supply Voltage for Sync. S+ 18 SYNC LEVEL The voltage applied to this pin controls the amplitude of the sync pulses that are applied to the common-mode voltages. 19 H Horizontal Sync Pulse Input. SYNC 20 V Vertical Sync Pulse Input. SYNC 21 V (SYNC) Negative Power Supply Voltage for Sync. S− 22 +IN G Noninverting Input, Green Amplifier. 23 −IN G Inverting Input, Green Amplifier. Exposed Paddle GND Signal Ground Reference. Rev. B | Page 9 of 24

AD8146/AD8147/AD8148 Data Sheet TYPICAL PERFORMANCE CHARACTERISTICS V = ±5V; V = 0 V (AD8146); SYNC LEVEL = 0 V (AD8147/AD8148); T = 25°C; R, = 200 Ω; C = 0 pF, unless otherwise noted. S OCM L dm L, dm T to T = −40°C to +85°C. MIN MAX 9 15 VOUT, dm = 2V p-p VOUT, dm = 2V p-p 8 14 7 13 ±2.5V 6 12 ±5.0V B) 5 B) 11 N (d 4 AADD88114466 ((±±25..50VV)) N (d 10 GAI 3 AADD88114477 ((±±25..50VV)) GAI 9 2 8 1 7 0 6 –1 5 10 FREQUE1N0C0Y (MHz) 1000 09327-010 10 FREQUE1N0C0Y (MHz) 1000 09327-013 Figure 6. AD8146/AD8147 Large Signal Frequency Response for Various Supplies Figure 9. AD8148 Large Signal Frequency Response for Various Supplies 9 15 VOUT, dm = 0.2V p-p VOUT, dm = 0.2V p-p 8 14 7 13 6 12 ±5.0V B) 5 B) 11 GAIN (d 43 AAAADDDD8888111144446677 ((((±±±±2525....5050VVVV)))) GAIN (d 109 ±2.5V 2 8 1 7 0 6 –110 FREQUE1N0C0Y (MHz) 1000 09327-011 510 FREQUE1N0C0Y (MHz) 1000 09327-014 Figure 7. AD8146/AD8147 Small Signal Frequency Response for Various Supplies Figure 10. AD8148 Small Signal Frequency Response for Various Supplies 6.5 12.5 VOUT, dm = 2V p-p VOUT, dm = 2V p-p 6.4 12.4 6.3 12.3 6.2 12.2 B) 6.1 B)12.1 ±2.5V N (d 6.0 N (d12.0 AI AI G 5.9 G11.9 ±5.0V 5.8 AD8146 (±2.5V) 11.8 AD8146 (±5.0V) 5.7 AD8147 (±2.5V) 11.7 AD8147 (±5.0V) 5.6 11.6 5.51 10FREQUENCY (MHz1)00 1000 09327-012 11.51 10FREQUENCY (MHz1)00 1000 09327-015 Figure 8. AD8146/AD8147 Large Signal 0.1 dB Flatness for Various Supplies Figure 11. AD8148 Large Signal 0.1 dB Flatness for Various Supplies Rev. B | Page 10 of 24

Data Sheet AD8146/AD8147/AD8148 1.5 1.5 VOUT, dm = 2V p-p VOUT, dm = 2V p-p VS = ±2.5V VS = ±2.5V 1.0 1.0 0.5 VS = ±5.0V 0.5 VS = ±5.0V V) V) E ( E ( G G A 0 A 0 T T L L O O V V –0.5 –0.5 –1.0 –1.0 –1.5 –1.5 0 2 4 6 8TIM1E0 (ns)12 14 16 18 20 09327-016 0 2 4 6 8TIM1E0 (ns)12 14 16 18 20 09327-019 Figure 12. AD8146/AD8147 Large Signal Transient Response for Various Supplies Figure 15. AD8148 Large Signal Transient Response for Various Supplies 150 150 VS = ±2.5V VOUT, dm = 0.2V p-p VS = ±2.5V VOUT, dm = 0.2V p-p 100 100 V) 50 VS = ±5.0V V) 50 VS = ±5.0V m m E ( E ( G 0 G 0 A A T T L L O O V V –50 –50 –100 –100 –150 –150 0 2 4 6 8TIM1E0 (ns)12 14 16 18 20 09327-017 0 2 4 6 8TIM1E0 (ns)12 14 16 18 20 09327-020 Figure 13. AD8146/AD8147 Small Signal Transient Response for Various Supplies Figure 16. AD8148 Small Signal Transient Response for Various Supplies –20 –20 ΔVOUT, cm/ΔVOUT, dm ΔVOUT, dm/ΔVIN, cm –25 ΔVOUT, dm = 2V p-p ΔVIN, cm = 2V p-p E ERROR (dB) –––334050 AD8146 EJECTION (dB) ––3400 ADA8D1841748 C R BALAN ––4550 AD8147 MODE –50 OUTPUT ––5650 AD8148 COMMON- ––6700 AD8146 –65 –70 –80 1 10FREQUENCY (MHz1)00 1000 09327-024 1 10FREQUENCY (MHz1)00 1000 09327-027 Figure 14. Output Balance vs. Frequency Figure 17. CMRR vs. Frequency Rev. B | Page 11 of 24

AD8146/AD8147/AD8148 Data Sheet –20 –20 ΔVOUT, dm/ΔVS+ ΔVOUT, dm/ΔVS– –30 ΔVS = 2V p-p –30 ΔVS = 2V p-p B) B) N (d –40 N (d –40 AD8148 O O AD8147 TI TI –50 EC –50 EC J J RE AD8148 RE –60 Y –60 Y PL PL –70 P P U –70 AD8147 U AD8146 R S R S –80 E E W –80 W PO AD8146 PO –90 –90 –100 –100 –110 0.1 1 FREQUE1N0CY (MHz) 100 1000 09327-028 0.1 1 FREQUE1N0CY (MHz) 100 1000 09327-051 Figure 18. Positive Power Supply Rejection vs. Frequency Figure 21. Negative Power Supply Rejection vs. Frequency 1000 –20 VS = ±5V ΔVOUT, dmB/ΔVIN, dmA –30 ΔVIN, dmA = 1V p-p –40 AD8148 –50 OISE (nV/Hz) 100 AD8146 OLATION (dB) –––678000 AD8147 AD8146 N S I –90 AD8148 –100 AD8147 –110 10 –120 0.01 0.1 1 FRE1Q0UENCY1 0(k0Hz) 1000 10000 100000 09327-029 0.1 1 FREQUE1N0CY (MHz) 100 1000 09327-052 Figure 19. Output-Referred Voltage Noise vs. Frequency Figure 22. Amplifier-to-Amplifier Isolation vs. Frequency 10 10 INPUT × 2 (VS = ±5.0V) INPUT × 4 (VS = ±5.0V) 8 8 OUTPUT (VS = ±5.0V) OUTPUT (VS = ±5.0V) 6 6 INPUT × 2 (VS = ±2.5V) INPUT × 4 (VS = ±2.5V) 4 4 E (V) 2 E (V) 2 G G TA 0 OUTPUT (VS = ±2.5V) TA 0 OUTPUT (VS = ±2.5V) L L VO –2 VO –2 –4 –4 –6 –6 –8 –8 –10 –10 0 100 200 300 400TIM5E0 0(ns)600 700 800 900 1000 09327-030 0 100 200 300 400TIM5E0 0(ns)600 700 800 900 1000 09327-033 Figure 20. AD8146/AD8147 Output Overdrive Recovery Figure 23. AD8148 Output Overdrive Recovery Rev. B | Page 12 of 24

Data Sheet AD8146/AD8147/AD8148 59 62 IS+ (±5.0V) 57 60 IS+ (±5.0V) A) 55 A) 58 m m T ( T ( RL, dm = OPEN CIRCUIT N N E 53 E 56 R R UR RL, dm = OPEN CIRCUIT UR C C Y 51 Y 54 L L P P P P SU 49 IS+ (±2.5V) SU 52 IS+ (±2.5V) 47 50 45 48 –60 –40 –20 0TEMP2E0RATU4R0E (°C6)0 80 100 120 09327-054 –60 –40 –20 0TEMP2E0RATU4R0E (°C6)0 80 100 120 09327-056 Figure 24. AD8146 Supply Current vs. Temperature Figure 26. AD8147/AD8148 Supply Current vs. Temperature –35 1.5 ΔVOUT,dm/ΔVOCM ΔVOCM=2Vp-p ±VS = 5.0V ±VS = 2.5V –40 1.0 R (dB) –45 AD8146 E (V) 0.5 R G M –50 A 0 C T OCM VOL VOUT, cm = 2V p-p V –55 –0.5 –60 –1.0 –65 –1.5 1 10FREQUENCY(MHz1)00 1000 09327-061 0 5 10 15 TIM2E0 (ns) 25 30 35 40 09327-037 Figure 25. VOCM Common-Mode Rejection Ratio Figure 27. AD8146 Large Signal VOCM Transient Response for Various Supplies Rev. B | Page 13 of 24

AD8146/AD8147/AD8148 Data Sheet THEORY OF OPERATION Each differential driver differs from a conventional op amp in Common-Mode Voltage that it has two outputs whose voltages move in opposite directions. Common-mode voltage refers to the average of two node Like an op amp, it relies on high open-loop gain and negative voltages with respect to a common reference. The output feedback to force these outputs to the desired voltages. The common-mode voltage is defined as drivers make it easy to perform single-ended-to-differential V = (V + V )/2 conversion, common-mode level shifting, and amplification of OUT, cm OP ON differential signals. Output Balance Previous differential drivers, both discrete and integrated Output balance is a measure of how well the differential output designs, were based on using two independent amplifiers and signals are matched in amplitude and how close they are to two independent feedback loops, one to control each of the exactly 180° apart in phase. Balance is most easily determined outputs. When these circuits are driven from a single-ended by placing a well-matched resistor divider between the differential source, the resulting outputs are typically not well balanced. output voltage nodes and comparing the magnitude of the signal at Achieving a balanced output has typically required exceptional the divider’s midpoint with the magnitude of the differential matching of the amplifiers and feedback networks. signal. By this definition, output balance error is the magnitude of the change in output common-mode voltage divided by the DC common-mode level shifting has also been difficult with magnitude of the change in output differential mode voltage in previous differential drivers. Level shifting has required the use response to a differential input signal. of a third amplifier and feedback loop to control the output common-mode level. Sometimes, the third amplifier was also ∆V used to attempt to correct an inherently unbalanced circuit. OutputBalance Error= OUT,cm ∆V Excellent performance over a wide frequency range has proven OUT,dm difficult with this approach. ANALYZING AN APPLICATION CIRCUIT Each of the drivers uses two feedback loops to separately The drivers use high open-loop gain and negative feedback to control the differential and common-mode output voltages. force their differential and common-mode output voltages to The differential feedback, set by the internal resistors, controls minimize the differential and common-mode input error only the differential output voltage. The internal common- voltages. The differential input error voltage is defined as the mode feedback loop controls only the common-mode output voltage between the differential inputs labeled V and V in AP AN voltage. This architecture makes it easy to transmit signals over Figure 28. For most purposes, this voltage can be assumed to be the common-mode voltage channels by simply applying the zero. Similarly, the difference between the actual output common- signal voltages to the VOCM inputs. The output common-mode mode voltage and the voltage applied to VOCM can also be voltage is forced, by internal common-mode feedback, to equal assumed to be zero. Starting from these two assumptions, the voltage applied to the VOCM input, without affecting the any application circuit can be analyzed. differential output voltage. CLOSED-LOOP GAIN The driver architecture results in outputs that are highly The differential mode gain of the circuit in Figure 28 can be balanced over a wide frequency range without requiring described by external components or adjustments. The common-mode feedback loop forces the signal component of the output common-mode voltage to be zeroed. The result is nearly VOUT,dm = RF V R perfectly balanced differential outputs of identical IN,dm G amplitude that are exactly 180° apart in phase. where: DEFINITION OF TERMS R is 1.0 kΩ and R is 500 Ω nominally for the AD8146 and F G Differential Voltage AD8147. R is 2.0 kΩ and R is 500 Ω nominally for the AD8148. F G Differential voltage refers to the difference between two node voltages that are balanced with respect to each other. For RF example, in Figure 28 the output differential voltage (or RG VAP + VIP VON equivalently output differential mode voltage) is defined as VIN, dm VOCM RL, dm VOUT, dm VOUT, dm = (VOP − VON) – VIN RG VAN RF VOP 09327-006 Figure 28. Internal Architecture and Signal Name Definitions Rev. B | Page 14 of 24

Data Sheet AD8146/AD8147/AD8148 CALCULATING THE INPUT IMPEDANCE OUTPUT COMMON-MODE CONTROL The effective input impedance of a circuit such as that in The AD8146 allows the user to control each of the three Figure 28 at V and V depends on whether the amplifier is common-mode output levels independently through the three IP IN being driven by a single-ended or differential signal source. For V input pins. The V pins pass a signal to the common- OCM OCM balanced differential input signals, the differential input impedance, mode output level of each of their respective amplifiers with R , between the inputs V and V for all devices is 330 MHz of small signal bandwidth and an internally fixed gain IN, dm IP IN of 1. In this way, additional control and communication signals R = 2 × R IN, dm G can be embedded on the common-mode levels as users see fit. In the case of a single-ended input signal (for example, if V is IN With no external circuitry, the level at the V input of each grounded and the input signal is applied to V ), the input OCM IP amplifier defaults to approximately midsupply. An internal impedance becomes resistive divider with an impedance of approximately 12.5 kΩ     sets this level. To limit common-mode noise in dc common- R = RG  mode applications, external bypass capacitors should be IN,dm  R  1− ( F ) connected from each of the VOCM input pins to ground.  2× RG+RF  SYNC-ON COMMON-MODE The single-ended input impedance of the AD8146 and the The AD8147 and AD8148 are specifically targeted at driving AD8147 is therefore 750 Ω, and the single-ended input RGB video signals over UTP cable using a sync-on common- impedance of the AD8148 is 833 Ω. mode technique. The common-mode outputs of each of the R, The input impedance of the circuit is effectively higher than it G, and B differential outputs are set using circuitry contained would be for a conventional op amp connected as an inverter within the device. This circuitry embeds the horizontal and because a fraction of the differential output voltage appears at vertical sync pulses on the three common-mode outputs in a the inputs as a common-mode signal, partially bootstrapping way that also results in low radiated energy. For a more detailed the voltage across the input resistor R . description of the sync scheme, see the Applications section. G INPUT COMMON-MODE VOLTAGE RANGE IN The sync-on common-mode circuit generates a current based SINGLE-SUPPLY APPLICATIONS on the SYNC LEVEL input pin (Pin 18). With the SYNC LEVEL input tied to GND, the common-mode output of all drivers is The driver inputs are designed to facilitate level-shifting of set at (V + V )/2. Using a resistor divider, a voltage can be ground-referenced input signals on a single power supply. For a S+ S− applied between GND and SYNC LEVEL that determines the single-ended input, this implies, for example, that the voltage at maximum deviation of the common-mode outputs from their V in Figure 28 would be 0 V when the negative power supply IN midsupply level. If, for instance, SYNC LEVEL = 0.5 V and the voltage of the amplifier is also set to 0 V. supply voltage is 5 V, the common-mode outputs fall within an It is important to ensure that the common-mode voltage at the envelope of 2.5 V ± 0.5 V. The state of each V output based OUT, cm amplifier inputs, VAP and VAN, stays within its specified range. on the HSYNC and VSYNC inputs is determined by the equations Because voltages VAP and VAN are driven to be essentially equal defined in the Applications section. by negative feedback, the input common-mode voltage of the In most cases, the sync-on common-mode circuit can be used amplifier can be expressed as a single term, V . V can be ACM ACM by directly applying the H and V signals to their respective calculated as SYNC SYNC AD8147 or AD8148 inputs. The logic thresholds of the H SYNC V =VOCM +2VICM and VSYNC inputs are set to nominally 1.4 V with respect to ACM 3 GND, and the exposed paddles of the AD8147 and AD8148 where V is the common-mode voltage of the input signal, are used as the GND references for the incoming sync pulses. ICM that is, V = (V + V )/2. When ±2.5 V supplies are used, however, external protection is ICM IP IN required to limit the positive excursion to less than 2.5 V. For more details, see the Applications section. The input paths from the H and V inputs to the switches SYNC SYNC in the current mode level-shifting circuit are well matched to eliminate false switching transients, maximizing common- mode balance and minimizing radiated energy. Rev. B | Page 15 of 24

AD8146/AD8147/AD8148 Data Sheet APPLICATIONS DRIVING RGB VIDEO SIGNALS OVER CATEGORY-5 VIDEO SYNC-ON COMMON-MODE UTP CABLE In computer video applications, the horizontal and vertical sync signals are often separate from the video information signals. The foremost application of the drivers is the transmission of For example, in typical computer monitor applications, the red, RGB video signals over UTP cable in KVM networks. The green, and blue (RGB) color signals are transmitted over separate excellent balance of the differential outputs ensures low radiated cables, as are the vertical and horizontal sync signals. When energy from each of the twisted pairs. Single-ended video signals transmitting these types of video signals over long distances on are easily converted to differential signals for transmission over UTP cable, it is desirable to reduce the required number of the cable, and the internally fixed gain of 2 or 4 automatically physical channels. One way to do this is to encode the vertical compensates for the losses incurred by the source and load and horizontal sync signals as weighted sums and differences of terminations. The common topologies used in KVM networks, the output common-mode signals. The RGB color signals are such as daisy-chained, star, and point-to-point, are supported each transmitted differentially over separate physical channels. by the drivers. Figure 29 shows the AD8146 in a triple single- The fact that the differential and common-mode signals are ended-to-differential application when driven from a 75 Ω orthogonal allows the RGB color and sync signals to be source, which is typical of how RGB video is driven over an separated at the channel’s receiver. UTP cable. +5V Cat-5 cable contains four balanced twisted-pair physical channels that can support both differential and common-mode 0.1µF ON ALL VS+ PINS VS+ signals. Transmitting typical computer monitor video over this AD8146 cable can be accomplished by using three of the twisted pairs for 1kΩ the RGB and sync signals and one wire of the fourth pair as a return path for the Schottky diode bias currents. Each color is 75Ω 500Ω 49.9Ω – transmitted differentially, one on each of the three pairs, and the VIDEO 82.5Ω +2.5V 500Ω VOCM A 49.9Ω OUT A encoded sync signals are transmitted among the common-mode SOURCE A + signals of each of the three pairs. To minimize EMI from the 39.2Ω 1kΩ sync signals, the common-mode signals on each of the three 1kΩ pairs produced by the sync encoding scheme induce electric and magnetic fields that for the most part cancel each other. A 75Ω 500Ω 49.9Ω – conceptual block diagram of the sync encoding scheme is VIDEO 82.5Ω +2.5V 500Ω VOCM B 49.9Ω OUT B presented in Figure 30. Because the AD8147/AD8148 have the SOURCE B + sync encoding scheme implemented internally, the user simply 39.2Ω 1kΩ applies the horizontal and vertical sync signals to the appropriate 1kΩ inputs. (See the Specifications tables for the high and low levels of the horizontal and vertical sync pulse voltages). 75Ω 500Ω 49.9Ω – VIDEO 82.5Ω +2.5V 500Ω VOCM C 49.9Ω OUT C SOURCE C + 39.2Ω 1kΩ OPD OUTPUT PULLDOWN VS– 09327-007 Figure 29. AD8146 in Single-Ended-to-Differential Application Rev. B | Page 16 of 24

Data Sheet AD8146/AD8147/AD8148 3.1 AD8147/AD8148 1kΩ 3.0 G 500Ω 2.9 +IN R –OUT R 2.8 500Ω VOCM R –IN R +OUT R 2.7 S 1kΩ T 2.6 VSYNC OL V 2.5 R 2.4 2.3 HSYNC 2.2 SYNC LEVEL 1kΩ 2.1 B 500Ω 2.0 +IN G –OUT G ×2 VOCM G 5.0 500Ω –IN G +OUT G 4.5 1kΩ 4.0 3.5 1kΩ 3.0 500Ω TS +IN B –OUT B OL 2.5 500Ω VOCM B V 2.0 HSYNC VSYNC –IN B +OUT B 1.5 1kΩ 1.0 OPD 0.5 VRGBOELRUCDEME EV NWVO OCVEMCOIGM C= HM=K2T =K2(IVN(K2VSG(YS– NYE2CNQVC S–U Y +AHN THSCIYS)O NY+NCN VCS) M+): I+VD SVMUMIDPISDPULSYPUPPLPYLY 09327-008 Figure 3100.. 9A8D8104.979 Syn1.c0-0On 1C.o01mm1oT.0nIM2-ME (o1µd.s0e)3 Sig1n.0a4ls in1 .S05ingle1 .506 V A1p.p07lica09327-009t ion Figure 30. AD8147/AD8148 Sync-On Common-Mode Encoding Scheme The transmitted common-mode sync signal magnitudes are scaled by applying a dc voltage to the SYNC LEVEL input, referenced to GND. The difference between the voltage applied to the SYNC LEVEL input and GND sets the peak deviation of the encoded sync signals about the midsupply, common-mode voltage. For example, with the SYNC LEVEL input set at 500 mV, the deviation of the encoded sync pulses about the nominal midsupply, common-mode voltage is typically ±500 mV. The equations in Figure 30 describe how the V and H signals SYNC SYNC are encoded on each color’s midsupply common-mode signal. In these equations, the weights of the V and H signals SYNC SYNC are ±1 (+1 for high and −1 for low), and the constant K is equal to the peak deviation of the encoded sync signals. Figure 31 shows how the sync signals appear on each common- mode voltage in a single 5 V supply application when the voltage applied to the SYNC LEVEL input is 500 mV, which is the typical setting for most applications. Rev. B | Page 17 of 24

AD8146/AD8147/AD8148 Data Sheet Sync pulse amplitudes applied to the AD8147 and AD8148 must Driver bandwidth is affected to a small degree when driving the be less than or equal to the positive supply voltage. In low 100 Ω load presented by the two cables, as compared with positive supply applications, such as those that use ±2.5 V supplies, driving a typical 200 Ω load. Figure 34 illustrates the AD8146/ external limiting may be required because many logic families AD8147/AD8148 bandwidths when driving a 100 Ω load. produce amplitudes up to 5 V. Figure 32 illustrates how to use a 15 monolithic triple diode to limit a sync pulse with 5 V amplitude to an amplitude of approximately 2 V. 12 AD8148 INCOMING SYNC PULSE +5V LIMITED 9 301Ω SYNC PULSE B) +2V d 0V 1 2 3 HN2D02FUTW1T1 0V AIN ( 6 6 5 4 06655-036 G 3 AADD88114476 Figure 32. Limiting Sync Pulse Amplitude in Low Positive Supply Applications 0 DRIVING TWO UTP CABLES WITH ONE DRIVER RL, dm = 100Ω VOUT = 2V p-p Some applications require driving two UTP cables with a single –3 driver. Each individual driver of the AD8146/AD8147/AD8148 1 10 FREQUENCY (M10H0z) 1000 09327-044 is capable of driving two doubly terminated cables, which places Figure 34. Large Signal Frequency Response Driving 100 Ω Loads a differential load of 100 Ω across the outputs of the driver. USING THE AD8146 AS A RECEIVER Figure 33 illustrates how to drive two cables. 49.9Ω While the AD8146 excels as a differential driver, it can also be AD8146/AD8147/AD8148 used as a differential-to-differential receiver applied as an 100Ω 49.9Ω UTP 100Ω input buffer that protects a more sophisticated device, such as a differential crosspoint switch. See Figure 35 for an illustration of this type of application. VOCM Because the AD8146 V input pins are uncommitted, any OCM incoming common-mode signal, such as encoded sync pulses, can be reproduced at the AD8146 outputs by stripping it from 49.9Ω the received signal and applying it directly to the V pin. OCM 49.9Ω 1 U00TΩP 100Ω 09327-034 Trehsies ttowr oo fs e1r0i9e.s8 5Ω4,. 9w Ωhi crhes wishtoerns lfooardmed a w diitfhfe trheen 1ti aklΩ t edrimffeinreanttiioanl Figure 33. Driving Two UTP Cables With One Driver input resistance of the AD8146, provides an overall termination of approximately 100 Ω. The received common-mode voltages are available at the center taps between the two resistors. Rev. B | Page 18 of 24

Data Sheet AD8146/AD8147/AD8148 VS+ = +2.5V VPOS = +2.5V AD8146 1kΩ CROSSPOINT SWITCH 54.9Ω 500Ω 10Ω INPUT I, NEGATIVE PHASE CHRAENDNEL 1U00TΩP 500Ω VOCM 10Ω INPUT I, POSITIVE PHASE 54.9Ω 1kΩ 1kΩ 54.9Ω 500Ω 10Ω INPUT J, NEGATIVE PHASE CGHARNENENEL 1U00TΩP 500Ω VOCM 10Ω INPUT J, POSITIVE PHASE 54.9Ω 1kΩ 1kΩ 54.9Ω 500Ω 10Ω INPUT K, NEGATIVE PHASE CHBALNUNEEL 1U00TΩP 500Ω VOCM 10Ω INPUT K, POSITIVE PHASE 54.9Ω 1kΩ VS– = –2.5V VNEG = –2.5V 09327-035 Figure 35. Using the AD8146 as a Differential Receiver Terminations are not required between the AD8146 and the LAYOUT AND POWER SUPPLY DECOUPLING switch if the interconnection lengths are kept short (less than CONSIDERATIONS two inches). The 10 Ω series resistors buffer the input Standard high speed PCB layout practices should be adhered capacitance of the switch (typically 2 pF) and produce a low- to when designing with the drivers. A solid ground plane is pass rolloff that is down by only 0.025 dB at 600 MHz. required and good wideband power supply decoupling OUTPUT PULL-DOWN (OPD) networks should be placed as close as possible to the supply pins. Small surface-mount ceramic capacitors are recommended The output pull-down feature, when used in conjunction with for these networks, and tantalum capacitors are recommended series Schottky diodes, offers a convenient means to multiplex a for bulk supply decoupling. number of driver outputs together to form a video network. The OPD pin is a binary input that controls the state of the outputs. Source termination resistors on the differential outputs must be Its binary input level is referenced to GND (see the Specifications placed as close as possible to the output pins to minimize load section for the logic levels). When the OPD input is driven to its capacitance due to the PCB traces. low state, the output is enabled and operates in normal fashion. DRIVING A CAPACITIVE LOAD In this state, the V input can be used to provide a positive OCM A purely capacitive load can react with the output impedance bias on the series diodes, allowing the drivers to transmit of any amplifier to produce an undesirable phase shift, which signals over the network. When the OPD input is driven to its reduces phase margin and results in high frequency ringing in high state, the outputs of the drivers are forced to a low voltage, the pulse response. The best way to minimize this effect is to irrespective of the level on the V input, reverse-biasing the OCM place a small resistor in series with each of the outputs of the series diodes and thus presenting high impedance to the amplifier to buffer the load capacitance. Most applications network. This feature allows a three-state output to be realized include 49.9 Ω source termination resistors, which effectively that maintains its high impedance state even when the drivers buffer any stray load capacitance. are not powered. It is recommended that the output pull-down feature only be used in conjunction with series diodes in such a way as to ensure that the diodes are reverse-biased when the output pull- down feature is asserted, because some loading conditions can prevent the output voltage from being pulled all the way down. Rev. B | Page 19 of 24

AD8146/AD8147/AD8148 Data Sheet Under no circumstances should capacitance be intentionally ADDING PRE-EMPHASIS TO THE AD8148 added to an output to introduce frequency domain peaking. UTP cables exhibit loss characteristics that are low pass in Figure 36 and Figure 37 illustrate how adding just 5 pF of nature and are exponential functions of the square root of the excessive load capacitance influences time and frequency frequency. Over wideband video bandwidths, the losses are domain responses. predominantly due to the skin effect, which causes the resistance of 2.0 the cable to increase with frequency. Even though the loss VS = ±5V 1.5 RL, dm = 200Ω characteristics are nonlinear, suitable linear networks can be CL = 5pF VOUT, dm = 2V p-p designed to approximately compensate for the losses. 1.0 Placing the compensation network at the transmitting end of E (V) 0.5 CL = 0pF the cable is referred to as pre-emphasis, because the higher G frequencies are emphasized, or boosted, before they are sent, to A 0 T L compensate for the low-pass response of the cable. Because the O V–0.5 higher frequencies experience more loss than the lower frequencies as they pass through the cable, the high and low frequencies –1.0 arrive at approximately the same level and at the end of the cable –1.5 when a properly designed pre-emphasis network is used at the transmitter. The ideal cascaded frequency response of the pre- –2.0 0 2 4 6 8TIM1E0 (ns)12 14 16 18 20 09327-031 emphasis network and the cable is therefore nominally flat. Figure 36. Large Signal Transient Responses at Various Capacitive Loads Because the AD8148 has an internally set, closed-loop gain of 4 (12 dB), it is possible to reduce the gain at low frequencies using 12 VS = ±5V external frequency selective components, then use these 11 RVOL,U dTm, d =m 2 =0 02ΩV p-p CL = 5pF components to provide increasing gain with increasing 10 frequency, back to a value close to 12 dB. These components, along 9 with the AD8148, form the pre-emphasis network. When properly B) 8 designed, the combined frequency response of the pre-emphasis N (d 7 network and cable is approximately flat with a gain of 2 (6 dB). AI G 6 Figure 38 illustrates how to construct a pre-emphasis network 5 CL = 0pF using the AD8148 that compensates for 30 meters of UTP cable. The network in the lower leg is required to match the transfer 4 function of the two feedback loops. 3 At dc, the capacitors are open circuits, and the network has a 2 10 FREQUE1N0C0Y (MHz) 1000 09327-032 gcoaimn poefn aspapter ofxoirm thaete clya b6l.e5 fdlaBt .l o(Tssh teh aadt doictciounras la 0t .f5r edqBu eisn acdiedse d to Figure 37. Large Signal Frequency Responses at Various Capacitive Loads below where the skin effect begins to take effect.) Moving up in frequency, the 30 pF capacitor begins to take effect and introduces While high frequency peaking is desirable in some cable a zero into the frequency response, causing the gain to increase equalization applications, it should be implemented using with frequency. Continuing to move up in frequency, the 30 pF methods that do not compromise the stability of the driver and capacitor becomes an effective short, and the 487 Ω resistor that do not depend on amplifier parasitic elements. The parasitic goes in parallel with the 442 Ω resistor, forming a pole in the elements are affected by process variations and cannot be response. Continuing to move up in frequency, the 18 pF depended upon for circuit designs. The amplifier may break capacitor takes effect, introducing another zero, and causes into oscillation when excess load capacitance is intentionally the gain to further increase with frequency until it becomes added. For more information on this topic, see the Adding Pre- an effective short, and the gain starts to flatten out until the Emphasis to the section for a description on how to introduce a amplifier response begins to roll off. The gain does not reach controlled amount of pre-emphasis for 30 meters of UTP using 12 dB before the amplifier begins to roll off because the 12 dB the AD8148. value is a high frequency asymptote. The pole and zero locations cited in the previous discussion are qualitative, but the discussion describes the basic principles involved with the operation of the pre-emphasis network. Rev. B | Page 20 of 24

Data Sheet AD8146/AD8147/AD8148 Figure 39 illustrates the frequency response of the pre-emphasis EXPOSED PADDLE (EP) network. The 24-lead LFCSP has an exposed paddle on the underside of Figure 40 illustrates the frequency response of the pre-emphasis its body. To achieve the specified thermal resistance, it must circuit cascaded with the cable compared with that of the cable have a good thermal connection to one of the PCB planes. The alone. It can be seen that the overall response is flat to within exposed paddle must therefore be soldered to a pad on the top ±0.4 dB. The ±0.4 dB ripple in the response is due to the fact of the board that is connected to an inner plane with several that the pre-emphasis network is linear, comprised of two real- thermal vias. The AD8147/AD8148 use the paddle as a ground axis pole/zero pairs, and the cable response is nonlinear. reference; therefore, for these parts, the PCB plane used must be the ground plane. 18pF 487Ω 30pF 2kΩ 75Ω 442Ω 500Ω 49.9Ω + 100 FEET VIDEO 82.5Ω AD8148 100Ω SOURCE 500Ω 49.9Ω UTP – 442Ω 2kΩ 487Ω 30pF 18pF 39.2Ω 09327-048 Figure 38. Pre-Emphasis Network Using the AD8148 for 30 Meters of UTP Cable 12 9 VS = ±5V VS = ±5V 11 6 PRE-EMPHASIS NETWORK WITH CABLE 10 3 B) B) d d N ( 9 N ( 0 AI AI G G 8 –3 CABLE ALONE 7 –6 6 –9 0.1 1 FREQUENCY (M1H0z) 100 09327-049 0.1 1 FREQUENCY (M1H0z) 100 09327-050 Figure 40. AD8148 Pre-Emphasis Network Cascaded With Figure 39. AD8148 Pre-Emphasis Network Frequency Response 30 Meters of UTP Cable vs. UTP Cable Alone Rev. B | Page 21 of 24

AD8146/AD8147/AD8148 Data Sheet OUTLINE DIMENSIONS 4.10 0.30 4.00 SQ 0.25 PIN 1 3.90 0.20 INDICATOR PIN 1 0.50 19 24 INDICATOR BSC 18 1 EXPOSED 2.20 PAD 2.10 SQ 2.00 13 6 0.50 12 7 0.25 MIN TOP VIEW 0.40 BOTTOM VIEW 0.30 FOR PROPER CONNECTION OF 0.80 THE EXPOSED PAD, REFER TO 0.75 0.05 MAX THE PIN CONFIGURATION AND 0.70 0.02 NOM FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. COPLANARITY SEATING 0.08 PLANE COMPLIANTTOJED0E.2C0 SRTEAFNDARDS MO-220-WGGD-8. 06-11-2012-A Figure 41. 24-Lead Lead Frame Chip Scale Package [LFCSP_WQ] 4 mm × 4 mm Body, Very Very Thin Quad (CP-24-10) Dimensions shown in millimeters ORDERING GUIDE Model1 Temperature Range Package Description Package Option AD8146ACPZ-R2 −40°C to +85°C 24-Lead Lead Frame Chip Scale Package [LFCSP_WQ] CP-24-10 AD8146ACPZ-R7 −40°C to +85°C 24-Lead Lead Frame Chip Scale Package [LFCSP_WQ] CP-24-10 AD8146ACPZ-RL −40°C to +85°C 24-Lead Lead Frame Chip Scale Package [LFCSP_WQ] CP-24-10 AD8147ACPZ-R2 −40°C to +85°C 24-Lead Lead Frame Chip Scale Package [LFCSP_WQ] CP-24-10 AD8147ACPZ-R7 −40°C to +85°C 24-Lead Lead Frame Chip Scale Package [LFCSP_WQ] CP-24-10 AD8147ACPZ-RL −40°C to +85°C 24-Lead Lead Frame Chip Scale Package [LFCSP_WQ] CP-24-10 AD8147-EVALZ Evaluation Board AD8148ACPZ-R2 −40°C to +85°C 24-Lead Lead Frame Chip Scale Package [LFCSP_WQ] CP-24-10 AD8148ACPZ-R7 −40°C to +85°C 24-Lead Lead Frame Chip Scale Package [LFCSP_WQ] CP-24-10 AD8148ACPZ-RL −40°C to +85°C 24-Lead Lead Frame Chip Scale Package [LFCSP_WQ] CP-24-10 1 Z = RoHS Compliant Part. Rev. B | Page 22 of 24

Data Sheet AD8146/AD8147/AD8148 NOTES Rev. B | Page 23 of 24

AD8146/AD8147/AD8148 Data Sheet NOTES ©2007–2014 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D09327-0-3/14(B) Rev. B | Page 24 of 24