Low Cost, Low Power, Differential ADC Driver Data Sheet AD8137 FEATURES FUNCTIONAL BLOCK DIAGRAM Fully differential AD8137 Extremely low power with power-down feature –IN 1 8 +IN 2.6 mA quiescent supply current @ 5 V VOCM 2 7 PD Hig41h51 00s pMµeAHe idzn l aprogwee sri-gdnoawl 3n dmBo bdaen @d w5 iVd th @ G = 1 +OVUST+ 43 65 V–OS–UT 04771-0-001 Figure 1. 450 V/µs slew rate 12-bit SFDR performance @ 500 kHz Fast settling time: 100 ns to 0.02% 3 Low input offset voltage: ±2.6 mV max 2 G = 1 Low input offset current: 0.45 µA max dB) 1 N ( 0 Differential input and output AI G –1 G = 2 Differential-to-differential or single-ended-to-differential OP –2 G = 5 operation LO –3 Rail-to-rail output ED- –4 S O –5 Adjustable output common-mode voltage CL –6 G = 10 Externally adjustable gain ED –7 Z Wide supply voltage range: 2.7 V to 12 V LI –8 A Available in small SOIC package RM –9 QAuPaPliLfiIeCdA fTorI OauNtoSm otive applications NO –––1112100.1VROG, =d m1k =Ω 0.1V1 p-p 10 100 10004771-0-0020 FREQUENCY (MHz) ADC drivers Figure 2. Small Signal Response for Various Gains Automotive vision and safety systems Automotive infotainment systems Portable instrumentation Battery-powered applications Single-ended-to-differential converters Differential active filters Video amplifiers Level shifters GENERAL DESCRIPTON The AD8137 is a low cost differential driver with a rail-to-rail closed-loop gain of the amplifier. The power-down feature is output that is ideal for driving ADCs in systems that are sensitive beneficial in critical low power applications. to power and cost. The AD8137 is easy to apply, and its internal The AD8137 is manufactured on Analog Devices, Inc., common-mode feedback architecture allows its output common- proprietary second-generation XFCB process, enabling it to mode voltage to be controlled by the voltage applied to one pin. achieve high levels of performance with very low power The internal feedback loop also provides inherently balanced consumption. outputs as well as suppression of even-order harmonic distortion The AD8137 is available in the small 8-lead SOIC package and products. Fully differential and single-ended-to-differential gain 3 mm × 3 mm LFCSP package. It is rated to operate over the configurations are easily realized by the AD8137. External extended industrial temperature range of −40°C to +125°C. feedback networks consisting of four resistors determine the Rev. E Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Tel: 781.329.4700 www.analog.com Trademarks and registered trademarks are the property of their respective owners. Fax: 781.461.3113 ©2004–2012 Analog Devices, Inc. All rights reserved.

AD8137 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Test Circuits ..................................................................................... 21 Applications ....................................................................................... 1 Theory of Operation ...................................................................... 22 Functional Block Diagram .............................................................. 1 Applications Information .............................................................. 23 General Descripton .......................................................................... 1 Analyzing a Typical Application with Matched R and R F G Revision History ............................................................................... 2 Networks ...................................................................................... 23 Specifications ..................................................................................... 3 Estimating Noise, Gain, and Bandwith with Matched Feedback Networks .................................................................... 23 Absolute Maximum Ratings ............................................................ 9 Driving an ADC with Greater than 12-Bit Performance ...... 27 Thermal Resistance ...................................................................... 9 Outline Dimensions ....................................................................... 29 Maximum Power Dissipation ..................................................... 9 Ordering Guide .......................................................................... 30 ESD Caution .................................................................................. 9 Automotive Products ................................................................. 30 Pin Configuration and Function Descriptions ........................... 10 Typical Performance Characteristics ........................................... 11 REVISION HISTORY 7/12—Rev. D to Rev. E 8/04—Rev. 0 to Rev. A. Changes to Features Section and Applications Section ............... 1 Added 8-Lead LFCSP ......................................................... Universal Added AD8137W ............................................................... Universal Changes to Layout .............................................................. Universal Updated Outline Dimensions ....................................................... 28 Changes to Product Title and Figure 1 ........................................... 1 Changes to Ordering Guide .......................................................... 29 Changes to Specifications ................................................................. 3 Added Automotive Products Section .......................................... 29 Changes to Absolute Maximum Ratings ........................................ 6 Changes to Figure 4 and Figure 5 .................................................... 7 7/10—Rev. C to Rev. D Added Figure 6, Figure 20, Figure 23, Figure 35, Figure 48, Changes to Power-Down Section, Added Figure 68, and Figure 58; Renumbered Sequentially ...................................... 7 Renumbered Subsequent Figures ................................................. 24 Changes to Figure 32 ...................................................................... 12 Changes to Ordering Guide .......................................................... 27 Changes to Figure 40 ...................................................................... 13 Changes to Figure 55 ...................................................................... 16 12/09—Rev. B to Rev. C Changes to Table 7 and Figure 63................................................. 18 Changes to Product Title, Applications Section, and General Changes to Equation 19 ................................................................. 19 Description Section .......................................................................... 1 Changes to Figure 64 and Figure 65............................................. 20 Changes to Input Resistance Parameter Unit, Table 3 ................. 5 Changes to Figure 66 ...................................................................... 22 Added EPAD Mnemonic/Description, Table 6 ............................ 7 Added Driving an ADC with Greater Than 12-Bit Added Figure 61; Renumbered Sequentially .............................. 17 Performance Section ...................................................................... 22 Moved Test Circuits Section .......................................................... 18 Changes to Ordering Guide .......................................................... 24 Changes to Power Down Section ................................................. 24 Updated Outline Dimensions ....................................................... 24 Updated Outline Dimensions ....................................................... 26 5/04—Revision 0: Initial Version 7/05—Rev. A to Rev. B Changes to Ordering Guide .......................................................... 24 Rev. E | Page 2 of 32

Data Sheet AD8137 SPECIFICATIONS V = ±5 V, V = 0 V (@ 25°C, differential gain = 1, R = R = R = 1 kΩ, unless otherwise noted, T to T = −40°C to +125°C). S OCM L, dm F G MIN MAX Table 1. Parameter Conditions Min Typ Max Unit DIFFERENTIAL INPUT PERFORMANCE Dynamic Performance −3 dB Small Signal Bandwidth V = 0.1 V p-p 64 76 MHz O, dm AD8137W only: T -T 63 MHz MIN MAX −3 dB Large Signal Bandwidth V = 2 V p-p 79 110 MHz O, dm AD8137W only: T -T 79 MHz MIN MAX Slew Rate V = 2 V step 450 V/µs O, dm Settling Time to 0.02% V = 3.5 V step 100 Ns O, dm Overdrive Recovery Time G = 2, V = 12 V p-p triangle wave 85 Ns I, dm Noise/Harmonic Performance SFDR V = 2 V p-p, f = 500 kHz 90 dB O, dm C V = 2 V p-p, f = 2 MHz 76 dB O, dm C Input Voltage Noise f = 50 kHz to 1 MHz 8.25 nV/√Hz Input Current Noise f = 50 kHz to 1 MHz 1 pA/√Hz DC Performance Input Offset Voltage V = V = V = 0 V −2.6 ±0.7 +2.6 mV IP IN OCM AD8137W only: T -T −5.0 +5.0 mV MIN MAX Input Offset Voltage Drift T to T 3 µV/°C MIN MAX Input Bias Current T to T 0.5 1.0 µA MIN MAX Input Offset Current 0.1 0.45 µA AD8137W only: T -T 0.45 µA MIN MAX Open-Loop Gain 91 dB Input Characteristics Input Common-Mode Voltage Range −4 +4 V AD8137W only: T -T −4 +4 V MIN MAX Input Resistance Differential 800 KΩ Common-mode 400 KΩ Input Capacitance Common-mode 1.8 pF CMRR ΔV = ±1 V 66 79 dB ICM AD8137W only: T -T 66 dB MIN MAX Output Characteristics Output Voltage Swing Each single-ended output, R = 1 kΩ V + 0.55 V − 0.55 V L, dm S− S+ AD8137W only: T -T V + 0.55 V − 0.55 V MIN MAX S− S+ Output Current 20 mA Output Balance Error f = 1 MHz −64 dB V to V PERFORMANCE OCM O, cm V Dynamic Performance OCM −3 dB Bandwidth V = 0.1 V p-p 58 MHz O, cm Slew Rate V = 0.5 V p-p 63 V/µs O, cm Gain 0.992 1.000 1.008 V/V AD8137W only: T -T 0.990 1.008 V/V MIN MAX V Input Characteristics OCM Input Voltage Range −4 +4 V AD8137W only: T -T −4 +4 V MIN MAX Input Resistance 35 kΩ Input Offset Voltage −28 ±11 +28 mV AD8137W only: T -T −28 +28 mV MIN MAX Input Voltage Noise f = 100 kHz to 1 MHz 18 nV/√Hz Rev. E | Page 3 of 32

AD8137 Data Sheet Parameter Conditions Min Typ Max Unit Input Bias Current 0.3 1.1 µA AD8137W only: T -T 1.1 µA MIN MAX CMRR ΔV /ΔV , ΔV = ±0.5 V 62 75 dB O, dm OCM OCM AD8137W only: T -T 62 dB MIN MAX Power Supply Operating Range +2.7 ±6 V AD8137W only: T -T +2.7 ±6 V MIN MAX Quiescent Current 3.2 3.60 mA AD8137W only: T -T 3.65 mA MIN MAX Quiescent Current, Disabled Power-down = low 750 900 µA AD8137W only: T -T 900 µA MIN MAX PSRR ΔV = ±1 V 79 91 dB S AD8137W only: T -T 79 dB MIN MAX PD Pin Threshold Voltage V + 0.7 V + 1.7 V S− S− AD8137W only: T -T V + 0.7 V + 1.7 V MIN MAX S− S− Input Current Power-down = high/low 150/210 170/240 µA AD8137W only: T -T 180/245 µA MIN MAX OPERATING TEMPERATURE RANGE −40 +125 °C Rev. E | Page 4 of 32

Data Sheet AD8137 V = 5 V, V = 2.5 V (@ 25°C, differential gain = 1, R = R = R = 1 kΩ, unless otherwise noted, T to T = −40°C to +125°C). S OCM L, dm F G MIN MAX Table 2. Parameter Conditions Min Typ Max Unit DIFFERENTIAL INPUT PERFORMANCE Dynamic Performance −3 dB Small Signal Bandwidth V = 0.1 V p-p 63 75 MHz O, dm AD8137W only: T -T 61 MHz MIN MAX −3 dB Large Signal Bandwidth V = 2 V p-p 76 107 MHz O, dm AD8137W only: T -T 76 MHz MIN MAX Slew Rate V = 2 V step 375 V/µs O, dm Settling Time to 0.02% V = 3.5 V step 110 ns O, dm Overdrive Recovery Time G = 2, V = 7 V p-p triangle wave 90 ns I, dm Noise/Harmonic Performance SFDR V = 2 V p-p, f = 500 kHz 89 dB O, dm C V = 2 V p-p, f = 2 MHz 73 dB O, dm C Input Voltage Noise f = 50 kHz to 1 MHz 8.25 nV/√Hz Input Current Noise f = 50 kHz to 1 MHz 1 pA/√Hz DC Performance Input Offset Voltage V = V = V = 0 V −2.7 ±0.7 +2.7 mV IP IN OCM AD8137W only: T -T −5.0 +5.0 mV MIN MAX Input Offset Voltage Drift T to T 3 µV/°C MIN MAX Input Bias Current T to T 0.5 0.9 µA MIN MAX Input Offset Current 0.1 0.45 µA AD8137W only: T -T 0.45 µA MIN MAX Open-Loop Gain 89 dB Input Characteristics Input Common-Mode Voltage Range 1 4 V AD8137W only: T -T 1 4 V MIN MAX Input Resistance Differential 800 kΩ Common-mode 400 kΩ Input Capacitance Common-mode 1.8 pF CMRR ΔV = ±1 V 64 90 dB ICM AD8137W only: T -T 64 dB MIN MAX Output Characteristics Output Voltage Swing Each single-ended output, R = 1 kΩ V + 0.45 V − 0.45 V L, dm S− S+ AD8137W only: T -T V + 0.45 V − 0.45 V MIN MAX S− S+ Output Current 20 mA Output Balance Error f = 1 MHz −64 dB V to V PERFORMANCE OCM O, cm V Dynamic Performance OCM −3 dB Bandwidth V = 0.1 V p-p 60 MHz O, cm Slew Rate V = 0.5 V p-p 61 V/µs O, cm Gain 0.980 1.000 1.020 V/V AD8137W only: T -T 0.975 1.020 V/V MIN MAX V Input Characteristics OCM Input Voltage Range 1 4 V AD8137W only: T -T 1 4 V MIN MAX Input Resistance 35 kΩ Input Offset Voltage −25 ±7.5 +25 mV AD8137W only: T -T −25 +25 mV MIN MAX Rev. E | Page 5 of 32

AD8137 Data Sheet Parameter Conditions Min Typ Max Unit Input Voltage Noise f = 100 kHz to 5 MHz 18 nV/√Hz Input Bias Current 0.25 0.9 µA AD8137W only: T -T 0.9 µA MIN MAX CMRR ΔV /ΔV , ΔV = ±0.5 V 62 75 dB O, dm OCM OCM AD8137W only: T -T 62 dB MIN MAX Power Supply Operating Range +2.7 ±6 V AD8137W only: T -T +2.7 ±6 V MIN MAX Quiescent Current 2.6 2.8 mA AD8137W only: T -T 2.8 mA MIN MAX Quiescent Current, Disabled Power-down = low 450 600 µA AD8137W only: T -T 600 µA MIN MAX PSRR ΔV = ±1 V 79 91 dB S AD8137W only: T -T 79 dB MIN MAX PD Pin Threshold Voltage V + 0.7 V + 1.5 V S− S− AD8137W only: T -T V + 0.7 V + 1.5 V MIN MAX S− S− Input Current Power-down = high/low 50/110 60/120 µA AD8137W only: T -T 60/125 µA MIN MAX OPERATING TEMPERATURE RANGE −40 +125 °C Rev. E | Page 6 of 32

Data Sheet AD8137 V = 3 V, V = 1.5 V (@ 25°C, differential gain = 1, R = R = R = 1 kΩ, unless otherwise noted, T to T = −40°C to +125°C). S OCM L, dm F G MIN MAX Table 3. Parameter Conditions Min Typ Max Unit DIFFERENTIAL INPUT PERFORMANCE Dynamic Performance −3 dB Small Signal Bandwidth V = 0.1 V p-p 61 73 MHz O, dm AD8137W only: T -T 58 MHz MIN MAX −3 dB Large Signal Bandwidth V = 2 V p-p 62 93 MHz O, dm AD8137W only: T -T 62 MHz MIN MAX Slew Rate V = 2 V step 340 V/µs O, dm Settling Time to 0.02% V = 3.5 V step 110 Ns O, dm Overdrive Recovery Time G = 2, V = 5 V p-p triangle wave 100 Ns I, dm Noise/Harmonic Performance SFDR V = 2 V p-p, f = 500 kHz 89 dB O, dm C V = 2 V p-p, f = 2 MHz 71 dB O, dm C Input Voltage Noise f = 50 kHz to 1 MHz 8.25 nV/√Hz Input Current Noise f = 50 kHz to 1 MHz 1 pA/√Hz DC Performance Input Offset Voltage V = V = V = 0 V −2.75 ±0.7 +2.75 mV IP IN OCM AD8137W only: T -T −5.25 +5.25 mV MIN MAX Input Offset Voltage Drift T to T 3 µV/°C MIN MAX Input Bias Current T to T 0.5 0.9 µA MIN MAX Input Offset Current 0.1 0.4 µA AD8137W only: T -T 0.4 µA MIN MAX Open-Loop Gain 87 dB Input Characteristics Input Common-Mode Voltage Range 1 2 V AD8137W only: T -T 1 2 V MIN MAX Input Resistance Differential 800 kΩ Common-mode 400 kΩ Input Capacitance Common-mode 1.8 pF CMRR ΔV = ±1 V 64 80 dB ICM AD8137W only: T -T 64 dB MIN MAX Output Characteristics Output Voltage Swing Each single-ended output, R = 1 kΩ V + 0.37 V − 0.37 V L, dm S− S+ AD8137W only: T -T V + 0.37 V − 0.37 V MIN MAX S− S+ Output Current 20 mA Output Balance Error f = 1 MHz −64 dB V to V PERFORMANCE OCM O, cm V Dynamic Performance OCM −3 dB Bandwidth V = 0.1 V p-p 61 MHz O, cm Slew Rate V = 0.5 V p-p 59 V/µs O, cm Gain 0.960 1.00 1.040 V/V AD8137W only: T -T 0.955 1.040 V/V MIN MAX V Input Characteristics OCM Input Voltage Range 1.0 2.0 V AD8137W only: T -T 1.0 2.0 V MIN MAX Input Resistance 35 kΩ Input Offset Voltage −25 ±5.5 +25 mV AD8137W only: T -T −25 +25 mV MIN MAX Input Voltage Noise f = 100 kHz to 5 MHz 18 nV/√Hz Input Bias Current 0.3 0.7 µA AD8137W only: T -T 0.7 µA MIN MAX Rev. E | Page 7 of 32

AD8137 Data Sheet Parameter Conditions Min Typ Max Unit CMRR ΔV /ΔV , ΔV = ±0.5 V 62 74 dB O, dm OCM OCM AD8137W only: T -T 62 dB MIN MAX Power Supply Operating Range +2.7 ±6 V AD8137W only: T -T +2.7 ±6 V MIN MAX Quiescent Current 2.3 2.5 mA AD8137W only: T -T 2.5 mA MIN MAX Quiescent Current, Disabled Power-down = low 345 460 µA AD8137W only: T -T 460 µA MIN MAX PSRR ΔV = ±1 V 78 90 dB S AD8137W only: T -T 78 dB MIN MAX PD Pin Threshold Voltage V + 0.7 V + 1.5 V S− S− AD8137W only: T -T V + 0.7 V + 1.5 V MIN MAX S− S− Input Current Power-down = high/low 8/65 10/70 µA AD8137W only: T -T 10/75 µA MIN MAX OPERATING TEMPERATURE RANGE −40 +125 °C Rev. E | Page 8 of 32

Data Sheet AD8137 ABSOLUTE MAXIMUM RATINGS The power dissipated in the package (P ) is the sum of the Table 4. D quiescent power dissipation and the power dissipated in the Parameter Rating package due to the load drive for all outputs. The quiescent Supply Voltage 12 V power is the voltage between the supply pins (V) times the V V to V S OCM S+ S− quiescent current (I). The load current consists of differential Power Dissipation See Figure 3 S and common-mode currents flowing to the load, as well as Input Common-Mode Voltage V to V S+ S− currents flowing through the external feedback networks and Storage Temperature Range −65°C to +125°C the internal common-mode feedback loop. The internal resistor Operating Temperature Range −40°C to +125°C tap used in the common-mode feedback loop places a 1 kΩ Lead Temperature (Soldering, 10 sec) 300°C differential load on the output. RMS output voltages should be Junction Temperature 150°C considered when dealing with ac signals. Stresses above those listed under Absolute Maximum Ratings Airflow reduces θ . In addition, more metal directly in contact JA may cause permanent damage to the device. This is a stress with the package leads from metal traces, through holes, ground, rating only; functional operation of the device at these or any and power planes reduces the θ . JA other conditions above those indicated in the operational Figure 3 shows the maximum safe power dissipation in the section of this specification is not implied. Exposure to absolute package vs. the ambient temperature for the 8-lead SOIC maximum rating conditions for extended periods may affect (125°C/W) and 8-lead LFCSP (θ = 70°C/W) on a JEDEC device reliability. JA standard 4-layer board. θ values are approximations. JA THERMAL RESISTANCE 3.0 θ is specified for the worst-case conditions, that is, θ is JA JA specified for the device soldered in a circuit board in still air. W)2.5 N ( O Table 5. Thermal Resistance TI LFCSP A2.0 Package Type θJA θJC Unit SIP S 8-Lead SOIC/2-Layer 157 56 °C/W DI R 1.5 8-Lead SOIC/4-Layer 125 56 °C/W WE O 8-Lead LFCSP/4-Layer 70 56 °C/W P M 1.0 MU SOIC-8 XI MThAe XmIaMxiUmMum P sOafeW pEoRw eDr dISisSsiIpPaAtioTnIO inN th e AD8137 package MA0.50 04771-0-022 is limited by the associated rise in junction temperature (T) on –40–30–20–10 0 10 20 30 40 50 60 70 80 90100110120 J the die. At approximately 150°C, which is the glass transition AMBIENT TEMPERATURE (°C) Figure 3. Maximum Power Dissipation vs. temperature, the plastic changes its properties. Even temporarily Ambient Temperature for a 4-Layer Board exceeding this temperature limit may change the stresses that the package exerts on the die, permanently shifting the parametric performance of the AD8137. Exceeding a junction temperature ESD CAUTION of 175°C for an extended period can result in changes in the silicon devices, potentially causing failure. Rev. E | Page 9 of 32

AD8137 Data Sheet PIN CONFIGURATION AND FUNCTION DESCRIPTIONS AD8137 –IN 1 8 +IN VOCM 2 7 PD +OVUST+ 34 65 V–OS–UT 04771-0-001 Figure 4. Pin Configuration Table 6. Pin Function Descriptions Pin No. Mnemonic Description 1 −IN Inverting Input. 2 V An internal feedback loop drives the output common-mode voltage to be equal to the voltage applied to OCM the V pin, provided the operation of the amplifier remains linear. OCM 3 V Positive Power Supply Voltage. S+ 4 +OUT Positive Side of the Differential Output. 5 −OUT Negative Side of the Differential Output. 6 V Negative Power Supply Voltage. S− 7 PD Power Down. 8 +IN Noninverting Input. EPAD Exposed paddle may be connected to either ground plane or power plane. Rev. E | Page 10 of 32

Data Sheet AD8137 TYPICAL PERFORMANCE CHARACTERISTICS Unless otherwise noted, differential gain = 1, R = R = R = 1 kΩ, V = 5 V, T = 25°C, V = 2.5V. Refer to the basic test circuit in G F L, dm S A OCM Figure 60 for the definition of terms. 3 3 2 G = 1 2 dB) 1 dB) 1 G = 1 N ( 0 N ( 0 GAI –1 G = 2 GAI –1 OP –2 G = 5 OP –2 G = 5 G = 2 LO –3 LO –3 ED- –4 ED- –4 OS –5 OS –5 CL –6 G = 10 CL –6 G = 10 D D E –7 E –7 Z Z ALI –8 ALI –8 RM –9 RM –9 NO –––111102 VROG, =d m1k =Ω 0.1V p-p 04771-0-002 NO –––111210 RVOG, =d m1k =Ω 2.0V p-p 04771-0-004 0.1 1 10 100 1000 0.1 1 10 100 1000 FREQUENCY (MHz) FREQUENCY (MHz) Figure 5. Small Signal Frequency Response for Various Gains Figure 8. Large Signal Frequency Response for Various Gains 3 4 2 VS = +5 VS = +3 3 VS = +5 VS = +3 1 2 0 1 B) –1 VS =±5 B) 0 d d N ( –2 N ( –1 VS =±5 GAI –3 GAI –2 OP –4 OP –3 LO –5 LO –4 ED- –6 ED- –5 OS –7 OS –6 CL –8 CL –7 –9 –8 –––111210 VO, dm = 0.1V p-p 04771-0-003 ––1–1091 VO, dm = 2.0V p-p 04771-0-005 1 10 100 1000 1 10 100 1000 FREQUENCY (MHz) FREQUENCY (MHz) Figure 6. Small Signal Frequency Response for Various Power Supplies Figure 9. Large Signal Frequency Response for Various Power Supplies 3 4 2 3 T = +25°C 1 2 0 1 B) –1 B) 0 d T = +85°C d N ( –2 N ( –1 P GAI ––34 T = +25°C P GAI ––32 T = +85°C ED-LOO ––65 T = +125°C T =–40°C ED-LOO ––54 T = +125°C OS –7 OS –6 CL –8 CL –7 –9 –8 T =–40°C –––111210 VO, dm = 0.1V p-p 04771-0-006 ––11–109 VO, dm = 2.0V p-p 04771-0-007 1 10 100 1000 1 10 100 1000 FREQUENCY (MHz) FREQUENCY (MHz) Figure 7. Small Signal Frequency Response at Various Temperatures Figure 10. Large Signal Frequency Response at Various Temperatures Rev. E | Page 11 of 32

AD8137 Data Sheet 3 3 2 RL, dm= 1kΩ RL, dm = 500Ω 2 1 1 0 0 B) –1 RL, dm = 2kΩ B) –1 d d N ( –2 N ( –2 AI –3 AI –3 G G P –4 P –4 O O LO –5 LO –5 D- –6 D- –6 E E LOS –7 LOS –7 RL, dm = 2kΩ C –8 C –8 –9 –9 RL, dm = 500Ω –––111201 VO, dm = 0.1V p-p 04771-0-041 –––111012 VO, dm = 2V p-p RL, dm= 1kΩ 04771-0-043 1 10 100 1000 1 10 100 1000 FREQUENCY (MHz) FREQUENCY (MHz) Figure 11. Small Signal Frequency Response for Various Loads Figure 14. Large Signal Frequency Response for Various Loads 3 3 2 CF= 0pF 2 CF= 0pF 1 1 0 0 CF= 1pF B) –1 CF= 1pF B) –1 d d N ( –2 N ( –2 GAI –3 CF= 2pF GAI –3 CF= 2pF P –4 P –4 O O O –5 O –5 L L D- –6 D- –6 E E OS –7 OS –7 L L C –8 C –8 –9 –9 –––111210 VO, dm = 0.1V p-p 04771-0-008 –––111210 VO, dm = 2.0V p-p 04771-0-009 1 10 100 1000 1 10 100 1000 FREQUENCY (MHz) FREQUENCY (MHz) Figure 12. Small Signal Frequency Response for Various CF Figure 15. Large Signal Frequency Response for Various CF 2 3 1 VOCM = 4V VOCM = 2.5V 2 0 1 B) ––12 VOCM = 1V B) –01 N (d –3 N (d –2 0.5V p-p AI –4 AI –3 G G P –5 P –4 O O LO –6 LO –5 D- –7 D- –6 E E LOS –8 LOS –7 2V p-p C –9 C –8 –10 –9 1V p-p –––111312 VO, dm = 0.1V p-p 04771-0-042 –––111012 0.1V p-p 04771-0-044 1 10 100 1000 1 10 100 1000 FREQUENCY (MHz) FREQUENCY (MHz) Figure 13. Small Signal Frequency Response at Various VOCM Figure 16. Frequency Response for Various Output Amplitudes Rev. E | Page 12 of 32

Data Sheet AD8137 4 4 3 3 2 2 1 1 B) 0 B) 0 N (d –1 RF = 500Ω N (d –1 GAI –2 RF = 2kΩ GAI –2 OP –3 OP –3 RF = 2kΩ RF = 500Ω LO –4 RF = 1kΩ LO –4 ED- –5 ED- –5 RF = 1kΩ OS –6 OS –6 L L C –7 C –7 –8 –8 ––11–109 GVVSO=,= d1m±5 =V 0.1V p-p 04771-0-037 ––11–109 GVO =, d1m = 2V p-p 04771-0-036 1 10 100 1000 1 10 100 1000 FREQUENCY (MHz) FREQUENCY (MHz) Figure 17. Small Signal Frequency Response for Various RF Figure 20. Large Signal Frequency Response for Various RF –65 –40 G = 1 G = 1 –70 VO, dm = 2V p-p –50 VO, dm = 2V p-p –75 VS = +3V –60 c) c) dB –80 dB ON ( VS = +5V ON ( –70 VS = +3V TI –85 TI TOR VS =±5V TOR –80 VS = +5V S –90 S DI DI –95 –90 VS =±5V ––110005 04771-0-045 ––110100 04771-0-063 0.1 1 10 0.1 1 10 FREQUENCY (MHz) FREQUENCY (MHz) Figure 18. Second Harmonic Distortion vs. Frequency and Supply Voltage Figure 21. Third Harmonic Distortion vs. Frequency and Supply Voltage –50 –50 –55 SFCE C=O 5N00Dk HHAzRMONIC SOLID LINE –55 VS = +3V THIRD HARMONIC DASHED LINE –60 –60 VS = +5V Bc) –65 VS = +5V Bc) –65 N (d –70 N (d –70 RTIO –75 VS = +3V RTIO –75 O O DIST –80 VS = +3V DIST –80 VS = +5V –85 –85 –90 VS = +5V –90 VS = +3V ––19050 04771-0-027 ––19050 SFTHCE CI=RO D2NMHDHAHzRAMROMNOICNIDCASSOHLEIDDLLIINNEE 04771-0-026 0.25 1.25 2.25 3.25 4.25 5.25 6.25 7.25 8.25 9.25 0.25 1.25 2.25 3.25 4.25 5.25 6.25 7.25 8.25 9.25 VO, dm (V p-p) VO, dm (V p-p) Figure 19. Harmonic Distortion vs. Output Amplitude and Supply, Figure 22. Harmonic Distortion vs. Output Amplitude and Supply, FC = 2 MHz FC = 500 kHz Rev. E | Page 13 of 32

AD8137 Data Sheet –40 –40 VO, dm = 2V p-p VO, dm = 2V p-p –50 –50 –60 –60 c) c) N (dB –70 RL, dm = 200Ω N (dB –70 RL, dm = 200Ω O O TI TI R R DISTO –80 RL, dm= 1kΩ DISTO –80 RL, dm= 1kΩ –90 RL, dm = 500Ω –90 ––110100 04771-0-032 ––110100 RL, dm = 500Ω 04771-0-033 0.1 1 10 0.1 1 10 FREQUENCY (MHz) FREQUENCY (MHz) Figure 23. Second Harmonic Distortion at Various Loads Figure 26. Third Harmonic Distortion at Various Loads –40 –40 VO, dm = 2V p-p VO, dm = 2V p-p RG = 1kΩ RG = 1kΩ –50 –50 G = 2 –60 –60 G = 5 c) c) B G = 5 B d d N ( –70 N ( –70 O O RTI G = 1 RTI G = 2 O –80 O –80 T T S S DI DI G = 1 –90 –90 ––110100 04771-0-034 ––110100 04771-0-035 0.1 1 10 0.1 1 10 FREQUENCY (MHz) FREQUENCY (MHz) Figure 24. Second Harmonic Distortion at Various Gains Figure 27. Third Harmonic Distortion at Various Gains –40 –40 VO, dm = 2V p-p VO, dm = 2V p-p G = 1 G = 1 –50 –50 –60 –60 c) c) B B d d N ( –70 RF = 500Ω N ( –70 O O TI TI R R O –80 O –80 ST RF = 2kΩ ST DI DI –90 RF = 1kΩ –90 RF = 500Ω ––110100 04771-0-030 ––110100 RF = 1kΩ RF = 2kΩ 04771-0-031 0.1 1 10 0.1 1 10 FREQUENCY (MHz) FREQUENCY (MHz) Figure 25. Second Harmonic Distortion at Various RF Figure 28. Third Harmonic Distortion at Various RF Rev. E | Page 14 of 32

Data Sheet AD8137 –50 –50 FC = 500kHz FC = 500kHz VO, dm = 2V p-p VO, dm = 2V p-p –60 SECOND HARMONIC SOLID LINE –60 SECOND HARMONIC SOLID LINE THIRD HARMONIC DASHED LINE THIRD HARMONIC DASHED LINE c) –70 c) –70 B B d d N ( N ( O O TI –80 TI –80 R R O O T T S S DI –90 DI –90 ––110100 04771-0-028 ––110100 04771-0-029 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 0.5 0.7 0.9 1.1 1.3 1.5 1.7 1.9 2.1 2.3 2.5 VOCM (V) VOCM (V) Figure 29. Harmonic Distortion vs. VOCM, VS = 5 V Figure 32. Harmonic Distortion vs. VOCM, VS = 3 V 100 1000 Hz) √ E (nV/ √Hz) 100 OIS nV/ E N 10 SE ( LTAG NOIM O C V O 10 T V U P N I 1 04771-0-046 1 04771-0-047 10 100 1k 10k 100k 1M 10M 100M 10 100 1k 10k 100k 1M 10M 100M FREQUENCY (Hz) FREQUENCY (Hz) Figure 30. Input Voltage Noise vs. Frequency Figure 33. VOCM Voltage Noise vs. Frequency 20 –10 10 VININP,U cTm C= M0.R2RV =p-∆pVO, cm/∆VIN, cm –20 VVOO,C cMm C=M 0R.2RV =p-∆pVO, dm/∆VOCM 0 –10 –30 B) R (dB) ––2300 MRR (d –40 R C M M –50 C –40 OC V –50 –60 –60 ––7800 04771-0-013 ––7800 04771-0-012 1 10 100 1 10 100 FREQUENCY (MHz) FREQUENCY (MHz) Figure 31. CMRR vs. Frequency Figure 34. VOCM CMRR vs. Frequency Rev. E | Page 15 of 32

AD8137 Data Sheet 8 2.0 G = 2 INPUT× 2 6 1.5 VO, dm CF = 0pF OUTPUT INPUT VO, dm = 3.5V p-p 4 1.0 % 2 0 VOLTAGE (V) –202 AMPLITUDE (V)–00..505 ERROR =VO, dm - INPUT OR (V) 1DIV = 0. TSETTLE = 110ns RR –4 –1.0 E ––86 250ns/DIV 04771-0-016 ––21..05 50ns/DIV 04771-0-040 TIME (ns) TIME (ns) Figure 35. Overdrive Recovery Figure 38. Settling Time (0.02%) 1.5 100 CF = 0pF 2V p-p 75 1.0 CF = 1pF 50 CF = 0pF 1V p-p mV) 25 CF = 0pF CF = 1pF (V)m 0.5 CF = 1pF (O, dm 0 VO, d 0 V –25 –0.5 –50 ––17050 VO, dm = 100mV p-p 10ns/DIV 04771-0-015 ––11..05 20ns/DIV 04771-0-014 TIME (ns) TIME (ns) Figure 36. Small Signal Transient Response for Various Feedback Capacitances Figure 39. Large Signal Transient Response for Various Feedback Capacitances 100 1.5 75 RS = 111, CL= 5pF 1.0 50 RS = 111, CL= 5pF 25 0.5 V) (O, dm 0 (V)dm 0 RS = 60.4, CL= 15pF V RS = 60.4, CL= 15pF O, –25 V –0.5 –50 ––17050 20ns/DIV 04771-0-039 ––11..05 20ns/DIV 04771-0-038 TIME (ns) TIME (ns) Figure 37. Small Signal Transient Response for Various Capacitive Loads Figure 40. Large Signal Transient Response for Various Capacitive Loads Rev. E | Page 16 of 32

Data Sheet AD8137 –5 1000 PSRR =∆VO, dm/∆VS –15 100 –25 Ω) E ( C B) –35 AN 10 d D R ( –45 –PSRR PE R M PS –55 +PSRR UT I 1 P T U O –65 0.1 ––8755 04771-0-011 0.01 04771-0-061 0.1 1 10 100 0.01 0.1 1 10 100 FREQUENCY (MHz) FREQUENCY (MHz) Figure 41. PSRR vs. Frequency Figure 44. Single-Ended Output Impedance vs. Frequency 1 4.0 0 –1 3.5 –2 2V p-p B) –3 d N ( –4 3.0 GAI –5 V) 1V p-p D-LOOP –––876 VS = +5 VS =±5 V (O, cm 2.5 E OS –9 2.0 L C –10 –11 VS = +3 –––111432 VO, dm = 0.1V p-p 04771-0-010 11..50 20ns/DIV 04771-0-050 1 10 100 1000 FREQUENCY (MHz) TIME (ns) Figure 42. VOCM Small Signal Frequency Response for Various Supply Voltages Figure 45. VOCM Large Signal Transient Response 700 350 –300 V) m 600 AIL ( 500 345 –305 M R 400 VS+– VOP V) V) G FRO 230000 AIL (m 340 VON– VS– –310 AIL (m N R R WI 100 M M PUT S–1000 VS = +5V VS = +3V G FRO 335 –315 G FRO OUT–200 WIN 330 VS+– VOP –320 WIN NDED ––430000 VON– VS– VSOP SVON SINGLE-E–––765000000 04771-0-049 332205 ––333205 04771-0-065 200 1k 10k –40 –20 0 20 40 60 80 100 120 RESISTIVE LOAD (Ω) TEMPERATURE (°C) Figure 43. Output Saturation Voltage vs. Output Load Figure 46. Output Saturation Voltage vs. Temperature Rev. E | Page 17 of 32

AD8137 Data Sheet 0.3 15 2.60 0.2 10 2.55 VOS, cm VOS, dm A) V) 0.1 5 V) NT (m 2.50 m m E (OS, dm 0 0 (OS, cm Y CURR 2.45 V V L –0.1 5 PP 2.40 U S ––00..32 –1105 04771-0-052 22..3350 04771-0-051 –40 –20 0 20 40 60 80 100 120 –40 –20 0 20 40 60 80 100 120 TEMPERATURE (°C) TEMPERATURE (°C) Figure 47. Offset Voltage vs. Temperature Figure 50. Supply Current vs. Temperature 1.2 70� 1.0 50 A) 0.8 µT ( 30 N RRE 0.6 µA) 10 CU 0.4 (M AS VOC –10 T BI 0.2 I U P –30 IN 0 ––00..24 04771-0-059 ––5700 04771-0-056 0.50 1.50 2.50 3.50 4.50 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 VACM (V) VOCM (V) Figure 48. Input Bias Current vs. Input Common-Mode Voltage, VACM Figure 51. VOCM Bias Current vs. VOCM Input Voltage 0.40 3 –0.1 0.35 2 IBIAS –0.2 0.30 1 A) µ µI (A)BIAS0.25 IOS 0 (nA)IOS CURRENT (–0.3 M 0.20 –1 OC V –0.4 00..1150 ––32 04771-0-053 –0.5 04771-0-054 –40 –20 0 20 40 60 80 100 120 –40 –20 0 20 40 60 80 100 120 TEMPERATURE (°C) TEMPERATURE (°C) Figure 49. Input Bias and Offset Current vs. Temperature Figure 52. VOCM Bias Current vs. Temperature Rev. E | Page 18 of 32

Data Sheet AD8137 5 1.5 4 VS = +5V VS =±2.5V 3 1.0 RGL =, d1m ( R= F1 =k ΩRG = 1kΩ) INPUT = 1Vp-p @ 1MHz 2 mA) VO, dm 1 VS = +3V NT ( 0.5 m RE O, c 0 UR 0 V C –1 LY P –2 VS =±5V UP –0.5 S –3 ––45 04771-0-060 ––11..05 –0.5VPD –2.0V 2µs/DIV 04771-0-066 –5 –4 –3 –2 –1 0 1 2 3 4 5 VOCM TIME (µs) Figure 53. VO, cm vs. VOCM Input Voltage Figure 56. Power-Down Transient Response 40� 3.6 20 3.2 PD (0.8V TO 1.5V) 2.8 0 A) µCURRENT (A) ––2400 Y CURRENT (m 221...046 D –60 PL P P 1.2 U –80 S 0.8 ––110200 04771-0-057 0.40 100ns/DIV 04771-0-024 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 PD VOLTAGE (V) TIME (ns) Figure 54. PD Current vs. PD Voltage Figure 57. Power-Down Turn-On Time 3 3.4 PD (1.5V TO 0.8V) IS+ 3.0 2 A) A) 2.6 m m NT ( 1 NT ( 2.2 E E R R UR 0 UR 1.8 C C Y Y PL PL 1.4 P –1 P U U S S 1.0 ––23 IS– 04771-0-058 00..62 40ns/DIV 04771-0-025 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 PD VOLTAGE (V) TIME (ns) Figure 55. Supply Current vs. PD Voltage Figure 58. Power-Down Turn-Off Time Rev. E | Page 19 of 32

AD8137 Data Sheet 25 VS = ±5V VOCM = 0V G = +1 20 A) m NT ( 15 E R R U C LY 10 P P U S 5 0–5 –4 –3 P–O2WER–-1DOWN0 VOLT1AGE (2V) 3 4 5 04771-071 Figure 59. Supply Current vs. Power-Down Voltage Rev. E | Page 20 of 32

Data Sheet AD8137 TEST CIRCUITS RF 50Ω 52.3Ω RG= 1kΩ + CF – VTEST MIDSUPPLY VOCM AD8137 RL, dm1kΩ VO, dm 52.3Ω – + TSSEIOGSUNTRACLE 50Ω RG= 1kΩ CRFF 04771-0-023 Figure 60. Basic Test Circuit 50Ω RF= 1kΩ 52.3Ω RG= 1kΩ + RS – VTEST MIDSUPPLY VOCM AD8137 CL, dm RL, dm VO, dm 52.3Ω – + TSSEIOGSUNTRACLE 50Ω RG= 1kΩ RF= 1kΩ RS 04771-0-062 Figure 61. Capacitive Load Test Circuit, G = 1 Rev. E | Page 21 of 32

AD8137 Data Sheet THEORY OF OPERATION The AD8137 is a low power, low cost, fully differential voltage 100 feedback amplifier that features a rail-to-rail output stage, 80 60 common-mode circuitry with an internally derived common- 40 mode reference voltage, and bias shutdown circuitry. The amplifier 20 OPEN-LOOP GAIN (dB) uses two feedback loops to separately control differential and 0 –20 common-mode feedback. The differential gain is set with external –40 resistors as in a traditional amplifier, and the output common- –60 mode voltage is set by an internal feedback loop, controlled by –80 an external VOCM input. This architecture makes it easy to set –100 PHASE (DEGREES) –120 arbitrarily the output common-mode voltage level without –140 affecting the differential gain of the amplifier. –––211086000 04771-0-021 0.0001 0.001 0.01 0.1 1 10 100 VOCM FREQUENCY (MHz) Figure 63. Open-Loop Gain and Phase ACM In Figure 62, the common-mode feedback amplifier A CM –OUT CP +IN –INCN +OUT samples the output common-mode voltage, and by negative CC CC feedback forces the output common-mode voltage to be equal to the voltage applied to the V input. In other words, the OCM feedback loop servos the output common-mode voltage to the 04771-0-017 vseotlst atghee aVpOpClMie dle vtoe lt thoe aVpOpCrMo xinimpuatte. lAy nm iindtseurpnpall yb;i tahs egreenfoerrea,t othr e Figure 62. Block Diagram output common-mode voltage is set to approximately midsupply From Figure 62, the input transconductance stage is an H-bridge when the VOCM input is left floating. The source resistance of the whose output current is mirrored to high impedance nodes CP internal bias generator is large and can be overridden easily by an and CN. The output section is traditional H-bridge driven circuitry external voltage supplied by a source with a relatively small output with common emitter devices driving nodes +OUT and −OUT. resistance. The VOCM input can be driven to within approximately The 3 dB point of the amplifier is defined as 1 V of the supply rails while maintaining linear operation in the common-mode feedback loop. g BW = m 2π×C The common-mode feedback loop inside the AD8137 produces C outputs that are highly balanced over a wide frequency range where: without the requirement of tightly matched external components, g is the transconductance of the input stage. m because it forces the signal component of the output common- C is the total capacitance on node CP/CN (capacitances CP C mode voltage to be zeroed. The result is nearly perfectly balanced and CN are well matched). differential outputs of identical amplitude and exactly 180° For the AD8137, the input stage g is ~1 mA/V and the apart in phase. m capacitance C is 3.5 pF, setting the crossover frequency of the C amplifier at 41 MHz. This frequency generally establishes an amplifier’s unity gain bandwidth, but with the AD8137, the closed-loop bandwidth depends upon the feedback resistor value as well (see Figure 17). The open-loop gain and phase simulations are shown in Figure 63. Rev. E | Page 22 of 32

Data Sheet AD8137 APPLICATIONS INFORMATION ANALYZING A TYPICAL APPLICATION WITH Output balance is measured by placing a well-matched resistor MATCHED R AND R NETWORKS divider across the differential voltage outputs and comparing F G the signal at the divider’s midpoint with the magnitude of the Typical Connection and Definition of Terms differential output. By this definition, output balance is equal to Figure 64 shows a typical connection for the AD8137, using the magnitude of the change in output common-mode voltage matched external RF/RG networks. The differential input divided by the magnitude of the change in output differential terminals of the AD8137, VAP and VAN, are used as summing mode voltage: junctions. An external reference voltage applied to the V OCM ∆V terminal sets the output common-mode voltage. The two OutputBalance = O,cm (3) output terminals, VOP and VON, move in opposite directions ∆VO,dm in a balanced fashion in response to an input signal. The differential negative feedback drives the voltages at the summing CF junctions V and V to be essentially equal to each other. AN AP V = V (4) AN AP RF VIP RG VAP + VON – The common-mode feedback loop drives the output common- mode voltage, sampled at the midpoint of the two internal VOCM AD8137 RL, dm VO, dm VIN RG VAN – VOP + cseotm amt tohne -Vmode t etramp rinesails. tTorhsi si ne nFsiugurerse t6h2a,t t o equal the voltage OCM RF V CF 04771-0-055 VOP =VOCM + O2,dm (5) and Figure 64. Typical Connection V The differential output voltage is defined as V =V − O,dm (6) ON OCM 2 V = V − V (1) O, dm OP ON ESTIMATING NOISE, GAIN, AND BANDWITH WITH Common-mode voltage is the average of two voltages. The MATCHED FEEDBACK NETWORKS output common-mode voltage is defined as Estimating Output Noise Voltage and Bandwidth V +V V = OP ON (2) The total output noise is the root-sum-squared total of several O,cm 2 statistically independent sources. Because the sources are Output Balance statistically independent, the contributions of each must be Output balance is a measure of how well V and V are individually included in the root-sum-square calculation. Table 7 OP ON matched in amplitude and how precisely they are 180° out of lists recommended resistor values and estimates of bandwidth phase with each other. It is the internal common-mode feedback and output differential voltage noise for various closed-loop loop that forces the signal component of the output common- gains. For most applications, 1% resistors are sufficient. mode toward zero, resulting in the near perfectly balanced Table 7. Recommended Values of Gain-Setting Resistors and differential outputs of identical amplitude and are exactly 180° Voltage Gain for Various Closed-Loop Gains out of phase. The output balance performance does not require 3 dB Bandwidth Total Output tightly matched external components, nor does it require that Gain R (Ω) R (Ω) (MHz) Noise (nV/√Hz) G F the feedback factors of each loop be equal to each other. Low 1 1 k 1 k 72 18.6 frequency output balance is ultimately limited by the mismatch 2 1 k 2 k 40 28.9 of an on-chip voltage divider. 5 1 k 5 k 12 60.1 10 1 k 10 k 6 112.0 Rev. E | Page 23 of 32

AD8137 Data Sheet Feedback Factor Notation The differential output voltage noise contains contributions from the AD8137’s input voltage noise and input current noise When working with differential drivers, it is convenient to as well as those from the external feedback networks. introduce the feedback factor β, which is defined as The contribution from the input voltage noise spectral density R β≡ G (14) is computed as R +R F G  R  This notation is consistent with conventional feedback analysis Vo_n1=vn1+RF , or equivalently, vn/β (7) and is very useful, particularly when the two feedback loops are G not matched. where v is defined as the input-referred differential voltage n Input Common-Mode Voltage noise. This equation is the same as that of traditional op amps. The linear range of the V and V terminals extends to within The contribution from the input current noise of each input is AN AP approximately 1 V of either supply rail. Because V and V are computed as AN AP essentially equal to each other, they are both equal to the amplifier’s Vo_n2=i (R ) (8) n F input common-mode voltage. Their range is indicated in the where i is defined as the input noise current of one input. Each specifications tables as input common-mode range. The voltage n input needs to be treated separately because the two input currents at VAN and VAP for the connection diagram in Figure 64 can be are statistically independent processes. expressed as The contribution from each RG is computed as VAN = VAP = VACM =  R (V +V )  R  Vo_n3= 4kTRGRRF  (9) RF +FRG × IP 2 IN +RF +GRG ×VOCM (15) G where V is the common-mode voltage present at the amplifier This result can be intuitively viewed as the thermal noise of ACM input terminals. each R multiplied by the magnitude of the differential gain. G Using the β notation, Equation (15) can be written as The contribution from each R is computed as F V = βV + (1 − β)V (16) Vo_n4= 4kTR (10) ACM OCM ICM F or equivalently, Voltage Gain V = V + β(V − V ) (17) ACM ICM OCM ICM The behavior of the node voltages of the single-ended-to- where V is the common-mode voltage of the input signal, differential output topology can be deduced from the signal ICM that is definitions and Figure 64. Referring to Figure 64, C = 0 and F setting V = 0, one can write: V +V IN V ≡ IP IN V −V V −V ICM 2 IP AP = AP ON (11) RG RF For proper operation, the voltages at VAN and VAP must stay within their respective linear ranges.  R  V =V =V  G  (12) Calculating Input Impedance AN AP OPR +R  F G The input impedance of the circuit in Figure 64 depends on Solving the previous two equations and setting VIP to Vi gives whether the amplifier is being driven by a single-ended or a the gain relationship for VO, dm/Vi. differential signal source. For balanced differential input VOP−VON =VO,dm = RRGF Vi (13) signaRls, the = d i2fRfer ential input impedance (RIN, dm) is simply (18) IN, dm G An inverting configuration with the same gain magnitude can For a single-ended signal (for example, when V is grounded IN be implemented by simply applying the input signal to V and IN and the input signal drives V ), the input impedance becomes IP setting V = 0. For a balanced differential input, the gain from VIN, dm to IVPO, dm is also equal to RF/RG, where VIN, dm = VIP − VIN. RIN =1− RGRF (19) 2(RG+RF) Rev. E | Page 24 of 32

Data Sheet AD8137 5V 0.1µF 0.1µF 1kΩ 50Ω 1kΩ 8 3 5 1.0nF + VDD VOCM 2 AD8137 VIN– +2.5V 1 GND VIN – 4 AD7450A –2.5V 6 VREFB VIN+ 1kΩ 1kΩ 50Ω 1.0nF GND VREF +1.88V 2.5kΩ VACM WITH +1.25V 2.5V VREFB= 0 +0.63V ADR525A 2.5V SHUNT VREFA REFERENCE 04771-0-018 Figure 65. AD8137 Driving AD7450A, 12-Bit ADC The input impedance of a conventional inverting op amp 5V configuration is simply R ; however, it is higher in Equation 19 G because a fraction of the differential output voltage appears at 0.1µF 1kΩ the summing junctions, V and V . This voltage partially 3 AN AP 1kΩ 8 5 bootstraps the voltage across the input resistor R , leading to + the increased input resistance. G VIN VOCM 2 AD8137 0V TO 5V 1 – Input Common-Mode Swing Considerations 4 6 In some single-ended-to-differential applications, when using a 1kΩ 1kΩ single-supply voltage, attention must be paid to the swing of the 5V TO 0.1µF AD7450A 10kΩ input common-mode voltage, VACM. VREF 0.1µF ADR525A Consider the case in Figure 65, where VIN is 5 V p-p swinging 10µF + + 0.1µF R2E.5FVE SRHEUNNCTE about a baseline at ground and VREFB is connected to ground. AD8031 wThiteh ian pvuert ys ilgonwa lo tuot pthuet rAeDsis8t1a3n7c ei.s originating from a source – 04771-0-019 The circuit has a differential gain of 1.0 and β = 0.5. V has an ICM Figure 66. Low-Z Bias Source amplitude of 2.5 V p-p and is swinging about ground. Using the Another way to avoid the input common-mode swing limitation results in Equation 16, the common-mode voltage at the inputs of is to use dual power supplies on the AD8137. In this case, the the AD8137, V , is a 1.25 V p-p signal swinging about a baseline ACM biasing circuitry is not required. of 1.25 V. The maximum negative excursion of V in this case is ACM 0.63 V, which exceeds the lower input common-mode voltage limit. Bandwidth vs. Closed-Loop Gain One way to avoid the input common-mode swing limitation is The 3 dB bandwidth of the AD8137 decreases proportionally to bias VIN and VREF at midsupply. In this case, VIN is 5 V p-p to increasing closed-loop gain in the same way as a traditional swinging about a baseline at 2.5 V, and VREF is connected to a voltage feedback operational amplifier. For closed-loop gains low-Z 2.5 V source. VICM now has an amplitude of 2.5 V p-p and greater than 4, the bandwidth obtained for a specific gain can is swinging about 2.5 V. Using the results in Equation 17, VACM be estimated as is calculated to be equal to V because V = V . Therefore, ICM OCM ICM R VICM swings from 1.25 V to 3.75 V, which is well within the input f−3dB,VO,dm = R +GR ×(72MHz) (20) common-mode voltage limits of the AD8137. Another benefit G F seen by this example is that because V = V = V , no or equivalently, β(72 MHz). OCM ACM ICM wasted common-mode current flows. Figure 66 illustrates a way This estimate assumes a minimum 90° phase margin for the to provide the low-Z bias voltage. For situations that do not amplifier loop, a condition approached for gains greater than 4. require a precise reference, a simple voltage divider suffices to Lower gains show more bandwidth than predicted by the equation develop the input voltage to the buffer. due to the peaking produced by the lower phase margin. Rev. E | Page 25 of 32

AD8137 Data Sheet Estimating DC Errors Driving a Capacitive Load Primary differential output offset errors in the AD8137 are due A purely capacitive load reacts with the bondwire and pin to three major components: the input offset voltage, the offset inductance of the AD8137, resulting in high frequency ringing between the V and V input currents interacting with the in the transient response and loss of phase margin. One way to AN AP feedback network resistances, and the offset produced by the minimize this effect is to place a small resistor in series with dc voltage difference between the input and output common- each output to buffer the load capacitance. The resistor and load mode voltages in conjunction with matching errors in the capacitance forms a first-order, low-pass filter; therefore, the feedback network. resistor value should be as small as possible. In some cases, the ADCs require small series resistors to be added on their inputs. The first output error component is calculated as Figure 37 and Figure 40 illustrate transient response vs. capacitive R +R  Vo_e1=VIO FR G, or equivalently as VIO/β (21) load and were generated using series resistors in each output G and a differential capacitive load. where VIO is the input offset voltage. Layout Considerations The second error is calculated as Standard high speed PCB layout practices should be adhered R +R  R R  to when designing with the AD8137. A solid ground plane is Vo_e2=IIO FR GR G+RF =IIO(RF) (22) recommended and good wideband power supply decoupling G F G networks should be placed as close as possible to the supply pins. where I is defined as the offset between the two input bias IO To minimize stray capacitance at the summing nodes, the currents. copper in all layers under all traces and pads that connect to The third error voltage is calculated as the summing nodes should be removed. Small amounts of stray Vo_e3 = Δenr × (V − V ) (23) summing-node capacitance cause peaking in the frequency ICM OCM response, and large amounts can cause instability. If some stray where Δenr is the fractional mismatch between the two feedback summing-node capacitance is unavoidable, its effects can be resistors. compensated for by placing small capacitors across the feedback The total differential offset error is the sum of these three error resistors. sources. Terminating a Single-Ended Input Additional Impact of Mismatches in the Feedback Networks Controlled impedance interconnections are used in most high The internal common-mode feedback network still forces the speed signal applications, and they require at least one line output voltages to remain balanced, even when the RF/RG feed- termination. In analog applications, a matched resistive termination back networks are mismatched. The mismatch, however, causes is generally placed at the load end of the line. This section deals a gain error proportional to the feedback network mismatch. with how to properly terminate a single-ended input to the AD8137. Ratio-matching errors in the external resistors degrade the The input resistance presented by the AD8137 input circuitry ability to reject common-mode signals at the VAN and VIN input is seen in parallel with the termination resistor, and its loading terminals, similar to a four resistor, difference amplifier made effect must be taken into account. The Thevenin equivalent from a conventional op amp. Ratio-matching errors also produce a circuit of the driver, its source resistance, and the termination differential output component that is equal to the VOCM input resistance must all be included in the calculation as well. An voltage times the difference between the feedback factors (βs). exact solution to the problem requires solution of several In most applications using 1% resistors, this component amounts simultaneous algebraic equations and is beyond the scope of to a differential dc offset at the output that is small enough to this data sheet. An iterative solution is also possible and is easier, be ignored. especially considering the fact that standard resistor values are generally used. Rev. E | Page 26 of 32

Data Sheet AD8137 Figure 67 shows the AD8137 in a unity-gain configuration, and Power-Down with the following discussion, provides a good example of how The AD8137 features a PD pin that can be used to minimize the to provide a proper termination in a 50 Ω environment. quiescent current consumed when the device is not being used. +5V PD is asserted by applying a low logic level to Pin 7. The threshold between high and low logic levels is nominally 1.1 V above the negative supply rail. See Table 1 to Table 3 for the threshold limits. 0.1µF The AD8137 PD pin features an internal pull-up network that 1kΩ – enables the amplifier for normal operation. The AD8137 PD 50Ω 2V p-p 1kΩ 8 3 5 pin can be left floating (that is, no external connection is + VIN SIGNAL R52T.3Ω 0VVOCM 2 AD8137 required) and does not require an external pull-up resistor to SOURCE 1 ensure normal on operation (see Figure 68). – 4 1.02kΩ 6 Do not connect the PD pin directly to V in ±5 V applications. + S+ 0.1µF –5V1kΩ 04771-0-020 T(sheies Fciagnu rcea u5s9e) tahned a mmapyli ifniedru tcoe d orsacwil leaxticoensssi vaen dsu/oprp slyta cbuilrirteyn t issues. Figure 67. AD8137 with Terminated Input +VS The 52.3 Ω termination resistor, R , in parallel with the 1 kΩ T +VS input resistance of the AD8137 circuit, yields an overall input resistance of 50 Ω that is seen by the signal source. To have 50kΩ Q1 Q2 matched feedback loops, each loop must have the same R if it 5kΩ G PD REF A has the same R. In the input (upper) loop, R is equal to the 1 kΩ F G resistor in series with the (+) input plus the parallel combination 150kΩ tohfe RreTf oanred e tqhuea sl otou r1c.0e3 r eksΩis.t Tanhcee c loofs 5es0t Ωsta. nInd atrhde vuaplupee ris l 1o.o0p2, kRΩG is –VS 04771-072 Figure 68. PD Pin Circuit and is used for R in the lower loop. G DRIVING AN ADC WITH GREATER THAN 12-BIT Things become more complicated when it comes to determining the feedback resistor values. The amplitude of the signal source PERFORMANCE generator VIN is two times the amplitude of its output signal when Because the AD8137 is suitable for 12-bit systems, it is desirable terminated in 50 Ω. Therefore, a 2 V p-p terminated amplitude to measure the performance of the amplifier in a system with is produced by a 4 V p-p amplitude from VS. The Thevenin greater than 12-bit linearity. In particular, the effective number equivalent circuit of the signal source and RT must be used when of bits (ENOB) is most interesting. The AD7687, 16-bit, 250 KSPS calculating the closed-loop gain because RG in the upper loop is ADC performance makes it an ideal candidate for showcasing split between the 1 kΩ resistor and the Thevenin resistance the 12-bit performance of the AD8137. looking back toward the source. The Thevenin voltage of the For this application, the AD8137 is set in a gain of 2 and driven signal source is greater than the signal source output voltage single-ended through a 20 kHz band-pass filter, while the output when terminated in 50 Ω because R must always be greater T is taken differentially to the input of the AD7687 (see Figure 69). than 50 Ω. In this case, R is 52.3 Ω and the Thevenin voltage T This circuit has mismatched R impedances and, therefore, has a and resistance are 2.04 V p-p and 25.6 Ω, respectively. G dc offset at the differential output. It is included as a test circuit to Now the upper input branch can be viewed as a 2.04 V p-p illustrate the performance of the AD8137. Actual application source in series with 1.03 kΩ. Because this is to be a unity-gain circuits should have matched feedback networks. application, a 2 V p-p differential output is required, and R F For an AD7687 input range up to −1.82 dBFS, the AD8137 power must therefore be 1.03 kΩ × (2/2.04) = 1.01 kΩ ≈ 1 kΩ. supply is a single 5 V applied to V with V tied to ground. To S+ S− This example shows that when RF and RG are large compared to RT, increase the AD7687 input range to −0.45 dBFS, the AD8137 the gain reduction produced by the increase in RG is essentially supplies are increased to +6 V and −1 V. In both cases, the VOCM cancelled by the increase in the Thevenin voltage caused by RT pin is biased with 2.5 V and the PD pin is left floating. All voltage being greater than the output resistance of the signal source. In supplies are decoupled with 0.1 µF capacitors. Figure 70 and general, as R and R become smaller in terminated applications, F G Figure 71 show the performance of the −1.82 dBFS setup and the R needs to be increased to compensate for the increase in R . F G −0.45 dBFS setup, respectively. When generating the typical performance characteristics data, the measurements were calibrated to take the effects of the terminations on closed-loop gain into account. Rev. E | Page 27 of 32

AD8137 Data Sheet VS+ 1.0kΩ 20kHz GND V+ 499Ω 33Ω VIN + VDD BPF VOCM AD8137 1nF AD7687 – GND 499Ω 33Ω 1nF +2.5 VS– 1.0kΩ 04771-0-067 Figure 69. AD8137 Driving AD7687, 16-Bit 250 KSPS ADC 0 0 –10 THD =–93.63dBc –10 THD =–91.75dBc AMPLITUDE (dB OF FULL SCALE) ––––––––111––––––––11111567234567890123400000000000000000 20 40 60 80 10SSE0NINNROA B=D =9=1 1 128.4109.0.67d4BdB14004771-0-068 AMPLITUDE (dB OF FULL SCALE) –––––––––––––––11111112345678901234560000000000000000 20 40 60 80 10SSE0NINNROA B=D =9=1 1 128.4308.5.47d5BdB14004771-0-069 FREQUENCY (kHz) FREQUENCY (kHz) Figure 70. AD8137 Performance on Single 5 V Supply, −1.82 dBFS Figure 71. AD8137 Performance on +6 V, −1 V Supplies, −0.45 dBFS Rev. E | Page 28 of 32

Data Sheet AD8137 OUTLINE DIMENSIONS 5.00(0.1968) 4.80(0.1890) 8 5 4.00(0.1574) 6.20(0.2441) 3.80(0.1497) 1 4 5.80(0.2284) 1.27(0.0500) 0.50(0.0196) BSC 1.75(0.0688) 0.25(0.0099) 45° 0.25(0.0098) 1.35(0.0532) 8° 0.10(0.0040) 0° COPLANARITY 0.51(0.0201) 0.10 SEATING 0.31(0.0122) 0.25(0.0098) 10..2470((00..00510507)) PLANE 0.17(0.0067) COMPLIANTTOJEDECSTANDARDSMS-012-AA C(RINOEFNPEATRRREOENNLCLTEIHNEOGSNDELISYM)AEANNRDSEIAORRNOESUNANORDETEDAIN-POMPFRIFLOLMPIMIRLELIATIMTEEERTFSEO;RIRNECUQHSUEDIVIINMAELDENENSSTIIOGSNNFS.OR 012407-A Figure 72. 8-Lead Standard Small Outline Package [SOIC_N] Narrow Body (R-8) Dimensions shown in millimeters and (inches) 1.84 3.10 1.74 3.00SQ 2.90 1.64 0.50BSC 5 8 PIN1INDEX EXPOSED 1.55 AREA PAD 1.45 0.50 1.35 0.40 0.30 4 1 PIN1 TOPVIEW BOTTOMVIEW INDICATOR (R0.15) 0.80 FORPROPERCONNECTIONOF 0.75 0.05MAX TTHHEEEPXINPCOOSNEDFIGPAUDR,ARTEIOFNERANTOD 0.70 0.02NOM FUNCTIONDESCRIPTIONS COPLANARITY SECTIONOFTHISDATASHEET. SEATING 0.30 0.08 PLANE 0.25 0.203REF 0.C2O0MPLIANTTOJEDECSTANDARDSMO-229-WEED 12-07-2010-A Figure 73. 8-Lead Lead Frame Chip Scale Package [LFCSP_WD] 3 mm × 3 mm Body, Very Very Thin, Dual Lead (CP-8-13) Dimensions shown in millimeters Rev. E | Page 29 of 32

AD8137 Data Sheet ORDERING GUIDE Model1, 2 Temperature Range Package Description Package Option Branding AD8137YR −40°C to +125°C 8-Lead Standard Small Outline Package (SOIC_N) R-8 AD8137YR-REEL7 −40°C to +125°C 8-Lead Standard Small Outline Package (SOIC_N) R-8 AD8137YRZ −40°C to +125°C 8-Lead Standard Small Outline Package (SOIC_N) R-8 AD8137YRZ-REEL −40°C to +125°C 8-Lead Standard Small Outline Package (SOIC_N) R-8 AD8137YRZ-REEL7 −40°C to +125°C 8-Lead Standard Small Outline Package (SOIC_N) R-8 AD8137YCPZ-R2 –40°C to +125°C 8-Lead Lead Frame Chip Scale Package (LFCSP_WD) CP-8-13 HFB# AD8137YCPZ-REEL –40°C to +125°C 8-Lead Lead Frame Chip Scale Package (LFCSP_WD) CP-8-13 HFB# AD8137YCPZ-REEL7 –40°C to +125°C 8-Lead Lead Frame Chip Scale Package (LFCSP_WD) CP-8-13 HFB# AD8137WYCPZ-R7 –40°C to +125°C 8-Lead Lead Frame Chip Scale Package (LFCSP_WD) CP-8-13 H2G AD8137YCP-EBZ LFCSP Evaluation Board AD8137YR-EBZ SOIC Evaluation Board 1 Z = RoHS Compliant Part; # denotes that RoHS part may be top or bottom marked. 2 W = Qualified for Automotive Applications. AUTOMOTIVE PRODUCTS The AD8137W models are available with controlled manufacturing to support the quality and reliability requirements of automotive applications. Note that these automotive models may have specifications that differ from the commercial models; therefore, designers should review the Specifications section of this data sheet carefully. Only the automotive grade products shown are available for use in automotive applications. Contact your local Analog Devices account representative for specific product ordering information and to obtain the specific Automotive Reliability reports for these models. Rev. E | Page 30 of 32

Data Sheet AD8137 NOTES Rev. E | Page 31 of 32

AD8137 Data Sheet NOTES ©2004–2012 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D04771-0-7/12(E) Rev. E | Page 32 of 32

Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: A nalog Devices Inc.: AD8137YRZ AD8137YCPZ-REEL7 AD8137YRZ-REEL7 AD8137YRZ-REEL AD8137YCPZ-R2 AD8137WYCPZ-R7