Low Cost 270 MHz Differential Receiver Amplifiers AD8129/AD8130 FEATURES CONNECTION DIAGRAM High speed AD8129/ AD8130: 270 MHz, 1090 V/μs @ G = +1 AD8130 AD8129: 200 MHz, 1060 V/μs @ G = +10 +IN 1 8 –IN High CMRR –VS 2 + 7 +VS 94 dB min, dc to 100 kHz 80 dB min @ 2 MHz PD 3 6 OUT Hig7h0 idnBp @ut 1 im0 MpeHdza nce: 1 MΩ differential REF 4 5 FB 02464-001 Input common-mode range ±10.5 V Figure 1. Low noise The AD8129/AD8130 are differential-to-single-ended amplifiers AD8130: 12.5 nV/√Hz with extremely high CMRR at high frequency. Therefore, they AD8129: 4.5 nV/√Hz Low distortion, 1 V p-p @ 5 MHz can also be effectively used as high speed instrumentation amps AD8130, −79 dBc worst harmonic @ 5 MHz or for converting differential signals to single-ended signals. AD8129, −74 dBc worst harmonic @ 5 MHz User-adjustable gain The AD8129 is a low noise, high gain (10 or greater) version No external components for G = +1 intended for applications over very long cables, where signal Power supply range +4.5 V to ±12.6 V attenuation is significant. The AD8130 is stable at a gain of 1 Power-down and can be used for applications where lower gains are required. Both have user-adjustable gain to help compensate for losses in APPLICATIONS the transmission line. The gain is set by the ratio of two resistor High speed differential line receivers values. The AD8129/AD8130 have very high input impedance Differential-to-single-ended converters on both inputs, regardless of the gain setting. High speed instrumentation amps Level shifting GENERAL DESCRIPTION The AD8129/AD8130 have excellent common-mode rejection (70 dB @ 10 MHz), allowing the use of low cost, unshielded The AD8129/AD8130 are designed as receivers for the twisted-pair cables without fear of corruption by external noise transmission of high speed signals over twisted-pair cables to sources or crosstalk. The AD8129/AD8130 have a wide power work with the AD8131 or AD8132 drivers. Either can be used supply range from single +5 V to ±12 V, allowing wide common- for analog or digital video signals and for high speed data mode and differential-mode voltage ranges while maintaining transmission. signal integrity. The wide common-mode voltage range enables 120 the driver-receiver pair to operate without isolation transformers 110 in many systems where the ground potential difference between drive and receive locations is many volts. The AD8129/AD8130 100 have considerable cost and performance improvements over 90 op amps and other multiamplifier receiving solutions. B) d 80 R ( +VS MR 70 PD C 3 60 1 VIN 7 8 50 6 VOUT 4 40 2 5 3010k 100k FREQU1EMNCY (Hz) 10M 100M02464-002 RG RF Figure 2. AD8129 CMRR vs. Frequency VOUT=VIN[1+(RF/RG)–]VS 02464-003 Figure 3. Typical Connection Configuration Rev. C Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Tel: 781.329.4700 www.analog.com Trademarks and registered trademarks are the property of their respective owners. Fax: 781.461.3113 © 2005 Analog Devices, Inc. All rights reserved.

AD8129/AD8130 TABLE OF CONTENTS Features..............................................................................................1 Theory of Operation......................................................................32 Applications.......................................................................................1 Op Amp Configuration.............................................................32 Connection Diagram.......................................................................1 Applications.....................................................................................33 General Description.........................................................................1 Basic Gain Circuits.....................................................................33 Revision History...............................................................................2 Twisted-Pair Cable, Composite Video Receiver with Equalization Using an AD8130...................................................33 AD8129/AD8130 Specifications.....................................................3 Output Offset/Level Translator................................................34 5 V Specifications.........................................................................3 Resistorless Gain of 2.................................................................35 ±5 V Specifications.......................................................................5 Summer.......................................................................................35 ±12 V Specifications.....................................................................7 Cable-Tap Amplifier..................................................................35 Absolute Maximum Ratings............................................................9 Power-Down...............................................................................36 Thermal Resistance......................................................................9 Extreme Operating Conditions................................................36 ESD Caution..................................................................................9 Power Dissipation.......................................................................37 Typical Performance Characteristics...........................................10 Layout, Grounding, and Bypassing..........................................38 AD8130 Frequency Response Characteristics........................10 Outline Dimensions.......................................................................39 AD8129 Frequency Response Characteristics........................13 Ordering Guide..........................................................................40 AD8130 Harmonic Distortion Characteristics......................16 AD8129 Harmonic Distortion Characteristics......................18 AD8130 Transient Response Characteristics..........................23 AD8129 Transient Response Characteristics..........................26 REVISION HISTORY 11/05—Rev. B to Rev. C 3/05—Rev. 0 to Rev. A Changes to 5 V Specifications.........................................................3 Changes to Specifications.................................................................2 Changes to Table 4 and Maximum Power Dissipation Section..9 Replaced Figure 3..............................................................................5 Changes to Figure 16......................................................................11 Changes to Ordering Guide.............................................................6 Changes to Figure 17......................................................................12 Updated Outline Dimensions.......................................................27 Revision 0: Initial Version 9/05—Rev. A to Rev. B Extended Temperature Range...........................................Universal Deleted Figure 5................................................................................5 Added Thermal Resistance Section...............................................9 Updated Outline Dimensions.......................................................39 Changes to Ordering Guide..........................................................40 Rev. C | Page 2 of 40

AD8129/AD8130 AD8129/AD8130 SPECIFICATIONS 5 V SPECIFICATIONS AD8129 G = +10, AD8130 G = +1, T = 25°C, +V = 5 V, −V = 0 V, REF = 2.5 V, PD ≥ V , R = 1 kΩ, C = 2 pF, unless otherwise noted. A S S IH L L T to T = −40°C to +125°C, unless otherwise noted. MIN MAX Table 1. Model AD8129 AD8130 Parameter Conditions Min Typ Max Min Typ Max Unit DYNAMIC PERFORMANCE −3 dB Bandwidth V ≤ 0.3 V p-p 160 185 220 250 MHz OUT V = 1 V p-p 160 185 180 205 MHz OUT Bandwidth for 0.1 dB V ≤ 0.3 V p-p, 25/40 25 MHz OUT Flatness SOIC/MSOP Slew Rate V = 2 V p-p, 25% 810 930 810 930 V/μs OUT to 75% Settling Time V = 2 V p-p, 0.1% 20 20 ns OUT Rise and Fall Times V ≤ 1 V p-p, 10% 1.8 1.5 ns OUT to 90% Output Overdrive Recovery 20 30 ns NOISE/DISTORTION Second Harmonic/Third V = 1 V p-p, 5 MHz −68/−75 −72/−79 dBc OUT Harmonic V = 2 V p-p, 5 MHz −62/−64 −65/−71 dBc OUT V = 1 V p-p, 10 MHz −63/−70 −60/−62 dBc OUT V = 2 V p-p, 10 MHz −56/−58 −68/−68 dBc OUT IMD V = 2 V p-p, 10 MHz −67 −70 dBc OUT Output IP3 V = 2 V p-p, 10 MHz 25 26 dBm OUT Input Voltage Noise (RTI) f ≥ 10 kHz 4.5 12.3 nV/√Hz Input Current Noise (+IN, −IN) f ≥ 100 kHz 1 1 pA/√Hz Input Current Noise f ≥ 100 kHz 1.4 1.4 pA/√Hz (REF, FB) Differential Gain Error AD8130, G = +2, NTSC 0.3 0.13 % 100 IRE, R ≥ 150 Ω L Differential Phase Error AD8130, G = +2, NTSC 0.1 0.15 Degrees 100 IRE, R ≥ 150 Ω L INPUT CHARACTERISTICS Common-Mode Rejection DC to 100 kHz, 86 96 86 96 dB Ratio V = 1.5 V to 3.5 V CM V = 1 V p-p @ 1 MHz 80 80 dB CM V = 1 V p-p @ 10 MHz 70 70 dB CM CMRR with V = 1 V p-p V = 1 V p-p @ 1 kHz, 80 72 dB OUT CM V = ±0.5 V dc OUT Common-Mode Voltage V − V = 0 V 1.25 to 1.25 to V +IN −IN Range 3.7 3.8 Differential Operating Range ±0.5 ±2.5 V Differential Clipping Level ±0.6 ±0.75 ±0.85 ±2.3 ±2.8 ±3.3 V Resistance Differential 1 6 MΩ Common mode 4 4 MΩ Capacitance Differential 3 3 pF Common mode 4 4 pF Rev. C | Page 3 of 40

AD8129/AD8130 Model AD8129 AD8130 Parameter Conditions Min Typ Max Min Typ Max Unit DC PERFORMANCE Closed-Loop Gain Error V = ±1 V, R ≥ 150 Ω ±0.25 ±1.25 ±0.1 ±0.6 % OUT L T to T 20 20 ppm/°C MIN MAX Open-Loop Gain V = ±1 V 86 71 dB OUT Gain Nonlinearity V = ±1 V 250 200 ppm OUT Input Offset Voltage 0.2 0.8 0.4 1.8 mV T to T 2 20 μV/°C MIN MAX T to T 1.4 3.5 mV MIN MAX Input Offset Voltage vs. +V = 5 V, −V = −0.5 V −88 −80 −74 −70 dB S S Supply to +0.5 V −V = 0 V, +V = +4.5 V −100 −86 −90 −76 dB S S to +5.5 V Input Bias Current ±0.5 ±2 ±0.5 ±2 μA (+IN, −IN) Input Bias Current ±1 ±3.5 ±1 ±3.5 μA (REF, FB) T to T (+IN, −IN, 5 5 nA/°C MIN MAX REF, FB) Input Offset Current (+IN, −IN, REF, FB) ±0.08 ±0.4 ±0.08 ±0.4 μA T to T 0.2 0.2 nA/°C MIN MAX OUTPUT PERFORMANCE Voltage Swing R ≥ 150 Ω 1.1 3.9 1.1 3.9 V LOAD Output Current 35 35 mA Short-Circuit Current To common −60/+55 −60/+55 mA T to T −240 −240 μA/°C MIN MAX Output Impedance PD ≤ V , in power- 10 10 pF IL down mode POWER SUPPLY Operating Voltage Range Total supply voltage ±2.25 ±12.6 ±2.25 ±12.6 V Quiescent Supply Current 9.9 10.6 9.9 10.6 mA T to T 33 33 μA/°C MIN MAX PD ≤ V 0.65 0.85 0.65 0.85 mA IL PD ≤ V , T to T 1 1 mA IL MIN MAX PD PIN V +V − 1.5 +V − 1.5 V IH S S V +V − 2.5 +V − 2.5 V IL S S IIH PD = min VIH −30 −30 μA IIL PD = max VIL −50 −50 μA Input Resistance PD ≤ +V − 3 V 12.5 12.5 kΩ S PD ≥ +V − 2 V 100 100 kΩ S Enable Time 0.5 0.5 μs OPERATING TEMPERATURE −40 +125 −40 +125 °C RANGE Rev. C | Page 4 of 40

AD8129/AD8130 ±5 V SPECIFICATIONS AD8129 G = +10, AD8130 G = +1, T = 25°C, V = ±5 V, REF = 0 V, PD ≥ V , R = 1 kΩ, C = 2 pF, unless otherwise noted. T to T A S IH L L MIN MAX = −40°C to +125°C, unless otherwise noted. Table 2. AD8129 AD8130 Parameter Conditions Min Typ Max Min Typ Max Unit DYNAMIC PERFORMANCE −3 dB Bandwidth V ≤ 0.3 V p-p 175 200 240 270 MHz OUT V = 2 V p-p 170 190 140 155 MHz OUT Bandwidth for 0.1 dB V ≤ 0.3 V p-p, 30/50 45 MHz OUT Flatness SOIC/MSOP Slew Rate V = 2 V p-p, 925 1060 950 1090 V/μs OUT 25% to 75% Settling Time V = 2 V p-p, 0.1% 20 20 ns OUT Rise and Fall Times V ≤ 1 V p-p, 1.7 1.4 ns OUT 10% to 90% Output Overdrive Recovery 30 40 ns NOISE/DISTORTION Second Harmonic/Third V = 1 V p-p, 5 MHz −74/−84 −79/−86 dBc OUT Harmonic V = 2 V p-p, 5 MHz −68/−74 −74/−81 dBc OUT V = 1 V p-p, 10 MHz −67/−81 −74/−80 dBc OUT V = 1 V p-p, 10 MHz −61/−70 −74/−76 dBc OUT IMD V = 2 V p-p, 10 MHz −67 −70 dBc OUT Output IP3 V = 2 V p-p, 10 MHz 25 26 dBm OUT Input Voltage Noise (RTI) f ≥ 10 kHz 4.5 12.5 nV/√Hz Input Current Noise f ≥ 100 kHz 1 1 pA/√Hz (+IN, −IN) Input Current Noise f ≥ 100 kHz 1.4 1.4 pA/√Hz (REF, FB) Differential Gain Error AD8130, G = +2, NTSC 0.3 0.13 % 200 IRE, R ≥ 150 Ω L Differential Phase Error AD8130, G = +2, NTSC 0.1 0.15 Degrees 200 IRE, R ≥ 150 Ω L INPUT CHARACTERISTICS Common-Mode Rejection DC to 100 kHz, 94 110 90 110 dB Ratio V = −3 V to +3.5 V CM V = 1 V p-p @ 2 MHz 80 80 dB CM V = 1 V p-p @ 10 MHz 70 70 dB CM CMRR with V = 1 V p-p V = 2 V p-p @ 1 kHz, 100 83 dB OUT CM V = ±0.5 V dc OUT Common-Mode Voltage V − V = 0 V ±3.5 ±3.8 V +IN −IN Range Differential Operating ±0.5 ±2.5 V Range Differential Clipping Level ±0.6 ±0.75 ±0.85 ±2.3 ±2.8 ±3.3 V Resistance Differential 1 6 MΩ Common mode 4 4 MΩ Capacitance Differential 3 3 pF Common mode 4 4 pF Rev. C | Page 5 of 40

AD8129/AD8130 AD8129 AD8130 Parameter Conditions Min Typ Max Min Typ Max Unit DC PERFORMANCE Closed-Loop Gain Error V = ±1 V, R ≥ 150 Ω ±0.4 ±1.5 ±0.15 ±0.6 % OUT L T to T 20 10 ppm/°C MIN MAX Open-Loop Gain V = ±1 V 88 74 dB OUT Gain Nonlinearity V = ±1 V 250 200 ppm OUT Input Offset Voltage 0.2 0.8 0.4 1.8 mV T to T 2 20 μV/°C MIN MAX T to T 1.4 3.5 mV MIN MAX Input Offset Voltage vs. +V = +5 V, −V = −4.5 V −90 −84 −78 −74 dB S S Supply to −5.5 V −V = −5 V, +V = +4.5 V −94 −86 −80 −74 dB S S to +5.5 V Input Bias Current ±0.5 ±2 ±0.5 ±2 μA (+IN, −IN) Input Bias Current (REF, FB) ±1 ±3.5 ±1 ±3.5 μA T to T (+IN, −IN, 5 5 nA/°C MIN MAX REF, FB) Input Offset Current (+IN, −IN, REF, FB) ±0.08 ±0.4 ±0.08 ±0.4 μA T to T 0.2 0.2 nA/°C MIN MAX OUTPUT PERFORMANCE Voltage Swing R = 150 Ω/1 kΩ 3.6/4.0 3.6/4.0 ±V LOAD Output Current 40 40 mA Short-Circuit Current To common −60/+55 −60/+55 mA T to T −240 −240 μA/°C MIN MAX Output Impedance PD ≤ V , in power- 10 10 pF IL down mode POWER SUPPLY Operating Voltage Range Total supply voltage ±2.25 ±12.6 ±2.25 ±12.6 V Quiescent Supply Current 10.8 11.6 10.8 11.6 mA T to T 36 36 μA/°C MIN MAX PD ≤ V 0.68 0.85 0.68 0.85 mA IL PD ≤ V , T to T 1 1 mA IL MIN MAX PD PIN V +V − 1.5 +V − 1.5 V IH S S V +V − 2.5 +V − 2.5 V IL S S IIH PD = min VIH −30 −30 μA IIL PD = max VIL −50 −50 μA Input Resistance PD ≤ +V − 3 V 12.5 12.5 kΩ S PD ≥ +V − 2 V 100 100 kΩ S Enable Time 0.5 0.5 μs OPERATING TEMPERATURE −40 +125 −40 +125 °C RANGE Rev. C | Page 6 of 40

AD8129/AD8130 ±12 V SPECIFICATIONS AD8129 G = +10, AD8130 G = +1, T = 25°C, V = ±12 V, REF = 0 V, PD ≥ V , R = 1 kΩ, C = 2 pF, unless otherwise noted. T to A S IH L L MIN T = −40°C to +85°C, unless otherwise noted. MAX Table 3. AD8129 AD8130 Parameter Conditions Min Typ Max Min Typ Max Unit DYNAMIC PERFORMANCE −3 dB Bandwidth V ≤ 0.3 V p-p 175 200 250 290 MHz OUT V = 2 V p-p 170 195 150 175 MHz OUT Bandwidth for 0.1 dB Flatness V ≤ 0.3 V p-p, 50/70 110 MHz OUT SOIC/MSOP Slew Rate V = 2 V p-p, 25% 935 1070 960 1100 V/μs OUT to 75% Settling Time V = 2 V p-p, 0.1% 20 20 ns OUT Rise and Fall Times V ≤ 1 V p-p, 10% 1.7 1.4 ns OUT to 90% Output Overdrive Recovery 40 40 ns NOISE/DISTORTION Second Harmonic/Third V = 1 V p-p, 5 MHz −71/−84 −79/−86 dBc OUT Harmonic V = 2 V p-p, 5 MHz −65/−74 −74/−81 dBc OUT V = 1 V p-p, 10 MHz −65/−82 −74/−80 dBc OUT V = 2 V p-p, 10 MHz −59/−70 −74/−74 dBc OUT IMD V = 2 V p-p, 10 MHz −67 −70 dBc OUT Output IP3 V = 2 V p-p, 10 MHz 25 26 dBm OUT Input Voltage Noise (RTI) f ≥ 10 kHz 4.6 13 nV/√Hz Input Current Noise f ≥ 100 kHz 1 1 pA/√Hz (+IN, −IN) Input Current Noise f ≥ 100 kHz 1.4 1.4 pA/√Hz (REF, FB) Differential Gain Error AD8130, G = +2, NTSC 0.3 0.13 % 200 IRE, R ≥ 150 Ω L Differential Phase Error AD8130, G = +2, NTSC 0.1 0.2 Degrees 200 IRE, R ≥ 150 Ω L INPUT CHARACTERISTICS Common-Mode Rejection DC to 100 kHz, 92 105 88 105 dB Ratio V = ±10 V CM V = 1 V p-p @ 2 MHz 80 80 dB CM V = 1 V p-p @ 10 MHz 70 70 dB CM CMRR with V = 1 V p-p V = 4 V p-p @ 1 kHz, 93 80 dB OUT CM V = ±0.5 V dc OUT Common-Mode Voltage V − V = 0 V ±10.3 ±10.5 V +IN –IN Range Differential Operating Range ±0.5 ±2.5 V Differential Clipping Level ±0.6 ±0.75 ±0.85 ±2.3 ±2.8 ±3.3 V Resistance Differential 1 6 MΩ Common mode 4 4 MΩ Capacitance Differential 3 3 pF Common mode 4 4 pF Rev. C | Page 7 of 40

AD8129/AD8130 AD8129 AD8130 Parameter Conditions Min Typ Max Min Typ Max Unit DC PERFORMANCE Closed-Loop Gain Error V = ±1 V, R ≥ 150 Ω ±0.8 ±1.8 ±0.15 ±0.6 % OUT L T to T 20 10 ppm/°C MIN MAX Open-Loop Gain V = ±1 V 87 73 dB OUT Gain Nonlinearity V = ±1 V 250 200 ppm OUT Input Offset Voltage 0.2 0.8 0.4 1.8 mV T to T 2 20 μV/°C MIN MAX T to T 1.4 3.5 mV MIN MAX Input Offset Voltage vs. Supply +V = +12 V, −V = −88 −82 −77 −70 dB S S –11.0 V to −13.0 V −V = −12 V, +V = −92 −84 −88 −70 dB S S +11.0 V to +13.0 V Input Bias Current (+IN, −IN) ±0.25 ±2 ±0.25 ±2 μA Input Bias Current (REF, FB) ±0.5 ±3.5 ±0.5 ±3.5 μA T to T 2.5 2.5 nA/°C MIN MAX (+IN, −IN, REF, FB) Input Offset Current (+IN, −IN, REF, FB) ±0.08 ±0.4 ±0.08 ±0.4 μA T to T 0.2 0.2 nA/°C MIN MAX OUTPUT PERFORMANCE Voltage Swing RLOAD = 700 Ω ±10.8 ±10.8 V Output Current 40 40 mA Short-Circuit Current To common −60/+55 −60/+55 mA T to T −240 −240 μA/°C MIN MAX Output Impedance PD ≤ V , in power- 10 10 pF IL down mode POWER SUPPLY Operating Voltage Range Total supply voltage ±2.25 ±12.6 ±2.25 ±12.6 V Quiescent Supply Current 13 13.9 13 13.9 mA T to T 43 43 μA°C MIN MAX PD ≤ V 0.73 0.9 0.73 0.9 mA IL PD ≤ V , T to T 1.1 1.1 mA IL MIN MAX PD PIN V +V − 1.5 +V − 1.5 V IH S S V +V − 2.5 +V − 2.5 V IL S S IIH PD = min VIH −30 −30 μA IIL PD = max VIL −50 −50 μA Input Resistance PD ≤ +V − 3 V 3 3 kΩ S PD ≥ +V − 2 V 100 100 kΩ S Enable Time 0.5 0.5 μs OPERATING TEMPERATURE −40 +85 −40 +85 °C RANGE Rev. C | Page 8 of 40

AD8129/AD8130 ABSOLUTE MAXIMUM RATINGS Table 4. The power dissipated in the package (P ) is the sum of the D Parameter Rating quiescent power dissipation and the power dissipated in the Supply Voltage 26.4 V package due to the load drive. The quiescent power is the Power Dissipation Refer to Figure 4 voltage between the supply pins (V) times the quiescent S Input Voltage (Any Input) −VS − 0.3 V to +VS + 0.3 V current (IS). The power dissipated due to the load drive Differential Input Voltage (AD8129) depends upon the particular application. The power due to VS ≥ ±11.5 V ±0.5 V load drive is calculated by multiplying the load current by the Differential Input Voltage (AD8129) associated voltage drop across the device. RMS voltages and VS < ±11.5 V ±6.2 V currents must be used in these calculations. Differential Input Voltage (AD8130) ±8.4 V Storage Temperature Range −65°C to +150°C Airflow reduces θJA. In addition, more metal directly in contact Lead Temperature (Soldering, 10 sec) 300°C with the package leads from metal traces through holes, ground, Junction Temperature 150°C and power planes reduces the θJA. Stresses above those listed under Absolute Maximum Ratings Figure 4 shows the maximum safe power dissipation in the may cause permanent damage to the device. This is a stress package vs. the ambient temperature for the 8-lead SOIC rating only; functional operation of the device at these or any (121°C/W) and MSOP (θ = 142°C/W) packages on a JEDEC JA other conditions above those indicated in the operational standard 4-layer board. θ values are approximations. JA section of this specification is not implied. Exposure to absolute 1.75 maximum rating conditions for extended periods may affect device reliability. W)1.50 THERMAL RESISTANCE N ( O TI1.25 A θJA is specified for the worst-case conditions, that is, θJA is SIP specified for the device soldered in a circuit board in still air. DIS1.00 SOIC R Table 5. Thermal Resistance WE0.75 O Package Type θ Unit P MSOP JA M 8-Lead SOIC/4-Layer 121 °C/W MU0.50 XI 8-Lead MSOP/4-Layer 142 °C/W A M0.25 MThaex mimaxuimmu Pmo wsaefre Dpoiswseipr aditsisoinpa tion in the AD8129/AD8130 0–40–30–20–10 0AM10BI2E0NT3 T0EM40PE5R0AT6U0R7E0 (°8C0) 90100110120 02464-005 Figure 4. Maximum Power Dissipation vs. Temperature packages is limited by the associated rise in junction temp- erature (TJ) on the die. At approximately 150°C, which is the glass transition temperature, the plastic changes its properties. Even temporarily exceeding this temperature limit can change the stresses that the package exerts on the die, permanently shifting the parametric performance of the AD8129/AD8130. Exceeding a junction temperature of 150°C for an extended period can result in changes in the silicon devices, potentially causing failure. ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. Rev. C | Page 9 of 40

AD8129/AD8130 TYPICAL PERFORMANCE CHARACTERISTICS AD8130 FREQUENCY RESPONSE CHARACTERISTICS G = +1, R = 1 kΩ, C = 2 pF, V = 0.3 V p-p, T = 25°C, unless otherwise noted. L L OUT A 3 6 2 VOUT = 0.3V p-p VS =±2.5V 5 VS =±5V CL = 20pF 1 4 CL = 10pF 0 3 B)–1 VS =±5V B) 2 CL = 5pF N (d–2 VS =±12V N (d 1 AI AI G–3 G 0 –4 –1 CL = 2pF –5 –2 ––67 02464-006 ––34 02464-009 1 10 100 400 1 10 100 300 FREQUENCY (MHz) FREQUENCY (MHz) Figure 5. AD8130 Frequency Response vs. Supply, VOUT = 0.3 V p-p Figure 8. AD8130 Frequency Response vs. Load Capacitance 3 0.7 VOUT = 1V p-p VS =±2.5V RL = 1kΩ 2 0.6 VS =±5V 1 0.5 VS =±2.5V 0 0.4 dB)–1 VS =±12V dB) 0.3 VS =±5V N (–2 N ( 0.2 AI AI G–3 G 0.1 –4 0 –5 –0.1 ––67 02464-007 ––00..23 VS =±12V 02464-010 1 10 100 300 1 10 100 300 FREQUENCY (MHz) FREQUENCY (MHz) Figure 6. AD8130 Frequency Response vs. Supply, VOUT = 1 V p-p Figure 9. AD8130 Fine Scale Response vs. Supply, RL = 1 kΩ 3 0.5 VOUT = 2V p-p RL = 150Ω 2 VS =±5V 0.4 VS =±2.5V 1 0.3 VS =±2.5V 0 0.2 VS =±5V B)–1 VS =±12V B) 0.1 N (d–2 N (d 0 AI AI G–3 G–0.1 –4 –0.2 –5 –0.3 VS =±12V ––67 02464-008 ––00..45 02464-011 1 10 100 300 1 10 100 300 FREQUENCY (MHz) FREQUENCY (MHz) Figure 7. AD8130 Frequency Response vs. Supply, VOUT = 2 V p-p Figure 10. AD8130 Fine Scale Response vs. Supply, RL = 150 Ω Rev. C | Page 10 of 40

AD8129/AD8130 3 3 2 RL = 150Ω VS =±2.5V 2 GVS = = +±25V RF = RG = 750Ω RF = RG = 1kΩ 1 1 0 0 B)–1 VS =±5V B)–1 RF = RG = 499Ω d d N (–2 N (–2 AI VS =±12V AI G–3 G–3 RF = RG = 250Ω –4 –4 –5 –5 ––67 02464-012 ––67 02464-015 1 10 100 400 1 10 100 300 FREQUENCY (MHz) FREQUENCY (MHz) Figure 11. AD8130 Frequency Response vs. Supply, RL = 150 Ω Figure 14. AD8130 Frequency Response for Various RF/RG 3 0.3 G = +2 G = +2 2 VOUT = 0.3V p-p 0.2 RL = 1kΩ VS =±2.5V 1 VS =±2.5V 0.1 0 0 dB)–1 VS =±5V B)–0.1 GAIN (–2 VS =±12V AIN (d–0.2 –3 G–0.3 VS =±5V –4 –0.4 –5 –0.5 VS =±12V ––67 02464-013 ––00..67 02464-016 1 10 100 300 1 10 100 FREQUENCY (MHz) FREQUENCY (MHz) Figure 12. AD8130 Frequency Response vs. Supply, Figure 15. AD8130 Fine Scale Response vs. Supply, G = +2, VOUT = 0.3 V p-p G = +2, RL = 1 kΩ 3 0.3 G = +2 G=+2 2 VOUT = 2V p-p 0.2 RL=150Ω 1 VS =±2.5V 0.1 VS=±2.5V 0 0 GAIN (dB)––21 VVSS ==±±51V2V AIN (dB)––00..21 VS=±5V –3 G–0.3 –4 –0.4 VS=±12V –5 –0.5 ––67 02464-014 ––00..67 02464-017 1 10 100 300 1 10 100 FREQUENCY (MHz) FREQUENCY(MHz) Figure 13. AD8130 Frequency Response vs. Supply, Figure 16. AD8130 Fine Scale Response vs. Supply, G = +2, VOUT = 2 V p-p G = +2, RL = 150 Ω Rev. C | Page 11 of 40

AD8129/AD8130 3 3 2 GRL==+1250Ω 2 RL = 150Ω 1 VS=±2.5V 1 VS =±5V,±12V 0 VS=±5V 0 B) –1 B)–1 G = +10 G = +5 N (d –2 VS=±12V N (d–2 GAI –3 GAI–3 VS =±2.5V –4 –4 VS =±5V,±12V –5 –5 ––67 02464-018 ––67 02464-021 1 10 100 300 0.1 1 10 100 FREQUENCY(MHz) FREQUENCY (MHz) Figure 17. AD8130 Frequency Response vs. Supply, Figure 20. AD8130 Frequency Response vs. Supply, G = +2, RL = 150 Ω G = +5, G = +10, RL = 150 Ω 0.3 12 VOUT = 2V p-p 0dB = 1V rms 0.2 6 VS =±2.5V VS =±5V 0.1 0 V) 0 B –6 d GAIN (dB) –––000...321 VSV S= =±5±V2,.5±V12V VS =±12V UT VOLTAGE (–––112284 P T –0.4 U–30 G = +10 G = +5 O –0.5 –36 ––00..67 02464-019 ––4428 VS =±5V 02464-022 0.1 1 10 30 10 100 400 FREQUENCY (MHz) FREQUENCY (MHz) Figure 18. AD8130 Fine Scale Response vs. Supply, Figure 21. AD8130 Frequency Response for Various Output Levels G = +5, G = +10, VOUT = 2 V p-p 3 VOUT = 2V p-p 2 1 TEK P6245 1 FET PROBE 8 50Ω 6 0 4 B)–1 5 RL CL d N (–2 AI VS =±12V G = +5 RG RF G–3 –4 VS =±5V,±12V G RF RG –5 VS =±2.5V 1 0Ω – ––670.1 1 G 1=0 +10 10002464-020 1250 844..099699kkΩΩΩ 54249k99ΩΩΩ 02464-023 FREQUENCY (MHz) Figure 19. AD8130 Frequency Response vs. Supply, Figure 22. AD8130 Basic Frequency Response Test Circuit G = +5, G = +10, VOUT = 2 V p-p Rev. C | Page 12 of 40

AD8129/AD8130 AD8129 FREQUENCY RESPONSE CHARACTERISTICS G = +10, R = 1 kΩ, C = 2 pF, V = 0.3 V p-p, T = 25°C, unless otherwise noted. L L OUT A 3 4 VOUT = 0.3V p-p VS =±5V CL = 20pF 2 VS =±2.5V VS =±5V 3 CL = 10pF 1 2 0 1 B) –1 VS =±12V B) 0 N (d –2 N (d–1 CL = 5pF AI AI G –3 G–2 CL = 2pF –4 –3 –5 –4 ––67 02464-024 ––56 02464-027 1 10 100 300 1 10 100 300 FREQUENCY (MHz) FREQUENCY (MHz) Figure 23. AD8129 Frequency Response vs. Supply, VOUT = 0.3 V p-p Figure 26. AD8129 Frequency Response vs. Load Capacitance 3 0.5 2 VOUT = 1V p-p VS =±5V 0.4 RL = 1kΩ VS =±2.5V 1 VS =±2.5V 0.3 VS =±5V 0 0.2 B)–1 VS =±12V B) 0.1 d d GAIN (––32 GAIN (–0.10 VS =±12V –4 –0.2 –5 –0.3 ––67 02464-025 ––00..45 02464-028 1 10 100 300 1 10 100 300 FREQUENCY (MHz) FREQUENCY (MHz) Figure 24. AD8129 Frequency Response vs. Supply, VOUT = 1 V p-p Figure 27. AD8129 Fine Scale Response vs. Supply, RL = 1 kΩ 3 0.3 2 VOUT = 2V p-p VS =±2.5V 0.2 RL = 150Ω VS =±2.5V 1 0.1 0 0 AIN (dB)––21 VS V=S± 5=V±12V AIN (dB)––00..21 VS =V±5SV =±12V G–3 G–0.3 –4 –0.4 –5 –0.5 ––67 02464-026 ––00..67 02464-029 1 10 100 300 1 10 100 300 FREQUENCY (MHz) FREQUENCY (MHz) Figure 25. AD8129 Frequency Response vs. Supply, VOUT = 2 V p-p Figure 28. AD8129 Fine Scale Response vs. Supply, RL = 150 Ω Rev. C | Page 13 of 40

AD8129/AD8130 3 0.8 2 RL = 150Ω 0.6 GVS = = +±150V 2kΩ/221Ω 909Ω/100Ω VS =±2.5V 1 0.4 499Ω/54.9Ω 0 0.2 SOIC –1 0 B) B) N (d –2 VS =±5V N (d –0.2 499Ω/54.9Ω AI VS =±12V AI 909Ω/100Ω G –3 G 0.2 μSOIC –4 0 –5 –0.2 2kΩ/221Ω ––67 02464-030 ––00..46 02464-033 10 100 300 1 10 100 300 FREQUENCY (MHz) FREQUENCY (MHz) Figure 29. AD8129 Frequency Response vs. Supply, RL = 150 Ω Figure 32. AD8129 Fine Scale Response vs. SOIC and MSOP for Various RF/RG 3 0.2 G = +20 G = +20 2 VOUT = 0.3V p-p 0.1 RL = 1kΩ 1 0 0 VS =±5V,±12V –0.1 VS =±5V –1 –0.2 B) B) d d N ( –2 N ( –0.3 GAI –3 GAI –0.4 VS =±12V –4 VS =±2.5V –0.5 VS =±2.5V –5 –0.6 ––67 02464-031 ––00..78 02464-034 1 10 100 300 1 10 30 FREQUENCY (MHz) FREQUENCY (MHz) Figure 30. AD8129 Frequency Response vs. Supply, Figure 33. AD8129 Fine Scale Response vs. Supply G = +20, VOUT = 0.3 V p-p 3 0.3 G = +20 G = +20 2 VOUT = 2V p-p 0.2 RL = 150Ω 1 0.1 VS =±5V,±12V 0 VS =±5V,±12V 0 GAIN (dB) –––123 GAIN (dB)–––000...321 –4 VS =±2.5V –0.4 –5 –0.5 VS =±2.5V ––67 02464-032 ––00..67 02464-035 1 10 100 300 0.1 1 10 30 FREQUENCY (MHz) FREQUENCY (MHz) Figure 31. AD8129 Frequency Response vs. Supply, Figure 34. AD8129 Fine Scale Response vs. Supply G = +20, VOUT = 2 V p-p Rev. C | Page 14 of 40

AD8129/AD8130 3 3 G = +20 RL = 150Ω 2 RL = 150Ω 2 1 1 0 0 VS =±5V,±12V –1 –1 dB) dB) G = +100 G = +50 N ( –2 N ( –2 AI AI G –3 G –3 VS =±2.5V –4 –4 VS =±5V –5 VS =±2.5V –5 VS =±12V ––67 02464-036 ––67 02464-039 1 10 100 300 0.1 1 10 50 FREQUENCY (MHz) FREQUENCY (MHz) Figure 35. AD8129 Frequency Response vs. Supply, Figure 38. AD8129 Frequency Response vs. Supply, G = +20, RL = 150 Ω G = +50, G = +100, RL = 150 Ω 0.2 12 VOUT = 2V p-p 0dB = 1V rms 0.1 VS =±12V 6 0 0 –0.1 G = +100 BV) –6 AIN (dB) ––00..32 VS =±2.5V G = +50 VOLTAGE (d ––1128 G –0.4 VS =±5V T –24 U P –0.5 UT –30 O –0.6 VS=±12V –36 ––00..78 02464-037 ––4428 VS =±5V 02464-040 0.1 1 10 10 100 400 FREQUENCY (MHz) FREQUENCY (MHz) Figure 36. AD8129 Fine Scale Response vs. Supply, Figure 39. AD8129 Frequency Response for Various Output Levels G = +50, G = +100, VOUT = 2 V p-p 3 2 VOUT = 2V p-p 1 0 1 TEK P6245 FET PROBE B) –1 G = +100 G = +50 50Ω 8 6 d 4 AIN ( –2 5 RL CL G –3 –4 VS =±2.5V RG RF –5 VS =±5V ––670.1 F1REQUENCY (MHVzS) =±1120V 5002464-038 1125G00000 2222RkkkkFΩΩΩΩ 42121200R.152ΩGΩΩΩ 02464-041 Figure 37. AD8129 Frequency Response vs. Supply, Figure 40. AD8129 Basic Frequency Response Test Circuit G = +50, G = +100, VOUT = 2 V p-p Rev. C | Page 15 of 40

AD8129/AD8130 AD8130 HARMONIC DISTORTION CHARACTERISTICS R = 1 kΩ, C = 2 pF, T = 25°C, unless otherwise noted. L L A –60 –51 VOUT = 1V p-p VOUT = 1V p-p G = +1 –57 VS =±5V G = +1 –66 –63 VS =±12V VS =±12V –69 Bc) –72 Bc) HD2 (d –78 G = +1 HD3 (d ––8715 VS =±12V VS =±5V G = +1 VS =±12V VS =±5V –87 –84 –90 G = +2 02464-042 ––9993 G = +2 02464-045 1 10 40 1 10 40 FREQUENCY (MHz) FREQUENCY (MHz) Figure 41. AD8130 Second Harmonic Distortion vs. Frequency Figure 44. AD8130 Third Harmonic Distortion vs. Frequency –54 –45 VOUT = 2V p-p VOUT = 2V p-p G = +2, VS =±12V –51 –60 G = +1 G = +2, VS =±5V VS =±5V –57 –63 Bc) –66 Bc) HD2 (d –72 HD3 (d –69 VS =±12V –75 VS =±5V G = +1 –81 –78 VS =±12V –84 G = +2 VS =±5V VSG = =± +121V 02464-043 ––9837 G = +2 02464-046 1 10 40 1 10 40 FREQUENCY (MHz) FREQUENCY (MHz) Figure 42. AD8130 Second Harmonic Distortion vs. Frequency Figure 45. AD8130 Third Harmonic Distortion vs. Frequency –55 –46 fC = 5MHz VS =±12V fC = 5MHz VS =±12V –61 VS =±5V –52 –58 VS =±5V –67 –64 G = +1 c) c) B B D2 (d –73 D3 (d –70 G = +1 G = +2 H H –76 –79 G = +2 VS =±12V –82 VS =±12V –85 VS =±5V –91 02464-044 ––9848 VS =±5V 02464-047 0.5 1 10 0.5 1 10 VOUT (V p-p) VOUT (V p-p) Figure 43. AD8130 Second Harmonic Distortion vs. Output Voltage Figure 46. AD8130 Third Harmonic Distortion vs. Output Voltage Rev. C | Page 16 of 40

AD8129/AD8130 –43 –46 VS =±2.5V VS =±2.5V G = +2, HD3 –52 fC = 5MHz –49 G = +1, HD3 G = +1 –58 –55 VOUT = 2V p-p –64 G = +1, HD2 D2 (dBc) –61 G = +2 D (dBc) –70 G = +2, HD2 G = +2, HD2 H H –76 –67 –82 G = +2, HD3 –73 –79 G = +1 G = +2 VOUT = 1V p-p 02464-048 ––9848 02464-050 1 10 40 0 0.5 1.0 1.5 2.0 2.5 3.0 FREQUENCY (MHz) VOUT(V p-p) Figure 47. AD8130 Second Harmonic Distortion vs. Frequency Figure 49. AD8130 Harmonic Distortion vs. Output Voltage –42 VS =±2.5V –48 –54 –60 VOUT = 2V p-p Bc) –66 d G = +2 D3 ( –72 H G = +1 –78 G = +1 –84 G = +2 ––9960 VOUT = 1V p-p 02464-049 1 10 40 FREQUENCY (MHz) Figure 48. AD8130 Third Harmonic Distortion vs. Frequency Rev. C | Page 17 of 40

AD8129/AD8130 AD8129 HARMONIC DISTORTION CHARACTERISTICS R = 1 kΩ, C = 2 pF, T = 25°C, unless otherwise noted. L L A –51 –54 VOUT = 1V p-p VOUT = 1V p-p G = +10, –60 VS =±5V –57 G = +10, –63 –66 VS =±12V HD2 (dBc) ––6795 GVS = = +±150V,GVS = = +±1102,V HD3 (dBc)––7728 GVS = = +±250V, –84 G = +20, ––8817 GVS = = +±2V50SV, =±12V 02464-051 ––9960 GVS = = +±2102,V 02464-054 1 10 40 1 10 40 FREQUENCY (MHz) FREQUENCY (MHz) Figure 50. AD8129 Second Harmonic Distortion vs. Frequency Figure 53. AD8129 Third Harmonic Distortion vs. Frequency –42 –45 VOUT = 2V p-p VOUT = 2V p-p G = +10, –48 –51 VS =±5V G = +10 G = +10, –54 –57 VS =±12V G = +10, D2 (dBc)––6606 GVS = = +±2102,V VS =±12V G = +20 D3 (dBc) ––6639 GVS = = +±1102,V H H –72 –75 G = +20, ––7884 GVS = = +±250V, GVS = = +±150V, 02464-052 ––8817 GVS = = +±150V, GVS = = V+S±2 10=2,±V5V 02464-055 1 10 40 1 10 40 FREQUENCY (MHz) FREQUENCY (MHz) Figure 51. AD8129 Second Harmonic Distortion vs. Frequency Figure 54. AD8129 Third Harmonic Distortion vs. Frequency –50 –48 fC = 5MHz fC = 5MHz G = +10, –56 –54 VS =±12V G = +10, –60 VS =±5V –62 G = +10, –66 dBc) –68 VS =±12V G = +10, Bc)–72 D2 ( VS =±5V 3 (d H D–78 –74 H G = +20, GVS = = +±250V, –84 VS =±5V –80 G = +20, –860.5 1 GVS = = +±2102,V 1002464-053 ––99060.5 1 VS =±12V 1002464-056 VOUT(V p-p) VOUT (V p-p) Figure 52. AD8129 Second Harmonic Distortion vs. Output Voltage Figure 55. AD8129 Third Harmonic Distortion vs. Output Voltage Rev. C | Page 18 of 40

AD8129/AD8130 –44 –39 VS =±2.5V G = +1 –50 VOUT = 2V p-p –45 VVOS U=T± =5 V2V p-p –51 fRCL = = 5 1MkHΩz –56 c) B –57 Bc) G = +20 N (d 2 (d–62 TIO –63 HD VOUT = 1V p-p OR –68 DIST –69 HD2 –75 –74 –80 G = +10 02464-057 ––8871 HD3 02464-060 1 10 40 –5 –4 –3 –2 –1 0 1 2 3 4 5 FREQUENCY (MHz) VCM(V) Figure 56. AD8129 Second Harmonic Distortion vs. Frequency Figure 59. AD8130 Harmonic Distortion vs. Common-Mode Voltage –42 –61 VS =±2.5V G = +1 VOUT = 1V p-p –48 fC = 5MHz VOUT = 2V p-p –67 HD2 –54 VS =±2.5V –60 Bc) –73 HD2 Bc) G = +20 N (d VS =±5V,±12V HD3 (d––6762 VOUT = 1V p-p STORTIO –79 VSH =D±35V G = +10 DI –85 –78 HD3 VS =±12V –91 ––9804 02464-058 –97 VS H=D±32.5V 02464-061 1 10 40 100 1k FREQUENCY (MHz) RL(Ω) Figure 57. AD8129 Third Harmonic Distortion vs. Frequency Figure 60. AD8130 Harmonic Distortion vs. Load Resistance –50 –50 VfCS == 5±M2.H5zV GfC == +51MHz VOUT = 2V p-p –56 –56 HD2 VS =±2.5V –62 c) –62 G = +20 G = +20 dB c) HD3 HD2 N ( HD2 D (dB –68 G H=D +210 RTIO –68 VS =±5V,±12V H O T S –74 DI –74 G = +10 HD3 –80 –80 HD3 –86 02464-059 –86 VS =±2.5V VS =±H5DV3,±12V 02464-062 0 0.5 1.0 1.5 2.0 2.5 3.0 100 1k VOUT(V p-p) RL(Ω) Figure 58. AD8129 Harmonic Distortion vs. Output Voltage Figure 61. AD8130 Harmonic Distortion vs. Load Resistance Rev. C | Page 19 of 40

AD8129/AD8130 –36 G = +10 –42 VOUT = 2V p-p RVSL == ±15kVΩ VCM –48 fC = 5MHz c) B N (d –54 200Ω RL O ORTI –60 1:2 RL ST CL DI –66 HD2 RG RF ––7782–5 –4 –3 –2 –1 VCM0(V)HD13 2 3 4 502464-063 #M# ITTNC4I--46C-T1IR,WfCC,Uf≤CI T1>S0 1®M0:HMzHz 1212G00 42209RkkΩ9FΩΩΩ 421R920–915GΩΩΩ 02464-066 Figure 62. AD8129 Harmonic Distortion vs. Common-Mode Voltage Figure 65. AD8129/AD8130 Basic Distortion Test Circuit, VCM = 0 V, Unless Otherwise Noted –48 100 G = +10 VOUT = 1V p-p fC = 5MHz –54 VS =±2.5V –60 HD2 VS =±12V Hz) N (dBc) –68 VS =±5V SE (pA/√ 10 DISTORTIO –72 VS =±V1S2 V=±5V RRENT NOI1.0 –78 U C HD3 –84 –90 VS =±2.5V 02464-064 0.1 02464-067 100 1k 10 100 1k 10k 100k 1M 10M RL(Ω) FREQUENCY(Hz) Figure 63. AD8129 Harmonic Distortion vs. Load Resistance Figure 66. AD8129/AD8130 Input Current Noise vs. Frequency –44 100 G = +10 VOUT = 2V p-p fC = 5MHz –50 VS =±2.5V VS =±12V Hz) √ Bc) –56 VS =±5V nV/ N (d SE ( AD8130 O OI ORTI –62 VS =±2.5V NT N 10 DIST –68 RRE AD8129 U HD3 VS =±12V C –74 –80100 VS =±5V 1k02464-065 1 02464-068 RL(Ω) 10 100 1k 10k 100k 1M 10M FREQUENCY(Hz) Figure 64. AD8129 Harmonic Distortion vs. Load Resistance Figure 67. AD8129/AD8130 Input Voltage Noise vs. Frequency Rev. C | Page 20 of 40

AD8129/AD8130 –30 –30 –40 –40 N (dB) –50 dB) –50 CTIO –60 ON ( –60 E TI EJ –70 EC –70 R J ODE –80 E RE –80 VS =±2.5V M D MON- –90 VS =±2.5V N-MO –90 OM–100 MO–100 C––111200 VS =±5V,±12V 02464-069 COM––111200 VS =±5V,±12V  02464-072 10k 100k 1M 10M 100M 10k 100k 1M 10M 100M FREQUENCY (Hz) FREQUENCY (Hz) Figure 68. AD8130 Common-Mode Rejection vs. Frequency Figure 71. AD8139 Common-Mode Rejection vs. Frequency 0 0 –10 –10 ON (dB)––2300 ON (dB) ––2300 ECTI–40 ECTI –40 EJ EJ Y R–50 Y R –50 PPL–60 PPL –60 U U R S–70 VS =±12V R S –70 WE WE VS =±12V O–80 O –80 P VS =±5V P VS =±2.5V –1–9000 VS =±2.5V 02464-070 –1–9000 VS =±5V 02464-073 1k 10k 100k 1M 10M 100M 1k 10k 100k 1M 10M 100M FREQUENCY (Hz) FREQUENCY (Hz) Figure 69. AD8130 Positive Power Supply Rejection vs. Frequency Figure 72. AD8129 Positive Power Supply Rejection vs. Frequency 0 0 –10 –10 –20 B)–20 d N (dB)–30 TION (–30 O C EJECTI––4500 Y REJE––4500 R L PLY –60 UPP–60 UP–70 VS =±2.5V R S–70 R S WE VS =±5V E–80 O–80 OW P VS =±12V P–1–9000 VS =±5V VS =±12V 02464-071 –1–0900 VS =±2.5V 02464-074 1k 10k 100k 1M 10M 100M 1k 10k 100k 1M 10M 100M FREQUENCY (Hz) FREQUENCY (Hz) Figure 70. AD8130 Negative Power Supply Rejection vs. Frequency Figure 73. AD8129 Negative Power Supply Rejection vs. Frequency Rev. C | Page 21 of 40

AD8129/AD8130 80 100 VS =±5V 70 180 60 10 GAIN (dB)5400 GAIN 135 N (Degrees) DANCE ()Ω 1 OPEN-LOOP 3200 –++ 1kΩVOUT 2pF PHASE 90 PHASE MARGI OUTPUT IMPE100m AD8130, G = +1 10 – 45 10m 100Ω 1kΩ –1001k V1I0Nk 10F0RkEQUENC1MY (Hz) 10M φM=1 0508M° 3000M 02464-075 1m1k 10kAD81291F, 0RG0E k=Q +U1E0NCY 1(HMz) 10M 10002464-077M Figure 74. AD8130 Open-Loop Gain and Phase vs. Frequency Figure 76. Closed-Loop Output Impedance vs. Frequency 90 80 180 GAIN 70 GAIN (dB)6500 135N (Degrees) P GI OO40 90 AR L M EN-30 VOUT PHASE SE P A O20 1kΩ 2pF 45 PH 100Ω 1kΩ 10 φM= 56° VIN 01k 10k 100kFREQUE1MNCY (Hz)10M 100M 300M0 02464-076 Figure 75. AD8129 Open-Loop Gain and Phase vs. Frequency Rev. C | Page 22 of 40

AD8129/AD8130 AD8130 TRANSIENT RESPONSE CHARACTERISTICS G = +1, R = 1 kΩ, C = 2 pF, V = ±5 V, T = 25°C, unless otherwise noted. L L S A VOUT = 1V p-p VS =±2.5V VS =±5V VOUT = 0.2V p-p VS =±2.5V VS =±12V 250mV 5.00ns 02464-078 50mV 5.00ns 02464-081 Figure 77. AD8130 Transient Response, VS = ±2.5 V, VOUT = 1 V p-p Figure 80. AD8130 Transient Response vs. Supply, VOUT = 0.2 V p-p VVOS U=T± =5 V1V p-p VS =±2.5V VS =±5V CVOL U=T 5 =p F1V p-p VS =±12V 250mV 5.00ns 02464-079 250mV 5.00ns 02464-082 Figure 78. AD8130 Transient Response, VS = ±5 V, VOUT = 1 V p-p Figure 81. AD8130 Transient Response vs. Supply, VOUT = 1 V p-p, CL = 5 pF VVOS U=T± =1 21VV p-p VS =±2.5V VS =±5V CVOL U=T 5 =p F2V p-p VS =±12V 250mV 5.00ns 02464-080 500mV 5.00ns 02464-083 Figure 79. AD8130 Transient Response, VS = ±12 V, VOUT = 1 V p-p Figure 82. AD8130 Transient Response vs. Supply, VOUT = 2 V p-p, CL = 5 pF Rev. C | Page 23 of 40

AD8129/AD8130 CL = 10pF CL = 5pF VOUT = 0.2 V p-p GVO =U +T 2= 1V p-p CL = 2pF VS =±5V, CL = 10pF VS =±5V, CL = 2pF 50mV 10.00ns 02464-084 250mV 5.00ns 02464-087 Figure 83. AD8130 Transient Response vs. Load Capacitance, Figure 86. AD8130 Transient Response vs. Load Capacitance, VOUT = 0.2 V p-p VOUT = 1 V p-p, G = +2 VOUT = 2V p-p G = +2 2V p-p VS =±5V 1V p-p VS =±12V 0.5V p-p 500mV 5.00ns 02464-085 500mV 5.00ns 02464-088 Figure 84. AD8130 Transient Response vs. Output Amplitude, Figure 87. AD8130 Transient Response vs. Supply, VOUT = 2 V p-p, G = +2 VOUT = 0.5 V p-p, 1 V p-p, 2 V p-p VOUT = 8V p-p G = +2 VS =±5V 4V p-p CL = 10pF 2V p-p CL = 2pF 1V p-p 1.00V 5.00ns 02464-086 2.00V 5.00ns 02464-089 Figure 85. AD8130 Transient Response vs. Output Amplitude, Figure 88. AD8130 Transient Response vs. Load Capacitance, VOUT = 1 V p-p, 2 V p-p, 4 V p-p VOUT = 8 V p-p Rev. C | Page 24 of 40

AD8129/AD8130 G = +5 VS =±5V 4V p-p CL = 10pF VIN 2V p-p VOUT 1V p-p 1.00V 5.00ns 02464-090 1.00V 10.0ns 02464-093 Figure 89. AD8130 Transient Response with +3 V Common-Mode Input Figure 92. AD8130 Transient Response vs. Output Amplitude VOUT = 8V p-p G = +5 VS =±5V CL = 10pF VOUT VIN 1.00V 5.00ns 02464-091 2.00V 10.0ns 02464-094 Figure 90. AD8130 Transient Response with −3 V Common-Mode Input Figure 93. AD8130 Transient Response, VOUT = 8 V p-p, G = +5, VS = ±5 V VOUT = 10V p-p GVS = = +±212V VOUT = 20V p-p GVS = = +±512V CL = 10pF 2.50V 5.00ns 02464-092 5.00V 10.0ns 02464-095 Figure 91. AD8130 Transient Response, VOUT = 10 V p-p, G = +2, VS = ±12 V Figure 94. AD8130 Transient Response, VOUT = 20 V p-p, G = +5, VS = ±12 V Rev. C | Page 25 of 40

AD8129/AD8130 AD8129 TRANSIENT RESPONSE CHARACTERISTICS G = +10, R = 2 kΩ, R = 221 Ω, R = 1 kΩ, C = 1 pF, V = ±5 V, T = 25°C, unless otherwise noted. F G L L S A VS =±2.5V VOUT = 1V p-p VS =±5V VOUT = 0.4V p-p VS =±2.5V VS =±12V 250mV 5.00ns 02464-096 100mV 5.00ns 02464-099 Figure 95. AD8129 Transient Response, VS = ±2.5 V, VOUT = 1 V p-p Figure 98. AD8129 Transient Response vs. Supply, VOUT = 0.4 V p-p VS =±5V VOUT = 1V p-p VS =±5V CVOL U=T 5 =p F1V p-p VS =±2.5V VS =±12V 250mV 5.00ns 02464-097 250mV 5.00ns 02464-100 Figure 96. AD8129 Transient Response, VS = ±5 V, VOUT = 1 V p-p Figure 99. AD8129 Transient Response vs. Supply, VOUT = 1 V p-p, CL = 5 pF VS =±12V VOUT = 1V p-p VS =±2.5V CVOL U=T 5 =p F2V p-p VS =±5V VS =±12V 250mV 5.00ns 02464-098 250mV 5.00ns 02464-101 Figure 97. AD8129 Transient Response, VS = ±12 V, VOUT = 1 V p-p Figure 100. AD8129 Transient Response vs. Supply, VOUT = 2 V p-p, CL = 5 pF Rev. C | Page 26 of 40

AD8129/AD8130 CL = 5pF VOUT = 0.4V p-p VOUT = 1V p-p GCL = = + 2200pF CL = 10pF CL = 2pF 100mV 5.00ns 02464-102 250mV 5.00ns 02464-105 Figure 101 Transient Response vs. Load Capacitance, VOUT = 0.4 V p-p Figure 104. AD8129 Transient Response, VOUT = 1 V p-p, VS = ±2.5 V to ±12 V VOUT = 2V p-p G = +20 VO = 2V p-p CL = 20pF VO = 1V p-p VO = 0.5V p-p 500mV 5.00ns 02464-103 500mV 5.00ns 02464-106 Figure 102. Transient Response vs. Output Amplitude, Figure 105. AD8129 Transient Response, VOUT = 2 V p-p, VS = ±5 V VOUT = 0.5 V p-p, 1 V p-p, 2 V p-p VOUT = 8V p-p G = +20 VO = 4V p-p CL = 20pF VO = 2V p-p VO = 1V p-p 1.00V 5.00ns 02464-104 2.00V 5.00ns 02464-107 Figure 103. Transient Response vs. Output Amplitude, Figure 106. AD8129 Transient Response, VOUT = 8 V p-p, VS = ±5 V VOUT = 1 V p-p, 2 V p-p, 4 V p-p Rev. C | Page 27 of 40

AD8129/AD8130 G = +50 VIN 4V p-p CVSL == ±250VpF VOUT 2V p-p 1V p-p 1.00V 5.00ns 02464-108 1.00V 12.5ns 02464-111 Figure 107. AD8129 Transient Response Figure 110. AD8129 Transient Response vs. Output Amplitude, with +3.5 V Common-Mode Input VOUT = 1 V p-p, 2 V p-p, 4 V p-p VOUT = 8V p-p G = +50 VS =±5V CL = 20pF VOUT VIN 02464-109 2.00V 12.5ns 02464-112 Figure 108. AD8129 Transient Response Figure 111. AD8129 Transient Response, VOUT = 8 V p-p, G = +50, VS = ±5 V with −3.5 V Common-Mode Input VOUT = 10V p-p GVS = = +±2102V VOUT = 20V p-p GVS = = +±5102V CL = 20pF CL = 10pF 2.50V 5.00ns 02464-110 5.00V 12.5ns 02464-113 Figure 109. AD8129 Transient Response, VOUT = 10 V p-p, G = +20 Figure 112. AD8129 Transient Response, VOUT = 20 V p-p, G = +50, VS = ±12 V Rev. C | Page 28 of 40

AD8129/AD8130 23 G = +1 G = +1 VS =±5V VS =±5V RL = 1kΩ V) A) 20 %/DI Y CURRENT (m 17 NEARITY (0.005 UPPL ONLI S 14 N N AI G 11 02464-114 –1.0 –0.8 –0.6 –0.4 –0.2 0 0.2 0.4 0.6 0.8 1.002464-117 –5 –4 –3 –2 –1 0 1 2 3 4 5 DIFFERENTIAL INPUT (V) OUTPUT VOLTAGE (V) Figure 113. AD8130 DC Power Supply Current vs. Differential Input Voltage Figure 116. AD8130 Gain Nonlinearity, VOUT = 2 V p-p 37 G = +1 G = +1 VS =±10V VRSL == ±15kVΩ V) mA)31 08%/DI NT ( Y (0. E T PPLY CURR25 ONLINEARI U N S19 N AI 13 02464-115 G–2.5 –2.0 –1.5 –1.0 –0.5 0 0.5 1.0 1.5 2.0 2.502464-118 –1.0 –0.8 –0.6 –0.4 –0.2 0 0.2 0.4 0.6 0.8 1.0 DIFFERENTIAL INPUT (V) OUTPUT VOLTAGE (V) Figure 114. AD8129 DC Power Supply Current vs. Differential Input Voltage Figure 117. AD8130 Gain Nonlinearity, VOUT = 5 V p-p 3.0 4 VS =±5V AD8130 3 2.0 VOUT = 100mV AC @ 1kHz 2 V) T ( 1.0 PU AD8129 1 TIAL IN 0 AD8129 V) (OUT 0 N V RE –1 FE–1.0 F DI –2 AD8130 –2.0 –3.0 02464-116 ––43–5 –4 –3 –2 –1 0 1 2 3 4 502464-119 –50 –35 –20 –5 10 25 40 55 70 85 100 TEMPERATURE(°C) DIFFERENTIAL INPUT (V) Figure 115. AD8129/AD8130 Input Differential Voltage Range vs. Figure 118. AD8130 Differential Input Clipping Level Temperature, 1% Gain Compression Rev. C | Page 29 of 40

AD8129/AD8130 G = +10 15 VS =±5V RL = 1kΩ V) 14 DI %/ A) TY (0.005 RENT (m13 NEARI Y CUR12 ONLI UPPL11 N S N AI G–1.0 –0.8 –0.6 –0.4 –0.2 0 0.2 0.4 0.6 0.8 1.002464-120 190 0 5 10 15 20 25 3002464-123 OUTPUT VOLTAGE (V) TOTAL SUPPLY VOLTAGE (V) Figure 119. AD8129 Gain Nonlinearity, VOUT = 2 V p-p Figure 122. Quiescent Power Supply Current vs. Total Supply Voltage G = +10 17 VS =±12V 16 RL = 1kΩ V) 15 %/DI A)14 VS =±12 2 m NONLINEARITY (0. UPPLY CURRENT (11113201 VS =±5VS =±2.5 N S GAI 9 –5 –4 –3 –2 –1 0 1 2 3 4 5 02464-121 87 02464-124 –50 –35 –20 –5 10 25 40 55 70 85 100 115125 OUTPUT VOLTAGE (V) TEMPERATURE (°C) Figure 120. AD8129 Gain Nonlinearity, VOUT = 10 V p-p Figure 123. Quiescent Power Supply Current vs. Temperature 8 0.60 40 VS =±10V 6 4 A) nA) AGE (V) 2 RENT (μ0.45 IOS IB 30RRENT ( T R U PUT VOL–02 BIAS CU FFSET C OUT–4 NPUT 0.30 20PUT O I N I ––86–1.0 –0.8 –0.6 –0D.4IFF–E0R.2ENTI0AL IN0P.U2T (V0).4 0.6 0.8 1.002464-122 0.15–50 –35 –20 –5 TE1M0PERA25TURE4 0(°C) 55 70 85 10010 02464-125 Figure 121. AD8129 Differential Input Clipping Level Figure 124. Input Bias Current and Input Offset Current vs. Temperature Rev. C | Page 30 of 40

AD8129/AD8130 4.00 4.0 3.75 VS = 5V 3.50 AD8130 AD8129 3.5 V) 3.25 SOURCING MODE ( 32..0705 VS = 5V AGE (V)3.0 MON 2.50 VAOUCT A =T 1 10k0HmzV VOLT +100°C –40°C +25°C COM 2.25 PUT 2.0 UT 2.00 UT P O N 1.75 SINKING I 1.5 1.50 AD8129 AD8130 11..2050 02464-126 1.0 VAOUCT A =T 1 10k0HmzV 02464-129 –50 –35 –20 –5 10 25 40 55 70 85 100 0 5 10 15 20 25 30 35 40 TEMPERATURE (°C) OUTPUT CURRENT (mA) Figure 125. Common-Mode Voltage Range vs. Temperature, Figure 128. Output Voltage Range vs. Output Current, Typical 1% Gain Compression Typical 1% Gain Compression 4.00 4.0 VS =±5V 3.75 AD8130 3.50 3.5 V) MODE ( 33..2050 VS =±5V AD8129 GE (V) 3.0 ON 2.75 VOUT = 100mV LTA +100°C –40°C +25°C M AC AT 1kHz O M V CO –3.00 UT –3.0 NPUT –3.25 AD8129 OUTP I –3.50 AD8130 –3.5 ––34..7050 02464-127 –4.0 VAOUCT A =T 1 10k0HmzV 02464-130 –50 –35 –20 –5 10 25 40 55 70 85 100 0 5 10 15 20 25 30 35 40 TEMPERATURE (°C) OUTPUT CURRENT (mA) Figure 126. Common-Mode Voltage Range vs. Temperature, Figure 129. Output Voltage Range vs. Output Current, Typical 1% Gain Compression Typical 1% Gain Compression 11.0 11 VS =±12V 10.5 AD8130 10.0 10 VS =±12V T COMMON MODE (V) ––99998.....05505 VAOUCT A =T 1 10k0AHmDzV8129 UTPUT VOLTAGE (V) –99 +100°C –40°C +25°C U O P IN–10.0 AD8129 AD8130 –10 ––1101..50 02464-128 –11 02464-131 –50 –35 –20 –5 10 25 40 55 70 85 100 0 5 10 15 20 25 30 35 40 TEMPERATURE (°C) OUTPUT CURRENT (mA) Figure 127. Common-Mode Voltage Range vs. Temperature, Figure 130. Output Voltage Range vs. Output Current, Typical 1% Gain Compression Typical 1% Gain Compression Rev. C | Page 31 of 40

AD8129/AD8130 THEORY OF OPERATION The AD8129/AD8130 use an architecture called active feedback, Therefore, the input dynamic ranges are limited to about which differs from that of conventional op amps. The most 2.5 V for the AD8130 and 0.5 V for the AD8129 (see the obvious differentiating feature is the presence of two separate AD8129/AD8130 Specifications section for more detail). For pairs of differential inputs compared with a conventional op this and other reasons, it is not recommended to reverse the amp’s single pair. Typically, for the active feedback architecture, input and feedback stages of the AD8129/AD8130, even though one of these input pairs is driven by a differential input signal, some apparently normal functionality may be observed under while the other is used for the feedback. This active stage in the some conditions. A few simple circuits can illustrate how the feedback path is where the term active feedback is derived. active feedback architecture of the AD8129/AD8130 operates. The active feedback architecture offers several advantages over a OP AMP CONFIGURATION conventional op amp in many types of applications. Among these If only one of the input stages of the AD8129/AD8130 is used, it are excellent common-mode rejection, wide input common-mode functions very much like a conventional op amp (see Figure 131). range, and a pair of inputs that are high impedance and completely Classical inverting and noninverting op amps circuits can be balanced in a typical application. In addition, while an external created, and the basic governing equations are the same as for a feedback network establishes the gain response as in a conventional conventional op amp. The unused input pins form the second op amp, its separate path makes it completely independent of input and should be shorted together and tied to ground or a the signal input. This eliminates any interaction between the midsupply voltage when they are not used. feedback and input circuits, which traditionally causes problems with CMRR in conventional differential-input op amp circuits. +V Another advantage is the ability to change the polarity of the 0.1μF 10μF gain merely by switching the differential inputs. A high input- 3 7 impedance inverting amplifier can be made. Besides a high 1 + PD +VS input impedance, a unity-gain inverter with the AD8130 has 8 6 VOUT a noise gain of unity. This produces lower output noise and VIN 4 + higher bandwidth than op amps that have noise gain equal 5 –VS 2 to 2 for a unity-gain inverter. RF The two differential input stages of the AD8129/AD8130 are RG ecaocnhv etrrat nthsceo rnedspuecctatnivcee dsitfafgeerse nthtiaatl airnep wute lvl omltaatgcehse tdo. Tinhteesren astl ages –V 0.1μF 10μF 02464-132 NOTES currents. The currents are then summed and converted to a 1. THIS CIRCUIT IS PROVIDED TO DEMONSTRATE DEVICE OPERATION. IT IS NOT RECOMMENDED voltage, which is buffered to drive the output. The compensation TO USE THIS CIRCUIT IN PLACE OF AN OP AMP. capacitor is in the summing circuit. Figure 131. With Both Inputs Grounded, the Feedback Stage Functions like an Op Amp: VOUT = VIN (1 + RF/RG). When the feedback path is closed around the part, the output With the unused pair of inputs shorted, there is no differential drives the feedback input to the voltage that causes the internal voltage between them. This dictates that the differential input currents to sum to 0. This occurs when the two differential voltage of the used inputs is also 0 for closed-loop applications. inputs are equal and opposite; that is, their algebraic sum is 0. Because this is the governing principle of conventional op amp In a closed-loop application, a conventional op amp has its circuits, an active feedback amplifier can function as a differential input voltage driven to near 0 under nontransient conventional op amp under these conditions. conditions. The AD8129/AD8130 generally has differential Note that this circuit is presented only for illustration purposes input voltages at each of its input pairs, even under equilibrium to show the similarities of the active feedback architecture conditions. As a practical consideration, it is necessary to limit functionality to conventional op amp functionality. If it is the differential input voltage internally with a clamp circuit. desired to design a circuit that can be created from a conven- tional op amp, it is recommended to choose a conventional op amp with specifications that are better suited to that application. These op amp principles are the basis for offsetting the output, as described in the Output Offset/Level Translator section. Rev. C | Page 32 of 40

AD8129/AD8130 APPLICATIONS BASIC GAIN CIRCUITS TWISTED-PAIR CABLE, COMPOSITE VIDEO RECEIVER WITH EQUALIZATION USING AN AD8130 The gain of the AD8129/AD8130 can be set with a pair of feedback resistors. The basic configuration is shown in Figure 132. The AD8130 has excellent common-mode rejection at its The gain equation is the same as that of a conventional op amp: inputs. This makes it an ideal candidate for a receiver for signals G = 1 + RF/RG. For unity-gain applications using the AD8130, that are transmitted over long distances on twisted-pair cables. RF can be set to 0 (short circuit), and RG can be removed (see Category 5 cables are very common in office settings and are Figure 133). The AD8129 is compensated to operate at gains of extensively used for data transmission. These cables can also be 10 and higher; therefore, shorting the feedback path to obtain used for the analog transmission of signals such as video. unity gain causes oscillation. These long cables pick up noise from the environment they pass +V through. This noise does not favor one conductor over another and therefore is a common-mode signal. A receiver that rejects AD8129/ AD8130 0.1μF 10μF the common-mode signal on the cable can greatly enhance the 3 7 signal-to-noise ratio performance of the link. VIN 1 + PD +VS 8 The AD8130 is also very easy to use as a differential receiver, 6 VOUT 4 + because the differential inputs and the feedback inputs are 5 –VS entirely separate. This means that there is no interaction 2 RF between the feedback network and the termination network, as there would be in conventional op amp types of receivers. RG –V 0.1μF 10μF 02464-133 Aofn tohteh seirg insasul aet w loitnhg leorn dgi sctaabnlceess i.s A thttaetn tuhaetrioe nis i ms aolsroe aat tfeunnucatitoionn Figure 132. Basic Gain Circuit: VOUT = VIN (1 + RF/RG) of frequency; it increases to roughly the square root of frequency. +V For good fidelity of video circuits, the overall frequency AD8130 response of the transmission channel should be flat vs. 0.1μF 10μF frequency. Because the cable attenuates the high frequencies, a 3 7 VIN 1 + PD +VS frequency-selective boost circuit can be used to undo this effect. 8 These circuits are called equalizers. 6 VOUT 4 + 5 –VS An equalizer uses frequency-dependent elements (Ls and Cs) to 2 create a frequency response that is the opposite of the rest of the channel’s response to create an overall flat response. There are many ways to create such circuits, but a common technique is to –V 0.1μF 10μF 02464-134 popu ta tmhep fcrierqcuueitn. cTyh-ese AleDct8iv1e3 0e lienm peanrttsi cinu ltahr em feaekdebs atchkis p eaatshie orf an Figure 133. An AD8130 with Unity Gain than other circuits, because, once again, the feedback path is completely independent of the input path and there is no The input signal can be applied either differentially or in a interaction. single-ended fashion—all that matters is the magnitude of the differential signal between the two inputs. For single-ended The circuit in Figure 134 was developed as a receiver/equalizer input applications, applying the signal to the +IN with −IN for transmitting composite video over 300 meters of Category 5 grounded creates a noninverting gain, while reversing these cable. This cable has an attenuation of approximately 20 dB at connections creates an inverting gain. Because the two inputs 10 MHz for 300 meters. At 100 MHz, the attenuation is are high impedance and matched, both of these conditions approximately 60 dB (see Figure 135). provide the same high input impedance. Thus, an advantage of the active feedback architecture is the ability to make a high input impedance inverting op amp. If conventional op amps are used, a high impedance buffer followed by an inverting stage is needed. This requires two op amps. Rev. C | Page 33 of 40

AD8129/AD8130 +V It is difficult to calculate the exact component values via strictly mathematical means, because the equations for the cable AD8130 0.1μF 10μF attenuation are approximate and have functions that are not 3 7 simply related to the responses of RC networks. The method VIN 100Ω 1 + PD +VS used in this design was to approximate the required response 8 6 VOUT via graphical means from the frequency response and then 4 + 5 –VS select components that would approximate this response. The 2 circuit was then built, measured, and finally adjusted to obtain R1 RF an acceptable response—in this case, flat to 9 MHz to within 100Ω RG 1kΩ 0.1μF 10μF approximately 1 dB (see Figure 137). 200CpF1 499Ω –V 02464-135 20 Figure 134. An Equalizer Circuit for Composite Video Transmissions 10 over 300 Meters of Category-5 Cable 0 20 –10 10 E S –20 N 0 O SP –30 –10 RE E O –40 NS –20 I/ O –50 P S –30 RE –60 O –40 I/ –70 –50 –80 ––6700 10k 100k FREQUE1MNCY (Hz) 10M 100M02464-138 Figure 137. Combined Response of Cable Plus Equalizer –80 10k 100k FREQUE1MNCY (Hz) 10M 100M02464-136 OUTPUT OFFSET/LEVEL TRANSLATOR Figure 135. Transmission Response of 300 Meters of Category-5 Cable The circuit in Figure 133 has the reference input (Pin 4) tied to ground, which produces a ground-referenced output signal. If it The feedback network is between Pin 6 and Pin 5 and from is desired to offset the output voltage from ground, the REF Pin 5 to ground. C1 and RF create a corner frequency of about input can be used (see Figure 138). The level VOFFSET appears at 800 kHz. The gain increases to provide about 15 dB of boost the output with unity gain. at 8 MHz. The response of this circuit is shown in Figure 136. +V 20 10 AD8130 0.1μF 10μF 0 3 7 ONSE ––1200 VOFFSVEITN 481 ++ PD +VS 6 VOUT = VIN+VOFFSET SP –30 5 –VS E R 2 O –40 I/ –50 ––6700 –V 0.1μF 10μF 02464-139 Figure 138. The Voltage Applied to Pin 4 to the Unity-Gain Output Voltage –8010k 100k FREQUE1NMCY (Hz) 10M 100M02464-137 If the circuit has a gain higPhroedru tcheda nb yu VnINi ty, the gain must be Figure 136. Frequency Response of Equalizer Circuit factored in. If R is connected to ground, the voltage applied to G REF is multiplied by the gain of the circuit and appears at the output—just like a noninverting conventional op amp. This situation is not always desirable; the user may want V to OFFSET appear at the output with unity gain. Rev. C | Page 34 of 40

AD8129/AD8130 One way to accomplish this is to drive both REF and R with +V G the desired offset signal (see Figure 139). Superposition can be AD8130 used to solve this circuit. First, break the connection between 0.1μF 10μF VOFFSET and RG. With RG grounded, the gain from Pin 4 to VOUT 3 7 is 1 + RF/RG. With Pin 4 grounded, the gain though RG to VOUT VIN 1 + PD +VS 8 is −R/R . The sum of these is 1. If V is delivered from a low impedFanGce source, this works fine. HRoEwF ever, if the delivered 4 + 6 VOUT 5 –VS offset voltage is derived from a high impedance source, such as 2 a voltage divider, its impedance affects the gain equation. This makes the circuit more complicated because it creates an interaction between the gain and offset voltage. –V 0.1μF 10μF 02464-142 +V Figure 141. Gain-of-2 Connections with No Resistors AD8129/ SUMMER AD8130 0.1μF 10μF 3 7 A general summing circuit can be made by the previous VIN 1 + PD +VS technique. A unity-gain configured AD8130 has one signal 8 6 VOUT = applied to +IN, while the other signal is applied to REF. The VOFFSET 4 + VIN×(1+RF/RG)+VOFFSET output is the sum of the two input signals (see Figure 142). 5 –VS RG 2 +V RF –V 0.1μF 10μF 02464-140 AD8130 3 7 0.1μF 10μF Figure 139. In this Circuit, VOFFSET Appears at the Output with Unity Gain. This V1 1 + PD +VS Circuit Works Well if the VOFFSET Source Impedance Is Low. 8 6 VOUT= V1 + V2 V2 4 + A way around this is to apply the offset voltage to a voltage 5 –VS divider whose attenuation factor matches the gain of the 2 amplifier and then apply this voltage to the high impedance REF input. This circuit first divides the desired offset voltage by the gain, and the amplifier multiplies it back up to unity (see –V 0.1μF 10μF 02464-143 Figure 140). Figure 142. A Summing Circuit that is Noninverting with High Input Impedance +V This circuit offers several advantages over a conventional op AD8129/ AD8130 amp inverting summing circuit. First, the inputs are both high 0.1μF 10μF 3 7 impedance and the circuit is noninverting. It would require VIN 1 + PD +VS significant additional circuitry to make an op amp summing 8 VOFFSET RF 4 + 6 VVOINU×T (=1+RF/RG)+VOFFSET circuit that has high input impedance and is noninverting. RG 5 –VS Another advantage is that the AD8130 circuit still preserves the 2 full bandwidth of the part. In a conventional summing circuit, RG RF the noise gain is increased for each additional input, so the –V 0.1μF 10μF 02464-141 bfoaunrd swigidntahls r ceaspno bnes esu dmecmreeads ebsy a acpcpolrydiningg tlyh.e Bmy ttoh itsw toec AhDni8q1u3e0, s Figure 140. Adding an Attenuator at the Offset Input Causes It to Appear at and then summing the two outputs by a third AD8130. the Output with Unity Gain. CABLE-TAP AMPLIFIER RESISTORLESS GAIN OF 2 It is often desirable to have a video signal drive several pieces of The voltage applied to the REF input (Pin 4) can also be a high equipment. However, the cable should only be terminated once at bandwidth signal. If a unity-gain AD8130 has both +IN and its endpoint; therefore, it is not appropriate to have a termination REF driven with the same signal, there is unity gain from V IN at each device. A loop-through connection allows a device to tap and unity gain from V . Thus, the circuit has a gain of 2 and REF the video signal while not disturbing it by any excessive loading. requires no resistors (see Figure 141). Rev. C | Page 35 of 40

AD8129/AD8130 Such a connection, also referred to as a cable-tap amplifier, can EXTREME OPERATING CONDITIONS be simply made with an AD8130 (see Figure 143). The circuit is The AD8129/AD8130 are designed to provide high configured with unity gain, and if no output offset is desired, performance over a wide range of supply voltages. However, the REF pin is grounded. The negative differential input is there are some extremes of operating conditions that have connected directly to the shield of the cable (or an associated been observed to produce suboptimal results. One of these connector) at the point at which it wants to be tapped. conditions occurs when the AD8130 is operated at unity gain +V with low supply voltage—less than approximately ±4 V. AD8130 At unity gain, the output drives FB directly. With supplies of 75Ω 0.1μF 10μF ±V less than approximately ±4 V at unity gain, the output can S 3 7 drive FB’s voltage too close to the rail for the circuit to stay 1 + PD +VS 8 properly biased. This can lead to a parasitic oscillation. 6 VOUT 4 + A way to prevent this is to limit the input signal swing with 5 –VS 2 clamp diodes. Common silicon-junction signal diodes like the 1N4148 have a forward bias of approximately 0.7 V when about VIDEO IN 1 mA of current flows through them. Two series pairs of such 75Ω –V 0.1μF 10μF 02464-144 dbeio udseesd c toon cnleacmtepd t ahnet iinpparuatl lseigl nacarlo asnsd t hper edvieffnetr ethnitsia clo inndpuittiso nca. nIt Figure 143. The AD8130 Can Tap the Video Signal at Any Point Along the should be noted that the REF input can also shift the output Cable Without Loading the Signal. signal; therefore, this technique only works when REF is at The center conductor connects to the positive differential input ground or close to it (see Figure 145). of the AD8130. The amplitude of the video signal at this point is +V unity, because it is between the two termination resistors. The AD8130 provides a high impedance to this signal so that the AD8130 signal is not disturbed. A buffered unity-gain version of the 0.1μF 10μF video signal appears at the output. VIN 3 7 1N4148 1 + PD +VS POWER-DOWN 8 6 VOUT The AD8129/AD8130 have a power-down pin that can be used VIN 54 + –VS to lower the quiescent current when the amplifier is not being 2 used. A logic low level on the PD pin causes the part to power down. Because there is no ground pin on the AD8129/AD8130, there is no logic reference to interface to standard logic levels. –V 0.1μF 10μF 02464-146 For this reason, the reference level for the PD input is VS. If Figure 145. Clamping Diodes at the Input Limits the Input Swing Amplitude the AD8129/AD8130 are run with V = 5 V, there is direct S compatibility with logic families. However, if V is higher than S this, a level-shift circuit is needed to interface to conventional logic levels. A simple level-shifting circuit that is compatible with common logic families is presented in Figure 144. +VS 7 1kΩ +VS 3 PD LOW = 4.99kΩ 2N2222 POWER-DOWN OR EQ AADD88112390/ 02464-145 Figure 144. Circuit that Shifts the Logic Level When VS Is Not Equal to Approximately 5 V. Rev. C | Page 36 of 40

AD8129/AD8130 The power dissipation is a function of several operating Another problem can occur with the AD8129 operating conditions, including the supply voltage, the input differential at a supply voltage of greater than or equal to ±12 V. The voltage, the output load, and the signal frequency. architecture causes the supply current to increase as the input differential voltage increases. If the AD8129 differential inputs A basic starting point is to calculate the quiescent power are overdriven too far, excessive current can flow into the device dissipation with no signal and no differential input voltage. and potentially cause permanent damage. This is just the product of the total supply voltage and the quiescent operating current. The maximum operating supply A practical means to prevent this from occurring is to clamp the voltage is 26.4 V, and the quiescent current is 13 mA. This inputs differentially with a pair of antiparallel Schottky diodes causes a quiescent power dissipation of 343 mW. For the (see Figure 146). These diodes have a lower forward voltage of MSOP package, the θ specification is 142°C/W. Therefore, approximately 0.4 V. If the differential voltage across the inputs JA the quiescent power causes about a 49°C rise above ambient is restricted to these conditions, no excess current is drawn by in the MSOP package. the AD8129 under these operating conditions. The current consumption is also a function of the differential If the supply voltage is restricted to less than ±11 V, the internal input voltage (see Figure 113 and Figure 114). This current clamping circuit limits the differential voltage and excessive should be added onto the quiescent current and then multiplied supply current is not drawn. The external clamp circuit is not by the total supply voltage to calculate the power. needed. +V The AD8129/AD8130 can directly drive loads of as low as 100 Ω, such as a terminated 50 Ω cable. The worst-case power AD8129 dissipation in the output stage occurs when the output is at 0.1μF 10μF VIN 3 3 7 midsupply. As an example, for a 12 V supply with the output AGILENT 1 + PD +VS driving a 250 Ω load to ground, the maximum power dissipation HSMS 2822 8 in the output occurs when the output voltage is 6 V. The load VIN 1 2 4 + 6 VOUT current is 6 V/250 Ω = 24 mA. This same current flows through 5 –VS the output across a 6 V drop from V. It dissipates 144 mW. For 2 S the 8-lead MSOP package, this causes a temperature rise of 20°C above ambient. Although this is a worst-case number, it is –V 0.1μF 10μF 02464-147 appopwaerre ndti stshipata ttihoins .c an be a considerable additional amount of Figure 146. Schottky Diodes Across the Inputs Limits the Input Differential Voltage Several changes can be made to alleviate this. One is to use the standard 8-lead SOIC package. This lowers the thermal impedance In both circuits, the input series resistors function to limit the to 121°C/W, which is a 15% improvement. Another is to use a current through the diodes when they are forward biased. As a lower supply voltage unless absolutely necessary. practical matter, these resistors must be matched so that the CMRR is preserved at high frequencies. These resistors have Finally, do not use the AD8129/AD8130 when it is operating on minimal effect on the CMRR at low frequency. high supply voltages to directly drive a heavy load. It is best to use a second op amp after the output stage. Some of the gain POWER DISSIPATION can be shifted to this stage so that the signal swing at the output The AD8129/AD8130 can operate with supply voltages from of the AD8129/AD8130 is not too large. +5 V to ±12 V. The major reason for such a wide supply range is to provide a wide input common-mode range for systems that can require this. This would be encountered when significant common-mode noise couples into the input path. For applications that do not require a wide dynamic range for the input or output, it is recommended to operate with lower supply voltages. The AD8129/AD8130 is also available in a very small 8-lead MSOP package. This package has higher thermal impedance than larger packages and operates at a higher temperature with the same amount of power dissipation. Certain operating conditions that are within the specifications range of the parts can cause excess power dissipation. Caution should be exercised. Rev. C | Page 37 of 40

AD8129/AD8130 LAYOUT, GROUNDING, AND BYPASSING The AD8129/AD8130 are very high speed parts that can be sensitive to the PCB environment in which they operate. Realizing their superior specifications requires attention to various details of standard high speed PCB design practice. The first requirement is for a good solid ground plane that covers as much of the board area around the AD8129/AD8130 as possible. The only exception to this is that the ground plane around the FB pin should be kept a few millimeters away, and the ground should be removed from the inner layers and the opposite side of the board under this pin. This minimizes the stray capacitance on this node and helps preserve the gain flatness vs. frequency. The power supply pins should be bypassed as close as possible to the device to the nearby ground plane. Good high frequency ceramic chip capacitors should be used, and the bypassing should be done with a capacitance value of 0.01 μF to 0.1 μF for each supply. Farther away, low frequency bypassing should be provided with 10 μF tantalum capacitors from each supply to ground. The signal routing should be short and direct to avoid parasitic effects. Where possible, signals should be run over ground planes to avoid radiating or to avoid being susceptible to other radiation sources. Rev. C | Page 38 of 40

AD8129/AD8130 OUTLINE DIMENSIONS 5.00 (0.1968) 4.80 (0.1890) 8 5 4.00 (0.1574) 6.20 (0.2440) 3.80 (0.1497) 1 4 5.80 (0.2284) 1.27 (0.0500) 0.50 (0.0196) BSC 1.75 (0.0688) 0.25 (0.0099)× 45° 0.25 (0.0098) 1.35 (0.0532) 0.10 (0.0040) 0.51 (0.0201) 8° COPL0A.1N0ARITY SEPALTAINNGE 0.31 (0.0122) 00..2157 ((00..00009687)) 0° 10..2470 ((00..00510507)) COMPLIANT TO JEDEC STANDARDS MS-012-AA CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. Figure 147. 8-Lead Standard Small Outline Package [SOIC] Narrow Body (R-8) Dimensions shown in millimeters and (inches) 3.20 3.00 2.80 8 5 5.15 3.20 4.90 3.00 4.65 2.80 1 4 PIN 1 0.65 BSC 0.95 0.85 1.10 MAX 0.75 0.80 0.15 0.38 0.23 8° 0.60 0.00 0.22 0.08 0° 0.40 COPLANARITY SEATING 0.10 PLANE COMPLIANT TO JEDEC STANDARDS MO-187-AA Figure 148. 8-Lead Mini Small Outline Package [MSOP] (RM-8) Dimensions shown in millimeters Rev. C | Page 39 of 40

AD8129/AD8130 ORDERING GUIDE Model Temperature Range1 Package Description Package Option Branding AD8129AR −40°C to +85°C 8-Lead SOIC R-8 AD8129AR-REEL −40°C to +85°C 8-Lead SOIC, 13" Tape and Reel R-8 AD8129AR-REEL7 −40°C to +85°C 8-Lead SOIC, 7" Tape and Reel R-8 AD8129ARZ2 −40°C to +85°C 8-Lead SOIC R-8 AD8129ARZ-REEL2 −40°C to +85°C 8-Lead SOIC, 13" Tape and Reel R-8 AD8129ARZ-REEL72 −40°C to +85°C 8-Lead SOIC, 7" Tape and Reel R-8 AD8129ARM −40°C to +85°C 8-Lead MSOP RM-8 HQA AD8129ARM-REEL −40°C to +85°C 8-Lead MSOP, 13" Tape and Reel RM-8 HQA AD8129ARM-REEL7 −40°C to +85°C 8-Lead MSOP, 7" Tape and Reel RM-8 HQA AD8129ARMZ2 −40°C to +85°C 8-Lead MSOP RM-8 HQA# AD8129ARMZ-REEL2 −40°C to +85°C 8-Lead MSOP, 13" Tape and Reel RM-8 HQA# AD8129ARMZ-REEL72 −40°C to +85°C 8-Lead MSOP, 7" Tape and Reel RM-8 HQA# AD8130AR −40°C to +85°C 8-Lead SOIC R-8 AD8130AR-REEL −40°C to +85°C 8-Lead SOIC, 13" Tape and Reel R-8 AD8130AR-REEL7 −40°C to +85°C 8-Lead SOIC, 7" Tape and Reel R-8 AD8130ARZ2 −40°C to +85°C 8-Lead SOIC R-8 AD8130ARZ-REEL2 −40°C to +85°C 8-Lead SOIC, 13" Tape and Reel R-8 AD8130ARZ-REEL72 −40°C to +85°C 8-Lead SOIC, 7" Tape and Reel R-8 AD8130ARM −40°C to +85°C 8-Lead MSOP RM-8 HPA AD8130ARM-REEL −40°C to +85°C 8-Lead MSOP, 13" Tape and Reel RM-8 HPA AD8130ARM-REEL7 −40°C to +85°C 8-Lead MSOP, 7" Tape and Reel RM-8 HPA AD8130ARMZ2 −40°C to +85°C 8-Lead MSOP RM-8 HPA# AD8130ARMZ-REEL2 −40°C to +85°C 8-Lead MSOP, 13" Tape and Reel RM-8 HPA# AD8130ARMZ-REEL72 −40°C to +85°C 8-Lead MSOP, 7" Tape and Reel RM-8 HPA# 1 Operating temperature range for ±5 V or +5 V operation is −40°C to +125°C. 2 Z = Pb-free part; # indicates lead-free, may be top or bottom marked. © 2005 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. C02464–0–11/05(C) Rev. C | Page 40 of 40

Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: A nalog Devices Inc.: AD8129AR-EBZ AD8129ARM-EBZ AD8129ARMZ AD8129ARZ AD8130AR AD8130AR-EBZ AD8130ARM AD8130ARM-EBZ AD8130ARMZ AD8130ARZ AD8130ARMZ-REEL7 AD8130ARZ-REEL7 AD8129ARMZ-REEL AD8129ARMZ-REEL7 AD8129ARZ-REEL AD8129ARZ-REEL7 AD8130ARMZ-REEL AD8130AR-REEL7 AD8130ARZ-REEL