Ultralow Distortion, High Speed, 0.95 nV/√Hz Voltage Noise Op Amp Data Sheet AD8099 FEATURES CONNECTION DIAGRAMS Ultralow noise: 0.95 nV/√Hz, 2.6 pA/√Hz AD8099 TOP VIEW Ultralow distortion (Not to Scale) 2nd harmonic R = 1 kΩ , G = +2 L DISABLE 1 8 +VS −92 dB at 10 MHz FEEDDBACK 2 7 VOUT 3rd harmonic R = 1 kΩ , G = +2 L –IN 3 6 CC −105 dB at 10 MHz +IN 4 5 –VS HiG−gh3a idsnpB be baeandnd dwwididthth p roduct (GBWP): 3.8 GHz N1.OSTTOOE LTSDHEER G TRHOEU ENXDP POLSAENDE P.ADDLE 04511-0-001 Figure 1. 8-Lead LFCSP (CP-8-13) 700 MHz (G = +2) 550 MHz (G = +10) AD8099 TOP VIEW Slew rate (Not to Scale) 475 V/µs (G = +2) FEEDBACK 1 8 DISABLE 1350 V/µs (G = +10) –IN 2 7 +VS New pinout +IN 3 6 VOUT Custom external compensation, gain range –1, +2 to +10 –VS 4 5 CC SOuffpspelty v coultraregnet: :0 1.55 mmVA m ax N1.OSTTOOE LTSDHEER G TRHOEU ENXDP POLSAENDE P.ADDLE 04511-0-002 Figure 2. 8-Lead SOIC-EP (RD-8-1) Wide supply voltage range: 5 V to 12 V The AD8099 drives 100 Ω loads at breakthrough performance APPLICATIONS levels with only 15 mA of supply current. With the wide supply Preamplifiers voltage range (5 V to 12 V), low offset voltage (0.1 mV typ), wide Receivers bandwidth (700 MHz for G = +2), and a GBWP up to 3.8 GHz, Instrumentation the AD8099 is designed to work in a wide variety of applications. Filters The AD8099 is available in a 3 mm × 3 mm lead frame chip scale Intermediate frequency (IF) and baseband amplifiers package (LFCSP) with a new pinout that is specifically optimized Analog-to-digital drivers for high performance, high speed amplifiers. The new LFCSP and Digital-to-analog converter (DAC) buffers pinout enable the breakthrough performance that previously was Optical electronics not achievable with amplifiers. The AD8099 is rated to work GENERAL DESCRIPTION over the extended industrial temperature range, −40°C to +125°C. The AD8099 is an ultralow noise (0.95 nV/√Hz) and distortion –40 G = +2 (–92 dBc at 10 MHz) voltage feedback op amp, the combination –50 VVOS U=T± =5 V2V p-p of which makes it ideal for 16- and 18-bit systems. The AD8099 RL = 1kΩ features a new, highly linear, low noise input stage that increases Bc) –60 d the full power bandwidth (FPBW) at low gains with high slew N ( –70 O rates. The Analog Devices, Inc., proprietary next generation TI R –80 O extra fast complimentary bipolar (XFCB) process enables such T high performance amplifiers with relatively low power. C DIS –90 NI–100 The AD8099 features external compensation, which lets the user MO set the gain bandwidth product. External compensation allows AR–110 H gains from +2 to +10 with minimal trade-off in bandwidth. The –120 SOLID LINE– SECOND HARMONIC AgwiviDtihn8og0u 9tth9 t ear dalsdeosi infgegna eoturf frf lebesax anibndi lweitxiydt rttoehm u oserel ydt hihseit goehnrt tisiorleenw d. Tyrnahateem AoicfD 1r83a0n590g9e V /µs, –1300.1 F1R.0EQDUOENTTCEYD ( MLIHNzE)– T1H0IR.0D HARMONIC 04511-A-013 Figure 3. Harmonic Distortion vs. Frequency and Gain (SOIC) settles to 0.1% in 18 ns and recovers from overdrive in 50 ns. Rev. E Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Tel: 781.329.4700 ©2003–2016 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com

AD8099 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Using the AD8099 ...................................................................... 16 Applications ....................................................................................... 1 Circuit Components .................................................................. 16 General Description ......................................................................... 1 Recommended Values ............................................................... 17 Connection Diagrams ...................................................................... 1 Circuit Configurations .............................................................. 17 Revision History ............................................................................... 2 Performance vs. Component Values ........................................ 19 Specifications ..................................................................................... 3 Total Output Noise Calculations and Design ......................... 21 Specifications with ±5 V Supply ................................................. 3 Input Bias Current and DC Offset ........................................... 21 Specifications with +5 V Supply ................................................. 4 DISABLE Pin and Input Bias Cancellation ............................. 21 Absolute Maximum Ratings ............................................................ 5 16-Bit ADC Driver ..................................................................... 22 Maximum Power Dissipation ..................................................... 5 Circuit Considerations .............................................................. 23 ESD Caution .................................................................................. 5 Design Tools and Technical Support ....................................... 23 Typical Performance Characteristics ............................................. 6 Outline Dimensions ....................................................................... 24 Theory of Operation ...................................................................... 15 Ordering Guide .......................................................................... 24 Applications Information .............................................................. 16 REVISION HISTORY 7/2016—Rev. D to Rev. E 6/2004—Rev. A to Rev. B Changed CP-8-2 to CP-8-13 ........................................ Throughout Change to General Description Section ......................................... 1 Changes to Figure 1 and Figure 2 ................................................... 1 Changes to Maximum Power Dissipation Section ........................ 5 Changes to Figure 67 ...................................................................... 19 Changes to Applications Section ................................................. 16 Added Figure 68 to Figure 70; Renumbered Sequentially ........ 19 Changes to Table 7 .......................................................................... 24 Changes to Figure 71 ...................................................................... 20 Changes to Ordering Guide .......................................................... 26 Added Figure 72 and Figure 73..................................................... 20 Changes to PCB Layout Section ................................................... 23 1/2004—Rev. 0 to Rev. A Updated Outline Dimensions ....................................................... 24 Inserted Figure 3 ................................................................................ 1 Changes to Ordering Guide ......................................................... 24 Changes to Specifications Section ................................................... 3 Inserted Figure 22 to Figure 34 ........................................................ 8 8/2013—Rev. C to Rev. D Inserted Figure 51 to Figure 55 ..................................................... 14 Changes to Figure 42 Caption ....................................................... 12 Changes to Theory of Operation Section.................................... 16 Changes to Figure 49 ...................................................................... 13 Changes to Circuit Components Section .................................... 17 Changes to Ordering Guide .......................................................... 25 Changes to Table 4 .......................................................................... 18 Changes to Figure 60 ...................................................................... 18 1/2013—Rev. B to Rev. C Changes to Total Output Noise Calculations and Added EPAD Note to Figure 1 and Figure 2 ................................. 1 Design Section ................................................................................ 21 Changes to PCB Layout Section and Design Tools and Changes to Figure 60 ...................................................................... 22 Technical Support Section ............................................................. 23 Changes to Figure 62 ...................................................................... 23 Deleted Figure 72, Figure 73, Evaluation Boards Section, Changes to 16-Bit ADC Driver Section ...................................... 23 and Table 7 ....................................................................................... 24 Changes to Table 6 .......................................................................... 23 Updated Outline Dimensions ....................................................... 25 Additions to PCB Layout Section ................................................. 23 Changes to Ordering Guide .......................................................... 26 11/2003—Revision 0: Initial Version Rev. E | Page 2 of 26

Data Sheet AD8099 SPECIFICATIONS SPECIFICATIONS WITH ±5 V SUPPLY T = 25°C, G = +2, R = 1 kΩ to ground, unless otherwise noted. Refer to Figure 60 through Figure 66 for component values and gain A L configurations. Table 1. Parameter Test Conditions/Comments Min Typ Max Unit DYNAMIC PERFORMANCE −3 dB Bandwidth G = +5, V = 0.2 V p-p 450 510 MHz OUT G = +5, V = 2 V p-p 205 235 MHz OUT Bandwidth for 0.1 dB Flatness (SOIC/LFCSP) G = +2, V = 0.2 V p-p 34/25 MHz OUT Slew Rate G = +10, V = 6 V Step 1120 1350 V/µs OUT G = +2, V = 2 V Step 435 470 V/µs OUT Settling Time to 0.1% G = +2, V = 2 V Step 18 ns OUT NOISE/DISTORTION PERFORMANCE Harmonic Distortion (dBc) HD2/HD3 f = 500 kHz, V = 2 V p-p, G = +10 −102/−111 dBc C OUT f = 10 MHz, V = 2 V p-p, G = +10 −84/−92 dBc C OUT Input Voltage Noise f = 100 kHz 0.95 nV/√Hz Input Current Noise f = 100 kHz, DISABLE pin floating 2.6 pA/√Hz f = 100 kHz, DISABLE pin = +VS 5.2 pA/√Hz DC PERFORMANCE Input Offset Voltage 0.1 0.5 mV Input Offset Voltage Drift 2.3 µV/°C Input Bias Current DISABLE pin floating −6 −13 µA DISABLE pin = +VS −0.1 −2 µA Input Bias Current Drift 3 nA/°C Input Bias Offset Current 0.06 1 µA Open-Loop Gain 82 85 dB INPUT CHARACTERISTICS Input Resistance Differential mode 4 kΩ Common mode 10 MΩ Input Capacitance 2 pF Input Common-Mode Voltage Range −3.7 to +3.7 V Common-Mode Rejection Ratio V = ±2.5 V 98 105 dB CM DISABLE PIN DISABLE Input Voltage Output disabled <2.4 V Turn-Off Time 50% of DISABLE to < 10% of final V , ns OUT VIN = 0.5 V, G = +2 105 Turn-On Time 50% of DISABLE to < 10% of final V , ns OUT V = 0.5 V, G = +2 39 IN Enable Pin Leakage Current DISABLE = +5 V 17 21 µA DISABLE Pin Leakage Current DISABLE = −5 V 35 44 µA OUTPUT CHARACTERISTICS Output Overdrive Recovery Time (Rise/Fall) V = −2.5 V to +2.5 V, G =+2 30/50 ns IN Output Voltage Swing R = 100 Ω −3.4 to +3.5 −3.6 to +3.7 V L R = 1 kΩ −3.7 to +3.7 −3.8 to +3.8 V L Short-Circuit Current Sinking and sourcing 131/178 mA Off Isolation f = 1 MHz, DISABLE = low −61 dB POWER SUPPLY Operating Range ±5 ±6 V Quiescent Current 15 16 mA Quiescent Current (Disabled) DISABLE = Low 1.7 2 mA Positive Power Supply Rejection Ratio +V = 4 V to 6 V, −V = −5 V (input referred) 85 91 dB S S Negative Power Supply Rejection Ratio +V = 5 V, −V = −6 V to −4 V (input referred) 86 94 dB S S Rev. E | Page 3 of 26

AD8099 Data Sheet SPECIFICATIONS WITH +5 V SUPPLY V = 5 V at T = 25°C, G = +2, R = 1 kΩ to midsupply, unless otherwise noted. Refer to Figure 60 through Figure 66 for component S A L values and gain configurations. Table 2. Parameter Test Conditions/Comments Min Typ Max Unit DYNAMIC PERFORMANCE −3 dB Bandwidth G = +5, V = 0.2 V p-p 415 440 MHz OUT G = +5, V = 2 V p-p 165 210 MHz OUT Bandwidth for 0.1 dB Flatness (SOIC/LFCSP) G = +2, V = 0.2 V p-p 33/23 MHz OUT Slew Rate G = +10, V = 2 V Step 630 715 V/µs OUT G = +2, V = 2 V Step 340 365 V/µs OUT Settling Time to 0.1% G = +2, V = 2 V Step 18 ns OUT NOISE/DISTORTION PERFORMANCE Harmonic Distortion (dBc) HD2/HD3 f = 500 kHz, V = 1 V p-p, G = +10 −82/−94 dBc C OUT f = 10 MHz, V = 1 V p-p, G = +10 −80/−75 dBc C OUT Input Voltage Noise f = 100 kHz 0.95 nV/√Hz Input Current Noise f = 100 kHz, DISABLE pin floating 2.6 pA/√Hz f = 100 kHz, DISABLE pin = +VS 5.2 pA/√HZ DC PERFORMANCE Input Offset Voltage 0.1 0.5 mV Input Offset Voltage Drift 2.5 µV/°C Input Bias Current DISABLE pin floating −6.2 −13 µA DISABLE pin = +VS −0.2 −2 µA Input Bias Offset Current 0.05 1 µA Input Bias Offset Current Drift 2.4 nA/°C Open-Loop Gain V = 1 V to 4 V 76 81 dB OUT INPUT CHARACTERISTICS Input Resistance Differential mode 4 kΩ Common mode 10 MΩ Input Capacitance 2 pF Input Common-Mode Voltage Range 1.3 to 3.7 V Common-Mode Rejection Ratio V = 2 V to 3 V 88 105 dB CM DISABLE PIN DISABLE Input Voltage Output disabled <2.4 V 50% of DISABLE to <10% of Final V , OUT Turn-Off Time V = 0.5 V, G = +2 105 ns IN 50% of DISABLE to <10% of Final V , OUT Turn-On Time V = 0.5 V, G = +2 61 ns IN Enable Pin Leakage Current DISABLE = 5 V 16 21 µA DISABLE Pin Leakage Current DISABLE = 0 V 33 44 µA OUTPUT CHARACTERISTICS Overdrive Recovery Time (Rise/Fall) V = 0 to 2.5 V, G = +2 50/70 ns IN Output Voltage Swing R = 100 Ω 1.5 to 3.5 1.2 to 3.8 V L R = 1 kΩ 1.2 to 3.8 1.2 to 3.8 V L Short-Circuit Current Sinking and Sourcing 60/80 mA Off Isolation f = 1 MHz, DISABLE = Low −61 dB POWER SUPPLY Operating Range ±5 ±6 V Quiescent Current 14.5 15.4 mA Quiescent Current (Disabled) DISABLE = Low 1.4 1.7 mA Positive Power Supply Rejection Ratio +V = 4.5 V to 5.5 V, −V = 0 V (input referred) 84 89 dB S S Negative Power Supply Rejection Ratio +V =5 V, −V= −0.5 V to +0.5 V (input referred) 84 90 dB S S Rev. E | Page 4 of 26

Data Sheet AD8099 ABSOLUTE MAXIMUM RATINGS TPaarbalme 3e.t er Rating PD =(VS×IS)+V2S ×VROULT –VORULT2 Supply Voltage 12.6 V RMS output voltages should be considered. If R is referenced to L Power Dissipation See Figure 4 V−, as in single-supply operation, then the total drive power is S Differential Input Voltage ±1.8 V V × I . If the rms signal levels are indeterminate, consider the S OUT Differential Input Current ±10mA worst case, when V = V/4 for R to midsupply: OUT S L SOtpoeraragtein Tge mTepmepraetruarteu rRea Rnagneg e −−6450°°CC ttoo ++112255°°CC P =(V ×I )+(VS/4)2 Lead Temperature (Soldering 10 sec) 300°C D S S RL Junction Temperature 150°C In single-supply operation with R referenced to V–, worst case L S is V = V/2. Stresses at or above those listed under Absolute Maximum OUT S Ratings may cause permanent damage to the product. This is a Airflow increases heat dissipation, effectively reducing θJA. Also, stress rating only; functional operation of the product at these more metal directly in contact with the package leads from metal or any other conditions above those indicated in the operational traces, through holes, ground, and power planes reduce the θJA. section of this specification is not implied. Operation beyond Soldering the exposed paddle to the ground plane significantly the maximum operating conditions for extended periods may reduces the overall thermal resistance of the package. Take care affect product reliability. to minimize parasitic capacitances at the input leads of high MAXIMUM POWER DISSIPATION speed op amps, as discussed in the PCB Layout section. Figure 4 shows the maximum safe power dissipation in the The maximum safe power dissipation in the AD8099 package is package versus the ambient temperature for the exposed paddle limited by the associated rise in junction temperature (T) on J (EPAD) SOIC-8 (70°C/W), and LFCSP (70°C/W), packages on the die. The plastic encapsulating the die locally reaches the a JEDEC standard 4-layer board. θ values are approximations. junction temperature. At approximately 150°C, which is the JA glass transition temperature, the plastic changes its properties. 4.0 Even temporarily exceeding this temperature limit may change s) 3.5 the stresses that the package exerts on the die, permanently att W shifting the parametric performance of the AD8099. Exceeding N ( 3.0 O a junction temperature of 150°C for an extended period can ATI 2.5 result in changes in silicon devices, potentially causing failure. SIP DIS 2.0 The still-air thermal properties of the package and PCB (θJA), R E the ambient temperature (T ), and the total power dissipated in W 1.5 A O LFCSP AND SOIC P the package (PD) determine the junction temperature of the die. M 1.0 U The junction temperature can be calculated as M XI ( ) A 0.5 T =T + P ×θ M J A D JA Tquhiee spcoewnte rp odwisseirp datisesdip inat itohne panacdk tahgee p(PowD)e irs dthises ispuamte do fi nth teh e 0.0–40 –20 0AMBIE2N0T TEM40PERAT6U0RE (°C8)0 100 120 04511-0-115 Figure 4. Maximum Power Dissipation package due to the load drive for all outputs. The quiescent power is the voltage between the supply pins (V) times the ESD CAUTION S quiescent current (I). Assuming the load (R) is referenced to S L midsupply, the total drive power is V/2 × I , some of which is S OUT dissipated in the package and some in the load (V × I ). OUT OUT The difference between the total drive power and the load power is the drive power dissipated in the package. P = Quiescent Power + (Total Drive Power − Load Power) D Rev. E | Page 5 of 26

AD8099 Data Sheet TYPICAL PERFORMANCE CHARACTERISTICS Default conditions: V = ±5 V, T = 25°C, R = 1 kΩ tied to ground unless otherwise noted. Refer to Figure 63 through Figure 66 for S A L component values and gain configurations. 4 VOUT = 0.2V p-p G = +2 4 3 VS =±5V VOUT = 0.2V p-p G = +2 B) 2 RLOAD = 1kΩ GAIN (dB) 0123 VRSL O=A±D5 =V 1kΩ G = +5 OOP GAIN (d –101 OOP –1 ED-L ––32 G = +20 G = +5 L –2 S ZED CLOSED- ––––6543 GG = =– 1+20 G = +10 MALIZED CLO ––––7654 G =–1 MALI –7 NOR ––98 G = +10 NOR –1––0981 10 FREQUENCY (M10H0z) 1000 04511-0-074 –101 10 FREQUENCY (M10H0z) 1000 04511-0-073 Figure 5. Small Signal Frequency Response for Various Gains (SOIC) Figure 8. Small Signal Frequency Response for Various Gains (LFCSP) 17 17 G = +5 RL = 1kΩ, CSP G = +5 16 VVSO U=T± =5 V0.2V p-p RL = 100Ω, CSP 16 RVOL U=T 1 =k Ω0.2V p-p 15 15 dB) 14 dB) 14 N ( N ( VS =±5V, SOIC AI 13 AI 13 OP G 12 RL = 1kΩ, SOIC OP G 12 O O OSED-L 1101 RL = 100Ω, SOIC OSED-L 1101 VS =±2.5V, CSP L L C 9 C 9 VS =±5V, CSP 8 8 71 10FREQUENCY (MHz1)00 1000 04511-0-076 71 10FREQUVES N=C±Y2 .(5MVH, zS1)O0I0C 1000 04511-0-077 Figure 6. Small Signal Frequency Response for Various Load Resistors Figure 9. Small Signal Frequency Response for Various Supply Voltages 11 11 VOUT = 0.2V p-p +125°C VOUT = 0.2V p-p +125°C +85°C 10 10 9 9 +85°C dB) 8 dB) 8 N ( N ( AI 7 AI 7 G G –40°C OOP 6 +25°C OOP 6 D-L 5 D-L 5 E E OS 4 OS 4 CL 3 –40°C CL 3 +25°C G = +2 G = +2 2 VS =±5V 2 VS =±5V 11RL = 1kΩ 10 FREQUENCY (M10H0z) 1000 04511-0-098 11RL = 1kΩ 10 FREQUENCY (M10H0z) 1000 04511-0-097 Figure 7. Small Signal Frequency Response for Various Temperatures (SOIC) Figure 10. Small Signal Frequency Response for Various Temperatures (LFCSP) Rev. E | Page 6 of 26

Data Sheet AD8099 20 90 –30 G = +5 5pF, CSP 19 VS =±5V 80 –45 18 70 MAGNITUDE –60 s) OOP GAIN (dB) 11116475 1pF, SOIC OP GAIN (dB) 456000 PHASE –––1970055 PHASE (Degree ED-L 13 N-LO 30 –120 OOP CLOS 1121 1pF, CSP OPE 1200 ––115305 OPEN-L 10 5pF, SOIC 0 VRSL == ±15kVΩ –165 91 10FREQUENCY (MHz1)00 1000 04511-0-104 –100.00U1NCOM0P.0E1NSATE0D.1FREQU1E.0NCY (MH10z) 100 1000 –180 04511-0-080 Figure 11. Small Signal Frequency Response for Various Capacitive Loads Figure 14. Open Loop Frequency Response 1 2 G = +2 G = +10 G = +2 0 1 dB) –1 dB) 0 G = +10 N ( N ( AI –2 AI –1 G G = +20 G OP –3 OP –2 G = +20 O O D-L –4 D-L –3 OSE –5 G = +5 OSE –4 L L D C –6 D C –5 E E Z –7 Z –6 LI LI A A G = +5 M –8 M –7 OR VS =±5V OR VS =±5V N –9 VOUT = 2V p-p N –8 VOUT = 2V p-p –101RLOAD = 1kΩ 10FREQUENCY (MHz1)00 1000 04511-0-011 –91RLOAD = 1kΩ 10FREQUENCY (MHz1)00 1000 04511-0-012 Figure 12. Large Signal Frequency Response for Various Gains (SOIC) Figure 15. Large Signal Frequency Response for Various Gains (LFCSP) 6.5 6.5 VS =±5V VOUT = 1.4V p-p VS =±5V VOUT = 1.4V p-p G = +2 G = +2 6.4 RL = 150Ω 6.4 RL = 150Ω 6.3 6.3 dB) 6.2 dB) 6.2 N ( N ( AI 6.1 AI 6.1 G G OP 6.0 OP 6.0 O O D-L 5.9 D-L 5.9 OSE 5.8 VOUT = 200mV p-p OSE 5.8 VOUT = 200mV p-p L L C C 5.7 5.7 5.6 5.6 5.51 FREQUEN10CY (MHz) 100 04511-0-009 5.51 FREQUEN10CY (MHz) 100 04511-0-008 Figure 13. 0.1 dB Flatness (SOIC) Figure 16. 0.1 dB Flatness (LFCSP) Rev. E | Page 7 of 26

AD8099 Data Sheet 15 15 RL = 1kΩ, CSP VS =±5V, CSP 14 14 13 13 RL = 100Ω, CSP VS =±2.5V, CSP B) 12 B) 12 d d AIN ( 11 RL = 100Ω, SOIC AIN ( 11 OP G 10 OP G 10 VS =±5V, SOIC O O D-L 9 D-L 9 E E OS 8 OS 8 CL 7 RL = 1kΩ, SOIC CL 7 G = +5 G = +5 VS =±2.5V, SOIC 6 VS =±5V 6 RL = 1kΩ 51VOUT = 2V p-p 10FREQUENCY (MHz1)00 1000 04511-0-078 51VOUT = 2V p-p 10FREQUENCY (MHz1)00 1000 04511-0-079 Figure 17. Large Signal Frequency Response for Various Load Resistances Figure 20. Large Signal Frequency Response for Various Supply Voltages 100.0 –10 G = +2 RL = 1kΩ –20 VS =±5V 10.0 VDIS = 0V –30 Ωk) B) PUT IMPEDANCE ( 01..10 OFF ISOLATION (d –––465000 CSP SOIC IN –70 0.01 –80 VS =±5V 0.0011G = +2 10FREQUENCY (MHz1)00 1000 04511-0-105 –900.1 1 FREQUEN10CY (MHz) 100 1000 04511-0-094 Figure 18. Input Impedance vs. Frequency Figure 21. Off Isolation vs. Frequency 100 –50 G = +5 VOUT = 2V p-p –60 VS =±5V G = +5 RL = 100Ω Ω) 10 dBc) –70 E ( N ( C O AN RTI –80 SOIC ED 1 G = +2 G = +10 TO P S T IM C DI –90 UTPU MONI–100 O 0.1 AR CSP H –110 SSOOLLIIDD LLIINNEESS–– SSEECCOONNDD HHAARRMMOONNIICCSS 0.010.1VS =±5V 1 FREQUEN10CY (MHz) 100 1000 04511-0-100 –1200.1 F1R.0EDDQOOUTTTTEEENDDC YLL II(NNMEEHS–z )–T HTHIR1IRD0.D 0H HAARRMMOONNICICSS 04511-A-008 Figure 19. Output Impedance vs. Frequency for Various Gains Figure 22. Harmonic Distortion vs. Frequency Rev. E | Page 8 of 26

Data Sheet AD8099 –50 –50 G = +5 G = +5 VOUT = 2V p-p VOUT = 2V p-p –60 VS =±5V –60 VS =±5V RL = 1kΩ RL = 1kΩ Bc) –70 Bc) –70 d d N ( N ( O –80 O –80 TI TI R R O O T –90 T –90 S S DI DI C –100 C –100 NI NI O O M M R–110 R–110 A A H H –120 –120 SOLID LINE– SECOND HARMONIC SOLID LINE– SECOND HARMONIC –1300.1 F1R.0EQDUOENTTCEYD ( MLIHNzE)– T1H0IR.0D HARMONIC 04511-A-009 –1300.1 F1R.0EQDUOENTTCEYD ( MLIHNzE)– T1H0IR.0D HARMONIC 04511-A-012 Figure 23. Harmonic Distortion vs. Frequency (SOIC) Figure 26. Harmonic Distortion vs. Frequency (LFCSP) –40 –40 G = +2 G = +2 –50 VVOS U=T± =5 V2V p-p –50 VVOS U=T± =5 V2V p-p RL = 1kΩ RL = 1kΩ c) –60 c) –60 B B d d N ( –70 N ( –70 O O TI TI R –80 R –80 O O T T DIS –90 DIS –90 C C NI–100 NI–100 O O M M AR–110 AR–110 H H –120 –120 SOSLOIDL ILDI NLEINSE–– S SEECCOONNDD H HAARRMMOONNICICS SOLID LINE– SECOND HARMONIC –1300.1 F1R.0EDQODUTOTETENTDCE YLD I( NMLEIHN–zE )T–H TIRH1D0IR. 0HDA HRAMROMNOICNSIC 04511-A-010 –1300.1 F1R.0EQDUOENTTCEYD ( MLIHNzE)– T1H0IR.0D HARMONIC 04511-A-013 Figure 24. Harmonic Distortion vs. Frequency (SOIC) Figure 27. Harmonic Distortion vs. Frequency (LFCSP) –40 –40 G =–1 G =–1 –50 VVOS U=T± =5 V2V p-p –50 VVOS U=T± =5 V2V p-p RL = 1kΩ RL = 1kΩ c) –60 c) –60 B B d d N ( –70 N ( –70 O O TI TI R –80 R –80 O O T T DIS –90 DIS –90 C C NI–100 NI–100 O O M M AR–110 AR–110 H H –120 –120 SOLID LINE– SECOND HARMONIC SOLID LINE– SECOND HARMONIC –1300.1 F1R.0EQDUOENTTCEYD ( MLIHNzE)– T1H0IR.0D HARMONIC 04511-A-011 –1300.1 F1R.0EQDUOENTTCEYD ( MLIHNzE)– T1H0IR.0D HARMONIC 04511-A-014 Figure 25. Harmonic Distortion vs. Frequency (SOIC) Figure 28. Harmonic Distortion vs. Frequency (LFCSP) Rev. E | Page 9 of 26

AD8099 Data Sheet –50 –50 G = +10 G = +10 RL = 1kΩ RL = 1kΩ –60 –60 VS =±2.5V VS =±2.5V dBc) –70 VOUT = 1V p-p dBc) –70 VOUT = 1V p-p N ( N ( O O RTI –80 RTI –80 O O T T S S DI –90 DI –90 C C NI NI O O M–100 M–100 HAR–110 VVSO U=T± =5 V2V p-p HAR–110 VVOS U=T± =5 V2V p-p SOLID LINES– SECOND HARMONICS SSOOLLIIDD LLIINNEESS–– SSEECCOONNDD HHAARRMMOONNIICCSS –1200.1 F1R.0EDQOUTTEENDC YL I(NMEHSz)– TH1IR0.D0 HARMONICS 04511-A-015 –1200.1 1.0FREDDQOOUTTTTEEENDDC YLL II(NNMEEHS–z1 )–T0 HT.0HIRIRDD H HAARRMMOONNICICSS 04511-A-018 Figure 29. Harmonic Distortion vs. Frequency and Supply Voltage (SOIC) Figure 32. Harmonic Distortion vs. Frequency for Various Supplies (LFCSP –40 –40 G = +5 G = +5 VS =±5V VS =±5V –50 f = 10MHz –50 f = 10MHz RL = 100Ω RL = 100Ω c) c) dB –60 dB –60 N ( N ( O O RTI –70 RTI –70 O O T T S S DI –80 DI –80 C C NI NI O O M –90 M –90 R R A A H H –100 –100 SOLID LINE– SECOND HARMONIC SOLID LINE– SECOND HARMONIC –1101 2 OUT3PUT ADMOPTL4TITEUDD LEIN (VE 5p– -TpH)IRD H6ARMONIC7 04511-A-016 –1101 2 OUT3PUT ADMOPTL4TITEUDD LEIN (VE 5p– -TpH)IRD H6ARMONIC7 04511-A-019 Figure 30. Harmonic Distortion vs. Output Amplitude (SOIC) Figure 33. Harmonic Distortion vs. Output Amplitude (LFCSP) –40 –40 G = +5 G = +5 VS =±5V VS =±5V –50 f = 10MHz –50 f = 10MHz RL = 1kΩ RL = 1kΩ Bc) –60 Bc) –60 d d N ( N ( O –70 O –70 TI TI R R O O T –80 T –80 S S DI DI C –90 C –90 NI NI O O M M R–100 R–100 A A H H –110 –110 SOLID LINE– SECOND HARMONIC SOLID LINE– SECOND HARMONIC –1201 2 OU3TPUT ADMOP4TLTITEUDD LEIN (V5E p– -TpH)IRD6 HARMON7IC 04511-A-017 –1201 2 OU3TPUT ADMO4PTLTITEUDD LEIN 5(VE p– -TpH)IRD6 HARMON7IC 04511-A-021 Figure 31. Harmonic Distortion vs. Output Amplitude (SOIC) Figure 34. Harmonic Distortion vs. Output Amplitude (LFCSP) Rev. E | Page 10 of 26

Data Sheet AD8099 0.20 0.20 10pF, 20Ω RSNUB 10pF, 20Ω RSNUB 0.15 0.15 0.10 0.10 E (V) 0.05 1pF E (V) 0.05 1pF G G A A T T L 0 L 0 O O V V T T U–0.05 U–0.05 P P UT RSNUB UT RSNUB O–0.10 O–0.10 CL RL CL RL –0.15 G = +5 –0.15 G = +5 VS =±5V VS =±5V –0.200 5RL = 110kΩ 15 20TIME25 (ns)30 35 40 45 50 04511-0-095 –0.200 5RL = 110kΩ 15 20TIME25 (ns)30 35 40 45 50 04511-0-096 Figure 35. Small Signal Transient Response for Various Capacitive Loads Figure 38. Small Signal Transient Response for Various Capacitive Loads (SOIC) (LFCSP) 0.15 0.20 VS =±5.0V VS =±2.5V AND±2.5V, CSP 0.15 CSP VCSS P=±5.0V 0.10 0.10 E (V) 0.05 E (V) 0.05 G G OLTA 0 OLTA 0 VSSO I=C±5.0V V V T T TPU–0.05 TPU–0.05 U U O O–0.10 VS =±2.5V SOIC ––00..11500GRL = = + 11k0Ω 10 20TAIMNDE (±nV2s.S5) V=3,0 ±S5O.0IVC 40 50 04511-0-107 ––00..21050RGVOL = U= T+ 1 5=k Ω20, 011m000VΩ p-p 20TIME (ns)30 40 50 04511-0-102 Figure 36. Small Signal Transient Response for Various Supply Voltages Figure 39. Small Signal Transient Response for Various Supply Voltages 5 3.5 INPUT× 2 TURN OFF TURN ON 4 INPUT INPUT 3.0 3 V) 2 RL = 100Ω V) 2.5 GE( 1 GE ( 2.0 A A VOLT 0 VOLT 1.5 VS =±5V PUT –1 PUT 1.0 G = 2 UT –2 UT O RL = 1kΩ O 0.5 –3 TURN ON TURN OFF –4 0 –50 100 200 300 400TIM5E0 0(ns)600 700 800 900 1000 04511-A-017 –0.5 0 50TIME (ns)100 150 200 04511-0-010 Figure 37. Output Overdrive Recovery for Various Resistive Loads Figure 40. Disable/Enable Switching Speed Rev. E | Page 11 of 26

AD8099 Data Sheet 1.5 1.5 0.3% VS =±2.5V OUTPUT 1.0 1.0 0.2% V) INPUT E (V) 0.5 AGE ( 0.5 0.1% G T OLTA 0 T VOL 0 0% V U UT NP ERROR OUTP –0.5 TPUT/I –0.5 –0.1% U O –1.0 –1.0 –0.2% G = +2 –1.50GRL = = + 11k0Ω 10 20TIME (nVsS) =30±5.0V 40 50 04511-0-106 –1.50 5 10 15 T2I0ME (n2s5) 30 35RVsL O=A±D45 0=V 1kΩ45–0.3% 04511-0-052 Figure 41. Large Signal Transient Response vs. Supply Voltage (LFCSP) Figure 44. Short Term Settling Time (LFCSP) 1.5 1.5 0.3% VS =±5.0V OUTPUT 1.0 1.0 0.2% V) INPUT E (V) 0.5 VS =±2.5V AGE ( 0.5 0.1% G T OLTA 0 T VOL 0 0% V U UT NP ERROR OUTP –0.5 TPUT/I –0.5 –0.1% U O –1.0 –1.0 –0.2% G = +2 G = +10 RLOAD = 1kΩ –1.50RL = 1kΩ 10 20TIME (ns)30 40 50 04511-0-118 –1.50 5 10 15 T2I0ME (n2s5) 30 35Vs =±450V 45–0.3% 04511-0-051 Figure 42. Large Signal Transient Response vs. Supply Voltage (SOIC) Figure 45. Short Term Settling Time (SOIC) 1.5 VS =±5V 1.5 G = +2 0.30% OUTPUT VS =±5V 1.0 1.0 0.20% E (V) 0.5 VS =±2.5V AGE (V) 0.5 INPUT 0.10% G T A L T O UT VOL 0 NPUT V 0 ERROR 0% TP –0.5 T/I –0.5 –0.10% U U O P T U –1.0 O –1.0 –0.20% RL = 1kΩ, 100Ω –1.50G = +5 10 20TIME (ns)30 40 50 04511-0-101 –1.50 50 100 150 200TIM2E5 0(µs)300 350 400 450 500–0.30% 04511-0-050 Figure 43. Large Signal Transient Response for Various Supply Voltages and Figure 46. Long Term Settling Time Load Resistances (SOIC and LFCSP) Rev. E | Page 12 of 26

Data Sheet AD8099 –20 0 G = +2 G = +5 –30 RL = 1kΩ –10 RL = 1kΩ dB) –40 dB) –20 N ( N ( –30 O –50 O CTI CTI –40 NEGATIVE JE –60 JE E E R R –50 DE –70 LY O P –60 ON-M –80 R SUP –70 POSITIVE M E OM –90 OW –80 C P –100 –90 –1100.1 1.0 FREQUEN10CY (MHz) 100 1000 04511-0-113 –1000.01 0.10 FR1E.0QUENCY (M1H0z) 100 1000 04511-0-114 Figure 47. Common-Mode Rejection vs. Frequency Figure 50. Power Supply Rejection vs. Frequency 1000 1000 Hz) Hz) A A E (p 100 E (p 100 S S OI OI N N T T N N E E R R R R U 10 U 10 C C T T U U P P N N I I 11 10 100 1kFRE1Q0UkENC10Y0 (kHz)1M 10M 100M 1G 04511-0-004 11 10 100 1kFRE1Q0UkENC10Y0 (kHz)1M 10M 100M 1G 04511-0-003 Figure 48. Input Current Noise vs. Frequency (DISABLE = Open) Figure 51. Input Current Noise vs. Frequency (DISABLE = +VS) 100 VS =±5V N = 1,200 120 XX =–70µV σ = 80µV Hz) V 100 E (n 10 OIS 80 E N UNT AG CO 60 T L O 1 T V 40 U P N I 20 0.11 10 100 1kFRE1Q0UkENC10Y0 (kHz)1M 10M 100M 1G 04511-0-005 0–300 –200 –1V0O0FFSET (µV0) 100 200 04511-0-075 Figure 49. Input Voltage Noise vs. Frequency Figure 52. Input Offset Voltage Distribution Rev. E | Page 13 of 26

AD8099 Data Sheet 400 20 300 18 VS =5V µV) 200 mA) 16 VS =±5V E ( T ( G N A E LT 100 RR 14 VO CU VS =5V OFFSET 0 VS =±5V SUPPLY 12 –100 10 –200–40 –25 –10 5 T2E0MPE35RATU50RE (C65) 80 95 110 125 04511-A-003 8–40 –25 –10 5 T2E0MPE35RATU50RE (C65) 80 95 110 125 04511-A-006 Figure 53. Input Offset Voltage vs. Temperature Figure 56. Supply Current vs. Temperature –5.4 1.0 IB+, VS =±5V 0.8 –5.6 IB+, VS =±5V 0.6 0.4 A) –5.8 A) µ µ NT ( IB–, VS =±5V NT ( 0.2 RRE –6.0 RRE 0 IB–, VS =±5V IB+, VS =5V U U S C IB–, VS =5V S C –0.2 A –6.2 A BI BI –0.4 –0.6 –6.4 IB+, VS =5V –0.8 IB–, VS =5V –6.6–40 –25 –10 5 T2E0MPE35RATU50RE (C65) 80 95 110 125 04511-A-004 –1.0–40 –25 –10 5 T2E0MPE35RATU50RE (C65) 80 95 110 125 04511-A-007 Figure 54. Input Bias Current vs. Temperature (DISABLE Pin Floating) Figure 57. Input Bias Current vs. Temperature (DISABLE Pin = +VS) 1.24 V) 1.22 –VS +VOUT E ( AG VS =±5V LT 1.20 O V TION 1.18 +VS–VOUT A R TU –VS +VOUT A 1.16 S T U P +VS–VOUT UT 1.14 O 1.12–40 –25 –V10S =5–V5 T2E0MPE35RATU50RE (C65) 80 95 110 125 04511-A-005 Figure 55. Output Saturation Voltage vs. Temperature Rev. E | Page 14 of 26

Data Sheet AD8099 THEORY OF OPERATION The AD8099 is a voltage feedback op amp that employs a new the feedback loop. While using the secondary output for feed- highly linear low noise input stage. With this input stage, the back, inductance in the primary output now helps to isolate AD8099 can achieve better than 90 dB distortion for a 2 V p-p, capacitive loads from the output impedance of the amplifier. 10 MHz output signal with an input referred voltage noise of Since the SOIC has greater inductance in its output, the SOIC less than 1 nV/√Hz. This noise level and distortion performance drives capacitive loads better than the LFCSP. Using the primary has been previously achievable only with fully uncompensated output for feedback with both packages results in the LFCSP amplifiers. The AD8099 achieves this level of performance for driving capacitive load better than the SOIC. gains as low as +2. This new input stage also triples the achievable The LFCSP and SOIC pinouts are identical, except for the slew rate for comparably compensated 1 nV/√Hz amplifiers. rotation of all pins counterclockwise by one pin on the LFCSP. The simplified AD8099 topology is shown in Figure 58. The This isolates the inputs from the negative power supply pin, amplifier is a single gain stage with a unity gain output buffer removing a mutually inductive coupling that is most prominent fabricated in the Analog Devices extra fast complimentary while driving heavy loads. For this reason, the LFCSP second bipolar (XFCB) process. The AD8099 has 85 dB of open-loop harmonic, while driving a heavy load, is significantly better gain and maintains precision specifications such as CMRR, than that of the SOIC. PSRR, V , and V /T to levels that are normally associated OS OS A three-state input pin is provided on the AD8099 for a high with topologies having two or more gain stages. impedance power-down and an optional input bias current cancellation circuit. The high impedance output allows several AD8099 devices to drive the same ADC or output line time inter- gm R1 CC BUFFER RL VOUT 04511-0-060 lsetaavtee.d S. ePeu Tllainbgle t h5 ef oDrI tShArBesLhEo pldin le lvoewls a. cWtivhaetens tthhee DhiIgShA iBmLpEe dpainnc ies Figure 58. AD8099 Topology left floating, the AD8099 operates normally. With the DISABLE pin pulled within 0.7 V of the positive supply, an optional input The AD8099 can be externally compensated down to a gain of 2 bias current cancellation circuit is turned on, which lowers the through the use of an RC network. Above gains of 15, no external input bias current to less than 200 nA. In this mode, the user compensation network is required. To realize the full gain can drive the AD8099 with a high dc source impedance and still bandwidth product of the AD8099, no PCB trace should be maintain minimal output referred offset without having to use connected to or within close proximity of the external compen- impedance matching techniques. In addition, the AD8099 can sation pin for the lowest possible capacitance. be ac-coupled while setting the bias point on the input with a External compensation allows the user to optimize the closed- high dc impedance network. The input bias current cancellation loop response for minimal peaking while increasing the gain circuit doubles the input referred current noise, but this effect is bandwidth product in higher gains, lowering distortion errors minimal as long as wideband impedance is kept low (see Figure 48 that are normally more prominent with internally compensated and Figure 51). parts in higher gains. For a fixed gain bandwidth, wideband A pair of internally connected diodes limits the differential distortion products would normally increase by 6 dB going voltage between the noninverting input and the inverting input from a closed-loop gain of 2 to 4. Increasing the gain bandwidth of the AD8099. Each set of diodes has two series diodes, which product of the AD8099 eliminates this effect with increasing are connected in anti-parallel. This limits the differential voltage closed-loop gain. between the inputs to approximately 1.8 V. All of the AD8099 The AD8099 is available in both a SOIC and an LFCSP, each of pins are ESD protected with voltage limiting diodes connected which has a thermal pad for lower operating temperature. To between both rails. The protection diodes can handle 5 mA of help avoid this pad in board layout, both packages have an extra steady state current. Currents should be limited to 5 mA or less output pin on the opposite side of the package for ease in con- through the use of a series limiting resistor. necting a feedback network to the inputs. The secondary output pin also isolates the interaction of any capacitive load on the output and self-inductance of the package and bond wire from Rev. E | Page 15 of 26

AD8099 Data Sheet APPLICATIONS INFORMATION USING THE AD8099 CF—Creates a zero in the loop response to compensate the pole created by the input capacitance (including stray capacitance) The AD8099 offers unrivaled noise and distortion performance and the feedback resistor, R. C helps reduce high frequency F F in low signal gain configurations. In low gain configurations peaking and ringing in the closed-loop response. The typical (less than 15), the AD8099 requires external compensation. The range is 0.5 pF to 1.5 pF for the evaluation circuits used here. amount of gain and performance needed determines the R1—This resistor terminates the input of the amplifier to the compensation network. source resistance of the signal source, typically 50 Ω. (This is Understanding the subtleties of the AD8099 gives the user insight application specific and not always required.) on how to exact its peak performance. Use the component values R—Many high speed amplifiers in low gain configurations and circuit configurations shown in the Applications Information S require that the input stage be terminated into a nominal section as starting points for designs. Specific circuit applications impedance to maintain stability. The value of R should be kept dictate the final configuration and value of the components. S to 50 Ω or lower to maintain low noise performance. At higher CIRCUIT COMPONENTS gains, R may be reduced or even eliminated. Typical range is S The circuit components are referenced in Figure 59, the 0 Ω to 50 Ω. recommended noninverting circuit schematic for the AD8099. C —The compensation capacitor decreases the open-loop gain C See Table 4 for typical component values and performance data. at higher frequencies where the phase is degrading. By decreas- CF +VS C2 ing the open-loop gain here, the phase margin is increased and 10F the amplifier is stabilized. Typical range is 0 pF to 5 pF. The RF value of CC is gain dependent. C3 0.1F R —The series lead inductance of the package and the com- RG 2 1 7 peCnsation capacitance (CC) forms a series resonant circuit. RS AD80995 6 VOUT RC dampens this resonance and prevents oscillations. The VIN 3 4 recommended value of RC is 50 Ω for a closed-loop gain of 2. R1 8 This resistor introduces a zero in the open-loop response and DISABLE RC C1 must be kept low so that this zero occurs at a higher frequency. C5 0.1F The purpose of the compensation network is to decrease the C4 CC open-loop gain. If the resistance becomes too large, the gain is 10F reduced to the resistor value, and not necessarily to 0 Ω, which –VS 04511-0-061 ivsa wluhea rta an gsien igsl e0 cΩap taoc 5it0o rΩ w. ould do over frequency. Typical Figure 59. Wideband Noninverting Gain Configuration (SOIC) C1—To lower the impedance of R , C1 is placed in parallel with C RF and RG—The feedback resistor and the gain set resistor RC. C1 is not required, but greatly reduces peaking at low determine the noise gain of the amplifier; typical RF values closed-loop gains. The typical value range is 0 pF to 2 pF. range from 250 Ω to 499 Ω. C2 and C3—Bypass capacitors are connected between both supplies for optimum distortion and PSRR performance. These capacitors should be placed as close as possible to the supply pins of the amplifier. For C3 and C5, a 0508 case size should be used. The 0508 case size offers reduced inductance and better frequency response. C4 and C2—Electrolytic bypass capacitors. Rev. E | Page 16 of 26

Data Sheet AD8099 RECOMMENDED VALUES Table 4. Recommended Values and AD8099 Performance Feedback Compensation −3 dB SS Output Noise Total Output Noise Network Values Network Values Bandwidth Slew Rate Peaking (AD8099 Only) Including Resistors Gain Package RF RG RS CF RC CC C1 (MHz) (V/µs) (dB) (nV/√Hz) (nV/√Hz) −1, 2 SOIC 250 250 50 1.5 50 4 1.5 440/700 515 0.3/3.1 2.1 4 2 LFCSP 250 250 50 0.5 50 5 2 700 475 3.2 2.1 4 −1 LFCSP 250 250 50 1.0 50 5 2 420 475 0.8 2.1 4 5 LFCSP/SOIC 499 124 20 0.5 50 1 0 510 735 1.4 4.9 8.6 10 LFCSP/SOIC 499 54 0 0 0 0.5 0 550 1350 0.8 9.6 13.3 20 LFCSP/SOIC 499 26 0 0 0 0 0 160 1450 0 19 23.3 CIRCUIT CONFIGURATIONS CF 1pF +VS C2 Figure 60 through Figure 66 show typical schematics for the 10µF RF AD8099 in various gain configurations. Table 4 data was 250Ω C3 collected using the schematics shown in Figure 60 through 0.1µF Figure 66. Resistor R1, as shown in Figure 60 through Figure 66, 2R50GΩ 2 VIN 3 8 inso trhme atle ostp eeqrautiiponm, ebnutt ties rsmhoinwant iionn t hrees sicshtoerm. Rat1ic iss fnoor tc oremqpulierteedn efossr. R501Ω 5R0SΩ 4AD805996 7 R1kLΩ VOUT 1.C5pFF 1 RC C1 RF +VS 1C0µ2F DISABLE 0.C15µF 50Ω 2pF 250Ω C3 CC VIN50RΩ1 25R5R00GSΩΩ 32AD810499750.16µF R1kLΩVOUT Figure 62. Amplifier1 CC0oµ4Fnf–igVuSratio5npF for LFCSP, Gain = −1 04511-0-108 8 CF RC C1 0.5pF DISABLE 50Ω 1.5pF +VS C2 C5 10µF 0.1µF RF 250Ω C3 C4 CC 0.1µF Figure 60. Amplifier Con1f0iµgFur–aVtSion fo4rp FSOIC Package, Gain = −1 04511-0-116 VIN 25R5R00GSΩΩ 43AD82059986 7 R1kLΩVOUT R1 1 1.C5pFF +VS C2 50DΩISABLE R50CΩ C2p1F RF 10µF 0.C15µF VIN 25R5R00GSΩΩ 23250AΩD810499750.C163µF R1kLΩ VOUT Figure 63. Amplifie1rC0 Cµ4oFn–fVigSuratC5iopCnF for LFCSP, Gain = +2 04511-0-053 R1 8 50Ω RC C1 DISABLE 50Ω 1.5pF C5 0.1µF CC C4 4pF 10µF –VS 04511-0-054 Figure 61. Amplifier Configuration for SOIC Package, Gain = +2 Rev. E | Page 17 of 26

AD8099 Data Sheet CF +VS C2 0.5pF +VS C2 RF 10F 10F 499 RF C3 499 C3 RG 0.1F 0.1F 26 FB 1R24G FB – +V – +V AD8099 VO VOUT VIN 2R0S +AD80–9V9CC VO R1kL VOUT VIN R501 + D –V CC R1kL R1 D 50 RC DISABLE C5 DISABLE 50 0.1F C5 0.1F C4 CC 10F 1C04F–VS 1pF 04511-0-055 Figure 66. Amplifier Configuration–V fSor LFCSP and SOIC Packages, Gain04511-0-057 = +20 Figure 64. Amplifier Configuration for LFCSP and SOIC Package, Gain = +5 +VS C2 10F RF 499 C3 0.1F 5R4G FB – +V AD8099 VO VOUT VIN + –V CC R1kL R1 D 50 DISABLE C5 0.1F CC C4 0.5pF 10F –VS 04511-0-056 Figure 65. Amplifier Configuration for LFCSP and SOIC Packages, Gain = +10 Rev. E | Page 18 of 26

Data Sheet AD8099 PERFORMANCE vs. COMPONENT VALUES 12 RS = 0 11 The influence that each component has on the AD8099 10 frequency response can be seen in Figure 68 to Figure 73. In 9 Figure 68 to Figure 73, all component values are held constant, B) except for the individual component shown, which is varied. N (d 8 AI 7 For example, in the R performance plot (Figure 69), all G components are held Sc onstant except RS, which is varied from LOOP 65 RS = 50 0 Ω to 50 Ω. Figure 69 clearly indicates that R has a major D- S SE 4 influence on the peaking and the bandwidth of the AD8099. O CL 3 RS = 20 CF +VS C2 2 VGS = = + ±25V 10F 1 RLOAD = 1k RF 0.C13F 01SOICPACKAGE10 FREQUENCY1 0(0MHz) 1000 10000 04511-0-034 RG 2 1 7 Figure 69. Frequency Response for Various Values of RS VIN RS 3AD804995 6 VOUT 109 VGS = = +±25V R1 8 RLOAD = 1k 8 SOIC PACKAGE DISABLE RC C1 C5 B) 7 0.1F d N ( 6 RC = 50 C4 CC GAI 5 10F P O O 4 SOIC PINOUT SHOWN –VS 04511-0-117 CLOSED-L 32 RC = 20 Figure 67. Complete Noninverting Amplifier Configuration for SOIC Package 1 with Compensation Network 0 109 RF = RG = 200 –11 10 FREQUENCY1 0(R0MCH =z) 35 1000 3000 04511-0-030 8 Figure 70. Frequency Response for Various Values of RC B) 7 d N ( 6 AI P G 5 RF = RG = 300 O O 4 ED-L 3 RF = RG = 250 S LO 2 C 1 VGS = = + ±25V 0 RLOAD = 1k –11SOICPACKAGE10 FREQUENCY1 0(0MHz) 1000 3000 04511-0-032 Figure 68. Frequency Response for Various Values of RF and RG Rev. E | Page 19 of 26

AD8099 Data Sheet 10 10 9 CF = 0.5pF 9 VGS = = +±25V CC = 3pF RLOAD = 1k 8 8 SOIC PACKAGE CC = 4pF B) 7 B) 7 d d AIN ( 6 CF = 1pF AIN ( 6 G 5 G 5 OOP 4 CF = 1.5pF OOP 4 CC = 5pF L L ED- 3 ED- 3 S S LO 2 LO 2 C C 1 VS =±5V 1 G = +2 0 RLOAD = 1k 0 –11SOIC PACKAGE10 FREQUENCY1 (0M0Hz) 1000 3000 04511-0-058 –11 10 FREQUENCY1 (0M0Hz) 1000 3000 04511-0-024 Figure 71. Frequency Response for Various Values of CF Figure 73. Frequency Response for Various Values of CC 9 8 C1 = 0pF 7 B) 6 d N ( 5 AI G 4 P O O 3 L ED- 2 S LO 1 C C1 = 1.5pF 0 VS =±5V G = +2 –1 RLOAD = 1k –21SOIC PACKAGE10 FREQUENCY1 (0M0Hz) C1 = 2pF1000 3000 04511-0-020 Figure 72. Frequency Response for Various Values of C1 Rev. E | Page 20 of 26

Data Sheet AD8099 TOTAL OUTPUT NOISE CALCULATIONS AND INPUT BIAS CURRENT AND DC OFFSET DESIGN In high noise gain configurations, the effects of output offset To analyze the noise performance of an amplifier circuit, voltage can be significant, even with low input bias currents and the individual noise sources must be identified. A user must input offset voltages. Figure 75 shows a comprehensive offset then determine if the source has a significant contribution to voltage model, which can be used to determine the referred to overall noise performance of the amplifier. To simplify the output (RTO) offset voltage of the amplifier or referred to input noise calculations, this data sheet works with noise spectral (RTI) offset voltage. densities rather than actual voltages to leave bandwidth out R2 of the expressions (noise spectral density, which is generally GAIN FROM = "A" TO OUTPUT expressed in nV/√Hz, is equivalent to the noise in a 1 Hz NOISE GAIN = bandwidth). B R1 IB– NG = 1 +R2 R1 The noise model shown in Figure 74 has six individual noise VOS VOUT sources: the Johnson noise of the three resistors, the op amp A R3 IB+ voltage noise, and the current noise in each input of the amplifier. GAIN FROM =–R2 "B" TO OUTPUT R1 Each noise source has its own contribution to the noise at the output. Noise is generally specified referred to input (RTI), but OFFSET (RTO) = VOS 1 +RR21 + IB+× R3 1 +RR12 – IB–× R2 it is often simpler to calculate the noise referred to the output OFFSET (RTI) = VOS + IB+× R3– IB– RR11×+ RR22 (RTO) and then divide by the noise gain to obtain the RTI noise. BAolll trzemsisatnonr’ss hCaovnes ata Jnoth (n1s.o3n8 ×n o1i0se−2 o3 fJ /√K()4,k TB TisR th),e w ahbesorelu kt ei s OFFSET (RFOTIR) =B VIAOSS C U RIFR IEB+N =T ICBA– NACNEDL RL3A T = I O RRN11:×+ RR22 04511-0-071 temperature in Kelvin, B is the bandwidth in Hz, and R is Figure 75. Op Amp Total Offset Voltage Model the resistance in ohms. A simple relationship, which is easy to For RTO calculations, the input offset voltage and the voltage remember, is that a 50 Ω resistor generates a Johnson noise of generated by the bias current flowing through R3 are multiplied 1 nV√Hz at 25°C. The AD8099 amplifier has roughly the same by the noise gain of the amplifier. The voltage generated by I equivalent noise as a 50 Ω resistor. B− through R2 is summed together with the previous offset voltages to VN, R2 R2 arrive at a final output offset voltage. The offset voltage can also GAIN FROM = be referred to the input (RTI) by dividing the calculated output 4kTR2 "A" TO OUTPUT NOISE GAIN = offset voltage by the noise gain. B VN, R1 R1 IN– VN NG = 1 +RR12 As seen in Figure 75, if IB+ and IB– are the same and R3 equals 4kTR1 the parallel combination of R1 and R2, then the RTI offset A VN, R3 R3 IN+ VOUT voltage can be reduced to only VOS. This is a common method GAIN FROM =–R2 used to reduce output offset voltage. Keeping resistances low 4kTR3 "B" TO OUTPUT R1 helps to minimize offset error voltage and keeps the voltage noise low. 2 VN2 + 4kTR3 + 4kTR1 R 1 R +2 R2 DISABLE PIN AND INPUT BIAS CANCELLATION 2 2 RRTTIO N NOOISISEE = = NG+IN× +R2RTI3 N2 O+ IISNE–2 RR11 +× RR22 + 4kTR2 R1R +1 R2 04511-0-070 dTDihIsSeaA bAlBeD,L a8En0 p9di9 nr eD idsIu SbcArtoiBouLngE ho tpf titonh ewp ieintrhpfoiunrtm 0b.si7a t sVh cr euoefr rtfehunent c.p tWoioshintesiv;n ee tnshuaebp lpel,y , Figure 74. Op Amp Noise Analysis Model the input bias current is reduced by an approximate factor of 60. In applications where noise sensitivity is critical, care must be However, the input current noise doubles to 5.2 pA/√Hz. Table 5 taken not to introduce other significant noise sources to the outlines the DISABLE pin functionality. amplifier. Each resistor is a noise source. Attention to design, layout, and component selection is critical to maintain low Table 5. DISABLE Pin Truth Table noise performance. A summary of noise performance for the Supply Voltage ±5 V +5 V amplifier and associated resistors can be seen in Table 4. Disable −5 to +2.4 0 to 2.4 Enable Open Open Low Input Bias Current 4.3 to 5 4.3 to 5 Rev. E | Page 21 of 26

AD8099 Data Sheet AVDD DVDD 0.1F 0.1F REF AGND AVDD DGND DVDD +VS C1 REF 10F RF 150 1F 47F C2 0.1F AD7667 1R50G 1 REFGND 2 7 R7 RS AD8099 6 15 IN VIN 50 3 4 5 C6 INGND 8 2.7nF RC C1 DISABLE 50 2pF CC C4 9pF +2.5V 10F 59R01 59R02 0.C15F –VS 04511-0-072 Figure 76. ADC Driver 16-BIT ADC DRIVER Table 6. ADC Driver Performance, f = 20 kHz, C Ultralow noise and distortion performance make the AD8099 VOUT = 2.24 V p-p an ideal ADC driver. Even though the AD8099 is not unity-gain Parameter Measurement (dB) stable, it can be configured to produce a net gain of +1 amplifier, as Second Harmonic Distortion −111.4 shown in Figure 76. This is achieved by combining a gain of +2 Third Harmonic Distortion −103.2 and a gain of −1 for a net gain of +1. The input range of the THD −101.4 ADC is 0 V to 2.5 V. SFDR 102.2 SNR 88.1 Table 6 shows the performance data of the AD8099 and the AD7667, a 1 MSPS 16-bit ADC. Rev. E | Page 22 of 26

Data Sheet AD8099 CIRCUIT CONSIDERATIONS used, they should be stitched together with multiple vias. The returns for the input, output terminations, bypass capacitors, and Optimizing the performance of the AD8099 requires attention R should all be kept as close to the AD8099 as possible. Ground to detail in layout and signal routing of the board. Power supply G vias should be placed at the very end of the component mounting bypassing, parasitic capacitance, and component selection all pad to provide a solid ground return. The output load ground and contribute to the overall performance of the amplifier. The the bypass capacitor grounds should be returned to a common AD8099 features an exposed paddle on the backs of both the point on the ground plane to minimize parasitic inductance and LFCSP and SOIC packages. The exposed paddle provides a low improve distortion performance. The AD8099 packages feature thermal resistive path to the ground plane. For best performance, an exposed paddle. For optimum performance, solder this solder the exposed paddle to the ground plane. paddle to ground. For more information on PCB layout and PCB Layout design considerations, refer to section 7-2 of the 2002 Analog The compensation network is determined by the amplifier Devices Op Amp Applications book. gain requirements. For lower gains, the layout and component Power Supply Bypassing placement are more critical. For higher gains, there are fewer compensation components, which results in a less complex The AD8099 power supply bypassing has been optimized layout. for each gain configuration as shown in Figure 60 through Figure 66 in the Circuit Configurations section. The values Parasitics shown should be used when possible. Bypassing is critical for The area surrounding the compensation pin is very sensitive to stability, frequency response, distortion, and PSRR performance. parasitic capacitance. To realize the full gain bandwidth product The 0.1 µF capacitors shown in Figure 60 through Figure 66 of the AD8099, there should be no trace connected to or within should be as close to the supply pins of the AD8099 as possible close proximity of the external compensation pin for the lowest and the electrolytic capacitors beside them. possible capacitance. When compensation is required, the traces Component Selection to the compensation pin, the negative supply, and the interconnect between components (C , C1, and R in Figure 59) should be Smaller components less than 1206 SMT case size, offer smaller C C made as wide as possible to minimize inductance. mounting pads, which have fewer parasitics and allow for a more compact layout. It is critical for optimum performance that high All ground and power planes under the pins of the AD8099 quality, tight tolerance (where critical), and low drift components should be cleared of copper to prevent parasitic capacitance be used. For example, tight tolerance and low drift is critical in between the input and output pins to ground. A single mount- the selection of the feedback capacitor used in Figure 60. The ing pad on a SOIC footprint can add as much as 0.2 pF of feedback compensation capacitor in Figure 60 is 1.5 pF. This capacitance to ground as a result of not clearing the ground or capacitor should be specified with NPO material. NPO material power plane under the AD8099 pins. Parasitic capacitance can typically has a ±30 ppm/°C change over −55°C to +125°C cause peaking and instability, and should be minimized to temperature range. For a 100°C change, this results in a 4.5 fF ensure proper operation. change in capacitance, compared to an X7R material, which The new pinout of the AD8099 reduces the distance between results in a 0.23 pF change, a 15% change from the nominal value. the output and the inverting input of the amplifier. This helps This can introduce excessive peaking, as shown in Figure 71. to minimize the parasitic inductance and capacitance of the DESIGN TOOLS AND TECHNICAL SUPPORT feedback path, which, in turn, reduces ringing and second harmonic distortion. Analog Devices is committed to the design process by providing Grounding technical support and online design tools. Analog Devices offers technical support via evaluation boards, sample ICs, When possible, ground and power planes should be used. Ground SPICE models, interactive evaluation tools, application notes, and power planes reduce the resistance and inductance of the phone and email support—all available at www.analog.com. power supply feeds and ground returns. If multiple planes are Rev. E | Page 23 of 26

AD8099 Data Sheet OUTLINE DIMENSIONS 5.00 4.90 2.29 4.80 0.356 8 5 6.20 4.00 6.00 3.90 5.80 2.29 3.80 0.457 1 4 FOR PROPER CONNECTION OF 1.27 BSC BOTTOM VIEW THE EXPOSED PAD, REFER TO 3.81 REF THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TOP VIEW SECTION OF THIS DATA SHEET. 1.75 1.65 0.50 45° 1.35 1.25 0.25 0.25 0.17 0.10 MAX SEATING PLANE 0.51 0.05 NOM 8° 1.04 REF 0.31 COPL0A.1N0ARITY 0° 10..2470 COMPLIANTTO JEDEC STANDARDS MS-012-AA 06-02-2011-B Figure 77. 8-Lead Standard Small Outline Package with Exposed Pad [SOIC_N_EP] Narrow Body (RD-8-1) Dimensions shown in millimeters 1.84 3.10 1.74 3.00SQ 2.90 1.64 0.50BSC 5 8 PIN1INDEX EXPOSED 1.55 AREA PAD 1.45 0.50 1.35 0.40 0.30 4 1 PIN1 TOPVIEW BOTTOMVIEW INDICATOR (R0.15) 0.80 FORPROPERCONNECTIONOF 0.75 0.05MAX THEEXPOSEDPAD,REFERTO THEPINCONFIGURATIONAND 0.70 0.02NOM FUNCTIONDESCRIPTIONS COPLANARITY SECTIONOFTHISDATASHEET. SEATING 0.30 0.08 PLANE 0.25 0.203REF 0.C2O0MPLIANTTOJEDECSTANDARDSMO-229-WEED 12-07-2010-A Figure 78. 8-Lead Lead Frame Chip Scale Package [LFCSP] 3 mm × 3 mm Body and 0.75 mm Package Height (CP-8-13) Dimensions shown in millimeters ORDERING GUIDE Model1 Temperature Range Package Description Package Option Branding Ordering Quantity AD8099ARDZ −40°C to +125°C 8-Lead SOIC_N_EP RD-8-1 98 AD8099ARDZ-REEL −40°C to +125°C 8-Lead SOIC_N_EP RD-8-1 2,500 AD8099ARDZ-REEL7 −40°C to +125°C 8-Lead SOIC_N_EP RD-8-1 1,000 AD8099ACPZ-R2 −40°C to +125°C 8-Lead LFCSP CP-8-13 HDB 250 AD8099ACPZ-REEL −40°C to +125°C 8-Lead LFCSP CP-8-13 HDB 5,000 AD8099ACPZ-REEL7 −40°C to +125°C 8-Lead LFCSP CP-8-13 HDB 1,500 1 Z = RoHS Compliant Part. Rev. E | Page 24 of 26

Data Sheet AD8099 NOTES Rev. E | Page 25 of 26

AD8099 Data Sheet NOTES ©2003–2016 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D04511-0-7/16(E) Rev. E | Page 26 of 26