Dual 160 MHz Rail-to-Rail Amplifier AD8042 FEATURES CONNECTION DIAGRAM Single AD8041 and quad AD8044 also available Fully specified at +3 V, +5 V, and ±5 V supplies OUT1 1 8 +VS Output swings to within 30 mV of either rail –IN1 2 7 OUT2 Input voltage range extends 200 mV below ground +IN1 3 6 –IN2 No phase reversal with inputs 0.5 V beyond supplies LHoigwh p sopweeedr oafn 5d. 2fa mstA s eptetrl ianmg polnif 5ie Vr –VS 4 AD8042 5 +IN2 01059-001 Figure 2. 8-Lead PDIP and 8-Lead SOIC_N 160 MHz, −3 dB bandwidth (G = +1) 200 V/μs slew rate The output voltage swing extends to within 30 mV of each rail, 39 ns settling time to 0.1% providing the maximum output dynamic range. Additionally, it Good video specifications (RL = 150 Ω, G = +2) features gain flatness of 0.1 dB to 14 MHz while offering differential Gain flatness of 0.1 dB to 14 MHz gain and phase error of 0.04% and 0.06° on a single 5 V supply. 0.02% differential gain error This combination of features makes the AD8042 useful for 0.04° differential phase error professional video electronics, such as cameras, video switchers, Low distortion: −64 dBc worst harmonic @ 10 MHz or any high speed portable equipment. The low distortion and Drives 50 mA 0.5 V from supply rails fast settling of the AD8042 make it ideal for buffering single- supply, high speed analog-to-digital converters (ADCs). APPLICATIONS The AD8042 offers a low power supply current of 12 mA Video switchers maximum and can run on a single 3.3 V power supply. These Distribution amplifiers features are ideally suited for portable and battery-powered Analog-to-digital drivers applications where size and power are critical. Professional cameras CCD Imaging systems The wide bandwidth of 160 MHz along with 200 V/μs of slew Ultrasound equipment (multichannel) rate on a single 5 V supply make the AD8042 useful in many general-purpose, high speed applications where single supplies GENERAL DESCRIPTION from +3.3 V to +12 V and dual power supplies of up to ±6 V are needed. The AD8042 is available in 8-lead PDIP and 8-lead The AD8042 is a low power voltage feedback, high speed amplifier SOIC_N packages. designed to operate on +3 V, +5 V, or ±5 V supplies. It has true single-supply capability with an input voltage range extending 15 VS = 5V 200 mV below the negative rail and within 1 V of the positive rail. 12 G = +1 CL = 5pF 9 RL = 2kΩ TO 2.5V G = +1 B) RL = 2kΩTO 2.5V N (d 6 AI 3 G 5.0V P O 0 O L D- –3 E S 2.5V LO –6 C –9 0V ––1125 01059-003 1 10 100 500 1V 1µs 01059-002 Figure 3. FFRreEqQuUeEnNcCyY R (eMspHoz)nse Figure 1. Output Swing: Gain = +1, VS = +5 V Rev. E Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Tel: 781.329.4700 www.analog.com Trademarks and registered trademarks are the property of their respective owners. Fax: 781.461.3113 ©2007 Analog Devices, Inc. All rights reserved.

AD8042 TABLE OF CONTENTS Features..............................................................................................1 Typical Performance Characteristics..............................................7 Applications.......................................................................................1 Applications Information..............................................................12 General Description.........................................................................1 Circuit Description....................................................................12 Connection Diagram.......................................................................1 Driving Capacitive Loads..........................................................12 Revision History...............................................................................2 Overdrive Recovery...................................................................12 Specifications.....................................................................................3 Layout Considerations...............................................................15 Absolute Maximum Ratings............................................................6 Outline Dimensions.......................................................................16 Maximum Power Dissipation.....................................................6 Ordering Guide..........................................................................16 ESD Caution..................................................................................6 REVISION HISTORY 12/07—Rev. D to Rev. E Changes to Figure 1 Caption...........................................................1 Changes to Table 1............................................................................3 Changes to Figure 5..........................................................................7 Changes to Figure 20........................................................................9 Changes to Layout and Figure 35.................................................12 Changes to Figure 38......................................................................13 Changes to Single-Ended-to-Differential Driver Section.........14 Updated Outline Dimensions.......................................................16 3/06—Rev. C to Rev. D Changes to Text Prior to Table 2.....................................................4 8/04—Rev. B to Rev. C Changes to Ordering Guide............................................................5 Changes to Outline Dimensions...................................................15 7/02—Rev. A to Rev. B Changes to Specifications................................................................2 Rev. E | Page 2 of 16

AD8042 SPECIFICATIONS T = 25°C, V = 5 V, R = 2 kΩ to 2.5 V, unless otherwise noted. A S L Table 1. Parameter Conditions Min Typ Max Unit DYNAMIC PERFORMANCE −3 dB Small Signal Bandwidth, V < 0.5 V p-p G = +1 125 160 MHz O Bandwidth for 0.1 dB Flatness G = +2, R = 150 Ω, R = 200 Ω 14 MHz L F Slew Rate G = –1, V = 2 V step 130 200 V/μs OUT Full Power Response V = 2 V p-p 30 MHz O Settling Time to 1% G = –1, V = 2 V step 26 ns OUT Settling Time to 0.1% 39 ns NOISE/DISTORTION PERFORMANCE Total Harmonic Distortion f = 5 MHz, V = 2 V p-p, G = +2, R = 1 kΩ –73 dB C OUT L Input Voltage Noise f = 10 kHz 15 nV/√Hz Input Current Noise f = 10 kHz 700 fA/√Hz Differential Gain Error (NTSC, 100 IRE) G = +2, R = 150 Ω to 2.5 V 0.04 0.06 % L G = +2, R = 75 Ω to 2.5 V 0.04 % L Differential Phase Error (NTSC, 100 IRE) G = +2, R = 150 Ω to 2.5 V 0.06 0.12 Degrees L G = +2, R = 75 Ω to 2.5 V 0.24 Degrees L Worst-Case Crosstalk f = 5 MHz, R = 150 Ω to 2.5 V –63 dB L DC PERFORMANCE Input Offset Voltage 3 9 mV T to T 12 mV MIN MAX Offset Drift 12 μV/°C Input Bias Current 1.2 3.2 μA T to T 4.8 μA MIN MAX Input Offset Current 0.2 0.5 μA Open-Loop Gain R = 1 kΩ 90 100 dB L T to T 90 dB MIN MAX INPUT CHARACTERISTICS Input Resistance 300 kΩ Input Capacitance 1.5 pF Input Common-Mode Voltage Range −0.2 to +4 V Common-Mode Rejection Ratio V = 0 V to 3.5 V 68 74 dB CM OUTPUT CHARACTERISTICS Output Voltage Swing R = 10 kΩ to 2.5 V 0.03 to 4.97 V L R = 1 kΩ to 2.5 V 0.10 to 4.9 0.05 to 4.95 V L R = 50 Ω to 2.5 V 0.4 to 4.4 0.36 to 4.45 V L Output Current T to T , V = 0.5 V to 4.5 V 50 mA MIN MAX OUT Short-Circuit Current Sourcing 90 mA Sinking 100 mA Capacitive Load Drive G = +1 20 pF POWER SUPPLY Operating Range 3 12 V Quiescent Current (Per Amplifier) 5.5 6.4 mA Power Supply Rejection Ratio V = 0 V to −1 V, or V = 5 V to 6 V 72 80 dB S– S+ OPERATING TEMPERATURE RANGE −40 +85 °C Rev. E | Page 3 of 16

AD8042 T = 25°C, V = 3 V, R = 2 kΩ to 1.5 V, unless otherwise noted. A S L Table 2. Parameter Conditions Min Typ Max Unit DYNAMIC PERFORMANCE −3 dB Small Signal Bandwidth, V < 0.5 V p-p G = +1 120 140 MHz O Bandwidth for 0.1 dB Flatness G = +2, R = 150 Ω, R = 200 Ω 11 MHz L F Slew Rate G = −1, V = 2 V step 120 170 V/μs OUT Full Power Response V = 2 V p-p 25 MHz O Settling Time to 1% G = −1, V = 1 V step 30 ns OUT Settling Time to 0.1% 45 ns NOISE/DISTORTION PERFORMANCE Total Harmonic Distortion f = 5 MHz, V = 2 V p-p, G = −1, R = 100 Ω –56 dB C OUT L Input Voltage Noise f = 10 kHz 16 nV/√Hz Input Current Noise f = 10 kHz 500 fA/√Hz Differential Gain Error (NTSC, 100 IRE) G = +2, R = 150 Ω to 1.5 V, Input V = 1 V 0.10 % L CM R = 75 Ω to 1.5 V, Input V = 1 V 0.10 % L CM Differential Phase Error (NTSC, 100 IRE) G = +2, R = 150 Ω to 1.5 V, Input V = 1 V 0.12 Degrees L CM R = 75 Ω to 1.5 V, Input V = 1 V 0.27 Degrees L CM Worst-Case Crosstalk f = 5 MHz, R = 1 kΩ to 1.5 V –68 dB L DC PERFORMANCE Input Offset Voltage 3 9 mV T to T 12 mV MIN MAX Offset Drift 12 μV/°C Input Bias Current 1.2 3.2 μA T to T 4.8 μA MIN MAX Input Offset Current 0.2 0.6 μA Open-Loop Gain R = 1 kΩ 90 100 dB L T to T 90 dB MIN MAX INPUT CHARACTERISTICS Input Resistance 300 kΩ Input Capacitance 1.5 pF Input Common-Mode Voltage Range –0.2 to +2 V Common-Mode Rejection Ratio V = 0 V to 1.5 V 66 74 dB CM OUTPUT CHARACTERISTICS Output Voltage Swing R = 10 kΩ to 1.5 V 0.03 to 2.97 V L R = 1 kΩ to 1.5 V 0.1 to 2.9 0.05 to 2.95 V L R = 50 Ω to 1.5 V 0.3 to 2.6 0.25 to 2.65 V L Output Current T to T , V = 0.5 V to 2.5 V 50 mA MIN MAX OUT Short-Circuit Current Sourcing 50 mA Sinking 70 mA Capacitive Load Drive G = +1 17 pF POWER SUPPLY Operating Range 3 12 V Quiescent Current (Per Amplifier) 5.5 6.4 mA Power Supply Rejection Ratio V = 0 V to –1 V, or V = 3 V to 4 V 68 80 dB S– S+ OPERATING TEMPERATURE RANGE 0 70 °C Rev. E | Page 4 of 16

AD8042 T = 25°C, V = ±5 V, R = 2 kΩ to 0 V, unless otherwise noted. A S L Table 3. Parameter Conditions Min Typ Max Unit DYNAMIC PERFORMANCE −3 dB Small Signal Bandwidth, V < 0.5 V p-p G = +1 125 170 MHz O Bandwidth for 0.1 dB Flatness G = +2, R = 150 Ω, R = 200 Ω 18 MHz L F Slew Rate G = −1, V = 2 V step 145 225 V/μs OUT Full Power Response V = 2 V p-p 35 MHz O Settling Time to 1% G = −1, V = 2 V step 22 ns OUT Settling Time to 0.1% 32 ns NOISE/DISTORTION PERFORMANCE Total Harmonic Distortion f = 5 MHz, V = 2 V p-p, G = +2, R = 1 kΩ –78 dB C O L Input Voltage Noise f = 10 kHz 15 nV/√Hz Input Current Noise f = 10 kHz 700 fA/√Hz Differential Gain Error (NTSC, 100 IRE) G = +2, R = 150 Ω 0.02 0.05 % L G = +2, R = 75 Ω 0.02 % L Differential Phase Error (NTSC, 100 IRE) G = +2, R = 150 Ω 0.04 0.10 Degrees L G = +2, R = 75 Ω 0.12 Degrees L Worst-Case Crosstalk f = 5 MHz, R = 150 Ω –63 dB L DC PERFORMANCE Input Offset Voltage 3 9.8 mV T to T 14 mV MIN MAX Offset Drift 12 μV/°C Input Bias Current 1.2 3.2 μA T to T 4.8 μA MIN MAX Input Offset Current 0.2 0.6 μA Open-Loop Gain R = 1 kΩ 90 94 dB L T to T 86 dB MIN MAX INPUT CHARACTERISTICS Input Resistance 300 kΩ Input Capacitance 1.5 pF Input Common-Mode Voltage Range −5.2 to +4 V Common-Mode Rejection Ratio V = –5 V to +3.5 V 66 74 dB CM OUTPUT CHARACTERISTICS Output Voltage Swing R = 10 kΩ −4.97 to +4.97 V L R = 1 kΩ −4.8 to +4.8 −4.9 to +4.9 V L R = 50 Ω −4 to +3.2 −4.2 to +3.5 V L Output Current T to T , V = −4.5 V to +4.5 V 50 mA MIN MAX OUT Short-Circuit Current Sourcing 100 mA Sinking 100 mA Capacitive Load Drive G = +1 25 pF POWER SUPPLY Operating Range 3 12 V Quiescent Current (Per Amplifier) 6 7 mA Power Supply Rejection Ratio V = −5 V to −6 V, or V = 5 V to 6 V 68 80 dB S– S+ OPERATING TEMPERATURE RANGE −40 +85 °C Rev. E | Page 5 of 16

AD8042 ABSOLUTE MAXIMUM RATINGS Table 4. Exceeding a junction temperature of 175°C for an extended Parameter Rating period can result in device failure. Supply Voltage 12.6 V Internal Power Dissipation1 While the AD8042 is internally short-circuit protected, this 8-Lead PDIP (N) 1.3 W may not be sufficient to guarantee that the maximum junction 8-Lead SOIC_N (R) 0.9 W temperature (150°C) is not exceeded under all conditions. To Input Voltage (Common Mode) ±V ± 0.5 V ensure proper operation, it is necessary to observe the S Differential Input Voltage ±3.4 V maximum power derating curves. Output Short-Circuit Duration Observe Power 2.0 Derating Curves 8-LEAD PLASTIC-DIP PACKAGE Storage Temperature Range (N, R) −65°C to +125°C W) Lead Temperature (Soldering, 10 sec) 300°C N ( O 1.5 1 Specification is for the device in free air: PATI TJ = 150°C 88--LLeeaadd SPODIICP:_ θNJ:A θ=J A9 =0 °1C5/5W°C /W. DISSI R 1.0 E Stresses above those listed under Absolute Maximum Ratings W O may cause permanent damage to the device. This is a stress M P 8-LEAD SOIC PACKAGE U rating only; functional operation of the device at these or any M 0.5 XI other conditions above those indicated in the operational MA smecatxiiomnu omf t rhaitsi nspge ccoifnicdaittiioonns i sf onro etx itmenpdlieedd .p Eexripoodssu mrea tyo aafbfescotl ute 0 01059-004 –50 –40 –30 –20 –10 0 10 20 30 40 50 60 70 80 90 device reliability. AMBIENT TEMPERATURE (°C) Figure 4. Maximum Power Dissipation vs. Temperature MAXIMUM POWER DISSIPATION The maximum power that can be safely dissipated by the ESD CAUTION AD8042 is limited by the associated rise in junction temperature. The maximum safe junction temperature for plastic encapsulated devices is determined by the glass transition temperature of the plastic, approximately 150°C. Exceeding this limit temporarily can cause a shift in parametric performance due to a change in the stresses exerted on the die by the package. Rev. E | Page 6 of 16

AD8042 TYPICAL PERFORMANCE CHARACTERISTICS 100 100 VS = 5V VS = 5V 90 T = 25°C T = 25°C 140 PARTS, SIDE 1 & 2 95 80 MEAN = –1.52mV STD DEVIATION = 1.15 70 SAMPLE SIZE = 280 B) CY 60 (140 AD8042s) AIN (d 90 N G UE 50 P 85 Q O E O R 40 L F N- E 80 30 P O 20 75 100 01059-005 70 01059-008 –6 –5 –4 –3 –2 –1 0 1 2 3 4 5 6 0 250 500 750 1000 1250 1500 1750 2000 VOS (mV) LOAD RESISTANCE (Ω) Figure 5. Typical Distribution of VOS Figure 8. Open-Loop Gain vs. RL to 2.5 V 30 VS = 5V 100 MEAN = –12.6µV/°C VS = 5V 25 STD DEVIATION = 2.02µV/°C RL = 1kΩ SAMPLE SIZE = 60 98 20 B) 96 UENCY 15 GAIN (d 94 FREQ 10 N-LOOP 92 E P O 90 5 0 –18 –16 –14 –12 –10 –8 –6 –4 –2 0 01059-006 8886 01059-009 VOS DRIFT (µV/°C) –40 –20 0 20 40 60 80 TEMPERATURE (°C) Figure 6. VOS Drift Over −40°C to +85°C Figure 9. Open-Loop Gain vs. Temperature 0 VS = 5V 100 –0.2 VCM = 0V VS = 5V –0.4 90 A) RL = 500Ω TO 2.5V CURRENT (µ –––100...086 GAIN (dB) 80 BIAS –1.2 OOP 70 RL = 50Ω TO 2.5V NPUT –1.4 PEN-L 60 I –1.6 O ––21..08–40 –30 –20 –10 0 10 20 30 40 50 60 70 80 90 01059-007 5400 01059-010 TEMPERATURE (°C) 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 Figure 7. IB vs. Temperature OUTPUT VOLTAGE (V) Figure 10. Open-Loop Gain vs. Output Voltage Rev. E | Page 7 of 16

AD8042 0.04 NTSC SUBCARRIER (3.579MHz) VS = +5V SE (nV/ Hz) 310000 DIFFERENTIALGAIN ERROR (%) 000...0001320 GRL = = + 1250Ω TO 2GRV.5SL V= == + ±1255V0Ω OI 30 N E –0.01 G 0.05 INPUT VOLTA 1031 01059-011 DIFFERENTIALPHASE ERROR (Degrees)–00000.....00000143210 VGRSL = == + +12550VΩ TO 2.5V VGRSL = == + ±1255V0Ω 01059-014 10 100 1k 10k 100k 1M 10M 100M 1G 0 10 20 30 40 50 60 70 80 90 100 FREQUENCY (Hz) MODULATING RAMP LEVEL (IRE) Figure 11. Input Voltage Noise vs. Frequency Figure 14. Differential Gain and Phase Errors –30 0.6 VS = 5V Bc) –40 RVSL == 31V00, ΩA VT O= –11.5,V 0.5 GRF = = + 2200Ω N (d 0.4 RL = 150Ω TO 2.5V ORTIO –50 RVSL == 51V00, ΩA VT O= +22.5,V N (dB) 0.3 RMONIC DIST ––6700 RVSL == 51V00, ΩA VT O= +21.5,V MALIZED GAI 00..210 14MHz A R H –80 O –0.1 L N OTA –90 RVSL == 15VkΩ, A TVO = 2 +.52V, –0.2 T –100 RVSL == 51VkΩ, A TVO = 2 +.51V, 01059-012 ––00..34 01059-015 1 2 3 4 5 6 7 8 910 1 10 100 500 FUNDAMENTAL FREQUENCY (MHz) FREQUENCY (MHz) Figure 12. Total Harmonic Distortion vs. Frequency Figure 15. 0.1 dB Gain Flatness –30 120 VS = 5V, G = +2, VS = 5V –40 RL = 1kΩ TO 2.5V 100 GRF = = + 2200Ω 80 RL = 150Ω TO 2.5V Bc) –50 10MHz B) 60 GAIN 45 WORST HARMONIC (d ––––67890000 5MHz 1MHz OPEN-LOOP GAIN (d–2420000 PHASE 0–––4915035PHASE (Degrees) –40 –180 ––111000 01059-013 ––6800 ––222750 01059-016 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 0.01 0.1 1 10 100 500 OUTPUT VOLTAGE (V p-p) FREQUENCY (MHz) Figure 13. Worst Harmonic vs. Output Voltage Figure 16. Open-Loop Gain and Phase vs. Frequency Rev. E | Page 8 of 16

AD8042 10 60 86 VGCRSLL = === + 5251VpkΩF TO 2.5V T = +85°C 55 GRCLL = == – 251kpΩF TO MIDPOINT VS = +3V, 0.1% B) 50 N (d 4 ns) LOOP GAI 20 T = –40°C T = +25°C NG TIME ( 4450 VS = +5V, 0.1% VS = +3V, 1% D- –2 LI LOSE –4 SETT 35 VS = ±5V, 0.1% C 30 –6 –1–08 01059-017 2250 VVSS == +±55VV,, 11%% 01059-020 1 10 100 500 0.5 1.0 1.5 2.0 FREQUENCY (MHz) INPUT STEP (V) Figure 17. Closed-Loop Frequency Response vs. Temperature Figure 20. Settling Time vs. Input Voltage 12 108 GCRLL = == + 521pkΩF VVRSSL ==A N++D35VV CL TO 1.5V dB) –100 TEST 1C.0IR2kCΩUINITC:M 1.02kΩ OUT VS = 5V OOP GAIN (dB) 642 RL AND CL TO 2.5V VS = ±5V DE REJECTION ( –––234000 1.02kΩ 1.02kΩ D-L 0 MO –50 SE N- LO –2 MO –60 C M –4 CO –70 ––68 01059-018 ––8900 01059-021 1 10 100 500 10k 100k 1M 10M 100M 500M FREQUENCY (MHz) FREQUENCY (Hz) Figure 18. Closed-Loop Frequency Response vs. Supply Figure 21. Common-Mode Rejection vs. Frequency VS = 5V 0.8 100 G = +1 VS = 5V RBT = 50Ω E (V) 0.7 5V – VOH (+125°C) ANCE (Ω) 10 RBT RBT = 0Ω VOLTAG 00..65 55VV –– VVOOHH ((+–5255°°CC)) T RESIST 1 VOUT URATION 0.4 PU AT 0.3 OUT 0.1 UT S 0.2 TP +VOL (+125°C) U 0.01 01059-019 O 0.10 ++VVOOLL ((+–5255°°CC)) 01059-022 0.01 0.1 1 10 100 500 0 5 10 15 20 25 30 35 40 45 50 FREQUENCY (MHz) LOAD CURRENT (mA) Figure 19. Output Resistance vs. Frequency Figure 22. Output Saturation Voltage vs. Load Current Rev. E | Page 9 of 16

AD8042 12.0 50 VS = ±5V VS = 5V 11.5 VOUT = 100mV STEP 40 11.0 A) G = +2 Y CURRENT (m 1100..50 VVSS == ++53VV ERSHOOT (%) 3200 L 9.5 V PP O G = +3 U S 9.0 10 88..50 01059-023 0 01059-026 –40 –30 –20 –10 0 10 20 30 40 50 60 70 80 90 0 20 40 60 80 100 120 140 160 180 200 TEMPERATURE (°C) LOAD CAPACITANCE (pF) Figure 23. Supply Current vs. Temperature Figure 26. Overshoot vs. Load Capacitance 10 6 VS = 5V VS = 5V 0 5 RF = 2kΩ RL = 2kΩ to 2.5V –10 4 –20 dB) 3 N ( G = +2 RR (dB) ––3400 –PSRR ZED GAI 21 PS –50 ALI 0 +PSRR RM G = +2 –60 NO –1 G = +10 RF = 200Ω –70 –2 G = +5 ––8900 01059-024 ––34 01059-027 10k 100k 1M 10M 100M 500M 1 10 100 500 FREQUENCY (Hz) FREQUENCY (MHz) Figure 24. PSRR vs. Frequency Figure 27. Closed-Loop Gain vs. Frequency Response 10 –10 9 VRGSL = == – ±215kVΩ –20 GVVSI N= = =+ 520V.6V p-p 8 –30 RF = 1kΩ AGE (V p-p) 76 LK (dB) ––5400 VVOOUUTT12,RL = 1VV5OO0ΩUUTT T12O, R2.L5 V= 1kΩ TO 2.5V OLT 5 STA –60 V S UT 4 RO –70 P C OUT 32 ––9800 VVOOUUTT21,RL = 150Ω TO 2.5V 10 01059-025 ––111000 VVOOUUTT21,RL = 1kΩ TO 2.5V 01059-028 0.1 1 10 100 0.1 1 10 100 200 FREQUENCY (MHz) FREQUENCY (MHz) Figure 25. Output Voltage vs. Frequency Figure 28. Crosstalk (Output-to-Output) vs. Frequency Rev. E | Page 10 of 16

AD8042 5V 4.770V GVS = = – 51V 2.6V AVSV == 51V RL = 150Ω TO 2.5V VIN = 100mV p-p 4V CL = 5pF RL = 1kΩ TO 2.5V 3V 2.5V 2V 1V 0V 0.5V 0.160V 200µs 01059-029 2.4V 25mV 10ns 01059-032 Figure 29. Output Swing with Load Reference to Supply Midpoint Figure 32. 100 mV Pulse Response, VS = 5 V 5V VS = 5V G = –1 G = –1 RL = 2kΩ TO 1.5V RL = 150Ω TO GND 4V 4.59V 3.0V 3V 1.5V 2V 1V 0V 0.035V 0V 0.5V 200µs 01059-030 0.5V 1µs 01059-033 Figure 30. Output Swing with Load Reference to Negative to Supply Figure 33. Rail-to-Rail Output Swing, VS = 3 V 4.5V AV = 2 AV = 1 VS = 5V 1.6V VS = 3V CL = 5pF VIN = 100mV p-p RL = 1kΩ TO 2.5V CL = 5pF 3.5V VIN = 1V p-p RL = 1kΩ TO 1.5V 2.5V 1.5V 1.5V 0.5V 0.5V 10ns 01059-031 1.4V 25mV 10ns 01059-034 Figure 31. 1 V Pulse Response, VS = 5 V Figure 34. 100 mV Pulse Response, VS = 3 V Rev. E | Page 11 of 16

AD8042 APPLICATIONS INFORMATION CIRCUIT DESCRIPTION DRIVING CAPACITIVE LOADS The AD8042 is fabricated on the Analog Devices, Inc., The capacitive load drive of the AD8042 can be increased by proprietary eXtra-Fast Complementary Bipolar (XFCB) adding a low valued resistor in series with the load. Figure 36 process, which enables the construction of PNP and NPN shows the effects of a series resistor on capacitive drive for transistors with similar fs in the 2 GHz to 4 GHz region. The varying voltage gains. As the closed-loop gain is increased, the t process is dielectrically isolated to eliminate the parasitic and larger phase margin allows for larger capacitive loads with less latch-up problems caused by junction isolation. These features overshoot. Adding a series resistor with lower closed-loop gains allow the construction of high frequency, low distortion accomplishes the same effect. For large capacitive loads, the amplifiers with low supply currents. This design uses a frequency response of the amplifier is dominated by the roll-off differential output input stage to maximize bandwidth and of the series resistor and capacitive load. headroom (see Figure 35). The smaller signal swings required 1000 on the first stage outputs (nodes SIP, SIN) reduce the effect of VS = 5V 200mV STEP WITH 90% OVERSHOOT nonlinear currents due to junction capacitances and improve the distortion performance. With this design, harmonic distortion RS RS = 5Ω of better than −77 dB @ 1 MHz into 100 Ω with V = 2 V p-p F) (gain = +2) on a single 5 V supply is achieved. OUT AD (p CL LO RS = 0Ω VCC VE 100 I1R26 I10 R39 I2 I3 Q25 Q50 I9 CITI Q36 PA Q4 Q5 Q51 Q39 I5 CA R15 R2 Q40 Q23 VEE RS = 20Ω VVIINNNP Q13 Q17 VEE Q22Q7 QR2213 RQ2727Q31 C3 VOUT 101 2 3 4 501059-037 SIP SIN C9 CLOSED-LOOP GAIN (V/V) Figure 36. Capacitive Load Drive vs. Closed-Loop Gain Q2 Q11 Q8 Q3 Q24 Q47 I8 OVERDRIVE RECOVERY VEE C7 R5 R21 R3 I7 VCC 01059-036 Overdrive of an amplifier occurs when the output and/or input Figure 35. Simplified Schematic range are exceeded. The amplifier must recover from this overdrive condition. As shown in Figure 37, the AD8042 recovers within The rail-to-rail output range of the AD8042 is provided by a 30 ns from negative overdrive and within 25 ns from positive complementary common-emitter output stage. High output overdrive. drive capability is provided by injecting all output stage predriver currents directly into the bases of the output devices Q8 and Q36. Biasing of Q8 and Q36 is accomplished by I8 and I5, along with a common-mode feedback loop (not shown). This circuit 5.0V topology allows the AD8042 to drive 40 mA of output current with the outputs within 0.5 V of the supply rails. On the input side, the device can handle voltages from 0.2 V 2.5V below the negative rail to within 1.2 V of the positive rail. Exceeding these values does not cause phase reversal; however, the input ESD devices do begin to conduct if the input voltages 0V G = +2 exceed the rails by greater than 0.5 V. VS = 5V 1V RVILN == 15kVΩ p T-pO 2.5V 50ns 01059-035 Figure 37. Overdrive Recovery Rev. E | Page 12 of 16

AD8042 Single-Supply Composite Video Line Driver The other extreme is for a video signal that is full white The two op amps of an AD8042 can be configured as a single- everywhere. The blanking intervals and sync tips of such a supply dual line driver for composite video. The wide signal signal have negative going excursions in compliance with swing of the AD8042 enables this function to be performed composite video specifications. The combination of horizontal without using any type of clamping or dc restore circuit, which and vertical blanking intervals limit such a signal to being at its can cause signal distortion. highest level (white) for only about 75% of the time. Figure 38 shows a schematic for a circuit that is driven by a As a result of the duty cycle variations between the two extremes single composite video source that is ac-coupled, level-shifted presented, a 1 V p-p composite video signal that is multiplied by and applied to both noninverting inputs of the two amplifiers. a gain of 2 requires about 3.2 V p-p of dynamic voltage swing at Each op amp provides a separate 75 Ω composite video output. the output for an op amp to pass a composite video signal of To obtain single-supply operation, ac coupling is used throughout. arbitrary duty cycle without distortion. The large capacitor values are required to ensure that there is Some circuits use a sync tip clamp along with ac coupling to minimal tilting of the video signals due to their low frequency hold the sync tips at a relatively constant level, which lowers the (30 Hz) signal content. The circuit shown was measured to have amount of dynamic signal swing required. However, these a differential gain of 0.06% and a differential phase of 0.06°. circuits can have artifacts, such as sync tip compression, unless The input is terminated in 75 Ω and ac-coupled via CIN to a they are driven by sources with very low output impedance. voltage divider that provides the dc bias point to the input. The AD8042 not only has ample signal swing capability to handle Setting the optimal bias point requires some understanding the dynamic range required without using a sync tip clamp but of the nature of composite video signals and the video also has good video specifications such as differential gain and performance of the AD8042. differential phase when buffering these signals in an ac-coupled +5V configuration. 4.99kΩ 0.1µF 10µF 10µF To test the dynamic range, the differential gain and differential 4.99kΩ 3 8 1000µF C7O5AΩX phase were measured for the AD8042 while the supplies were 1 2 VOUT varied. As the lower supply is raised to approach the video COMVIPDOESOI TINE 1RkFΩ 7R5TΩ R75LΩ signal, the first effect observed is that the sync tips become 0.1µF 75Ω 10kΩ RG compressed before the differential gain and differential phase are 1kΩ adversely affected. Therefore, there must be adequate swing in 220µF the negative direction to pass the sync tips without compression. 5 1000µF 7 6 VOUT As the upper supply is lowered to approach the video, the 4 7R5TΩ R75LΩ differential gain and differential phase was not significantly 0.1µF affected until the difference between the peak video output 1RkΩG 1RkFΩ and the supply reached 0.6 V. Therefore, the highest video level 220µF 01059-038 should be kept at least 0.6 V below the positive supply rail. Figure 38. Single-Supply Composite Video Line Driver Using AD8042 Therefore, it was found that the optimal point to bias the noninverting input is at 2.2 V dc. Operating at this point, the Signals of bounded peak-to-peak amplitude that vary in duty worst-case differential gain is measured at 0.06% and the worst- cycle require larger dynamic swing capability than their peak- case differential phase is 0.06°. to-peak amplitude after ac coupling. As a worst case, the dynamic signal swing required approaches twice the peak-to-peak value. The ac-coupling capacitors used in the circuit at first glance The two bounding cases are for a duty cycle that is mostly low, appear quite large. A composite video signal has a lower frequency but occasionally goes high at a fraction of a percent duty cycle, band edge of 30 Hz. The resistances at the various ac coupling and vice versa. points, especially at the output, are quite small. To minimize phase shifts and baseline tilt, the large value capacitors are required. Composite video is not quite this demanding. One bounding For video system performance that is not to be of the highest extreme is for a signal that is mostly black for an entire frame quality, the value of these capacitors can be reduced by a factor but has a white (full intensity), minimum width spike at least of up to five with only a slightly observable change in the picture once per frame. quality. Rev. E | Page 13 of 16

AD8042 Single-Ended-to-Differential Driver The cable has a characteristic impedance of about 120 Ω. Each Using a cross-coupled, single-ended-to-differential converter driver output is back terminated with a pair of 60.4 Ω resistors (SEDC), the AD8042 makes a good general-purpose differential to make the source look like 120 Ω. The receive end is terminated line driver. This SEDC can be used for applications such as with 121 Ω, and the signal is measured differentially with a pair driving Category-5 (CAT-5) twisted pair wires. Figure 39 shows of scope probes. One channel on the oscilloscope is inverted a configuration for a circuit that performs this function that can and then the signals are added. be used for video transmission over a differential pair or various Figure 40 shows the results of the circuit in Figure 39 driving data communication purposes. 50 meters of CAT-5 cable. +5V 0.1µF 10µF 1V 200mV 50ns VIN 1RkIΩN 3 8 1 1RkFΩ 60.4Ω VIN19000 49.9Ω 2 AMP1 RA 1kΩ 50m AD8042 1RkBΩ 1RkBΩ 121Ω VOUT VOUT RA 10 1kΩ 6 0% 7 60.4Ω 100Ω 5 A–M5VP42 0.1µF 10µF 01059-039 Figure 40. Differential D2r0i0vmerV Frequency Response 01059-040 Figure 39. Single-Ended-to-Differential Twisted Pair Line Driver Single-Supply Differential A/D Driver The single-ended-to-differential converter circuit is also useful Each of the op amps of the AD8042 is configured as a unity gain as a differential driver for video speed, single-ended, differential follower by the feedback resistors (R ). Each op amp output also A input ADCs. Figure 41 is a schematic that shows such a circuit drives the other as a unity gain inverter via R , creating a totally BB differentially driving an AD9220, a 12-bit, 10 MSPS ADC. symmetrical circuit. +5V If the noninverting input of AMP2 is grounded and a small +5V 0.1µF positive signal is applied to the noninverting input of AMP1, the output of AMP1 is driven to saturation in the positive direction and the input of AMP2 is driven to saturation in the VIN 0.1µF 1kΩ 3 8 11kΩ negative direction. This is similar to the way a conventional op 2 +5V +5V +5V amp behaves without any feedback. 1kΩ 0.1µF 0.1µF 0.1µF 28 15 26 If a resistor (RF) is connected from the output of AMP2 to the AD8042 1kΩ 1kΩ DVDD AVDD AVDD noninverting input of AMP1, negative feedback is provided, which lcilkoes eas c tohnev leonotpio. nAanl iinnvpeurtt irnesgi sotpo ra m(RpIN c) omnafikgeusr tahtieo cni rwcuitiht look 2.49kΩ+5V 65 1kΩ 7 VVIINNAB BBOIITTT R12 111432 differential outputs. 4 BIT 3 11 2.49kΩ 0.1µF CAPT BIT 4 10 The gain of this circuit from input to either output is ±RF/RIN, or 0.1µF 10/16 0.1µF AD9220 BIT 5 98 CAPB BIT 6 the single-ended-to-differential gain is 2 × RF/RIN. This gives the 0.1µF 18 BIT 7 7 VREF 6 circuit the advantage of being able to adjust its gain by changing 17 BIT 8 SENSE 5 a single resistor. 22 BIT 9 4 CML BIT 10 0.1µF 3 BIT 11 1 2 CLOCK CLK BIT 12 REFCOM DVSSAVSSAVSS 19 27 25 16 01059-041 Figure 41. AD8042 Differential Driver for the AD9220 12-Bit, 10 MSPS ADC Rev. E | Page 14 of 16

AD8042 The circuit was tested with a 1 MHz input signal and clocked 2kΩ 3kΩ ATT at 10 MHz. An FFT response of the digital output is shown in 6 2718AF 7 93DJ39 Figure 42. VIN 232Ω 5 1/2 1 4 VOUT AD8042 Pin 5 is biased at 2.5 V by the voltage divider and bypassed. 2kΩ 3kΩ This biases each output at 2.5 V. VIN is ac-coupled such that 10 5 V going positive makes VINA go positive and VINB go in 2 IN 1 the negative direction. The opposite happens for a negative 3 1/2 2 7 going VIN. 0.001µF AD8042 1 912Ω 9 6 0.0027µF 34Ω 2kΩ 2kΩ B/DIV) 2kΩ 32 1 249Ω VREC 5d 1/4 AL SCALE (1 9 82 73 64 5 Fig0u.0r0e12 4µk3FΩ. HDSL Line D2rkiΩver AD8044 01059-043 C TI ER LAYOUT CONSIDERATIONS V 01059-042 Tcahree fsuple actitfeiendti ohnig tho sbpoeaerdd p laeyrfoourtm aanndc ceo omf tphoen AenDt 8s0el4e2c trieoqnu. ires HARMONICS (dBc) Proper RF design techniques and low-pass parasitic component FUND FRQ1000977 THD –82.00 2ND –88.34 6TH –99.47 SMPL FRQ10000000 SNR 71.13 3RD –86.74 7TH –91.16 selection are necessary. SINAD 70.79 4TH –99.26 8TH –97.25 SFDR –86.74 5TH –90.67 9TH –91.61 The PCB should have a ground plane covering all unused Figure 42. FFT of the AD9220 Output When Driven by the AD8042 portions of the component side of the board to provide a low HDSL Line Driver impedance path. The ground plane should be removed from the area near the input pins to reduce the stray capacitance. High bit rate digital subscriber line (HDSL) is a popular means of providing data communication at DS1 rates (1.544 Mbps) Chip capacitors should be used for the supply bypassing. One over moderate distances via conventional telephone twisted pair end should be connected to the ground plane and the other wires. In these systems, the transceiver at the customer’s end is within ⅛-inch of each power pin. An additional large (0.47 μF powered sometimes via the twisted pair from a power source at to 10 μF) tantalum electrolytic capacitor should be connected in the central office. Sometimes, it is required to raise the dc voltage parallel, but not necessarily so close to supply current, for fast, of the power source to compensate for IR drops in long lines or large signal changes at the output. lines with narrow gauge wires. The feedback resistor should be located close to the inverting Because of the IR drop, it is highly desirable to keep the power input pin to keep the stray capacitance at this node to a consumption of the customer’s transceiver as low as possible. minimum. Capacitance variations of less than 1 pF at the One means to realize significant power savings is to run inverting input significantly affect high speed performance. the transceiver from a ±5 V supply instead of the more conventional ±12 V. Stripline design techniques should be used for long signal traces (greater than approximately one inch). These should be The high output swing and current drive capability of the designed with a characteristic impedance of 50 Ω or 75 Ω and AD8042 make it ideally suited to this application. Figure 43 be properly terminated at each end. shows a circuit for the analog portion of an HDSL transceiver using the AD8042 as the line driver. Rev. E | Page 15 of 16

AD8042 OUTLINE DIMENSIONS 0.400 (10.16) 0.365 (9.27) 0.355 (9.02) 8 5 0.280 (7.11) 0.250 (6.35) 1 4 0.240 (6.10) 0.325 (8.26) 0.310 (7.87) 0.100 (2.54) 0.300 (7.62) BSC 0.060 (1.52) 0.195 (4.95) 0.210 (5.33) MAX 0.130 (3.30) MAX 0.115 (2.92) 0.015 0.150 (3.81) (0.38) 0.015 (0.38) 0.130 (3.30) MIN GAUGE 0.115 (2.92) SEATING PLANE 0.014 (0.36) PLANE 0.010 (0.25) 0.022 (0.56) 0.008 (0.20) 0.005 (0.13) 0.430 (10.92) 0.018 (0.46) MIN MAX 0.014 (0.36) 0.070 (1.78) 0.060 (1.52) 0.045 (1.14) COMPLIANTTO JEDEC STANDARDS MS-001 CONTROLLING DIMENSIONSARE IN INCHES; MILLIMETER DIMENSIONS (RCINOEFRPEANRREERENN LCTEEHA EODSNSEL MSY)AAAYNR BDEE AR CROOEU NNNFODIGETUDAR-POEPFDRFOA INSPC RWHIAH ETOEQL UFEIO VORAR LU EHSNAETL ISFN FLDOEEARSDIGSN.. 070606-A Figure 44. 8-Lead Plastic Dual In-Line Package [PDIP] Narrow Body (N-8)—Dimensions shown in inches and (millimeters) 5.00(0.1968) 4.80(0.1890) 8 5 4.00 (0.1574) 6.20 (0.2441) 3.80 (0.1497) 1 4 5.80 (0.2284) 1.27 (0.0500) 0.50 (0.0196) BSC 1.75 (0.0688) 0.25 (0.0099) 45° 0.25 (0.0098) 1.35 (0.0532) 8° 0.10 (0.0040) 0° COPLANARITY 0.51 (0.0201) 0.10 SEATING 0.31 (0.0122) 0.25 (0.0098) 10..2470 ((00..00510507)) PLANE 0.17 (0.0067) COMPLIANTTO JEDEC STANDARDS MS-012-AA C(RINOEFNPEATRRREOENNLCLTEIHN EOGSN EDLSIYM)AEANNRDSEI AORRNOESU NANORDEET DAIN-PO MPFRIFLO LMPIIMRLELIATIMTEEER TFSEO; RIRN ECUQHSU EDI VIINMA LEDENENSSTIIOGSN NFS.OR 012407-A Figure 45. 8-Lead Standard Small Outline Package [SOIC_N] Narrow Body (R-8)—Dimensions shown in millimeters and (inches) ORDERING GUIDE Model Temperature Range Package Description Package Option AD8042AN –40°C to +85°C 8-Lead PDIP N-8 AD8042AR –40°C to +85°C 8-Lead SOIC_N R-8 AD8042AR-REEL –40°C to +85°C 8-Lead SOIC_N, 13" Reel R-8 AD8042AR-REEL7 –40°C to +85°C 8-Lead SOIC_N, 7" Reel R-8 AD8042ARZ1 –40°C to +85°C 8-Lead SOIC_N R-8 AD8042ARZ-REEL1 –40°C to +85°C 8-Lead SOIC_N, 13" Reel R-8 AD8042ARZ-REEL71 –40°C to +85°C 8-Lead SOIC_N, 7" Reel R-8 AD8042ACHIPS DIE 1 Z = RoHS Compliant Part. ©2007 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D01059-0-12/07(E) Rev. E | Page 16 of 16