a Low Distortion, Wide Bandwidth Voltage Feedback Clamp Amps AD8036/AD8037 FEATURES FUNCTIONAL BLOCK DIAGRAM Superb Clamping Characteristics 8-Lead Plastic DIP (N), Cerdip (Q), 3 mV Clamp Error and SO Packages 1.5 ns Overdrive Recovery Minimized Nonlinear Clamping Region 240 MHz Clamp Input Bandwidth NC 1 AD8036/ 8 V H (cid:1)3.9 V Clamp Input Range AD8037 Wide Bandwidth AD8036 AD8037 –INPUT 2 7 +VS Small Signal 240 MHz 270 MHz +INPUT 3 6 OUTPUT Large Signal (4 V p-p) 195 MHz 190 MHz –VS 4 5 VL Good DC Characteristics (Top View) 2 mV Offset NC = NO CONNECT 10 (cid:2)V/(cid:3)C Drift Ultralow Distortion, Low Noise large-signal bandwidths and ultralow distortion. The AD8036 –72 dBc typ @ 20 MHz achieves –66 dBc at 20 MHz, and 240 MHz small-signal and 4.5 nV/√Hz Input Voltage Noise 195 MHz large-signal bandwidths. The AD8036 and AD8037’s High Speed recover from 2× clamp overdrive within 1.5 ns. These character- Slew Rate 1500 V/(cid:2)s istics position the AD8036/AD8037 ideally for driving as well as Settling 10 ns to 0.1%, 16 ns to 0.01% buffering flash and high resolution ADCs. (cid:1)3 V to (cid:1)5 V Supply Operation In addition to traditional output clamp amplifier applications, APPLICATIONS the input clamp architecture supports the clamp levels as addi- ADC Buffer tional inputs to the amplifier. As such, in addition to static dc IF/RF Signal Processing clamp levels, signals with speeds up to 240 MHz can be applied High Quality Imaging to the clamp pins. The clamp values can also be set to any value Broadcast Video Systems within the output voltage range provided that VH is greater that Video Amplifier VL. Due to these clamp characteristics, the AD8036 and AD8037 Full Wave Rectifier can be used in nontraditional applications such as a full-wave rectifier, a pulse generator, or an amplitude modulator. These PRODUCT DESCRIPTION novel applications are only examples of some of the diverse The AD8036 and AD8037 are wide bandwidth, low distortion applications which can be designed with input clamps. clamping amplifiers. The AD8036 is unity gain stable. The The AD8036 is offered in chips, industrial (–40°C to +85°C) AD8037 is stable at a gain of two or greater. These devices and military (–55°C to +125°C) package temperature ranges allow the designer to specify a high (VCH) and low (VCL) output and the AD8037 in industrial. Industrial versions are available clamp voltage. The output signal will clamp at these specified in plastic DIP and SOIC; MIL versions are packaged in cerdip. levels. Utilizing a unique patent pending CLAMPIN™ input clamp architecture, the AD8036 and AD8037 offer a 10× 4 improvement in clamp performance compared to traditional AD8036 VH = 3V 3 output clamping devices. In particular, clamp error is typically 3 mV or less and distortion in the clamp region is minimized. olts 2 VH = 2V Tamhpisl ipfireor dwuhcetr cea an hbigeh u asnedd alosw a oculatpssuict avlo oltpa gaem apre o srp aec cifliaemd.p GE – V 1 VH = 1V A The AD8036 and AD8037, which utilize a voltage feedback LT 0 O architecture, meet the requirements of many applications which T V VL = –1V U–1 previously depended on current feedback amplifiers. The AD8036 P and AD8037 exhibit an exceptionally fast and accurate pulse OUT–2 VL = –2V response (16 ns to 0.01%), extremely wide small-signal and VL = –3V –3 CLAMPIN is a trademark of Analog Devices, Inc. –4 –4 –3 –2 –1 0 1 2 3 4 INPUT VOLTAGE – Volts REV.B Figure 1.Clamp DC Accuracy vs. Input Voltage Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. which may result from its use. No license is granted by implication or Tel: 781/329-4700 World Wide Web Site: http://www.analog.com otherwise under any patent or patent rights of Analog Devices. Fax: 781/326-8703 © Analog Devices, Inc., 2000

AD8036/AD8037–SPECIFICATIONS ((cid:1)V = (cid:1)5 V; R = 100 (cid:4); A = +1 (AD8036); A = +2 (AD8037), V , V open, unless ELECTRICAL CHARACTERISTICS S LOAD V V H L otherwise noted) AD8036A AD8037A Parameter Conditions Min Typ Max Min Typ Max Unit DYNAMIC PERFORMANCE Bandwidth (–3 dB) Small Signal V ≤ 0.4 V p-p 150 240 200 270 MHz OUT Large Signal1 8036, V = 2.5 V p-p; 8037, V = 3.5 V p-p 160 195 160 190 MHz OUT OUT Bandwidth for 0.1 dB Flatness V ≤ 0.4 V p-p OUT 8036,R =140 Ω; 8037,R =274Ω 130 130 MHz F F Slew Rate, Average +/– V = 4 V Step, 10–90% 900 1200 1100 1500 V/µs OUT Rise/Fall Time V = 0.5 V Step, 10–90% 1.4 1.2 ns OUT V = 4 V Step, 10–90% 2.6 2.2 ns OUT Settling Time To 0.1% V = 2 V Step 10 10 ns OUT To 0.01% V = 2 V Step 16 16 ns OUT HARMONIC/NOISE PERFORMANCE 2nd Harmonic Distortion 2Vp-p;20MHz,R =100Ω –59 –52 –52 –45 dBc L R = 500Ω –66 –59 –72 –65 dBc L 3rd Harmonic Distortion 2Vp-p;20MHz,R =100Ω –68 –61 –70 –63 dBc L R = 500Ω –72 –65 –80 –73 dBc L 3rd Order Intercept 25 MHz 46 41 dBm Noise Figure R = 50 Ω 18 14 dB S Input Voltage Noise 1 MHz to 200 MHz 6.7 4.5 nV√Hz Input Current Noise 1 MHz to 200 MHz 2.2 2.1 pA√Hz Average Equivalent Integrated Input Noise Voltage 0.1 MHz to 200 MHz 95 60 µV rms Differential Gain Error (3.58 MHz) R = 150 Ω 0.05 0.09 0.02 0.04 % L Differential Phase Error (3.58 MHz) R = 150 Ω 0.02 0.04 0.02 0.04 Degree L Phase Nonlinearity DC to 100 MHz 1.1 1.1 Degree CLAMP PERFORMANCE Clamp Voltage Range2 V or V ±3.3 ±3.9 ±3.3 ±3.9 V CH CL Clamp Accuracy 2× Overdrive, V = +2 V, V = –2 V ±3 ±10 ±3 ±10 mV CH CL T –T ±20 ±20 mV MIN MAX Clamp Nonlinearity Range3 100 100 mV Clamp Input Bias Current (V or V ) 8036, V = ±1 V; 8037, V = ±0.5 V ±40 ±60 ±50 ±70 µA H L H, L H, L T –T ±80 ±90 µA MIN MAX Clamp Input Bandwidth (–3 dB) V or V = 2 V p-p 150 240 180 270 MHz CH CL Clamp Overshoot 2× Overdrive, V or V = 2 V p-p 1 5 1 5 % CH CL Overdrive Recovery 2× Overdrive 1.5 1.3 ns DC PERFORMANCE4, R = 150 Ω L Input Offset Voltage5 2 7 2 7 mV T –T 11 10 mV MIN MAX Offset Voltage Drift ±10 ±10 µV/°C Input Bias Current 4 10 3 9 µA T –T 15 15 µA MIN MAX Input Offset Current 0.3 3 0.1 3 µA T –T 5 5 µA MIN MAX Common-Mode Rejection Ratio V = ±2 V 66 90 70 90 dB CM Open-Loop Gain V = ±2.5 V 48 55 54 60 dB OUT T –T 40 46 dB MIN MAX INPUT CHARACTERISTICS Input Resistance 500 500 kΩ Input Capacitance 1.2 1.2 pF Input Common-Mode Voltage Range ±2.5 ±2.5 V OUTPUT CHARACTERISTICS Output Voltage Range, R = 150 Ω ±3.2 ±3.9 ±3.2 ±3.9 V L Output Current 70 70 mA Output Resistance 0.3 0.3 Ω Short Circuit Current 240 240 mA POWER SUPPLY Operating Range ±3.0 ±5.0 ±6.0 ±3.0 ±5.0 ±6.0 V Quiescent Current 20.5 21.5 18.5 19.5 mA T –T 25 24 mA MIN MAX PowerSupply Rejection Ratio T –T 50 60 56 66 dB MIN MAX NOTES 1See Max Ratings and Theory of Operation sections of data sheet. 2See Max Ratings. 3Nonlinearity is defined as the voltage delta between the set input clamp voltage (VH or VL) and the voltage at which VOUT starts deviating from VIN (see Figure 73). 4Measured at AV = 50. 5Measured with respect to the inverting input. Specifications subject to change without notice. –2– REV. B

AD8036/AD8037 ABSOLUTE MAXIMUM RATINGS1 MAXIMUM POWER DISSIPATION SupplyVoltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.6V The maximum power that can be safely dissipated by these Voltage Swing × Bandwidth Product . . . . . . . . . . . 350 V-MHz devices is limited by the associated rise in junction temperature. |V –V | . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .≤ 6.3 V The maximum safe junction temperature for plastic encapsulated H IN |V –V | . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .≤ 6.3 V devices is determined by the glass transition temperature of the IntLernaINlPowerDissipation2 plastic, approximately 150°C. Exceeding this limit temporarily PlasticDIP Package (N) . . . . . . . . . . . . . . . . . . . .1.3Watts may cause a shift in parametric performance due to a change SmallOutlinePackage (SO) . . . . . . . . . . . . . . . . . .0.9Watts in the stresses exerted on the die by the package. Exceeding Input Voltage (Common Mode) . . . . . . . . . . . . . . . . . . . . ±V a junction temperature of 175°C for an extended period can S DifferentialInputVoltage . . . . . . . . . . . . . . . . . . . . . . . ±1.2V result in device failure. Output Short Circuit Duration While the AD8036 and AD8037 are internally short circuit pro- . . . . . . . . . . . . . . . . . . . . . . Observe Power Derating Curves tected, this may not be sufficient to guarantee that the maxi- Storage Temperature Range N, R . . . . . . . . .–65°C to +125°C mum junction temperature (150°C) is not exceeded under all Operating Temperature Range (A Grade) . . . –40°C to +85°C conditions. To ensure proper operation, it is necessary to observe Lead Temperature Range (Soldering10sec) . . . . . . . . . 300°C the maximum power derating curves. NOTES 1Stresses above those listed under Absolute Maximum Ratings may cause perma- 2.0 ndeenvitc de aamt athgee steo othr ea ndye voicthe.e rT choisn idsi tai ostnrse sasb roavtein tgh oonsely i;n fduinccattieodn ainl otpheer aotpioerna toifo tnhael s 8-LEAPDA PCLKAASGTEIC DIP TJ = +150(cid:3)C section of this specification is not implied. Exposure to absolute maximum rating att 2cSopnedciiftiicoantsi ofno ri se xfotern ddeevdic pe eirnio fdrese m aairy: affect device reliability. N – W1.5 8-Lead Plastic DIP: θJA = 90°C/W TIO 8-Lead SOIC: θJA = 155°C/W PA 8-Lead Cerdip: θ = 110°C/W. SI JA S DI1.0 METALIZATION PHOTO R E Dimensions shown in inches and (mm). W O Connect Substrate to –VS. M P 8-LEAD SOIC U0.5 PACKAGE –IN VH +VS M XI A 2 8 7 M 0 –50–40–30–20 –10 0 10 20 30 40 50 60 70 80 90 AMBIENT TEMPERATURE – (cid:3)C Figure 2.Plot of Maximum Power Dissipation vs. 0.046 (1.17) 6 OUT Temperature ORDERING GUIDE 3 4 5 8036 Temperature Package Package Model Range Description Option +IN –VS VL AD8036 AD8036AN –40°C to +85°C Plastic DIP N-8 0.050 (1.27) AD8036AR –40°C to +85°C SOIC SO-8 –IN VH +VS AD8036AR-REEL –40°C to +85°C 13" Tape and Reel SO-8 AD8036AR-REEL7 –40°C to +85°C 7" Tape and Reel SO-8 2 8 7 AD8036ACHIPS –40°C to +85°C Die AD8036-EB Evaluation Board 5962-9559701MPA –55°C to +125°C Cerdip Q-8 AD8037AN –40°C to +85°C Plastic DIP N-8 (01.0.1476) AD8037AR –40°C to +85°C SOIC SO-8 6 OUT AD8037AR-REEL –40°C to +85°C 13" Tape and Reel SO-8 AD8037AR-REEL7 –40°C to +85°C 7" Tape and Reel SO-8 AD8037ACHIPS –40°C to +85°C Die AD8037-EB Evaluation Board 3 4 5 8037 AD8037 +IN –VS VL 0.050 (1.27) CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily WARNING! accumulate on the human body and test equipment and can discharge without detection. Although the AD8036/AD8037 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. ESD SENSITIVE DEVICE REV. B –3–

AD8036/AD8037 AD8036–Typical Characteristics RF RF 10(cid:2)F 10(cid:2)F +VS +VH +VS GENPEURLSAETOR 0.1(cid:2)F GENPEURLSAETOR 0.1(cid:2)F 0.1(cid:2)F TR/TF = 350ps TR/TF = 350ps 130(cid:4) AD8036 VOUT 130(cid:4) AD8036 VOUT VIN 0.1(cid:2)F RL = 100(cid:4) VIN 0.1(cid:2)F RL = 100(cid:4) 49.9(cid:4) 10(cid:2)F 49.9(cid:4) 10(cid:2)F 0.1(cid:2)F –VS VL –VS TPC 1.Noninverting Configuration, G = +1 TPC 4.Noninverting Clamp Configuration, G = +1 TPC 2.Large Signal Transient Response; V = 4 V TPC 5.Clamped Large Signal Transient Response (2× O p-p, G = +1, R = 140 Ω Overdrive); V = 2 V p-p, G = +1, R = 140 Ω, V = +1 V, F O F H V = –1 V L TPC 3.Small Signal Transient Response; V = 400 mV p-p, TPC 6.Clamped Small Signal Transient Response O G = +1, R = 140 Ω (2× Overdrive); V = 400 mV p-p, G = +1, R = 140 Ω, F O F V = +0.2V, V = –0.2 V H L –4– REV. B

AD8036/AD8037 AD8037–Typical Characteristics RF RF GENPEURLSAETOR +VS 10(cid:2)F GENPEURLSAETOR +VH +VS 10(cid:2)F TR/TF = 350ps 0.1(cid:2)F TR/TF = 350ps 0.1(cid:2)F 0.1(cid:2)F RIN RIN 100(cid:4) AD8037 VOUT 100(cid:4) AD8037 VOUT VIN 0.1(cid:2)F RL = 100(cid:4) VIN 0.1(cid:2)F RL = 100(cid:4) 49.9(cid:4) 10(cid:2)F 49.9(cid:4) 0.1(cid:2)F 10(cid:2)F –VS VL –VS TPC 7.Noninverting Configuration, G = +2 TPC 10.Noninverting Clamp Configuration, G = +2 TPC 8.Large Signal Transient Response; V = 4 V p-p, TPC 11.Clamped Large Signal Transient Response O G = +2, RF = RIN = 274 Ω (2× Overdrive); VO = 2 V p-p, G = +2, RF = RIN = 274 Ω, V = +0.5 V, V = –0.5 V H L TPC 9.Small Signal Transient Response; TPC 12.Clamped Small Signal Transient Response V = 400 mV p-p, G = +2, R = R = 274 Ω (2× Overdrive); V = 400 mV p-p, G = +2, R = R = O F IN O F IN 274 Ω, V = +0.1 V, V = –0.1 V H L REV. B –5–

AD8036/AD8037 AD8036–Typical Characteristics 2 400 1 200(cid:4) RF 0 140(cid:4) VS = (cid:1)5V AIN – dB –––321 VVRSOL === (cid:1)1300500V(cid:4)mV p-p 10429(cid:4).9(cid:4) NDWIDTH – MHz335000 N PARGCLAK I=AN 1G =0E 0+(cid:4)1 4193.09(cid:4)(cid:4) AD8036 RL G –4 A B B 250 R PACKAGE –5 d 3 – –6 –7 200 –8 1M 10M 100M 1G 20 40 60 80 100 120 140 160 180 200 220 240 FREQUENCY – Hz VALUE OF FEEDBACK RESISTOR (RF) – (cid:4) TPC 13.AD8036 Small Signal Frequency Response, TPC 16.AD8036 Small Signal –3 dB Bandwidth vs. R F G = +1 0.2 2 0.1 158(cid:4) 1 250(cid:4) 0 150(cid:4) 0 –0.1 140(cid:4) –1 VO = 300mV p-p VS = (cid:1)5V N – dB––00..32 VRSL == (cid:1)1050V(cid:4) 130(cid:4) UT – dB––32 VROL == 120.50V(cid:4) p-p 50(cid:4) GAI–0.4 UTP–4 RF =T O50(cid:4) O 250(cid:4) –0.5 –5 BY 50(cid:4) –0.6 –6 –0.7 –7 –0.8 –8 1M 10M 100M 1G 1M 10M 100M 1G FREQUENCY – Hz FREQUENCY – Hz TPC 14.AD8036 0.1 dB Flatness, N Package (for R TPC 17.AD8036 Large Signal Frequency Response, Package Add 20 Ω to RF) G = +1 90 100 2 80 80 1 70 60 PHASE s 0 OP GAIN – dB 645000 GAIN 20400 RGIN – Degree N – dB–––321 VRVSOL === (cid:1)1300500V(cid:4)mV p-p140(cid:4) O 30 –20 A AI OPEN -L 1200 ––6400 PHASE M G––54 AD8036 (VO) 0 –80 –6 1V VH 100(cid:4) –10 –100 –7 VL (VIN) –20 –120 –8 10k 100k 1M 10M 100M 1G 100k 1M 10M 100M 1G FREQUENCY – Hz FREQUENCY – Hz TPC 15.AD8036 Open-Loop Gain and Phase Margin vs. TPC 18.AD8036 Clamp Input Bandwidth, V, V H L Frequency, R = 100 Ω L –6– REV. B

AD8036/AD8037 –30 0.06 % 0.04 – N – dBc –50 RVVGOSL = === + (cid:1)5210V50 Vp(cid:4)-p DIFF GAIN ––0000....00002420 O TI –70 –0.06 R 1st 2nd 3rd 4th 5th 6th 7th 8th 9th 10th 11th O T S DI 2ND HARMONIC s 0.04 ONIC –90 egree 0.02 M D HAR–110 3RD HARMONIC SE – 0.00 A H–0.02 P F –130 DIF–0.04 1st 2nd 3rd 4th 5th 6th 7th 8th 9th 10th 11th 10k 100k 1M 10M 100M FREQUENCY – Hz TPC 19.AD8036 Harmonic Distortion vs. Frequency, TPC 22.AD8036 Differential Gain and Phase Error, RL = 500 Ω G = +1, RL = 150 Ω, F = 3.58 MHz –30 VO = 2V p-p 0.05 VS = (cid:1)5V 0.04 dBc –50 RGL = = + 1100(cid:4) 0.03 – ON 2ND HARMONIC 0.02 RTI –70 % 0.01 O – DIST ROR 0 NIC –90 ER–0.01 O 3RD HARMONIC M –0.02 R A H–110 –0.03 –0.04 –130 –0.05 10k 100k 1M 10M 100M 0 5 10 15 20 25 30 35 40 45 FREQUENCY – Hz SETTLING TIME – ns TPC 20.AD8036 Harmonic Distortion vs. Frequency, TPC 23.AD8036 Short-Term Settling Time to 0.01%, 2 V R = 100 Ω Step, G = +1, R = 100 Ω L L 60 0.4 0.3 0.2 50 m 0.1 B d EPT – +40 OR – %–0.10 C R ER ER–0.2 T N I –0.3 30 –0.4 –0.5 –0.6 20 10 20 40 60 80 100 0 2 4 6 8 10 12 14 16 18 FREQUENCY – MHz SETTLING TIME - (cid:2)s TPC 21.AD8036 Third Order Intercept vs. Frequency TPC 24.AD8036 Long-Term Settling Time, 2 V Step, G = +1, R = 100 Ω L REV. B –7–

AD8036/AD8037 AD8037–Typical Characteristics 8 475 7 374 350 RVSL == (cid:1)1050V(cid:4) RIN RF 6 GAIN = +2 100(cid:4)AD8037 5 VO = 300mV p-p 274 MHz300 49.9(cid:4) RL dB 4 VRSL == (cid:1)1050V(cid:4) 174 TH – N – 3 WID250 GAI 2 AND R PACKAGE N PACKAGE B 1 dB 200 3 – 0 –1 150 –2 1M 10M 100M 1G 100 150 200 250 300 350 400 450 500 550 FREQUENCY – Hz VALUE OF RF,RIN – (cid:4) TPC 25.AD8037 Small Signal Frequency Response, TPC 28.AD8037 Small Signal –3 dB Bandwidth vs. R, R F IN G = +2 0.2 8 0.1 301 7 RF = 475(cid:4) 0 274 6 –0.1 VO = 3.00mV p-p 5 VO = 3.5 V p-p VS = (cid:1)5V 249 VS = (cid:1)5V RF = 75(cid:4) GAIN – dB–––000...432 RL = 100(cid:4) 224 GAIN – dB 234 RL = 100(cid:4) RF 4 T=7O 57(cid:4)5(cid:4) BY –0.5 1 100(cid:4) –0.6 0 –0.7 –1 –0.8 –2 1M 10M 100M 1G 1M 10M 100M 1G FREQUENCY – Hz FREQUENCY – Hz TPC 26.AD8037 0.1 dB Flatness, N Package TPC 29.AD8037 Large Signal Frequency Response, G = +2 (for R Package Add 20 Ω to R) F 65 8 60 7 55 100 50 PHASE 6 N -LOOP GAIN – dB23412345555000 GAIN –05–150000ARGIN – Degrees GAIN – dB 2345 VRVSOL === (cid:1)1230705040V(cid:4)(cid:4)mV p-p274(cid:4) OPE1050 –150PHASE M 01 1V ADV8H037100(cid:4) (VO) –5 –200 –1 VL (VIN) –10 –15 –250 –2 10k 100k 1M 10M 100M 1G 100k 1M 10M 100M 1G FREQUENCY – Hz FREQUENCY – Hz TPC 27.AD8037 Open-Loop Gain and Phase Margin TPC 30.AD8037 Clamp Input Bandwidth, VH, VL vs. Frequency, R = 100 Ω L –8– REV. B

AD8036/AD8037 –30 0.03 % 0.02 VO = 2V p-p N – 0.01 ON – dBc–50 RVGSL = == + (cid:1)52050V(cid:4) DIFF GAI––000...000120 RTI–70 –0.03 O 2ND HARMONIC 1st 2nd 3rd 4th 5th 6th 7th 8th 9th 10th 11th T S C DI–90 ees 0.03 NI gr 0.02 O e ARM 3RD HARMONIC E – D 00..0010 H–110 S HA–0.01 P F –0.02 F –130 DI–0.03 10k 100k 1M 10M 100M 1st 2nd 3rd 4th 5th 6th 7th 8th 9th 10th 11th FREQUENCY – Hz TPC 31.AD8037 Harmonic Distortion vs. Frequency, TPC 34.AD8037 Differential Gain and Phase Error R = 500 Ω G = +2, R = 150 Ω, F = 3.58 MHz L L –30 –0.05 –0.04 ON – dBc –50 RVVGSOL = === + (cid:1)1220V50 Vp(cid:4)-p 2ND HARMONIC ––00..0023 STORTI –70 OR – %–0.010 C DI ERR–0.01 NI –90 3RD HARMONIC O M –0.02 R HA –0.03 –110 –0.04 –0.05 –13010k 100k 1M 10M 100M 0 5 10 15 20 25 30 35 40 45 SETTLING TIME – ns FREQUENCY – Hz TPC 32.AD8037 Harmonic Distortion vs. Frequency, TPC 35.AD8037 Short-Term Settling Time to 0.01%, RL = 100 Ω 2 V Step, G = +2, RL = 100 Ω 60 0.4 0.3 0.2 50 m 0.1 B +d % 0 ERCEPT – 40 ERROR – ––00..21 T IN –0.3 30 –0.4 –0.5 –0.6 20 10 20 40 60 80 100 0 2 4 6 8 10 12 14 16 18 FREQUENCY – MHz SETTLING TIME – (cid:2)s TPC 33.AD8037 Third Order Intercept vs. Frequency TPC 36.AD8037 Long-Term Settling Time 2 V Step, R = 100 Ω L REV. B –9–

AD8036/AD8037–Typical Characteristics 32 17 28 15 Hz VS = (cid:1)5V Hz VS = (cid:1)5V E – nV/24 E – nV/13 G G A20 A11 OLT OLT V V E 16 E 9 S S OI OI N N UT 12 UT 7 P P N N I 8 I 5 4 3 10 100 1k 10k 100k 10 100 1k 10k 100k FREQUENCY – Hz FREQUENCY – Hz TPC 37.AD8036 Noise vs. Frequency TPC 40.AD8037 Noise vs. Frequency 80 80 75 75 70 –PSRR 70 –PSRR 65 65 +PSRR 60 60 55 55 +PSRR B50 50 d B RR – 4405 R – d4405 PS35 SR35 P 30 30 25 25 20 20 15 15 10 10 5 5 0 0 10k 100k 1M 10M 100M 1G 10k 100k 1M 10M 100M 1G FREQUENCY – Hz FREQUENCY – Hz TPC 38.AD8036 PSRR vs. Frequency TPC 41.AD8037 PSRR vs. Frequency 100 100 90 (cid:6)VVS C=M (cid:1) =5 V1V 90 (cid:6)VVS C=M (cid:1) =5 V1V RL = 100(cid:4) RL = 100(cid:4) 80 80 B 70 B 70 d d – – R R R 60 R 60 M M C C 50 50 40 40 30 30 20 20 100k 1M 10M 100M 1G 100k 1M 10M 100M 1G FREQUENCY – Hz FREQUENCY – Hz TPC 39.AD8036 CMRR vs. Frequency TPC 42.AD8037 CMRR vs. Frequency –10– REV. B

AD8036/AD8037 1k 1400 1300 100 VGS = = + (cid:1)15V 1200 V V/ 1100 – AD8037 (cid:4) 10 AIN 1000 +AOL – OUT OOP G 900 –AOL R 1 N -L 800 PE 700 O 0.1 600 500 AD8036 +AOL –AOL 0.01 400 0.1M 1.0M 10M 100M 300M –60 –40 –20 0 20 40 60 80 100 120 140 FREQUENCY – Hz JUNCTION TEMPERATURE – (cid:3)C TPC 43.AD8036 Output Resistance vs. Frequency TPC 46.Open-Loop Gain vs. Temperature 1k 74 –PSRR VS = (cid:1)5V 72 100 G = +2 AD8037 70 +PSRR (cid:4) 10 dB68 R – OUT 1 PSRR – 66 –PSRR AADD88003367 +PSRR 64 0.1 62 AD8036 0.01 60 0.1M 1.0M 10M 100M 300M –60 –40 –20 0 20 40 60 80 100 120 140 FREQUENCY – Hz JUNCTION TEMPERATURE – (cid:3)C TPC 44.AD8037 Output Resistance vs. Frequency TPC 47.PSRR vs. Temperature 4.2 96 4.1 RL=150 95 (cid:6)VCM = 2V +VOUT s4.0 94 olt –VOUT T SWING – V33..98 MRR – dB9932 PU3.7 C91 T U O 3.6 90 +VOUT 3.5 –VOUT RL= 50 89 3.4 –60 –40 –20 0 20 40 60 80 100 120 140 88 15 25 35 45 55 65 75 85 95 JUNCTION TEMPERATURE – (cid:3)C JUNCTION TEMPERATURE – (cid:3)C TPC 45.AD8036/AD8037 Output Swing vs. Temperature TPC 48.AD8036/AD8037 CMRR vs. Temperature REV. B –11–

AD8036/AD8037–Typical Characteristics 24 270 23 260 A mA22 AD8036, VS = (cid:1)6V T – m250 AD8036 ENT – 21 AD8037, VS = (cid:1)6V URREN240 AD8037 AD8037 ADS80IN3K6 R C PLY CUR20 AD8036, VS = (cid:1)5V CIRCUIT 230 SOURCE SUP19 AD8037, VS = (cid:1)5V ORT 220 H S 18 210 17 200 –60 –40 –20 0 20 40 60 80 100 120 140 –60 –40 –20 0 20 40 60 80 100 120 140 JUNCTION TEMPERATURE – (cid:3)C JUNCTION TEMPERATURE – (cid:3)C TPC 49.Supply Current vs. Temperature TPC 52.Short Circuit Current vs. Temperature –2.50 4.5 VS = (cid:1)6V –2.25 –IB 4.0 V m A AD8036 GE – –2.00 AD8037 VS = (cid:1)6V (cid:2)T – 3.5 +IB A–1.75 N ET VOLT–1.50 VS = (cid:1)5V VS = (cid:1)5V S CURRE3.0 AD8037 –IB S A FF–1.25 BI +IB O T 2.5 PUT –1.00 AD8036 NPU N I I 2.0 –0.75 –0.50 1.5 –60 –40 –20 0 20 40 60 80 100 120 140 –60 –40 –20 0 20 40 60 80 100 120 140 JUNCTION TEMPERATURE – (cid:3)C JUNCTION TEMPERATURE – (cid:3)C TPC 50.Input Offset Voltage vs. Temperature TPC 53.Input Bias Current vs. Temperature 44 48 40 3 WAFER LOTS 44 3 WAFER LOTS COUNT = 632 COUNT = 853 40 36 36 32 32 FREQ. DIST 28 28 NT24 FREQ. DIST NT U U24 CO20 CO20 16 16 12 12 8 8 4 4 0 0 –6 –5 –4 –3 –2 –1 0 1 2 3 4 –4.5 –4.0 –3.5 –3.0 –2.5 –2.0 –1.5 –1.0 –0.5 0 0.5 INPUT OFFSET VOLTAGE – mV INPUT OFFSET VOLTAGE – mV TPC 51.AD8036 Input Offset Voltage Distribution TPC 54.AD8037 Input Offset Voltage Distribution –12– REV. B

Clamp Characteristics–AD8036/AD8037 20 –80 15 AD8036, ACL = +1 –75 GE – mV 10 V–3CVL = V–2CVL = V–1CVL = AD8037, ACL = +2 N – dBc––7605 AHDA8R0M37O 3NRICD A 5 O T TI–60 R VOL 0 AD8036 STOR–55 AHDA8R0M37O 2NNICD AHDA8R0M36O 3NRICD O DI ERR –5 AD8037 NIC –50 AD8036 2ND UT MO–45 HARMONIC INP–10 VC+H1 V= VC+H2 V= VC+H3 V= HAR–40 VH A +D18V0 3 6 A +D08.50V37 –15 –35 VL –1V –0.5V G +1V +2V –20 –30 –3 –2 –1 0 1 2 3 0.6 0.65 0.7 0.75 0.8 0.85 0.9 0.95 1.0 OUTPUT VOLTAGE – Volts ABSOLUTE VALUE OF OUTPUT VOLTAGE – Volts TPC 55.Input Error Voltage vs. Clamped Output Voltage TPC 58.Harmonic Distortion as Output Approaches Clamp Voltage; V = 2 V p-p, R = 100 (cid:4), f = 20 MHz O L 20 80 15 VH = + 1V VL = – 1V A 60 10 (cid:2)– POSITIVE IBH, IBL DENOTES mV ENT 40 CCULARMREPN INTP FULTOSW V IHN, TVOL NEARITY – 50 BIAS CURR 200 IBL ONLI –5 PUT –20 IBH N N –10 P I M–40 A L –15 C –60 –20 –1.0 –0.8 –0.6 –0.4 –0.2 0.0 0.2 0.4 0.6 0.8 1.0 – 8 0–5 –4 –3 –2 –1 0 1 2 3 4 5 INPUT VOLTAGE AV – Volts INPUT CLAMP VOLTAGE (VH,VL) – Volts TPC 56.AD8036/AD8037 Nonlinearity Near Clamp Voltage TPC 59.AD8036/AD8037 Clamp Input Bias Current vs. Input Clamp Voltage +2V +2V +1V +1V 0V 0V REF REF TPC 57.AD8036 Clamp Overdrive (2×) Recovery TPC 60.AD8037 Clamp Overdrive (2×) Recovery REV. B –13–

AD8036/AD8037–Clamp Characteristics 0.5 0.5 0.4 0.4 0.3 0.3 0.2 0.2 % 0.1 % 0.1 ERROR – –0.10 ERROR – –0.10 –0.2 –0.2 –0.3 –0.3 –0.4 –0.4 –0.5 –0.5 0 10 20 30 40 50 60 70 80 90 0 10 20 30 40 50 60 70 80 90 SETTLING TIME – ns SETTLING TIME – ns TPC 61.AD8036 Clamp Settling (0.1%), V = +1 V, TPC 64.AD8037 Clamp Settling (0.1%), V = +0.5 V, H H V = –1 V, 2× Overdrive V = –0.5 V, 2× Overdrive L L 0.5 0.5 0.4 0.4 0.3 0.3 0.2 0.2 % 0.1 % 0.1 – – OR 0 OR 0 R R ER–0.1 ER–0.1 –0.2 –0.2 –0.3 –0.3 –0.4 –0.4 –0.5 –0.5 0 5 10 15 20 25 30 35 40 0 5 10 15 20 25 30 35 40 SETTLING TIME – ns SETTLING TIME – ns TPC 62.AD8036 Clamp Recovery Settling Time (High), TPC 65.AD8037 Clamp Recovery Settling Time (High), from +2× Overdrive to 0 V from +2× Overdrive to 0 V 0.5 0.5 0.4 0.4 0.3 0.3 0.2 0.2 % 0.1 % 0.1 OR – 0 OR – 0 R R ER–0.1 ER–0.1 –0.2 –0.2 –0.3 –0.3 –0.4 –0.4 –0.5 –0.5 0 5 10 15 20 25 30 35 40 0 5 10 15 20 25 30 35 40 SETTLING TIME – ns SETTLING TIME – ns TPC 63.AD8036 Clamp Recovery Settling Time (Low), TPC 66.AD8037 Clamp Recovery Settling Time (Low), from –2× Overdrive to 0 V from –2× Overdrive to 0 V –14– REV. B

AD8036/AD8037 THEORY OF OPERATION This estimation loses accuracy for gains of +2/–1 or lower due General to the amplifier’s damping factor. For these “low gain” cases, The AD8036 and AD8037 are wide bandwidth, voltage feedback the bandwidth will actually extend beyond the calculated value clamp amplifiers. Since their open-loop frequency response fol- (see Closed-Loop BW plots, TPCs 13 and 25). lows the conventional 6 dB/octave roll-off, their gain bandwidth Pulse Response product is basically constant. Increasing their closed-loop gain Unlike a traditional voltage feedback amplifier, where the slew results in a corresponding decrease in small signal bandwidth. This speed is dictated by its front end dc quiescent current and gain can be observed by noting the bandwidth specification, between bandwidth product, the AD8036 and AD8037 provide “on the AD8036 (gain of 1) and AD8037 (gain of 2). The AD8036/ demand” current that increases proportionally to the input AD8037 typically maintain 65 degrees of phase margin. This “step” signal amplitude. This results in slew rates (1200 V/µs) high margin minimizes the effects of signal and noise peaking. comparable to wideband current feedback designs. This, com- While the AD8036 and AD8037 can be used in either an invert- bined with relatively low input noise current (2.1 pA/√Hz), gives ing or noninverting configuration, the clamp function will only the AD8036 and AD8037 the best attributes of both voltage and work in the noninverting mode. As such, this section shows con- current feedback amplifiers. nections only in the noninverting configuration. Applications Large Signal Performance that require an inverting configuration will be discussed in the The outstanding large signal operation of the AD8036 and Applications section. In applications that do not require clamp- AD8037 is due to a unique, proprietary design architecture. ing, Pins 5 and 8 (respectively V and V ) may be left floating. L H In order to maintain this level of performance, the maximum See Input Clamp Amp Operation and Applications sections 350 V-MHz product must be observed, (e.g., @ 100 MHz, otherwise. V ≤ 3.5 V p-p). O Feedback Resistor Choice Power Supply and Input Clamp Bypassing The value of the feedback resistor is critical for optimum perfor- Adequate power supply bypassing can be critical when optimiz- mance on the AD8036 (gain +1) and less critical as the gain ing the performance of a high frequency circuit. Inductance in increases. Therefore, this section is specifically targeted at the power supply leads can form resonant circuits that produce the AD8036. peaking in the amplifier’s response. In addition, if large current At minimum stable gain (+1), the AD8036 provides optimum transients must be delivered to the load, then bypass capacitors dynamic performance with R = 140 Ω. This resistor acts only (typically greater than 1 µF) will be required to provide the best F as a parasitic suppressor against damped RF oscillations that settling time and lowest distortion. A parallel combination of at can occur due to lead (input, feedback) inductance and parasitic least 4.7 µF, and between 0.1 µF and 0.01 µF, is recommended. capacitance. This value of R provides the best combination of Some brands of electrolytic capacitors will require a small series F wide bandwidth, low parasitic peaking, and fast settling time. damping resistor ≈4.7 Ω for optimum results. In fact, for the same reasons, a 100–130 Ω resistor should be When the AD8036 and AD8037 are used in clamping mode, placed in series with the positive input for other AD8036 non- and a dc voltage is connected to clamp inputs V and V , a 0.1 µF H L inverting configurations. The correct connection is shown in bypassing capacitor is required between each input pin and Figure 3. ground in order to maintain stability. Driving Capacitive Loads +VS The AD8036 and AD8037 were designed primarily to drive 10(cid:2)F G = 1+RF nonreactive loads. If driving loads with a capacitive compo- RG VH 0.1(cid:2)F nent is desired, the best frequency response is obtained by 100 - 130(cid:4) the addition of a small series resistance as shown in Figure 4. VIN The accompanying graph shows the optimum value for R AD8036/ SERIES RTERM AD8037 VOUT vs. capacitive load. It is worth noting that the frequency response 0.1(cid:2)F of the circuit when driving large capacitive loads will be domi- VL 10(cid:2)F RF nloaatdeds obfy 6 t hpeF p oars sleivses ,r nooll -Roff of R SisE RnIeEcS easnsadr yC.L. For capacitive SERIES –VS RF RG RIN Figure 3.Noninverting Operation AD8036/ RSERIES For general voltage gain applications, the amplifier bandwidth RIN AD8037 R1kL(cid:4) CL can be closely estimated as: ω f ≅ O Figure 4.Driving Capacitive Loads 3dB  R  2π1+ F  R  G REV. B –15–

AD8036/AD8037 40 Operation of the AD8036 for negative input voltages and nega- tive clamp levels on V is similar, with comparator C control- L L ling S1. Since the comparators see the voltage on the +V pin IN as their common reference level, then the voltage V and V are H L defined as “High” or “Low” with respect to +V . For example, 30 IN if V is set to zero volts, V is open, and V is +1 V, compara- (cid:4) IN H L – tor C will switch S1 to “C,” so the AD8036 will buffer the S L ERIE voltage on VL and ignore +VIN. S R The performance of the AD8036 and AD8037 closely matches 20 the ideal just described. The comparator’s threshold extends from 60 mV inside the clamp window defined by the voltages on V and V to 60 mV beyond the window’s edge. Switch S1 is L H implemented with current steering, so that A1’s +input makes a 10 continuous transition from say, V to V as the input voltage 0 5 10 15 20 25 IN H CL– pF traverses the comparator’s input threshold from 0.9 V to 1.0 V for V = 1.0 V. Figure 5.Recommended R vs. Capacitive Load H SERIES The practical effect of these nonidealities is to soften the transition from amplification to clamping modes, without compromising INPUT CLAMPING AMPLIFIER OPERATION the absolute clamp limit set by the CLAMPIN circuit. Figure 7 The key to the AD8036 and AD8037’s fast, accurate clamp and is a graph of V vs. V for the AD8036 and a typical output amplifier performance is their unique patent pending CLAMPIN OUT IN clamp amplifier. Both amplifiers are set for G = +1 and V = 1 V. input clamp architecture. This new design reduces clamp errors H by more than 10× over previous output clamp based circuits, as The worst case error between V (ideally clamped) and V OUT OUT well as substantially increasing the bandwidth, precision and (actual) is typically 18 mV times the amplifier closed-loop gain. versatility of the clamp inputs. This occurs when V equals V (or V ). As V goes above IN H L IN and/or below this limit, V will settle to within 5 mV of the Figure 6 is an idealized block diagram of the AD8036 connected OUT ideal value. as a unity gain voltage follower. The primary signal path com- prises A1 (a 1200 V/µs, 240 MHz high voltage gain, differential In contrast, the output clamp amplifier’s transfer curve typically to single-ended amplifier) and A2 (a G = +1 high current gain will show some compression starting at an input of 0.8 V, and output buffer). The AD8037 differs from the AD8036 only in can have an output voltage as far as 200 mV over the clamp limit. that A1 is optimized for closed-loop gains of two or greater. In addition, since the output clamp in effect causes the am- plifier to operate open loop in clamp mode, the amplifier’s out- The CLAMPIN section is comprised of comparators C and H put impedance will increase, potentially causing additional errors. C , which drive switch S1 through a decoder. The unity-gain L buffers in series with +V , V , and V inputs isolate the input The AD8036’s and AD8037’s CLAMPIN input clamp architec- IN H L pins from the comparators and S1 without reducing bandwidth ture works only for noninverting or follower applications and, or precision. since it operates on the input, the clamp voltage levels V and H V , and input error limits will be multiplied by the amplifier’s The two comparators have about the same bandwidth as A1 L (240 MHz), so they can keep up with signals within the useful bandwidth of the AD8036. To illustrate the operation of the RF 140(cid:4) CLAMPIN circuit, consider the case where V is referenced to H 1 V, V is open, and the AD8036 is set for a gain of +1, by con- L necting its output back to its inverting input through the recom- –VIN A2 mended 140 Ω feedback resistor. Note that the main signal path +VIN +1 A A1 +1 VOUT always operates closed loop, since the CLAMPIN circuit only S1 B affects A1’s noninverting input. VH +1 fIof ra t0h eV c toon 2n eVc tvioolnta jgues tr admespc irsi baepdp,l iVed to tshheo uAlDd 8tr0a3c6k’ s+ +VVIN VL +1 C S1 A B C OUT IN perfectly up to 1 V, then should limit at exactly 1 V as +VIN CH VIN > VH 0 1 0 continues to 2 V. VL ≤ VIN ≤ VH 1 0 0 In practice, the AD8036 comes close to this ideal behavior. As VIN < VL 0 0 1 the +V input voltage ramps from zero to 1 V, the output of the CL IN high limit comparator C starts in the off state, as does the out- H put of C . When +V just exceeds V (ideally, by say 1 µV, L IN IN Figure 6.AD8036/AD8037 Clamp Amp System practically by about 18 mV), C changes state, switching S1 H from “A” to “B” reference level. Since the + input of A1 is now connected to V , further increases in +V have no effect on the H IN AD8036’s output voltage. In short, the AD8036 is now operat- ing as a unity-gain buffer for the V input, as any variation in H V , for V > 1 V, will be faithfully reproduced at V . H H OUT –16– REV. B

AD8036/AD8037 closed-loop gain at the output. For instance, to set an output Clamping with Gain limit of ±1 V for an AD8037 operating at a gain of 3.0, V and Figure 9 shows an AD8037 configured for a noninverting gain H V would need to be set to +0.333 V and –0.333 V, respectively. of two. The AD8037 is used in this circuit since it is compen- L sated for gains of two or greater and provides greater bandwidth. The only restriction on using the AD8036’s and AD8037’s In this case, the high clamping level at the output will occur at +V , V , V pins as inputs is that the maximum voltage differ- IN L H ence between +V and V or V should not exceed 6.3 V, and IN H L all three voltages be within the supply voltage range. For example, VH 0.1(cid:2)F +5V if V is set at –3 V, then V should not exceed +3.3 V. L IN 0.1(cid:2)F 10(cid:2)F 1.6 130(cid:4) VIN VH AD8036 VOUT 1.4 VL T U O – V 0.1(cid:2)F 10(cid:2)F E 1.2 0.1(cid:2)F T VOLTAG1.0 CLAMP AERDR80O3R6 – 25mV CLAMOPU TEPRURTO CRL –A >M2P00mV VL –5V 14R0F(cid:4) U P AD8036 T OU OUTPUT CLAMP AMP Figure 8.Unity Gain Noninverting Clamp 0.8 2 × V and the low clamping level at the output will be 2 × V . H L The equations governing the output clamp levels in circuits con- 0.6 figured for noninverting gain are: 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 INPUT VOLTAGE – +VIN V = G × V CH H Figure 7.Output Clamp Error vs. Input Clamp Error V = G × V CL L where: V is the high output clamping level CH AD8036/AD8037 APPLICATIONS V is the low output clamping level The AD8036 and AD8037 use a unique input clamping circuit CL G is the gain of the amplifier configuration to perform the clamping function. As a result, they provide the V is the high input clamping level (Pin 8) clamping function better than traditional output clamping H V is the low input clamping level (Pin 5) devices and provide additional flexibility to perform other L *Amplifier offset is assumed to be zero. unique applications. There are, however, some restrictions on circuit configurations; VH and some calculations need to be performed in order to figure 0.1(cid:2)F +5V the clamping level, as a result of clamping being performed at the input stage. 0.1(cid:2)F 10(cid:2)F 100(cid:4) The major restriction on the clamping feature of the AD8036/ VIN VH AD8037 is that clamping occurs only when using the amplifiers 49.9(cid:4) AD8037 VOUT in the noninverting mode. To clamp in an inverting circuit, an VL additional inverting gain stage is required. Another restriction is 0.1(cid:2)F 10(cid:2)F that VH be greater than VL, and that each be within the output 0.1(cid:2)F voltage range of the amplifier (±3.9 V). VH can go below ground –5V and VL can go above ground as long as VH is kept higher than VL. 27R4G(cid:4) VL 27R4F(cid:4) Unity Gain Clamping The simplest circuit for calculating the clamp levels is a unity gain follower as shown in Figure 8. In this case, the AD8036 Figure 9.Gain of Two Noninverting Clamp should be used since it is compensated for noninverting unity gain. This circuit will clamp at an upper voltage set by V (the voltage H applied to Pin 8) and a lower voltage set by V (the voltage L applied to Pin 5). REV. B –17–

AD8036/AD8037 +5V 806(cid:4) +5V 0.1(cid:2)F 100(cid:4) +5V 0.1(cid:2)F 10(cid:2)F –0.5V to +0.5V 100(cid:4) 1N5712 AD9002 10µF 0.1(cid:2)F VIN R3 49.9(cid:4) AD8VH037 –2V to 0V 49.9(cid:4) VIN = –2V TO 0V AD780 2.5V 750(cid:4) VL CLRAAMNPGIENG 0.1(cid:2)F –2.1V to +0.1V SUBSTRATE 100(cid:4) 0.1(cid:2)F 10(cid:2)F DIODE –5V 806(cid:4) 0.1(cid:2)F R1 R2 0.1(cid:2)F 499(cid:4) –5V 301(cid:4) –5.2V Figure 10.Gain of Two, Noninverting with Offset AD8037 Driving an AD9002—8-Bit, 125 MSPS A/D Converter Clamping with an Offset it goes no more than 100 mV outside of this range in either di- Some op amp circuits are required to operate with an offset rection. Thus, the high clamping level should be set at +0.1 V voltage. These are generally configured in the inverting mode and the low clamping level should be set at –2.1 V as seen at the where the offset voltage can be summed in as one of the inputs. input of the AD9002 (output of AD8037). Since AD8036/AD8037 clamping does not function in the in- Because the clamping is done at the input stage of the AD8037, verting mode, it is not possible to clamp with this configuration. the clamping level as seen at the output is affected by not only Figure 10 shows a noninverting configuration of an AD8037 the gain of the circuit as previously described, but also by the that provides clamping and also has an offset.The circuit shows offset. Thus, in order to obtain the desired clamp levels, V H the AD8037 as a driver for an AD9002, an 8-bit, 125 MSPS must be biased at +0.55 V while V must be biased at –0.55 V. L A/D converter and illustrates some of the considerations for us- The clamping levels as seen at the output can be calculated by ing an AD8037 with offset and clamping. the following: The analog input range of the AD9002 is from ground to –2 V. V = V + G × V The input should not go more than 0.5 V outside this range in CH OFF H order to prevent disruptions to the internal workings of the A/D VCL = VOFF + G × VL and to avoid drawing excess current. These requirements make Where V is the offset voltage that appears at the output. OFF the AD8037 a prime candidate for signal conditioning. The resistors used to generate the voltages for V and V should H L When an offset is added to a noninverting op amp circuit, it is be kept to a minimum in order to reduce errors due to clamp fed in through a resistor to the inverting input. The result is that bias current. This current is dependent on V and V (see TPC H L the op amp must now operate at a closed-loop gain greater than 59) and will create a voltage drop across whatever resistance is unity. For this circuit a gain of two was chosen which allows the in series with each clamp input. This extra error voltage is use of the AD8037. The feedback resistor, R2, is set at 301 Ω multiplied by the closed-loop gain of the amplifier and can be for optimum performance of the AD8037 at a gain of two. substantial, especially in high closed-loop gain configurations. There is an interaction between the offset and the gain, so some A 0.1 µF bypass capacitor should be placed between input calculations must be performed to arrive at the proper values for clamp pins VH and VL and ground to ensure stable operation. R1 and R3. For a gain of two the parallel combination of resis- The 1N5712 Schottky diode is used for protection from forward tors R1 and R3 must be equal to the feedback resistor R2. Thus biasing the substrate diode in the AD9002 during power-up R1 × R3/R1 + R3 = R2 = 301 Ω transients. The reference used to provide the offset is the AD780 whose Programmable Pulse Generator output is 2.5 V. This must be divided down to provide the 1 V The AD8036/AD8037’s clamp output can be set accurately and offset desired. Thus has a well controlled flat level. This along with wide bandwidth and high slew rate make them very well suited for programmable 2.5 V × R1/(R1 + R3) = 1 V level pulse generators. When the two equations are solved simultaneously we get R1 = Figure 11 is a schematic for a pulse generator that can directly 499 Ω and R3 = 750 Ω (using closest 1% resistor values in all accept TTL generated timing signals for its input and generate cases). This positive 1 V offset at the input translates to a –1 V pulses at the output up to 24 V p-p with 2500 V/µs slew rate. offset at the output. The output levels can be programmed to anywhere in the range The usable input signal swing of the AD9002 is 2 V p-p. This is –12 V to +12 V. centered about the –1 V offset making the usable signal range from 0 V to –2 V. It is desirable to clamp the input signal so that –18– REV. B

AD8036/AD8037 VH 0.1(cid:2)F +5V +15V 0.1(cid:2)F 10(cid:2)F 200(cid:4) 100(cid:4) TTLIN VH 100(cid:4) 0.1(cid:2)F 10(cid:2)F VH (cid:7) 10 1.3k(cid:4) AD8037 VL (cid:7) 10 VL AD811 PULSE OUT –15V 0.1(cid:2)F 10(cid:2)F 0.1(cid:2)F 0.1(cid:2)F 10(cid:2)F –5V VL 274(cid:4) –15V 604(cid:4) 274(cid:4) 150(cid:4) Figure 11.Programmable Pulse Generator The circuit uses an AD8037 operating at a gain of two with an The circuit is configured as an inverting amplifier with a gain AD811 to boost the output to the ±12 V range. The AD811 was of one. The input drives the inverting amplifier and also directly chosen for its ability to operate with ±15 V supplies and its high drives V , the lower level clamping input. The high level clamp- L slew rate. ing input, V , is left floating and plays no role in this circuit. H R1 and R2 act as a level shifter to make the TTL signal levels be When the input is negative, the amplifier acts as a regular unity- approximately symmetrical above and below ground. This ensures gain inverting amplifier and outputs a positive signal at the same that both the high and low logic levels will be clamped by the amplitude as the input with opposite polarity. V is driven nega- L AD8037. For well controlled signal levels in the output pulse, tive by the input, so it performs no clamping action, because the the high and low output levels should result from the clamping positive output signal is always higher than the negative level action of the AD8037 and not be controlled by either the high driving V . L or low logic levels passing through a linear amplifier. For good When the input is positive, the output result is the sum of two rise and fall times at the output pulse, a logic family with high separate effects. First, the inverting amplifier multiplies the input speed edges should be used. by –1 because of its unity-gain inverting configuration. This The high logic levels are clamped at two times the voltage at VH, effectively produces an offset as explained above, but with a while the low logic levels are clamped at two times the voltage dynamic level that is equal to –1 times the input. at V . The output of the AD8037 is amplified by the AD811 L Second, although the positive input is grounded (through 100 Ω), operating at a gain of 5. The overall gain of 10 will cause the the output is clamped at two times the voltage applied to V (a high output level to be 10 times the voltage at V , and the low L H positive, dynamic voltage in this case). The factor of two is output level to be 10 times the voltage at V . L because the noise gain of the amplifier is two. High Speed, Full-Wave Rectifier The sum of these two actions results in an output that is equal The clamping inputs are additional inputs to the input stage of to unity times the input signal for positive input signals, see Fig- the op amp. As such they have an input bandwidth comparable ure 13. For a input/output scope photo with an input signal of to the amplifier inputs and lend themselves to some unique 20 MHz and amplitude ±1 V, see Figure 14. functions when they are driven dynamically. Figure 12 is a schematic for a full-wave rectifier, sometimes INPUT called an absolute value generator. It works well up to 20 MHz and can operate at significantly higher frequencies with some degradation in performance. The distortion performance is sig- nificantly better than diode based full-wave rectifiers, especially at high frequencies. LOWER CLAMPING LEVEL WITH +5V NO NEG INPUT FULL WAVE RECTIFIED OUTPUT 0.1(cid:2)F 10(cid:2)F 100(cid:4) VH AD8037 VOUT = VIN VL 0.1(cid:2)F 10(cid:2)F –1 (cid:7) INPUT LCOLAWMEPRING 27R4G(cid:4) 27R4F(cid:4) –5V OUTPUT LEVEL VIN Figure 13. Figure 12.Full-Wave Rectifier REV. B –19–

AD8036/AD8037 The modulation signal is applied to both the input of a unity gain inverting amplifier and to V , the lower clamping input. L V is biased at 0.5 V dc. H To understand the circuit operation, it is helpful to first con- sider a simpler circuit. If both V andV were dc biased at L H –0.5 V and the carrier and modulation inputs driven as above, the output would be a 2 V p-p square wave at the carrier fre- quency riding on a waveform at the modulating frequency. The inverting input (modulation signal) is creating a varying offset to the 2 V p-p square wave at the output. Both the high and low levels clamp at twice the input levels on the clamps because the noise gain of the circuit is two. Figure 14.Full-Wave Rectifier Scope Thus for either positive or negative input signals, the output is When VL is driven by the modulation signal instead of being held unity times the absolute value of the input signal. The circuit at a dc level, a more complicated situation results. The resulting can be easily configured to produce the negative absolute value waveform is composed of an upper envelope and a lower enve- of the input by applying the input to V instead of V . lope with the carrier square wave in between. The upper and H L lower envelope waveforms are 180° out of phase as in a typical The circuit can get to within about 40 mV of ground during the AM waveform. time when the input crosses zero. This voltage is fixed over a wide frequency range and is a result of the switching between The upper envelope is produced by the upper clamp level being the conventional op amp input and the clamp input. But because offset by the waveform applied to the inverting input. This offset there are no diodes to rapidly switch from forward to reverse bias, is the opposite polarity of the input waveform because of the the performance far exceeds that of diode based full wave rectifiers. inverting configuration. The 40 mV offset mentioned can be removed by adding an off- The lower envelope is produced by the sum of two effects. First, set to the circuit. A 27.4 kΩ input resistor to the inverting input it is offset by the waveform applied to the inverting input as in will have a gain of 0.01, while changing the gain of the circuit the case of the simplified circuit above. The polarity of this off- by only 1%. A plus or minus 4 V dc level (depending on the set is in the same direction as the upper envelope. Second, the polarity of the rectifier) into this resistor will compensate for output is driven in the opposite direction of the offset at twice the offset. the offset voltage by the modulation signal being applied to VL. This results from the noise gain being equal to two, and since Full wave rectifiers are useful in many applications including there is no inversion in this connection, it is opposite polarity AM signal detection, high frequency ac voltmeters and various from the offset. arithmetic operations. The result at the output for the lower envelope is the sum of Amplitude Modulator these two effects, which produces the lower envelope of an In addition to being able to be configured as an amplitude amplitude modulated waveform. See Figure 16. demodulator (AM detector), the AD8037 can also be config- ured as an amplitude modulator as shown in Figure 15. VH +5V 0.1(cid:2)F 10(cid:2)F 100(cid:4) CARRIER IN VH AD8037 AM OUT VL 0.1(cid:2)F 10(cid:2)F RG RF 274(cid:4) 274(cid:4) –5V Figure 16.AM Waveform MODULATION IN The depth of modulation can be modified in this circuit by changing the amplitude of the modulation signal. This changes Figure 15.Amplitude Modulator the amplitude of the upper and lower envelope waveforms. The positive input of the AD8037 is driven with a square wave The modulation depth can also be changed by changing the dc of sufficient amplitude to produce clamping action at both the bias applied to V . In this case the amplitudes of the upper and high and low levels. This is the higher frequency carrier signal. H lower envelope waveforms stay constant, but the spacing between them changes. This alters the ratio of the envelope amplitude to the amplitude of the overall waveform. –20– REV. B

AD8036/AD8037 Layout Considerations VH +VS The specified high speed performance of the AD8036 and 1k(cid:4) AD8037 requires careful attention to board layout and component selection. Proper RF design techniques and low pass parasitic RF –VS component selection are mandatory. 0.1(cid:2)F The PCB should have a ground plane covering all unused +VS portions of the component side of the board to provide a low RG impedance path. The ground plane should be removed from the area near the input pins to reduce stray capacitance. AADD88003367/ RO VOUT RS Chip capacitors should be used for supply and input clamp IN bypassing (see Figure 17). One end should be connected to RT –VS the ground plane and the other within 1/8 inch of each power 0.1(cid:2)F +VS and clamp pin. An additional large (0.47 µF–10 µF) tantalum electrolytic capacitor should be connected in parallel, though 1k(cid:4) not necessarily so close, to supply current for fast, large signal VL –VS changes at the output. NONINVERTING CONFIGURATION The feedback resistor should be located close to the inverting input pin in order to keep the stray capacitance at this node to a +VS C1 C3 C5 minimum. Capacitance variations of less than 1 pF at the invert- OPTIONAL 0.01(cid:2)F 0.1(cid:2)F 10(cid:2)F ing input will significantly affect high speed performance. C2 C4 C6 Stripline design techniques should be used for long signal traces 0.01(cid:2)F 0.1(cid:2)F 10(cid:2)F (greater than about 1 inch). These should be designed with a –VS characteristic impedance of 50 Ω or 75 Ω and be properly termi- SUPPLY BYPASSING nated at each end. Figure 17.Noninverting Configurations for Evaluation Evaluation Board Boards An evaluation board for both the AD8036 and AD8037 is available that has been carefully laid out and tested to demon- strate that the specified high speed performance of the device can be realized. For ordering information, please refer to the Ordering Guide. The layout of the evaluation board can be used as shown or serve as a guide for a board layout. Table I. AD8036A AD8037A Gain Gain Component +1 +2 +10 +100 +2 +10 +100 R 140 Ω 274 Ω 2 kΩ 2 kΩ 274 Ω 2 kΩ 2 kΩ F R 274 Ω 221 Ω 20.5 Ω 274 Ω 221 Ω 20.5 Ω G R (Nominal) 49.9 Ω 49.9 Ω 49.9 Ω 49.9 Ω 49.9 Ω 49.9 Ω 49.9 Ω O R 130 Ω 100 Ω 100 Ω 100 Ω 100 Ω 100 Ω 100 Ω S R (Nominal) 49.9 Ω 49.9 Ω 49.9 Ω 49.9 Ω 49.9 Ω 49.9 Ω 49.9 Ω T Small Signal BW (MHz) 240 90 10 1.3 275 21 3 REV. B –21–

AD8036/AD8037 Figure 18.Evaluation Board Silkscreen (Top) Figure 20.Board Layout (Solder Side) Figure 19.Evaluation Board Silkscreen (Bottom) Figure 21.Board Layout (Component Side) –22– REV. B

AD8036/AD8037 OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 8-Lead Plastic DIP (N Package) 0.430 (10.92) 0.348 (8.84) 8 5 B) 00..228400 ((76..1110)) ev. 1 4 0 (r PIN 1 0.100 (2.54) 00..332050 ((87..2652)) 2/0 1 BSC 0.060 (1.52) 0– 0.210 0.015 (0.38) 0.195 (4.95) 7– (5.33) 0.115 (2.93) 5 MAX 0.130 10 0.160 (4.06) (3.30) C0 0.115 (2.93) MIN 0.015 (0.381) 0.022 (0.558) 0.070 (1.77) SEATING 0.008 (0.204) 0.014 (0.356) 0.045 (1.15) PLANE 8-Lead Plastic SOIC (SO Package) 0.1968 (5.00) 0.1890 (4.80) 8 5 0.1574 (4.00) 0.2440 (6.20) 0.1497 (3.80) 1 4 0.2284 (5.80) PIN 1 0.05B00S C(1.27) 00..00109969 ((00..5205))(cid:7) 45(cid:3) 0.0688 (1.75) 0.0098 (0.25) 0.0532 (1.35) 0.0040 (0.10) 8(cid:3) SEATING 0.0192 (0.49) 0.0098 (0.25) 0(cid:3) 0.0500 (1.27) PLANE 0.0138 (0.35) 0.0075 (0.19) 0.0160 (0.41) 8-Lead Cerdip (Q Package) 0.005 (0.13) 0.055 (1.4) MIN MAX 8 5 0.310 (7.87) PIN 1 0.220 (5.59) 1 4 0.100 (2.54) BSC 0.405 (10.29) MAX 00..322900 ((87..1337)) A. 0.060 (1.52) S. 0.200.(5.08) 0.015 (0.38) U. MAX N 0.200 (5.08) 0(3.1.8510) D I 0.125 (3.18) MIN E 15° T SEATING 0° 0.015 (0.38) N 0.023 (0.58) 0.070 (1.78)PLANE 0.008 (0.20) RI 0.014 (0.36) 0.030 (0.76) P REV. B –23–