2.7 V, 800 μA, 80 MHz Rail-to-Rail I/O Amplifiers Data Sheet AD8031/AD8032 FEATURES CONNECTION DIAGRAMS Low power NC 1 8 NC OUT1 1 AD8032 8 +VS Supply current 800 μA/amplifier –IN 2 – 7 +VS –IN1 2 –+ 7 OUT2 HigF8uh0l sMlypH espze,de −c ai3fn idedBd f abastat +n sd2e.wt7ti lVdin,t g+h 5 o(G Vn , =5 a +Vn1d ) ±5 V supplies –+VINS 43NC=ANDO+8C0O3N1NEC65T ONCUT 01056-001 +–INVS1 43 +– 65 –+IINN22 01056-002 Figure 1. 8-Lead PDIP (N) and Figure 2. 8-Lead PDIP (N), 30 V/μs slew rate SOIC_N (R) SOIC_N (R), and MSOP (RM) 125 ns settling time to 0.1% Rail-to-rail input and output AD8031 VOUT 1 5 +VS No phase reversal with input 0.5 V beyond supplies Input CMVR extends beyond rails by 200 mV –VS 2 + – LoOwu dtipsutot rstwioinn g to within 20 mV of either rail +IN 3 4 –IN 01056-003 Figure 3. 5-Lead SOT-23 (RJ-5) −62 dB @ 1 MHz, V = 2 V p-p O −86 dB @ 100 kHz, V = 4.6 V p-p O Output current: 15 mA Operating on supplies from +2.7 V to +12 V and dual supplies High grade option: V (maximum) = 1.5 mV up to ±6 V, the AD8031/AD8032 are ideal for a wide range of OS applications, from battery-operated systems with large bandwidth APPLICATIONS requirements to high speed systems where component density requires lower power dissipation. The AD8031/AD8032 are High speed, battery-operated systems available in 8-lead PDIP and 8-lead SOIC_N packages and High component density systems operate over the industrial temperature range of −40°C to Portable test instruments +85°C. The AD8031A is also available in the space-saving A/D buffers 5-lead SOT-23 package, and the AD8032A is available in an Active filters 8-lead MSOP package. High speed, set-and-demand amplifiers GENERAL DESCRIPTION VIN=4.85Vp-p VGO=UT+1=4.65Vp-p The AD8031 (single) and AD8032 (dual) single-supply, voltage feedback amplifiers feature high speed performance with 1V/DIV 1V/DIV 80 MHz of small signal bandwidth, 30 V/μs slew rate, and 125 ns settling time. This performance is possible while consuming less tinhcarne a4s.0e mthWe o opfe rpaotwioenr tfirmome o af shiingghl es p5e Ved s,u bpapttley.r yT-hpeoswe efereadtu res 2µs/DIV 01056-004 2µs/DIV 01056-005 Figure 4. Input VIN Figure 5. Output VOUT systems without compromising dynamic performance. +5V The products have true single-supply capability with rail-to-rail – input and output characteristics and are specified for +2.7 V, +5 V, VOUT abneydo ±n5d Vea scuhp rpaliile. sT. Theh eo uintppuutt vvoollttaaggee r sawngine gcsa nto e wxtietnhdin t o2 05 0m0 Vm Vof VIN + 1kΩ 1.7pF +2.5V 01056-006 each rail providing the maximum output dynamic range. Figure 6. Rail-to-Rail Performance at 100 kHz The AD8031/AD8032 also offer excellent signal quality for only 800 μA of supply current per amplifier; THD is −62 dBc with a 2 V p-p, 1 MHz output signal, and –86 dBc for a 100 kHz, 4.6 V p-p signal on +5 V supply. The low distortion and fast settling time make them ideal as buffers to single-supply ADCs. Rev. G Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Tel: 781.329.4700 ©2014 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com

AD8031/AD8032 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Theory of Operation ...................................................................... 13 Applications ....................................................................................... 1 Input Stage Operation ................................................................ 13 General Description ......................................................................... 1 Overdriving the Input Stage...................................................... 13 Connection Diagrams ...................................................................... 1 Output Stage, Open-Loop Gain and Distortion vs. Clearance from Power Supply ..................................................................... 14 Revision History ............................................................................... 2 Output Overdrive Recovery ...................................................... 14 Specifications ..................................................................................... 3 Driving Capacitive Loads .......................................................... 15 +2.7 V Supply ................................................................................ 3 Applications ..................................................................................... 16 +5 V Supply ................................................................................... 4 A 2 MHz Single-Supply, Biquad Band-Pass Filter ................. 16 ±5 V Supply ................................................................................... 5 High Performance, Single-Supply Line Driver........................... 16 Absolute Maximum Ratings ............................................................ 6 Outline Dimensions ....................................................................... 18 Maximum Power Dissipation ..................................................... 6 Ordering Guide .......................................................................... 20 ESD Caution .................................................................................. 6 Typical Performance Characteristics ............................................. 7 REVISION HISTORY 3/14—Rev. F to Rev. G Changes to Second Paragraph of Theory of Operation Section ... 13 Changes to Ordering Guide .......................................................... 20 8/13—Rev. E to Rev. F Changed Input Current Noise at f = 100 kHz from 2.4 pA/√Hz to 0.4 pA/√Hz (Throughout) .......................................................... 3 6/13—Rev. D to Rev. E Changes to DC Performance Parameter, Table 1 ......................... 3 Updated Outline Dimensions ....................................................... 19 Changes to Ordering Guide .......................................................... 20 11/08—Rev. C to Rev. D Change to Table 3 Column Heading .............................................. 5 Change to Ordering Guide ............................................................ 20 7/06—Rev. B to Rev. C Updated Format .................................................................. Universal Updated Outline Dimensions ....................................................... 18 Change to Ordering Guide ............................................................ 20 9/99—Rev. A to Rev. B Rev. G | Page 2 of 20

Data Sheet AD8031/AD8032 SPECIFICATIONS +2.7 V SUPPLY @ T = 25°C, V = 2.7 V, R = 1 kΩ to 1.35 V, R = 2.5 kΩ, unless otherwise noted. A S L F Table 1. AD8031A/AD8032A AD8031B/AD8032B Parameter Conditions Min Typ Max Min Typ Max Unit DYNAMIC PERFORMANCE –3 dB Small Signal Bandwidth G = +1, V < 0.4 V p-p 54 80 54 80 MHz O Slew Rate G = −1, V = 2 V step 25 30 25 30 V/µs O Settling Time to 0.1% G = −1, V = 2 V step, C = 10 pF 125 125 ns O L DISTORTION/NOISE PERFORMANCE Total Harmonic Distortion f = 1 MHz, V = 2 V p-p, G = +2 −62 −62 dBc C O f = 100 kHz, V = 2 V p-p, G = +2 −86 −86 dBc C O Input Voltage Noise f = 1 kHz 15 15 nV/√Hz Input Current Noise f = 100 kHz 0.4 0.4 pA/√Hz f = 1 kHz 5 5 pA/√Hz Crosstalk (AD8032 Only) f = 5 MHz −60 −60 dB DC PERFORMANCE Input Offset Voltage V = V /2; V = 1.35 V ±1 ±6 ±0.5 ±1.5 mV CM CC OUT T to T ±6 ±10 ±1.6 ±2.5 mV MIN MAX Offset Drift V = V /2; V = 1.35 V 10 10 µV/°C CM CC OUT Input Bias Current V = V /2; V = 1.35 V 0.45 2 0.45 2 µA CM CC OUT T to T 2.2 2.2 µA MIN MAX Input Offset Current 50 500 50 500 nA Open-Loop Gain V = V /2; V = 0.35 V to 2.35 V 76 80 76 80 dB CM CC OUT T to T 74 74 dB MIN MAX INPUT CHARACTERISTICS Common-Mode Input Resistance 40 40 MΩ Differential Input Resistance 280 280 kΩ Input Capacitance 1.6 1.6 pF Input Voltage Range −0.5 to −0.5 to V +3.2 +3.2 Input Common-Mode Voltage Range −0.2 to −0.2 to V +2.9 +2.9 Common-Mode Rejection Ratio V = 0 V to 2.7 V 46 64 46 64 dB CM V = 0 V to 1.55 V 58 74 58 74 dB CM Differential Input Voltage 3.4 3.4 V OUTPUT CHARACTERISTICS Output Voltage Swing Low R = 10 kΩ 0.05 0.02 0.05 0.02 V L Output Voltage Swing High 2.6 2.68 2.6 2.68 V Output Voltage Swing Low R = 1 kΩ 0.15 0.08 0.15 0.08 V L Output Voltage Swing High 2.55 2.6 2.55 2.6 V Output Current 15 15 mA Short Circuit Current Sourcing 21 21 mA Sinking −34 −34 mA Capacitive Load Drive G = +2 (See Figure 46) 15 15 pF POWER SUPPLY Operating Range 2.7 12 2.7 12 V Quiescent Current per Amplifier 750 1250 750 1250 μA Power Supply Rejection Ratio V− = 0 V to −1 V or 75 86 75 86 dB S V+ = +2.7 V to +3.7 V S Rev. G | Page 3 of 20

AD8031/AD8032 Data Sheet +5 V SUPPLY @ T = 25°C, V = 5 V, R = 1 kΩ to 2.5 V, R = 2.5 kΩ, unless otherwise noted. A S L F Table 2. AD8031A/AD8032A AD8031B/AD8032B Parameter Conditions Min Typ Max Min Typ Max Unit DYNAMIC PERFORMANCE −3 dB Small Signal Bandwidth G = +1, V < 0.4 V p-p 54 80 54 80 MHz O Slew Rate G = −1, V = 2 V step 27 32 27 32 V/µs O Settling Time to 0.1% G = −1, V = 2 V step, C = 10 pF 125 125 ns O L DISTORTION/NOISE PERFORMANCE Total Harmonic Distortion f = 1 MHz, V = 2 V p-p, G = +2 −62 −62 dBc C O f = 100 kHz, V = 2 V p-p, G = +2 −86 −86 dBc C O Input Voltage Noise f = 1 kHz 15 15 nV/√Hz Input Current Noise f = 100 kHz 0.4 0.4 pA/√Hz f = 1 kHz 5 5 pA/√Hz Differential Gain R = 1 kΩ 0.17 0.17 % L Differential Phase R = 1 kΩ 0.11 0.11 Degrees L Crosstalk (AD8032 Only) f = 5 MHz −60 −60 dB DC PERFORMANCE Input Offset Voltage V = V /2; V = 2.5 V ±1 ±6 ±0.5 ±1.5 mV CM CC OUT T to T ±6 ±10 ±1.6 ±2.5 mV MIN MAX Offset Drift V = V /2; V = 2.5 V 5 5 µV/°C CM CC OUT Input Bias Current V = V /2; V = 2.5 V 0.45 1.2 0.45 1.2 µA CM CC OUT T to T 2.0 2.0 µA MIN MAX Input Offset Current 50 350 50 250 nA Open-Loop Gain V = V /2; V = 1.5 V to 3.5 V 76 82 76 82 dB CM CC OUT T to T 74 74 dB MIN MAX INPUT CHARACTERISTICS Common-Mode Input Resistance 40 40 MΩ Differential Input Resistance 280 280 kΩ Input Capacitance 1.6 1.6 pF Input Voltage Range −0.5 to −0.5 to V +5.5 +5.5 Input Common-Mode Voltage Range −0.2 to −0.2 to V +5.2 +5.2 Common-Mode Rejection Ratio V = 0 V to 5 V 56 70 56 70 dB CM V = 0 V to 3.8 V 66 80 66 80 dB CM Differential Input Voltage 3.4 3.4 V OUTPUT CHARACTERISTICS Output Voltage Swing Low R = 10 kΩ 0.05 0.02 0.05 0.02 V L Output Voltage Swing High 4.95 4.98 4.95 4.98 V Output Voltage Swing Low R = 1 kΩ 0.2 0.1 0.2 0.1 V L Output Voltage Swing High 4.8 4.9 4.8 4.9 V Output Current 15 15 mA Short Circuit Current Sourcing 28 28 mA Sinking −46 −46 mA Capacitive Load Drive G = +2 (See Figure 46) 15 15 pF POWER SUPPLY Operating Range 2.7 12 2.7 12 V Quiescent Current per Amplifier 800 1400 800 1400 µA Power Supply Rejection Ratio V− = 0 V to −1 V or 75 86 75 86 dB S V+ = +5 V to +6 V S Rev. G | Page 4 of 20

Data Sheet AD8031/AD8032 ±5 V SUPPLY @ T = 25°C, V = ±5 V, R = 1 kΩ to 0 V, R = 2.5 kΩ, unless otherwise noted. A S L F Table 3. AD8031A/AD8032A AD8031B/AD8032B Parameter Conditions Min Typ Max Min Typ Max Unit DYNAMIC PERFORMANCE −3 dB Small Signal Bandwidth G = +1, V < 0.4 V p-p 54 80 54 80 MHz O Slew Rate G = −1, V = 2 V step 30 35 30 35 V/µs O Settling Time to 0.1% G = −1, V = 2 V step, C = 10 pF 125 125 ns O L DISTORTION/NOISE PERFORMANCE Total Harmonic Distortion f = 1 MHz, V = 2 V p-p, G = +2 −62 −62 dBc C O f = 100 kHz, V = 2 V p-p, G = +2 −86 −86 dBc C O Input Voltage Noise f = 1 kHz 15 15 nV/√Hz Input Current Noise f = 100 kHz 0.4 0.4 pA/√Hz f = 1 kHz 5 5 pA/√Hz Differential Gain R = 1 kΩ 0.15 0.15 % L Differential Phase R = 1 kΩ 0.15 0.15 Degrees L Crosstalk (AD8032 Only) f = 5 MHz −60 −60 dB DC PERFORMANCE Input Offset Voltage V = 0 V; V = 0 V ±1 ±6 ±0.5 ±1.5 mV CM OUT T to T ±6 ±10 ±1.6 ±2.5 mV MIN MAX Offset Drift V = 0 V; V = 0 V 5 5 µV/°C CM OUT Input Bias Current V = 0 V; V = 0 V 0.45 1.2 0.45 1.2 µA CM OUT T to T 2.0 2.0 µA MIN MAX Input Offset Current 50 350 50 250 nA Open-Loop Gain V = 0 V; V = ±2 V 76 80 76 80 dB CM OUT T to T 74 74 dB MIN MAX INPUT CHARACTERISTICS Common-Mode Input Resistance 40 40 MΩ Differential Input Resistance 280 280 kΩ Input Capacitance 1.6 1.6 pF Input Voltage Range −5.5 to −5.5 to V +5.5 +5.5 Input Common-Mode Voltage Range −5.2 to −5.2 to V +5.2 +5.2 Common-Mode Rejection Ratio V = −5 V to +5 V 60 80 60 80 dB CM V = −5 V to +3.5 V 66 90 66 90 dB CM Differential/Input Voltage 3.4 3.4 V OUTPUT CHARACTERISTICS Output Voltage Swing Low R = 10 kΩ −4.94 −4.98 −4.94 −4.98 V L Output Voltage Swing High +4.94 +4.98 +4.94 +4.98 V Output Voltage Swing Low R = 1 kΩ −4.7 −4.85 −4.7 −4.85 V L Output Voltage Swing High +4.7 +4.75 +4.7 +4.75 V Output Current 15 15 mA Short Circuit Current Sourcing 35 35 mA Sinking −50 −50 mA Capacitive Load Drive G = +2 (See Figure 46) 15 15 pF POWER SUPPLY Operating Range ±1.35 ±6 ±1.35 ±6 V Quiescent Current per Amplifier 900 1600 900 1600 µA Power Supply Rejection Ratio V− = −5 V to −6 V or 76 86 76 86 dB S V+ = +5 V to +6 V S Rev. G | Page 5 of 20

AD8031/AD8032 Data Sheet ABSOLUTE MAXIMUM RATINGS Table 4. MAXIMUM POWER DISSIPATION Parameter Rating The maximum power that can be safely dissipated by the Supply Voltage 12.6 V AD8031/AD8032 is limited by the associated rise in junction Internal Power Dissipation1 temperature. The maximum safe junction temperature for 8-Lead PDIP (N) 1.3 W plastic encapsulated devices is determined by the glass 8-Lead SOIC_N (R) 0.8 W transition temperature of the plastic, approximately 150°C. 8-Lead MSOP (RM) 0.6 W Exceeding this limit temporarily can cause a shift in parametric 5-Lead SOT-23 (RJ) 0.5 W performance due to a change in the stresses exerted on the die Input Voltage (Common Mode) ±V ± 0.5 V S by the package. Exceeding a junction temperature of 175°C for Differential Input Voltage ±3.4 V an extended period can result in device failure. Output Short-Circuit Duration Observe Power Derating Curves While the AD8031/AD8032 are internally short-circuit Storage Temperature Range (N, R, RM, RJ) −65°C to +125°C protected, this may not be sufficient to guarantee that the Lead Temperature (Soldering 10 sec) 300°C maximum junction temperature (150°C) is not exceeded under all conditions. To ensure proper operation, it is necessary to 1 Specification is for the device in free air: 8-Lead PDIP: θJA = 90°C/W. observe the maximum power derating curves shown in Figure 7. 8-Lead SOIC_N: θJA = 155°C/W. 8-Lead MSOP: θJA = 200°C/W. 2.0 5-Lead SOT-23: θJA = 240°C/W. TJ = +150°C 8-LEAD PDIP W) Stresses above those listed under Absolute Maximum Ratings N ( O1.5 may cause permanent damage to the device. This is a stress ATI 8-LEAD SOIC P rating only; functional operation of the device at these or any SI S other conditions above those indicated in the operational R DI1.0 8-LEAD MSOP E section of this specification is not implied. Exposure to absolute W O maximum rating conditions for extended periods may affect M P device reliability. XIMU0.5 5-LEAD SOT-23 MA 0–50–40–30–20–A1M0BIE0NT1 T0EM2P0ER3A0TU4R0E (°5C0) 60 70 80 90 01056-007 Figure 7. Maximum Power Dissipation vs. Temperature ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. Rev. G | Page 6 of 20

Data Sheet AD8031/AD8032 TYPICAL PERFORMANCE CHARACTERISTICS 90 800 80 600 N=250 S IN BIN6700 ENT (nA) 420000 PART50 CURR 0 VS=2.7V VS=5V VS=10V OF 40 AS R BI–200 UMBE30 NPUT –400 N20 I –600 10 0 –5 –4 –3 –2 –1VOS0(mV)1 2 3 4 5 01056-008 –8000 1 2 CO3MMON4-MOD5EVOL6TAGE7(V) 8 9 10 01056-011 Figure 8. Typical VOS Distribution @ VS = 5 V Figure 11. Input Bias Current vs. Common-Mode Voltage 2.5 0 VS=5V –0.1 2.3 mV) mV) E ( E ( –0.2 G2.1 G OLTA VS=+5V OLTA –0.3 V V ET 1.9 ET S S OFF VS=±5V OFF –0.4 1.7 –0.5 1.5–40 –30 –20 –10 0TE1M0PE2R0AT3U0RE4(0°C)50 60 70 80 90 01056-009 –0.60 0.5 1.0 CO1M.5MO2N.-0MOD2.E5VO3L.T0AG3E.5(V) 4.0 4.5 5.0 01056-012 Figure 9. Input Offset Voltage vs. Temperature Figure 12. VOS vs. Common-Mode Voltage 1.00 1000 0.95 VS=5V A) 950 ±IS,VS=±5V 0.90 ER (µ 900 A)0.85 LIFI T BIAS (µ00..7850 ENT/AMP 880500 +IS,VS=+5V U R P0.70 R N U 750 I C 0.65 Y +IS,VS=+2.7V PL 700 0.60 P U S 0.55 650 0.50–40 –30 –20 –10 0TE1M0PE2R0AT3U0RE4(0°C)50 60 70 80 90 01056-010 600–40 –30 –20 –10 0 TE1M0PE2R0AT3U0RE4(0°C)50 60 70 80 90 01056-013 Figure 10. Input Bias Current vs. Temperature Figure 13. Supply Current vs. Temperature Rev. G | Page 7 of 20

AD8031/AD8032 Data Sheet 0 1.2 VCC=2.7V VCC 1.0 V (V)CC–0.5 V (V)EE 0.8 VCC=10V VIN RLOAVDOUT ROM –1.0 VCC=5V ROM VEE VCC DIFFERENCE F ––12..50 VCC=10V VIN VCC RLOAVDOUT DIFFERENCE F 00..64 VCC=5V 2 VEE 0.2 VCC 2 VCC=2.7V –2.5100 RLO1AkD(Ω) 10k 01056-014 0100 RLOA1kD(Ω) 10k 01056-017 Figure 14. +Output Saturation Voltage vs. RLOAD @ +85°C Figure 17. −Output Saturation Voltage vs. RLOAD @ +85°C 0 1.2 VCC=2.7V VCC 1.0 –0.5 V (V)CC V (V)EE 0.8 VCC=10V VIN RLOAVDOUT M –1.0 VCC=5V M VEE RO RO VCC E F E F 0.6 2 ENC –1.5 VCC ENC VCC=5V R R DIFFE –2.0 VCC=10V VIN RLOAVDOUT DIFFE 0.4 VEE 0.2 VCC 2 VCC=2.7V –2.5100 RLO1AkD(Ω) 10k 01056-015 0100 RLOA1kD(Ω) 10k 01056-018 Figure 15. +Output Saturation Voltage vs. RLOAD @ +25°C Figure 18. −Output Saturation Voltage vs. RLOAD @ +25°C 0 1.2 VCC=2.7V VCC 1.0 ROM V (V)CC––01..50 VCC=5V ROM V (V)EE 0.8 VCC=10V VIN VEE VCCRLOAVDOUT DIFFERENCE F ––12..50 VCC=10V VIN VCC RLOAVDOUT DIFFERENCE F 00..64 VCC=5V 2 VEE 0.2 VCC 2 VCC=2.7V –2.5100 RLO1AkD(Ω) 10k 01056-016 0100 RLOA1kD(Ω) 10k 01056-019 Figure 16. +Output Saturation Voltage vs. RLOAD @ −40°C Figure 19. −Output Saturation Voltage vs. RLOAD @ −40°C Rev. G | Page 8 of 20

Data Sheet AD8031/AD8032 110 VS=5V 105 500mV 1V 100 –AOL mA) 10 10900 95 T ( N B) 90 RE N (d 85 +AOL CUR 0 AI S G 80 BIA 75 UT VS=5V P –10 10 N 70 I 0% 65 500mV 60 0 2k 4kRLOAD(Ω)6k 8k 10k 01056-020 –1.5 0.5INPUTVO2L.5TAGE(V)4.5 6.5 01056-023 Figure 20. Open-Loop Gain (AOL) vs. RLOAD Figure 23. Differential Input Overvoltage I-V Characteristics 86 0.05 VRSL==51VkΩ N (%) 0 84 GAI–0.05 –AOL DIFF –0.10 B) 82 –0.15 N (d 1ST 2ND 3RD 4TH 5TH 6TH 7TH 8TH 9TH10TH11TH AI +AOL s) 0.10 G 80 ee egr 0.05 D 78 ASE ( 0 H P–0.05 76–40 –30 –20 –10 0TE1M0PE2R0AT3U0RE4(0°C)50 60 70 80 90 01056-021 DIFF –0.10 1ST 2ND 3RD 4TH 5TH 6TH 7TH 8TH 9TH10TH11TH 01056-024 Figure 21. Open Loop Gain vs. (AOL) Temperature Figure 24. Differential Gain and Phase @ VS = ±5 V; RL = 1 kΩ 110 100 RLOAD=10kΩ VS=5V VS=5V 100 Hz) 30 100 Hz) V/ VOLTAGENOISE A/ n p 90 E ( E ( dB) RLOAD=1kΩ NOIS 10 10 NOIS A (OL 80 TAGE 3 1 RENT L R 70 VO CU T CURRENTNOISE T U U NP 1 0.1 NP 60 I I 500 0.5 1.0 1.5 2.0VOU2T.5(V)3.0 3.5 4.0 4.5 5.0 01056-022 0.310 100 1kFREQU1E0NkCY(Hz1)00k 1M 10M 01056-025 Figure 22. Open-Loop Gain (AOL) vs. VOUT Figure 25. Input Voltage Noise vs. Frequency Rev. G | Page 9 of 20

AD8031/AD8032 Data Sheet 5 4 VS=5V 40 G=+1 dB) 32 RL=1kΩ GAIN 3200 AIN(dB) AIN ( 1 10 OPG G O ED 0 0 N-L Z E NORMALI –––123 SE(Degrees)––11–389500 PHASE ––2100OP A –4 PH–225 –5 0.1 FRE1QUENCY(MHz1)0 100 01056-026 0.3 1 FREQUENC1Y0(MHz) 100 01056-029 Figure 26. Unity Gain, −3 dB Bandwidth Figure 29. Open-Loop Frequency Response 3 –20 B) 21 VVSIN == 5–V16dBm +85°C ON (dBc) –30 G=+1,RL=2kΩTOVC2C AIN (d 0 –40°C TORTI –40 NORMALIZED G –––123 VIN VS 2kΩ VOUT +25°C TAL HARMONIC DIS –––567000 V2S.5=V2p.7-Vp V1S.3=V2p.7-Vp 2VVSp=-2p.7V –4 50Ω TO 4.8Vp-p VS=5V –5 0.1 FRE1QUENCY (MHz1)0 100 01056-027 –801k F10UkNDAMENTA1L0F0RkEQUENCY(1HMz) 10M 01056-030 Figure 27. Closed-Loop Gain vs. Temperature Figure 30. Total Harmonic Distortion vs. Frequency; G = +1 2 –20 N (dB) –110 RL+CLVSTO=+12.3.75VVVS=±5V VTROSL=+2.+C55VLV RTION (dBc) ––3400 GVRSL===+512VkΩTOV2CC GAI –2 STO –50 4.8Vp-p SED-LOOP ––43 GCRLL===+511pkΩF RMONIC DI ––6700 1Vp-p O –5 A 4.6Vp-p CL L H –80 –6 A T 4Vp-p –7 TO –90 –1800k 1M FREQUENCY1(0HMz) 100M 01056-028 –1001k F1U0kNDAMENTAL10F0RkEQUENCY(1HMz) 10M 01056-031 Figure 28. Closed-Loop Gain vs. Supply Voltage Figure 31. Total Harmonic Distortion vs. Frequency; G +2 Rev. G | Page 10 of 20

Data Sheet AD8031/AD8032 10 0 VS=±5V B) 8 TIO (d –20 VS=5V A p) ON R –40 T (V p- 6 VS=+5V JECTI –60 U E P R OUT 4 PLY –80 VS=+2.7V UP S 2 ER –100 W O P–120 01k 10k FREQU1E0N0kCY(Hz) 1M 10M 01056-032 100 1k 10kFREQU1E0N0kCY(Hz)1M 10M 100M 01056-035 Figure 32. Large Signal Response Figure 35. PSRR vs. Frequency VS=5V RL=10kΩTO2.5V 100 RBT=50Ω 5.5 VIN=6Vp-p 50 G=+1 4.5 10 Ω) 3.5 R (OUT 1 1V/DIV 2.5 1.5 0.5 0.1 RBT=0Ω RBT VOUT –0.5 0.1 FRE1QUENCY(MHz1)0 100 200 01056-033 10µs/DIV 01056-036 Figure 33. ROUT vs. Frequency Figure 36. Output Voltage 0 B) VS=5V INPUT VGS==+51V d TIO ( –20 5.5 IBNEPYUOTN=D6R50AmILVS A N R 4.5 O TI –40 3.5 C V REJE 1V/DI 2.5 E –60 1.5 D O M 0.5 N- MO –80 –0.5 M O C –100100 1k 1F0RkEQUENC10Y0(kHz) 1M 10M 01056-034 10µs/DIV 01056-037 Figure 34. CMRR vs. Frequency Figure 37. Output Voltage Phase Reversal Behavior Rev. G | Page 11 of 20

AD8031/AD8032 Data Sheet R+2L.5TVO RGF==+01Ω 2.56 RL=2kΩTO2.5V CL=5pFTO2.5V 2.54 VS=5V V V 2.52 DI DI V/ V/ 2.50 m m 500 20 2.48 2.46 VS=+5V 2.44 RL=1kΩ RLTO GND G=–1 0 10µs/DIV 01056-038 50ns/DIV 01056-041 Figure 38. Output Swing Figure 41. 100 mV Step Response G=+2 –50 3.1 RRFL==R2kGΩ=2.5kΩ dB) –60 2.9 CVSL==55VpF ALK( –70 mV/DIV 22..75 CROSST ––9800 VVSIN==±+21.50VdBm 00 –100 2 2.3 2.5kΩ 2.5kΩ 2.5kΩ 2.5kΩ 2.1 1.9 VIN 1kΩ VOUT 50Ω 50Ω TRANSMITTER RECEIVER 50ns/DIV 01056-039 00..11 FRE11QUENCY(MHz11)00 110000 220000 01056-042 Figure 39. 1 V Step Response Figure 42. Crosstalk vs. Frequency VS = 2.7V RL = 1kΩ 2.85 G = –1 2.35 V1.85 DI mV/1.35 5000.85 R1.L3 5TVO 0.35 RL TO GND 10µs/DIV 01056-040 Figure 40. Output Swing Rev. G | Page 12 of 20

Data Sheet AD8031/AD8032 THEORY OF OPERATION The AD8031/AD8032 are single and dual versions of high Switching to the NPN pair as the common-mode voltage is speed, low power, voltage feedback amplifiers featuring an driven beyond 1 V within the positive supply allows the amplifier innovative architecture that maximizes the dynamic range to provide useful operation for signals at either end of the capability on the inputs and outputs. The linear input common- supply voltage range and eliminates the possibility of phase mode range exceeds either supply voltage by 200 mV, and the reversal for input signals up to 500 mV beyond either power amplifiers show no phase reversal up to 500 mV beyond supply. supply. Offset voltage also changes to reflect the offset of the The output swings to within 20 mV of either supply when input pair in control. The transition region is small, approximately driving a light load; 300 mV when driving up to 5 mA. 180 mV. These sudden changes in the dc parameters of the input stage can produce glitches that adversely affect distortion. Fabricated on Analog Devices, Inc. eXtra Fast Complementary Bipolar (XFCB) process, the amplifier provides an impressive OVERDRIVING THE INPUT STAGE 80 MHz bandwidth when used as a follower and a 30 V/µs slew Sustained input differential voltages greater than 3.4 V should rate at only 800 µA supply current. Careful design allows the be avoided as the input transistors can be damaged. Input clamp amplifier to operate with a supply voltage as low as 2.7 V. diodes are recommended if the possibility of this condition INPUT STAGE OPERATION exists. A simplified schematic of the input stage appears in Figure 43. The voltages at the collectors of the input pairs are set to For common-mode voltages up to 1.1 V within the positive 200 mV from the power supply rails. This allows the amplifier supply (0 V to 3.9 V on a single 5 V supply), tail current I2 to remain in linear operation for input voltages up to 500 mV flows through the PNP differential pair, Q13 and Q17. Q5 is cut beyond the supply voltages. Driving the input common-mode off; no bias current is routed to the parallel NPN differential voltage beyond that point will forward bias the collector junction of pair, Q2 and Q3. As the common-mode voltage is driven within the input transistor, resulting in phase reversal. Sustaining this 1.1 V of the positive supply, Q5 turns on and routes the tail condition for any length of time should be avoided because it is current away from the PNP pair and to the NPN pair. During easy to exceed the maximum allowed input differential voltage this transition region, the input current of the amplifier changes when the amplifier is in phase reversal. magnitude and direction. Reusing the same tail current ensures that the input stage has the same transconductance, which determines the gain and bandwidth of the amplifier, in both regions of operation. VCC Q9 I920µA R2k1Ω I235µA R2k2Ω 1.1V 50kRΩ5 VIN R6 R7 Q3 Q2 1 Q6 Q10 1 Q5 850Ω 850Ω R8 R9 4 Q8 Q7 4 850Ω 850Ω VIP Q13 Q17 I4 OUTPUTSTAGE, 25µA COMMON-MODE FEEDBACK Q14 Q11 4 4 1 1 Q15 Q16 R3 R4 I1 2kΩ 2kΩ 5µA VEE Q18 Q4 01056-043 Figure 43. Simplified Schematic of AD8031 Input Stage Rev. G | Page 13 of 20

AD8031/AD8032 Data Sheet OUTPUT STAGE, OPEN-LOOP GAIN AND The open-loop gain of the AD8031 decreases approximately DISTORTION vs. CLEARANCE FROM POWER linearly with load resistance and depends on the output voltage. SUPPLY Open-loop gain stays constant to within 250 mV of the positive power supply, 150 mV of the negative power supply, and then The AD8031 features a rail-to-rail output stage. The output decreases as the output transistors are driven further into transistors operate as common-emitter amplifiers, providing the saturation. output drive current as well as a large portion of the amplifier’s open-loop gain. The distortion performance of the AD8031/AD8032 amplifiers differs from conventional amplifiers. Typically, the distortion I215µA Q42 Q51 I225µA performance of the amplifier degrades as the output voltage Q47 amplitude increases. DIFFERENTIAL DRIVE Q37 Q38 Used as a unity gain follower, the output of the AD8031/ FROM C9 INPUTSTAGE Q68 5pF AD8032 exhibits more distortion in the peak output voltage Q20 3R0209Ω + region around V − 0.7 V. This unusual distortion characteristic is CC Q21 Q27 C5 VOUT caused by the input stage architecture and is discussed in detail Q43 Q48 1+.5pF in the Input Stage Operation section, Q49 OUTPUT OVERDRIVE RECOVERY 25µIA4 25µIA5 Q50 Q44 01056-044 Oattuetmpuptt so vtoe rddrriivvee tohfe a onu atpmuptl vifoieltra ogcec tuor as wlehveeln o tuhtes iadme pitlsi fnieorr mal Figure 44. Output Stage Simplified Schematic range. After the overdrive condition is removed, the amplifier must recover to normal operation in a reasonable amount of The output voltage limit depends on how much current the time. As shown in Figure 45, the AD8031/AD8032 recover output transistors are required to source or sink. For applications within 100 ns from negative overdrive and within 80 ns from with low drive requirements (for instance, a unity gain follower positive overdrive. driving another amplifier input), the AD8031 typically swings within 20 mV of either voltage supply. As the required current RG RF RF=RG=2kΩ load increases, the saturation output voltage increases linearly as VOUT ILOAD × RC VIN 50Ω RL where: I is the required load current. LOAD R is the output transistor collector resistance. C For the AD8031, the collector resistances for both output transistors are typically 25 Ω. As the current load exceeds the VS=±2.5V rreaqteudi roeudt ptou td criuvrer ethnet oofu 1tp5u mt tAra, nthsies taomr oinutnot soaft ubraastei odnr irveea ccuhrerse intst 1V RVILN==1±k2Ω.5TVO GND 100ns 01056-045 Figure 45. Overdrive Recovery limit, and the amplifier’s output swing rapidly decreases. Rev. G | Page 14 of 20

Data Sheet AD8031/AD8032 1000 DRIVING CAPACITIVE LOADS VS=5V RS=5Ω 200mVSTEP Capacitive loads interact with an op amp’s output impedance to WITH30% OVERSHOOT create an extra delay in the feedback path. This reduces circuit F) RS=0Ω p stability and can cause unwanted ringing and oscillation. A D ( 100 A given value of capacitance causes much less ringing when the O L amplifier is used with a higher noise gain. VE RS=20Ω TI The capacitive load drive of the AD8031/AD8032 can be APACI 10 RS=20Ω RG RF increased by adding a low valued resistor in series with the C RS VOUT capacitive load. Introducing a series resistor tends to isolate the RS=0Ω,5Ω CL capacitive load from the feedback loop, thereby diminishing its icnafpluaceinticvee. Fdirgivuer efo 4r6 v sahroywinsg t vhoel teaffgeec gtsa ionfs a. Asesr itehse rcelsoissetodr- loono pth e 10 1 CLOSE2D-LOOP GA3IN(V/V) 4 5 01056-046 gain is increased, the larger phase margin allows for larger Figure 46. Capacitive Load Drive vs. Closed-Loop Gain capacitive loads with less overshoot. Adding a series resistor at lower closed-loop gains accomplishes the same effect. For large capacitive loads, the frequency response of the amplifier is dominated by the roll-off of the series resistor and capacitive load. Rev. G | Page 15 of 20

AD8031/AD8032 Data Sheet APPLICATIONS A 2 MHz SINGLE-SUPPLY, BIQUAD BAND-PASS FILTER 0 Figure 47 shows a circuit for a single-supply, biquad band-pass filter with a center frequency of 2 MHz. A 2.5 V bias level is –10 easily created by connecting the noninverting inputs of all three op amps to a resistor divider consisting of two 1 kΩ resistors connected between 5 V and ground. This bias point is also B) –20 d decoupled to ground with a 0.1 µF capacitor. The frequency AIN ( response of the filter is shown in Figure 48. G –30 To maintain an accurate center frequency, it is essential that the –40 op amp have sufficient loop gain at 2 MHz. This requires the choice of an op amp with a significantly higher unity gain, –50 cArDos8s0o3v1e/rA frDeq8u03en2 cisy .4 T0h Me uHnzi.t yM gualitnip, lcyrionsgs othvee ro fpreenqu-leonocpy g oafi nth bey 10k 100k FREQU1EMNCY(Hz) 10M 100M 01056-048 the feedback factors of the individual op amp circuits yields the Figure 48. Frequency Response of 2 MHz Band-Pass Filter loop gain for each gain stage. From the feedback networks of HIGH PERFORMANCE, SINGLE-SUPPLY LINE DRIVER the individual op amp circuits, it can be seen that each op amp has a loop gain of at least 21 dB. This level is high enough to Even though the AD8031/AD8032 swing close to both rails, the ensure that the center frequency of the filter is not affected by AD8031 has optimum distortion performance when the signal the op amp’s bandwidth. If, for example, an op amp with a gain has a common-mode level half way between the supplies and bandwidth product of 10 MHz was chosen in this application, when there is about 500 mV of headroom to each rail. If low the resulting center frequency would shift by 20% to 1.6 MHz. distortion is required in single-supply applications for signals that swing close to ground, an emitter-follower circuit can be R6 1kΩ used at the op amp output. C1 50pF 5V R2 10µF 2kΩ R4 2kΩ 5V 0.1µF 0.1µF 5V C2 VIN 3Rk1Ω1kΩ 2Rk3Ω 0.1µF 2Rk5Ω 50pF VIN 49.9Ω 23 7 6 2N3904 AD8031 4 AD8031 1/2 AD8032 AD18/2032 2.49kΩ 2.49kΩ 49.9Ω VOUT 0.1µF 1kΩ VOUT 01056-047 Figure 49. Low Distortion Line Driver for Si2n0g0lΩe-Supply, Ground Re4f9e.r9eΩnced Sig01056-049na ls Figure 47. A 2 MHz, Biquad Band-Pass Filter Using AD8031/AD8032 Figure 49 shows the AD8031 configured as a single-supply, gain- of-2 line driver. With the output driving a back-terminated 50 Ω line, the overall gain from V to V is unity. In addition IN OUT to minimizing reflections, the 50 Ω back termination resistor protects the transistor from damage if the cable is short circuited. The emitter follower, which is inside the feedback loop, ensures that the output voltage from the AD8031 stays about 700 mV above ground. Using this circuit, low distortion is attainable even when the output signal swings to within 50 mV of ground. The circuit was tested at 500 kHz and 2 MHz. Rev. G | Page 16 of 20

Data Sheet AD8031/AD8032 Figure 50 and Figure 51 show the output signal swing and This circuit could also be used to drive the analog input of a frequency spectrum at 500 kHz. At this frequency, the output single-supply, high speed ADC whose input voltage range is signal (at V ), which has a peak-to-peak swing of 1.95 V OUT referenced to ground (for example, 0 V to 2 V or 0 V to 4 V). In (50 mV to 2 V), has a THD of −68 dB (SFDR = −77 dB). this case, a back termination resistor is not necessary (assuming a short physical distance from transistor to ADC); therefore, the emitter of the external transistor would be connected directly to the ADC input. The available output voltage swing of the circuit 100 90 would therefore be doubled. 2V 1.5V 100 90 10 0% 50mV 0.5V 1µs 01056-050 Figure 50. Output Signal Swing of Low Distortion Line Driver at 500 kHz 10 +9dBm 0% V) 50mV 0.2V 200ns 01056-052 DI Figure 52. Output Signal Swing of Low Distortion Line Driver at 2 MHz B/ d 10 +7dBm E ( L A C S CAL DIV) TI B/ R d VE E (10 L A C START0Hz STOP5MHz 01056-051 TICAL S Figure 51. THD of Low Distortion Line Driver at 500 kHz ER V Figure 52 and Figure 53 show the output signal swing and fdreegqruaednactiyo snp ienc tsriugnma la qt u2 aMlitHy za.t Athse e hxpigehceter dfr, ethquereen icsy .s oWmhee n the START0Hz STOP20MHz 01056-053 Figure 53. THD of Low Distortion Line Driver at 2 MHz output signal has a peak-to-peak swing of 1.45 V (swinging from 50 mV to 1.5 V), the THD is −55 dB (SFDR = −60 dB). Rev. G | Page 17 of 20

AD8031/AD8032 Data Sheet OUTLINE DIMENSIONS 0.400 (10.16) 0.365 (9.27) 0.355 (9.02) 8 5 0.280 (7.11) 0.250 (6.35) 1 4 0.240 (6.10) 0.325 (8.26) 0.310 (7.87) 0.100 (2.54) 0.300 (7.62) BSC 0.060 (1.52) 0.195 (4.95) 0.210 (5.33) MAX 0.130 (3.30) MAX 0.115 (2.92) 0.015 0.150 (3.81) (0.38) 0.015 (0.38) 0.130 (3.30) MIN GAUGE 0.115 (2.92) SEATING PLANE 0.014 (0.36) PLANE 0.010 (0.25) 0.022 (0.56) 0.008 (0.20) 0.005 (0.13) 0.430 (10.92) 0.018 (0.46) MIN MAX 0.014 (0.36) 0.070 (1.78) 0.060 (1.52) 0.045 (1.14) COMPLIANTTO JEDEC STANDARDS MS-001 CONTROLLING DIMENSIONSARE IN INCHES; MILLIMETER DIMENSIONS (RCINEOFRPEANRERERENN LCTEEHA EODSNSEL MSY)AAAYNR BDEE AR CROOEU NNNFODIGETUDAR-POEPFDRFOA INSPC RWHIAH ETOEQL UFEIO VORAR LU EHSNAETL ISFN FLDOEEARSDIGSN.. 070606-A Figure 54. 8-Lead Plastic Dual In-Line Package [PDIP] Narrow Body (N-8) Dimensions shown in inches and (millimeters) 5.00(0.1968) 4.80(0.1890) 8 5 4.00(0.1574) 6.20(0.2441) 3.80(0.1497) 1 4 5.80(0.2284) 1.27(0.0500) 0.50(0.0196) BSC 1.75(0.0688) 0.25(0.0099) 45° 0.25(0.0098) 1.35(0.0532) 8° 0.10(0.0040) 0° COPLANARITY 0.51(0.0201) 0.10 SEATING 0.31(0.0122) 0.25(0.0098) 10..2470((00..00510507)) PLANE 0.17(0.0067) COMPLIANTTOJEDECSTANDARDSMS-012-AA C(RINEOFNPEATRRREOENNLCLTEIHNEOGSNDELISYM)AEANNRDSEIAORRNOESUNANORDETEDAIN-POMPFRIFLOLMPIMIRLELIATIMTEEERTFSEO;RIRNECUQHSUEDIVIINMAELDENENSSTIIOGSNNFS.OR 012407-A Figure 55. 8-Lead Standard Small Outline Package [SOIC_N] Narrow Body (R-8) Dimensions shown in millimeters and (inches) Rev. G | Page 18 of 20

Data Sheet AD8031/AD8032 3.00 2.90 2.80 1.70 5 4 3.00 1.60 2.80 1.50 2.60 1 2 3 0.95BSC 1.90 BSC 1.30 1.15 0.90 1.45MAX 0.20MAX 0.95MIN 0.08MIN 0.55 0.15MAX 10° 0.45 0.05MIN 0.50MAX SPELAATNIENG 5° B0S.6C0 0.35 0.35MIN 0° COMPLIANTTOJEDECSTANDARDSMO-178-AA 11-01-2010-A Figure 56. 5-Lead Small Outline Transistor Package [SOT-23] (RJ-5) Dimensions shown in millimeters 3.20 3.00 2.80 8 5 5.15 3.20 4.90 3.00 4.65 2.80 1 4 PIN 1 IDENTIFIER 0.65 BSC 0.95 15° MAX 0.85 1.10 MAX 0.75 0.80 0.15 0.40 6° 0.23 0.55 CO0P.0L50A.1N0ARICTOYMPLIANT0. 2T5O JEDEC STA0°NDARDS 0M.0O9-187-AA 0.40 10-07-2009-B Figure 57. 8-Lead Mini Small Outline Package [MSOP] (RM-8) Dimensions shown in millimeters Rev. G | Page 19 of 20

AD8031/AD8032 Data Sheet ORDERING GUIDE Model1 Temperature Range Package Description Package Option Branding AD8031ANZ –40°C to +85°C 8-Lead PDIP N-8 AD8031AR –40°C to +85°C 8-Lead SOIC_N R-8 AD8031ARZ –40°C to +85°C 8-Lead SOIC_N R-8 AD8031ARZ-REEL –40°C to +85°C 8-Lead SOIC_N, 13" Tape and Reel R-8 AD8031ARZ-REEL7 –40°C to +85°C 8-Lead SOIC_N, 7" Tape and Reel R-8 AD8031ART-R2 –40°C to +85°C 5-Lead SOT-23 RJ-5 H0A AD8031ART-REEL7 –40°C to +85°C 5-Lead SOT-23, 7" Tape and Reel RJ-5 H0A AD8031ARTZ-R2 –40°C to +85°C 5-Lead SOT-23 RJ-5 H04 AD8031ARTZ-REEL –40°C to +85°C 5-Lead SOT-23, 13" Tape and Reel RJ-5 H04 AD8031ARTZ-REEL7 –40°C to +85°C 5-Lead SOT-23, 7" Tape and Reel RJ-5 H04 AD8031BNZ –40°C to +85°C 8-Lead PDIP N-8 AD8031BR –40°C to +85°C 8-Lead SOIC_N R-8 AD8031BRZ –40°C to +85°C 8-Lead SOIC_N R-8 AD8031BRZ-REEL –40°C to +85°C 8-Lead SOIC_N, 13" Tape and Reel R-8 AD8031BRZ-REEL7 –40°C to +85°C 8-Lead SOIC_N, 7" Tape and Reel R-8 AD8031AR-EBZ 8-Lead SOIC Evaluation Board AD8031ART-EBZ 5-Lead SOT-23 Evaluation Board AD8032ANZ –40°C to +85°C 8-Lead PDIP N-8 AD8032AR –40°C to +85°C 8-Lead SOIC_N R-8 AD8032AR-REEL7 –40°C to +85°C 8-Lead SOIC_N, 7" Tape and Reel R-8 AD8032ARZ –40°C to +85°C 8-Lead SOIC_N R-8 AD8032ARZ-REEL –40°C to +85°C 8-Lead SOIC_N, 13" Tape and Reel R-8 AD8032ARZ-REEL7 –40°C to +85°C 8-Lead SOIC_N, 7" Tape and Reel R-8 AD8032ARM –40°C to +85°C 8-Lead MSOP RM-8 H9A AD8032ARM-REEL –40°C to +85°C 8-Lead MSOP, 13" Tape and Reel RM-8 H9A AD8032ARM-REEL7 –40°C to +85°C 8-Lead MSOP, 7" Tape and Reel RM-8 H9A AD8032ARMZ –40°C to +85°C 8-Lead MSOP RM-8 H9A# AD8032ARMZ-REEL –40°C to +85°C 8-Lead MSOP, 13" Tape and Reel RM-8 H9A# AD8032ARMZ-REEL7 –40°C to +85°C 8-Lead MSOP, 7" Tape and Reel RM-8 H9A# AD8032BNZ –40°C to +85°C 8-Lead PDIP N-8 AD8032BR –40°C to +85°C 8-Lead SOIC_N R-8 AD8032BR-REEL7 –40°C to +85°C 8-Lead SOIC_N, 7" Tape and Reel R-8 AD8032BRZ –40°C to +85°C 8-Lead SOIC_N R-8 AD8032BRZ-REEL –40°C to +85°C 8-Lead SOIC_N, 13" Tape and Reel R-8 AD8032BRZ-REEL7 –40°C to +85°C 8-Lead SOIC_N, 7" Tape and Reel R-8 AD8032ACHIPS Die AD8032AR-EBZ 8-Lead SOIC Evaluation Board AD8032ARM-EBZ 8-Lead MSOP Evaluation Board 1 Z = RoHS Compliant Part, # denotes lead-free product may be top or bottom marked. ©2014 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D01056-0-3/14(G) Rev. G | Page 20 of 20

Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: A nalog Devices Inc.: AD8031ANZ AD8031ARTZ-REEL7 AD8031ARZ AD8031BNZ AD8031BRZ AD8032ANZ AD8032AR AD8032ARMZ AD8032ARMZ-REEL7 AD8032ARZ AD8032BRZ AD8031AR AD8032BR AD8032ARM AD8031BR AD8031ART-REEL7 AD8031ARTZ-REEL AD8031ARZ-REEL AD8031ARZ-REEL7 AD8031BRZ-REEL7 AD8032ARM-REEL7 AD8032ARMZ-REEL AD8032ARZ-REEL AD8032ARZ-REEL7 AD8032BRZ-REEL AD8032BRZ-REEL7 AD8031ARTZ-R2