Low Noise, High Speed Amplifier for 16-Bit Systems AD8021 FEATURES CONNECTION DIAGRAM Low noise AD8021 LOGIC 2.1 nV/√Hz input voltage noise 1 8 DISABLE REFERENCE 2.1 pA/√Hz input current noise –IN 2 7 +VS Custom compensation +IN 3 6 VOUT HigCho nspsteaendt bandwidth from G = −1 to G = −10 –VS 4 5 CCOMP 01888-001 200 MHz (G = −1) Figure 1. SOIC-8 (R-8) and MSOP-8 (RM-8) 190 MHz (G = −10) Low power 34 mW or 6.7 mA typical for 5 V supply The AD8021 allows the user to choose the gain bandwidth Output disable feature, 1.3 mA product that best suits the application. With a single capacitor, Low distortion the user can compensate the AD8021 for the desired gain with −93 dBc second harmonic, f = 1 MHz C little trade-off in bandwidth. The AD8021 is a well-behaved −108 dBc third harmonic, f = 1 MHz C amplifier that settles to 0.01% in 23 ns for a 1 V step. It has a fast DC precision overload recovery of 50 ns. 1 mV maximum input offset voltage 0.5 μV/°C input offset voltage drift The AD8021 is stable over temperature with low input offset Wide supply range, 5 V to 24 V voltage drift and input bias current drift, 0.5 μV/°C and 10 nA/°C, Low price respectively. The AD8021 is also capable of driving a 75 Ω line Small packaging with ±3 V video signals. Available in SOIC-8 and MSOP-8 The AD8021 is both technically superior and priced considerably less than comparable amps drawing much higher quiescent APPLICATIONS current. The AD8021 is a high speed, general-purpose amplifier, ADC preamps and drivers ideal for a wide variety of gain configurations and can be used Instrumentation preamps throughout a signal processing chain and in control loops. The Active filters AD8021 is available in both standard 8-lead SOIC and MSOP Portable instrumentation packages in the industrial temperature range of −40°C to +85°C. Line receivers Precision instruments Ultrasound signal processing 24 High gain circuits VOUT = 50mV p-p 21 18 G =–10, RF = 1kΩ, RG = 100Ω, GENERAL DESCRIPTION B) RIN = 100Ω, CC = 0pF d15 The AD8021 is an exceptionally high performance, high speed AIN (12 G =–5, RF = 1kΩ, RG = 200Ω, voltage feedback amplifier that can be used in 16-bit resolution P G RIN = 66.5Ω, CC = 1.5pF O 9 systems. It is designed to have both low voltage and low current O L noise (2.1 nV/√Hz typical and 2.1 pA/√Hz typical) while operating SED- 6 G =–2, RF = 499Ω, RG = 249Ω, at the lowest quiescent supply current (7 mA @ ±5 V) among LO 3 RIN = 63.4Ω, CC = 4pF C today’s high speed, low noise op amps. The AD8021 operates 0 owveellr aas w friodme r sainnggele o 5f sVu psupplyp vlioelst,a mgeask firnogm it ± id2.e2a5l fVo rt oh i±g1h2 s Vpe, eads , ––63 GRI N= =– 15,6 R.2FΩ =, 4C9C9 =Ω ,7 RpFG = 499Ω, 01888-002 low power instruments. An output disable pin allows further 0.1M 1M 10M 100M 1G reduction of the quiescent supply current to 1.3 mA. FREQUENCY (Hz) Figure 2. Small Signal Frequency Response Rev. F Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Tel: 781.329.4700 www.analog.com Trademarks and registered trademarks are the property of their respective owners. Fax: 781.461.3113 ©2006 Analog Devices, Inc. All rights reserved.

AD8021 TABLE OF CONTENTS Features..............................................................................................1 Applications.....................................................................................19 Applications.......................................................................................1 Using the Disable Feature..........................................................20 General Description.........................................................................1 Theory of Operation......................................................................21 Connection Diagram.......................................................................1 PCB Layout Considerations......................................................21 Revision History...............................................................................2 Driving 16-Bit ADCs.................................................................22 Specifications.....................................................................................3 Differential Driver......................................................................22 Absolute Maximum Ratings............................................................7 Using the AD8021 in Active Filters.........................................23 Maximum Power Dissipation.....................................................7 Driving Capacitive Loads..........................................................23 ESD Caution..................................................................................7 Outline Dimensions.......................................................................25 Pin Configuration and Function Descriptions.............................8 Ordering Guide..........................................................................25 Typical Performance Characteristics.............................................9 Test Circuits.................................................................................17 REVISION HISTORY 5/06—Rev. E to Rev. F 7/03—Rev. B to Rev. C Updated Format..................................................................Universal Deleted All References to Evaluation Board...................Universal Changes to General Description....................................................1 Replaced Figure 2..............................................................................5 Changes to Figure 3..........................................................................7 Updated Outline Dimensions.......................................................20 Changes to Figure 60......................................................................19 2/03—Rev. A to Rev. B Changes to Table 9..........................................................................23 Edits to Evaluation Board Applications.......................................20 3/05—Rev. D to Rev. E Edits to Figure 17 ...........................................................................20 Updated Format..................................................................Universal 6/02—Rev. 0 to Rev. A Change to Figure 19.......................................................................11 Edits to Specifications.......................................................................2 Change to Figure 25.......................................................................12 Change to Table 7 and Table 8......................................................22 Change to Driving 16-Bit ADCs Section....................................22 10/03—Rev. C to Rev. D Updated Format..................................................................Universal Rev. F | Page 2 of 28

AD8021 SPECIFICATIONS V = ±5 V, @ T = 25°C, R = 1 kΩ, gain = +2, unless otherwise noted. S A L Table 1. AD8021AR/AD8021ARM Parameter Conditions Min Typ Max Unit DYNAMIC PERFORMANCE −3 dB Small Signal Bandwidth G = +1, C = 10 pF, V = 0.05 V p-p 355 490 MHz C O G = +2, C = 7 pF, V = 0.05 V p-p 160 205 MHz C O G = +5, C = 2 pF, V = 0.05 V p-p 150 185 MHz C O G = +10, C = 0 pF, V = 0.05 V p-p 110 150 MHz C O Slew Rate, 1 V Step G = +1, C = 10 pF 95 120 V/μs C G = +2, C = 7 pF 120 150 V/μs C G = +5, C = 2 pF 250 300 V/μs C G = +10, C = 0 pF 380 420 V/μs C Settling Time to 0.01% V = 1 V step, R = 500 Ω 23 ns O L Overload Recovery (50%) ±2.5 V input step, G = +2 50 ns DISTORTION/NOISE PERFORMANCE f = 1 MHz HD2 V = 2 V p-p −93 dBc O HD3 V = 2 V p-p −108 dBc O f = 5 MHz HD2 V = 2 V p-p −70 dBc O HD3 V = 2 V p-p −80 dBc O Input Voltage Noise f = 50 kHz 2.1 2.6 nV/√Hz Input Current Noise f = 50 kHz 2.1 pA/√Hz Differential Gain Error NTSC, R = 150 Ω 0.03 % L Differential Phase Error NTSC, R = 150 Ω 0.04 Degrees L DC PERFORMANCE Input Offset Voltage 0.4 1.0 mV Input Offset Voltage Drift T to T 0.5 μV/°C MIN MAX Input Bias Current +Input or −input 7.5 10.5 μA Input Bias Current Drift 10 nA/°C Input Offset Current 0.1 0.5 ±μA Open-Loop Gain 82 86 dB INPUT CHARACTERISTICS Input Resistance 10 MΩ Common-Mode Input Capacitance 1 pF Input Common-Mode Voltage Range −4.1 to +4.6 V Common-Mode Rejection Ratio V = ±4 V −86 −98 dB CM OUTPUT CHARACTERISTICS Output Voltage Swing −3.5 to +3.2 −3.8 to +3.4 V Linear Output Current 60 mA Short-Circuit Current 75 mA Capacitive Load Drive for 30% Overshoot V = 50 mV p-p/1 V p-p 15/120 pF O DISABLE CHARACTERISTICS Off Isolation f = 10 MHz −40 dB Turn-On Time V = 0 V to 2 V, 50% logic to 50% output 45 ns O Turn-Off Time V = 0 V to 2 V, 50% logic to 50% output 50 ns O DISABLE Voltage—Off/On V − V 1.75/1.90 V DISABLE LOGIC REFERENCE Enabled Leakage Current LOGIC REFERENCE = 0.4 V 70 μA DISABLE = 4.0 V 2 μA Rev. F | Page 3 of 28

AD8021 AD8021AR/AD8021ARM Parameter Conditions Min Typ Max Unit Disabled Leakage Current LOGIC REFERENCE = 0.4 V 30 μA DISABLE = 0.4 V 33 μA POWER SUPPLY Operating Range ±2.25 ±5 ±12.0 V Quiescent Current Output enabled 7.0 7.7 mA Output disabled 1.3 1.6 mA +Power Supply Rejection Ratio V = 4 V to 6 V, V = −5 V −86 −95 dB CC EE −Power Supply Rejection Ratio V = 5 V, V = −6 V to −4 V −86 −95 dB CC EE V = ±12 V, @ T = 25°C, R = 1 kΩ, gain = +2, unless otherwise noted. S A L Table 2. AD8021AR/AD8021ARM Parameter Conditions Min Typ Max Unit DYNAMIC PERFORMANCE −3 dB Small Signal Bandwidth G = +1, C = 10 pF, V = 0.05 V p-p 520 560 MHz C O G = +2, C = 7 pF, V = 0.05 V p-p 175 220 MHz C O G = +5, C = 2 pF, V = 0.05 V p-p 170 200 MHz C O G = +10, C = 0 pF, V = 0.05 V p-p 125 165 MHz C O Slew Rate, 1 V Step G = +1, C = 10 pF 105 130 V/μs C G = +2, C = 7 pF 140 170 V/μs C G = +5, C = 2 pF 265 340 V/μs C G = +10, C = 0 pF 400 460 V/μs C Settling Time to 0.01% V = 1 V step, R = 500 Ω 21 ns O L Overload Recovery (50%) ±6 V input step, G = +2 90 ns DISTORTION/NOISE PERFORMANCE f = 1 MHz HD2 V = 2 V p-p −95 dBc O HD3 V = 2 V p-p −116 dBc O f = 5 MHz HD2 V = 2 V p-p −71 dBc O HD3 V = 2 V p-p −83 dBc O Input Voltage Noise f = 50 kHz 2.1 2.6 nV/√Hz Input Current Noise f = 50 kHz 2.1 pA/√Hz Differential Gain Error NTSC, R = 150 Ω 0.03 % L Differential Phase Error NTSC, R = 150 Ω 0.04 Degrees L DC PERFORMANCE Input Offset Voltage 0.4 1.0 mV Input Offset Voltage Drift T to T 0.2 μV/°C MIN MAX Input Bias Current +Input or −input 8 11.3 μA Input Bias Current Drift 10 nA/°C Input Offset Current 0.1 0.5 ±μA Open-Loop Gain 84 88 dB INPUT CHARACTERISTICS Input Resistance 10 MΩ Common-Mode Input Capacitance 1 pF Input Common-Mode Voltage Range −11.1 to +11.6 V Common-Mode Rejection Ratio V = ±10 V −86 −96 dB CM Rev. F | Page 4 of 28

AD8021 AD8021AR/AD8021ARM Parameter Conditions Min Typ Max Unit OUTPUT CHARACTERISTICS Output Voltage Swing −10.2 to +9.8 −10.6 to +10.2 V Linear Output Current 70 mA Short-Circuit Current 115 mA Capacitive Load Drive for 30% Overshoot V = 50 mV p-p/1 V p-p 15/120 pF O DISABLE CHARACTERISTICS Off Isolation f = 10 MHz −40 dB Turn-On Time V = 0 V to 2 V, 50% logic to 50% output 45 ns O Turn-Off Time V = 0 V to 2 V, 50% logic to 50% output 50 ns O DISABLE Voltage—Off/On V − V 1.80/1.95 V DISABLE LOGIC REFERENCE Enabled Leakage Current LOGIC REFERENCE = 0.4 V 70 μA DISABLE = 4.0 V 2 μA Disabled Leakage Current LOGIC REFERENCE = 0.4 V 30 μA DISABLE = 0.4 V 33 μA POWER SUPPLY Operating Range ±2.25 ±5 ±12.0 V Quiescent Current Output enabled 7.8 8.6 mA Output disabled 1.7 2.0 mA +Power Supply Rejection Ratio V = 11 V to 13 V, V = −12 V −86 −96 dB CC EE −Power Supply Rejection Ratio V = 12 V, V = −13 V to −11 V −86 −100 dB CC EE V = 5 V, @ T = 25°C, R = 1 kΩ, gain = +2, unless otherwise noted. S A L Table 3. AD8021AR/AD8021ARM Parameter Conditions Min Typ Max Unit DYNAMIC PERFORMANCE −3 dB Small Signal Bandwidth G = +1, C = 10 pF, V = 0.05 V p-p 270 305 MHz C O G = +2, C = 7 pF, V = 0.05 V p-p 155 190 MHz C O G = +5, C = 2 pF, V = 0.05 V p-p 135 165 MHz C O G = +10, C = 0 pF, V = 0.05 V p-p 95 130 MHz C O Slew Rate, 1 V Step G = +1, C = 10 pF 80 110 V/μs C G = +2, C = 7 pF 110 140 V/μs C G = +5, C = 2 pF 210 280 V/μs C G = +10, C = 0 pF 290 390 V/μs C Settling Time to 0.01% V = 1 V step, R = 500 Ω 28 ns O L Overload Recovery (50%) 0 V to 2.5 V input step, G = +2 40 ns DISTORTION/NOISE PERFORMANCE f = 1 MHz HD2 V = 2 V p-p −84 dBc O HD3 V = 2 V p-p −91 dBc O f = 5 MHz HD2 V = 2 V p-p −68 dBc O HD3 V = 2 V p-p −81 dBc O Input Voltage Noise f = 50 kHz 2.1 2.6 nV/√Hz Input Current Noise f = 50 kHz 2.1 pA/√Hz Rev. F | Page 5 of 28

AD8021 AD8021AR/AD8021ARM Parameter Conditions Min Typ Max Unit DC PERFORMANCE Input Offset Voltage 0.4 1.0 mV Input Offset Voltage Drift T to T 0.8 μV/°C MIN MAX Input Bias Current +Input or −input 7.5 10.3 μA Input Bias Current Drift 10 nA/°C Input Offset Current 0.1 0.5 ±μA Open-Loop Gain 72 76 dB INPUT CHARACTERISTICS Input Resistance 10 MΩ Common-Mode Input Capacitance 1 pF Input Common-Mode Voltage Range 0.9 to 4.6 V Common-Mode Rejection Ratio 1.5 V to 3.5 V −84 −98 dB OUTPUT CHARACTERISTICS Output Voltage Swing 1.25 to 3.38 1.10 to 3.60 V Linear Output Current 30 mA Short-Circuit Current 50 mA Capacitive Load Drive for 30% Overshoot V = 50 mV p-p/1 V p-p 10/120 pF O DISABLE CHARACTERISTICS Off Isolation f = 10 MHz −40 dB Turn-On Time V = 0 V to 1 V, 50% logic to 50% output 45 ns O Turn-Off Time V = 0 V to 1 V, 50% logic to 50% output 50 ns O DISABLE Voltage—Off/On V − V 1.55/1.70 V DISABLE LOGIC REFERENCE Enabled Leakage Current LOGIC REFERENCE = 0.4 V 70 μA DISABLE = 4.0 V 2 μA Disabled Leakage Current LOGIC REFERENCE = 0.4 V 30 μA DISABLE = 0.4 V 33 μA POWER SUPPLY Operating Range ±2.25 ±5 ±12.0 V Quiescent Current Output enabled 6.7 7.5 mA Output disabled 1.2 1.5 mA +Power Supply Rejection Ratio V = 4.5 V to 5.5 V, V = 0 V −74 −82 dB CC EE −Power Supply Rejection Ratio V = 5 V, V = −0.5 V to +0.5 V −76 −84 dB CC EE Rev. F | Page 6 of 28

AD8021 ABSOLUTE MAXIMUM RATINGS Table 4. MAXIMUM POWER DISSIPATION Parameter Rating The maximum power that can be safely dissipated by the Supply Voltage 26.4 V AD8021 is limited by the associated rise in junction tempera- Power Dissipation Observed power ture. The maximum safe junction temperature for plastic derating curves encapsulated devices is determined by the glass transition Input Voltage (Common Mode) ±V ± 1 V S temperature of the plastic, approximately 150°C. Temporarily Differential Input Voltage1 ±0.8 V exceeding this limit can cause a shift in parametric performance Differential Input Current ±10 mA due to a change in the stresses exerted on the die by the package. Output Short-Circuit Duration Observed power derating curves Exceeding a junction temperature of 175°C for an extended Storage Temperature Range −65°C to +125°C period can result in device failure. Operating Temperature Range −40°C to +85°C While the AD8021 is internally short-circuit protected, this can Lead Temperature (Soldering, 10 sec) 300°C not be sufficient to guarantee that the maximum junction tem- perature (150°C) is not exceeded under all conditions. To ensure 1 The AD8021 inputs are protected by diodes. Current-limiting resistors are not used to preserve the low noise. If a differential input exceeds ±0.8 V, the proper operation, it is necessary to observe the maximum input current should be limited to ±10 mA. power derating curves. Stresses above those listed under Absolute Maximum Ratings 2.0 may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any W) other conditions above those indicated in the operational ON ( 1.5 section of this specification is not implied. Exposure to absolute ATI 8-LEAD SOIC P maximum rating conditions for extended periods may affect SSI DI device reliability. R 1.0 E W O P 8-LEAD MSOP M U M 0.5 XI A M 0.01 01888-004 –55 –45 –35 –25 –15 –5 5 15 25 35 45 55 65 75 85 AMBIENT TEMPERATURE (°C) Figure 3. Maximum Power Dissipation vs. Temperature1 1 Specification is for device in free air: 8-lead SOIC: θJA = 125°C/W; 8-lead MSOP: θJA = 145°C/W. ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. Rev. F | Page 7 of 28

AD8021 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS AD8021 LOGIC 1 8 DISABLE REFERENCE –IN 2 7 +VS +IN 3 6 VOUT –VS 4 5 CCOMP 01888-003 Figure 4. Pin Configuration Table 5. Pin Function Descriptions Pin No. Mnemonic Description 1 LOGIC REFERENCE Reference for Pin 81 Voltage Level. Connect to logic low supply. 2 −IN Inverting Input. 3 +IN Noninverting Input. 4 −V Negative Supply Voltage. S 5 C Compensation Capacitor. Tie to −V. (See the Applications section for value.) COMP S 6 V Output. OUT 7 +V Positive Supply Voltage. S 8 DISABLE Disable, Active Low. 1 When Pin 8 (DISABLE) is higher than Pin 1 (LOGIC REFERENCE) by approximately 2 V or more, the part is enabled. When Pin 8 is brought down to within about 1.5 V of Pin 1, the part is disabled. (See the Specifications tables for exact disable and enable voltage levels.) If the disable feature is not going to be used, Pin 8 can be tied to +VS or a logic high source, and Pin 1 can be tied to ground or logic low. Alternatively, if Pin 1 and Pin 8 are not connected, the part is in an enabled state. Rev. F | Page 8 of 28

AD8021 TYPICAL PERFORMANCE CHARACTERISTICS T = 25°C, V = ±5 V, R = 1 kΩ, G = +2, R = R = 499 Ω, R = 49.9 Ω, R = 976 Ω, R = 53.6 Ω, C = 7 pF, C = 0, C = 0, V = 2 V p-p, A S L F G S O D C L F OUT frequency = 1 MHz, unless otherwise noted. 24 9 G = +2 21 G = +10, RF = 1kΩ, RG = 110Ω, CC = 0pF 8 VS = ±2.5V VS = ±5V 18 7 B) N (d 15 G = +5, RF = 1kΩ, RG = 249Ω, CC = 2pF 6 GAI 12 B) 5 P d ED-LOO 96 G = +2, RF = RG = 499Ω, CC = 7pF GAIN ( 43 VS = ±12V S LO 3 2 C 0 G = +1, RF = 75Ω, CC = 10pF 1 VS = ±2.5V ––63 01888-005 –10 01888-008 0.1M 1M 10M 100M 1G 1M 10M 100M 1G FREQUENCY (Hz) FREQUENCY (Hz) Figure 5. Small Signal Frequency Response vs. Frequency and Gain, Figure 8. Small Signal Frequency Response vs. Frequency and Supply, VOUT = 50 mV p-p, Noninverting (See Figure 48) VOUT = 50 mV p-p, Noninverting (See Figure 48) 24 3 G = –1 21 2 VS = ±2.5V 18 G =–10, RF = 1kΩ, RG = 100Ω, 1 VS = ±5V RIN = 100Ω, CC = 0pF 15 0 GAIN (dB) 1962 GRI N= =– 56,6 R.5FΩ =, 1CkCΩ =, R1.G5 p=F 200Ω, GAIN (dB) –––123 VS = ±12V G =–2, RF = 499Ω, RG = 249Ω, 3 RIN = 63.4Ω, CC = 4pF –4 0 –5 ––63 GRI N= =– 15,6 R.2FΩ =, 4C9C9 =Ω ,7 RpFG = 499Ω, 01888-006 ––76 VS = ±2.5V 01888-009 0.1M 1M 10M 100M 1G 1M 10M 100M 1G FREQUENCY (Hz) FREQUENCY (Hz) Figure 6. Small Signal Frequency Response vs. Frequency and Figure 9. Small Signal Frequency Response vs. Frequency and Supply, Gain, VOUT = 50 mV p-p Inverting (See Figure 48) VOUT = 50 mV p-p, Inverting (See Figure 50) 9 9 G = +2 CC = 5pF G = +2 8 8 7 CC = 7pF 7 VOUT = 0.1V AND 50mV p-p 6 6 dB) 5 CC = 9pF N (dB) 5 N ( 4 AI 4 AI G VOUT = 4V p-p G 3 3 2 2 VOUT = 1V p-p 1 CC = 7pF 1 –10 CC = 9pF 01888-007 –10 01888-010 0.1M 1M 10M 100M 1G 1M 10M 100M 1G FREQUENCY (Hz) FREQUENCY (Hz) Figure 7. Small Signal Frequency Response vs. Frequency and Figure 10. Frequency Response vs. Frequency and VOUT, Noninverting Compensation Capacitor, VOUT = 50 mV p-p (See Figure 48) (See Figure 48) Rev. F | Page 9 of 28

AD8021 10 10 G = +2 G = +2 RF = 1kΩ 9 9 RF = RG RF = 499Ω 8 8 7 7 N (dB) 65 AIN (dB) 65 RRF F= = 2 5105Ω0Ω AI G G 4 RL = 1kΩ 4 3 3 RL = 100Ω 2 2 RF = 75Ω 10 01888-011 10 RF = 1kΩAND CF = 2.2pF 01888-014 0.1M 1M 10M 100M 1G 0.1M 1M 10M 100M 1G FREQUENCY (Hz) FREQUENCY (Hz) Figure 11. Large Signal Frequency Response vs. Frequency and Figure 14. Small Signal Frequency Response vs. Frequency and RF, Load, Noninverting (See Figure 49) Noninverting, VOUT = 50 mV p-p (See Figure 48) 9 15 G = +2 +85°C G = +2 8 12 +25°C 7 9 6 6 dB) 5 –40°C 5V0OmUTV =p-p dB) 3 RS = 49.9Ω N ( 4 +85°C N ( 0 AI AI G 3 VOUT = G–3 2V p-p 2 –6 RS = 100Ω 1 +25°C –9 –10 –40°C 01888-012 ––1125 RS = 249Ω 01888-015 1M 10M 100M 1G 0.1M 1M 10M 100M 1G FREQUENCY (Hz) FREQUENCY (Hz) Figure 12. Frequency Response vs. Frequency, Temperature, and Figure 15. Small Signal Frequency Response vs. Frequency and RS, VOUT, Noninverting (See Figure 48) Noninverting, VOUT = 50 mV p-p (See Figure 48) 18 100 G = +2 50pF 15 30pF 90 12 80 20pF 9 B) 70 180 GAIN (dB) –3630 100ppFF OPEN-LOOP GAIN (d 65430000 94100535 PHASE (Degrees) –6 20 –45 –1–291M 10M 100M 1G01888-013 100 ––1930501888-016 10k 100k 1M 10M 100M 1G FREQUENCY (Hz) FREQUENCY (Hz) Figure 13. Small Signal Frequency Response vs. Figure 16. Open-Loop Gain and Phase vs. Frequency, RG = 100 Ω, Frequency and Capacitive Load, Noninverting, VOUT = 50 mV p-p RF = 1 kΩ, RO = 976 Ω, RD = 53.6 Ω, CC = 0 pF (See Figure 50) (See Figure 49 and Figure 71) Rev. F | Page 10 of 28

AD8021 6.4 –20 G = +2 –30 6.2 VS = ±2.5V –40 f f 1 2 –50 Δf = 0.2MHz POUT B)6.0 m) –60 976Ω d B GAIN (5.8 VS = ±5V VS = ±12V P (dOUT ––7800 53.6Ω 50Ω –90 5.6 –100 5.4 01888-017 ––111200 01888-020 1M 10M 100M 9.5 9.7 10.0 10.3 10.5 FREQUENCY (Hz) FREQUENCY (MHz) Figure 17. 0.1 dB Flatness vs. Frequency and Supply, VOUT = 1 V p-p, Figure 20. Intermodulation Distortion vs. Frequency RL = 150 Ω, Noninverting (See Figure 49) –20 50 –30 –40 m) 45 B Bc) ––6500 SECOND EPT (d 40 d C N ( –70 ER VS =±5V DISTORTIO ––9800 RL = 100Ω RL = 1kΩ ORDER INT 3305 VS =±2.5V –100 D- R –110 THI 25 ––113200 THIRD 01888-018 20 01888-021 0.1M 1M 10M 20M 0 5 10 15 20 FREQUENCY (Hz) FREQUENCY (MHz) Figure 18. Second and Third Harmonic Distortion vs. Frequency and RL Figure 21. Third-Order Intercept vs. Frequency and Supply Voltage –30 –50 –40 –60 –50 –60 –70 DISTORTION (dBc)–1–––09780000 SVESC =O±N2D.5TVHIRD SECOND DISTORTION (dBc)–1––980000 SECOND STEHCIRROLDN =D 100Ω VS =±5V RL = 1kΩ –110 ––113200 THIRD SECOND VS =±12V 01888-019 ––112100 THIRD 01888-022 100k 1M 10M 20M 1 2 3 4 5 6 FREQUENCY (Hz) VOUT (V p-p) Figure 19. Second and Third Harmonic Distortion vs. Frequency and VS Figure 22. Second and Third Harmonic Distortion vs. VOUT and RL Rev. F | Page 11 of 28

AD8021 –50 3.5 –3.1 –60 3.4 –3.2 –70 SECOND GE (V)3.3 POSITIVE OUTPUT –3.3GE (V) TORTION (dBc) ––9800 THIRDfCS =E C5MOHNzD OUTPUT VOLTA33..21 ––33..45OUTPUT VOLTA DIS–100 fC = 1MHz POSITIVE 3.0 –3.6NEGATIVE –110 2.9 –3.7 –120 THIRD 01888-023 2.8 NEGATIVE OUTPUT –3.8 01888-026 1 2 3 4 5 6 0 400 800 1200 1600 2000 VOUT (V p-p) LOAD (Ω) Figure 23. Second and Third Harmonic Distortion vs. VOUT and Figure 26. DC Output Voltages vs. Load (See Figure 48) Fundamental Frequency (fC), G = +2 –40 120 –50 fC = 5MHz A)100 VS = ±12V m Bc) –60 SECOND ENT ( 80 VS = ±5.0V d R N ( –70 UR O C TI THIRD T 60 DISTOR ––8900 SECOND fC = 1MHz RT-CIRCUI 40 VS = ±2.5V O H –100 THIRD S 20 –110 01888-024 0 01888-027 1 2 3 4 5 6 –50 –30 –10 10 30 50 70 90 110 VOUT (V p-p) TEMPERATURE (°C) Figure 24. Second and Third Harmonic Distortion vs. VOUT and Figure 27. Short-Circuit Current to Ground vs. Temperature Fundamental Frequency (fC), G = +10 –70 50 fC = 1MHz G = 2 RL = 1kΩ 40 –80 RF = RG 30 RL = 1kΩ, 150Ω G = +2 20 c) B TORTION (d–1–0900 SECOND V (mV)OUT–1100 S DI –20 THIRD –110 –30 –120 01888-025 ––4500 01888-028 0 200 400 600 800 1000 0 40 80 120 160 200 FEEDBACK RESISTANCE (Ω) TIME (ns) Figure 25. Second and Third Harmonic Distortion vs. Feedback Resistor (RF) Figure 28. Small Signal Transient Response vs. RL, VO = 50 mV p-p, Noninverting (See Figure 49) Rev. F | Page 12 of 28

AD8021 2.0 GVO = = 2 4V p-p 2.0 VGO = = 2 2V p-p RL = 1kΩ 1.0 1.0 V) V) V (OUT RL = 150Ω V (OUT VS =±2.5V –1.0 –1.0 VS =±5V –2.0 01888-029 –2.0 01888-032 0 40 80 120 160 200 0 40 80 120 160 200 TIME (ns) TIME (ns) Figure 29. Large Signal Transient Response vs. RL, Noninverting Figure 32. Large Signal Transient Response vs. VS (See Figure 48) (See Figure 49) 5 VO = 4V p-p VGI N= =+2±3V 4 G =–1 VIN = 1V/DIV VOUT, RL = 1kΩ 3 VOUT = 2V/DIV VIN 2 1 RL = 150Ω S T OL –1 V VOUT –2 –3 ––45 01888-030 0 VIN100 200 300 400 50001888-033 0 50 100 150 200 250 TIME (ns) TIME (ns) Figure 30. Large Signal Transient Response, Inverting (See Figure 50) Figure 33. Overdrive Recovery vs. RL (See Figure 49) CL = 50pF VO = 4V p-p G = 2 2.0 G = 2 1.0 CL = 10pF, 0pF G N V) TTLI+0.01% V (OUT UT SE TP–0.01% U 25ns O –1.0 –2.0 01888-031 VERT = 0.2mV/DIV HOR = 5ns/DIV 01888-034 0 40 80 120 160 200 TIME (ns) Figure 31. Large Signal Transient Response vs. CL (See Figure 48) Figure 34. 0.01% Settling Time, 2 V Step Rev. F | Page 13 of 28

AD8021 100 100 80 60 Hz) √ 40 A/ p G (µV) 20 PULSE WIDTH = 120ns NOISE ( LIN 0 NT 10 T E SET –20 PULSE WIDTH = 300µs URR –40 T C U –60 5V NP I –1–08000 0V 4 t18 12 16 20 24 28 3201888-035 110 100 1k 10k 100k 1M 10M01888-038 TIME (µs) FREQUENCY (Hz) Figure 35. Long-Term Settling, 0 V to 5 V, VS = ±12 V, G = +13 Figure 38. Input Current Noise vs. Frequency 50 0.48 G = +1 40 0.44 30 20 mV) 0.40 T ( V) 10 SE m F (T OF 0.36 VOU–10 AGE LT 0.32 –20 O V –30 0.28 ––4500 01888-036 0.24 01888-039 0 40 80 120 160 200 –50 –25 0 25 50 75 100 TIME (ns) TEMPERATURE (°C) Figure 36. Small Signal Transient Response, VO = 50 mV p-p, G = +1 Figure 39. VOS vs. Temperature (See Figure 48) 100 8.4 8.0 Hz) A)μ SE (nV/√ RRENT ( 7.6 TAGE NOI 10 T BIAS CU 76..28 L U O P V 2.1nV/√Hz N I 6.4 1 01888-037 6.0 01888-040 10 100 1k 10k 100k 1M 10M –50 –25 0 25 50 75 100 FREQUENCY (Hz) TEMPERATURE (°C) Figure 37. Input Voltage Noise vs. Frequency Figure 40. Input Bias Current vs. Temperature Rev. F | Page 14 of 28

AD8021 –20 0 –30 –10 –40 –20 B) –50 N (d–30 O MRR (dB)––6700 D ISOLATI––4500 C–80 E–60 L B –90 SA–70 DI –100 –80 ––111200 01888-041 –1–9000 01888-044 10k 100k 1M 10M 100M 0.1M 1M 10M 100M 1G FREQUENCY (Hz) FREQUENCY (Hz) Figure 41. CMRR vs. Frequency (See Figure 51) Figure 44. Input-to-Output Isolation, Chip Disabled (See Figure 54) 300 300k 100 100k 30 30k E ()Ω 10 E ()Ω 10k C C AN 3 AN 3k D D PE 1 PE 1k M M UT I 0.3 UT I 300 P P UT 0.1 UT 100 O O 0.03 30 0.00.0031 01888-042 130 01888-045 10k 100k 1M 10M 100M 1G 10k 100k 1M 10M 100M 1G FREQUENCY (Hz) FREQUENCY (Hz) Figure 42. Output Impedance vs. Frequency, Chip Enabled Figure 45. Output Impedance vs. Frequency, Chip Disabled (See Figure 52) (See Figure 55) 0 DISABLE 4V –10 2V –20 –PSRR –30 2V VOUTPUT R (dB)––5400 VS =±2.5V +PSRR R tEN = 45ns PS–60 VS =±12V 1V –70 tDIS = 50ns –80 VS =±5V 0 100 200 300 400 50001888-043 –1–900010k 100k 1M 10M 100M 500M01888-046 TIME (ns) FREQUENCY (Hz) Figure 43. Enable (tEN)/Disable (tDIS) Time vs. VOUT (See Figure 53) Figure 46. PSRR vs. Frequency and Supply Voltage (See Figure 56 and Figure 57) Rev. F | Page 15 of 28

AD8021 8.5 8.0 A) m7.5 T ( N E R R7.0 U C Y L PP6.5 U S 6.0 5.5–50 –25 0 25 50 75 10001888-047 TEMPERATURE (°C) Figure 47. Quiescent Supply Current vs. Temperature Rev. F | Page 16 of 28

AD8021 TEST CIRCUITS 50Ω 50Ω CABLE RS +VS RO 50Ω CABLE AD+8V0S21 ANHNEPAT8WL7Y5OZ3REDKR 5 49.R9IΩN –VS CC RD 100Ω CC 5 50Ω RG CRFF 01888-048 49R9ΩG –VS479Rp9FFΩ 01888-052 Figure 48. Noninverting Gain Figure 52. Output Impedance, Chip Enabled FET AD8021 PROBE +VS +VS 50Ω CABLE RS 49.9Ω 50Ω 1 5 1.0V 49.9Ω LOGIC REF 976Ω 49.R9IΩN CL RL 8 DISABLE 5 53.6Ω –VS CC 4V 49.9Ω CC RG RF –VS 7pF CF 01888-049 499Ω 499Ω 01888-053 Figure 49. Noninverting Gain and FET Probe Figure 53. Enable/Disable +VS HP8753D RO 50Ω CABLE NETWORK 49.9Ω 5 ANALYZER RD 50Ω 50Ω 50Ω CABLE –VS CC 50Ω CABLE 50Ω 49.R9IΩN RG RF 01888-050 49.499Ω.9Ω 1 LOG+ICV SREFAD8021 FPERTOBE Figure 50. Inverting Gain 8 DISABLE 5 1kΩ HP8753D –VS 7CpCF ANNEATWLYOZREKR 499Ω 499Ω 01888-054 Figure 54. Input-to-Output Isolation, Chip Disabled 50Ω 50Ω AD8021 49.9Ω 499Ω +VS AD8021 HP8753D 1 8 +VS NETWORK 499Ω 5 ANALYZER CC 100Ω 5 50Ω 7pF –VS CC 55.6Ω 499Ω 499Ω 01888-051 Figure– V5S5.7 OpFutput Impedance, Chip Disabled 01888-055 Figure 51. CMRR Rev. F | Page 17 of 28

AD8021 BIAS BIAS HP8753D BNC HP8753D BNC NETWORK NETWORK ANALYZER ANALYZER 50Ω 50Ω +VS 50Ω –VS
50Ω 50ΩCABLE 50ΩCABLE +VS 49.9Ω, 5W 976Ω +VS 249Ω 5 976Ω 53.6Ω 249Ω 5 53.6Ω –VS 7CpCF CC 49.9Ω –VS 7pF 5W 499Ω 499Ω 01888-056 499Ω 499Ω 01888-057 Figure 56. Positive PSRR Figure 57. Negative PSRR Rev. F | Page 18 of 28

AD8021 APPLICATIONS degraded to about 20 MHz and the phase margin increases to The typical voltage feedback op amp is frequency stabilized 90° (Arrow B). However, by reducing C to 0 pF, the bandwidth with a fixed internal capacitor, C , using dominant pole C INTERNAL and phase margin return to about 200 MHz and 60° (Arrow C), compensation. To a first-order approximation, voltage feedback respectively. In addition, the slew rate is dramatically increased, op amps have a fixed gain bandwidth product. For example, if as it roughly varies with the inverse of C . its −3 dB bandwidth is 200 MHz for a gain of G = +1; at a gain C of G = +10, its bandwidth is only about 20 MHz. The AD8021 is 10 a voltage feedback op amp with a minimal C of about INTERNAL 9 1.5 pF. By adding an external compensation capacitor, C , the F) C p user can circumvent the fixed gain bandwidth limitation of E ( 8 C other voltage feedback op amps. AN 7 T ACI 6 Unlike the typical op amp with fixed compensation, the AP C 5 AD8021 allows the user to: N O TI 4 A • Maximize the amplifier bandwidth for closed-loop gains NS 3 E between 1 and 10, avoiding the usual loss of bandwidth MP 2 O and slew rate. C • Optimize the trade-off between bandwidth and phase 10 01888-059 1 2 3 4 5 6 7 8 9 10 11 margin for a particular application. NOISE GAIN (V/V) Figure 59. Suggested Compensation Capacitance vs. Gain for • Match bandwidth in gain blocks with different noise gains, Maintaining 1 dB Peaking such as when designing differential amplifiers (as shown in Table 6 and Figure 59 provide recommended values of com- Figure 65). pensation capacitance at various gains and the corresponding 110 180 slew rate, bandwidth, and noise. Note that the value of the 100 135 compensation capacitor depends on the circuit noise gain, not 90 90 the voltage gain. As shown in Figure 60, the noise gain, G , of 86 N B) 80 CC = 0pF (B) ((CA)) 45 an op amp gain block is equal to its noninverting voltage gain, N (d 70 CC = 10pF 0 es) regardless of whether it is actually used for inverting or nonin- P GAI 6500 Degre verting gain. Thus, PEN-LOO 4300 (C) PHASE ( NInovneirntivnegr tGinNg = G RNF =/R RG F+/R 1G + 1 O 20 RG RF 10 (B) RS 3 249Ω 1kΩ –100 (A) 01888-058 1 +AD8021 6 2 – 1k 10k 100k 1M 10M 100M 1G 10G 6 FREQUENCY (Hz) 2 5 AD8021 – Figure 58. Simplified Diagram of Open-Loop Gain and Phase Response –VS RF 3 5 1kΩ + G = –4 Figure 58 is the AD8021 gain and phase plot that has been CCOMP –VS GN = +5 sshimowplsi faie bda fnodrw inidsttrhu ocft iaobnoaul tp 2u0r0p oMseHs.z A arnrdo wa pAh ainse F migaurrgei n58 a t NOGNI N= VGENR =T I+N5G R24G9Ω INCVCEORMTPING 01888-060 about 60° when the desired closed-loop gain is G = +1 and Figure 60. The Noise Gain of Both is 5 the value chosen for the external compensation capacitor is C = 10 pF. If the gain is changed to G = +10 and C is fixed at C C 10 pF, then (as expected for a typical op amp) the bandwidth is Rev. F | Page 19 of 28

AD8021 C = C = 0, R = 1 kΩ, R = 49.9 Ω (see Figure 49). F L L IN Table 6. Recommended Component Values Noise Gain −3 dB Output Noise Output Noise (Noninverting SS BW (AD8021 Only) (AD8021 with Resistors) Gain) R (Ω) R (Ω) R (Ω) C (pF) Slew Rate (V/μs) (MHz) (nV/√Hz) (nV/√Hz) S F G COMP 1 75 75 NA 10 120 490 2.1 2.8 2 49.9 499 499 7 150 205 4.3 8.2 5 49.9 1 k 249 2 300 185 10.7 15.5 10 49.9 1 k 110 0 420 150 21.2 27.9 20 49.9 1 k 52.3 0 200 42 42.2 52.7 100 49.9 1 k 10 0 34 6 211.1 264.1 With the AD8021, a variety of trade-offs can be made to fine- Additionally, any resistance in series with the source creates a tune its dynamic performance. Sometimes more bandwidth pole with the input capacitance (as well as dampen high or slew rate is needed at a particular gain. Reducing the frequency resonance due to package and board inductance compensation capacitance, as illustrated in Figure 7, increases and capacitance), the effect of which is shown in Figure 15. the bandwidth and peaking due to a decrease in phase margin. It must also be noted that increasing resistor values increases On the other hand, if more stability is needed, increasing the the overall noise of the amplifier and that reducing the feedback compensation capacitor decreases the bandwidth while resistor value increases the load on the output stage, thus increasing the phase margin. increasing distortion (see Figure 22). As with all high speed amplifiers, parasitic capacitance and USING THE DISABLE FEATURE inductance around the amplifier can affect its dynamic response. Often, the input capacitance (due to the op amp itself, When Pin 8 (DISABLE) is higher than Pin 1 (LOGIC as well as the PC board) has a significant effect. The feedback REFERENCE) by approximately 2 V or more, the part is resistance, together with the input capacitance, can contribute enabled. When Pin 8 is brought down to within about 1.5 V to a loss of phase margin, thereby affecting the high frequency of Pin 1, the part is disabled. See Table 1 for exact disable and response, as shown in Figure 14. A capacitor (C) in parallel enable voltage levels. If the disable feature is not used, Pin 8 can F with the feedback resistor can compensate for this phase loss. be tied to V or a logic high source, and Pin 1 can be tied to S ground or logic low. Alternatively, if Pin 1 and Pin 8 are not connected, the part is in an enabled state. Rev. F | Page 20 of 28

AD8021 THEORY OF OPERATION The AD8021 is fabricated on the second generation of Analog PCB LAYOUT CONSIDERATIONS Devices proprietary High Voltage eXtra-Fast Complementary As with all high speed op amps, achieving optimum performance Bipolar (XFCB) process, which enables the construction of PNP from the AD8021 requires careful attention to PC board layout. and NPN transistors with similar f s in the 3 GHz region. The T Particular care must be exercised to minimize lead lengths transistors are dielectrically isolated from the substrate (and between the ground leads of the bypass capacitors and between each other), eliminating the parasitic and latch-up problems the compensation capacitor and the negative supply. Otherwise, caused by junction isolation. It also reduces nonlinear capaci- lead inductance can influence the frequency response and even tance (a source of distortion) and allows a higher transistor, f , T cause high frequency oscillations. Use of a multilayer printed for a given quiescent current. The supply current is trimmed, circuit board, with an internal ground plane, reduces ground which results in less part-to-part variation of bandwidth, slew noise and enables a compact component arrangement. rate, distortion, and settling time. Due to the relatively high impedance of Pin 5 and low values of As shown in Figure 61, the AD8021 input stage consists of an the compensation capacitor, a guard ring is recommended. The NPN differential pair in which each transistor operates at a guard ring is simply a PC trace that encircles Pin 5 and is 0.8 mA collector current. This allows the input devices a high connected to the output, Pin 6, which is at the same potential as transconductance; thus, the AD8021 has a low input noise of Pin 5. This serves two functions. It shields Pin 5 from any local 2.1 nV/√Hz @ 50 kHz. The input stage drives a folded cascode circuit noise generated by surrounding circuitry. It also that consists of a pair of PNP transistors. The folded cascode minimizes stray capacitance, which would tend to otherwise and current mirror provide a differential-to-single-ended reduce the bandwidth. An example of a guard ring layout is conversion of signal current. This current then drives the high shown in Figure 62. impedance node (Pin 5), where the C external capacitor is C connected. The output stage preserves this high impedance with Also shown in Figure 62, the compensation capacitor is located a current gain of 5000, so that the AD8021 can maintain a high immediately adjacent to the edge of the AD8021 package, spanning open-loop gain even when driving heavy loads. Pin 4 and Pin 5. This capacitor must be a high quality surface- mount COG or NPO ceramic. The use of leaded capacitors is Two internal diode clamps across the inputs (Pin 2 and Pin 3) not recommended. The high frequency bypass capacitor(s) protect the input transistors from large voltages that could should be located immediately adjacent to the supplies, otherwise cause emitter-base breakdown, which would result in Pin 4 and Pin 7. degradation of offset voltage and input bias current. To achieve the shortest possible lead length at the inverting +VS input, the feedback resistor R is located beneath the board and F spans the distance from the output, Pin 6, to inverting input Pin 2. The return node of Resistor R should be situated as close G as possible to the return node of the negative supply bypass capacitor connected to Pin 4. OUTPUT +IN (TOP VIEW) BYPASS CINTERNAL LOGIC REFERENCE 1 8 DISABLE CAPACITOR 1.5pF –IN –IN 2 +VS 7 –VS +IN 3 6 VOUT GROUND CCOMP CC 01888-061 –VS 4 5 CCOMP PLANE Figure 61. Simplified Schematic METAL BYPASS CAPACITOR COMPENSATION CAPACITOR GPRLOAUNNED 01888-062 Figure 62. Recommended Location of Critical Components and Guard Ring Rev. F | Page 21 of 28

AD8021 DRIVING 16-BIT ADCs Table 8. Summary of ADC Driver Performance (f = 100 kHz, V = 20 V p-p) Low noise and adjustable compensation make the AD8021 C OUT Parameter Measurement Unit especially suitable as a buffer/driver for high resolution ADCs. Second Harmonic Distortion −92.6 dBc As seen in Figure 19, the harmonic distortion is better than 90 dBc Third Harmonic Distortion −86.4 dBc at frequencies between 100 kHz and 1 MHz. This is an THD −84.4 dBc advantage for complex waveforms that contain high frequency SFDR +5.4 dBc information, because the phase and gain integrity of the sampled waveform can be preserved throughout the conversion process. DIFFERENTIAL DRIVER The increase in loop gain results in improved output regulation The AD8021 is uniquely suited as a low noise differential driver and lower noise when the converter input changes state during for many ADCs, balanced lines, and other applications requiring a sample. This advantage is particularly apparent when using differential drive. If pairs of internally compensated op amps are 16-bit high resolution ADCs with high sampling rates. configured as inverter and follower, the noise gain of the inverter Figure 63 shows a typical ADC driver configuration. The is higher than that of the follower section, resulting in an AD8021 is in an inverting gain of −7.5, f is 65 kHz, and its imbalance in the frequency response (see Figure 66). C output voltage is 10 V p-p. The results are listed in Table 7. A better solution takes advantage of the external compensation +12V +5V feature of the AD8021. By reducing the CCOMP value of the 3 inverter, its bandwidth can be increased to match that of the + 590Ω AD8021 6 IN follower, avoiding compromises in gain bandwidth and phase 2 5 HI delay. The inverting and noninverting bandwidths can be – CC closely matched using the compensation feature, thus 10pF AD7665 TS minimizing distortion. 2R00GΩ –12V 1.R5kFΩ 570kSPS 16 BI Figure 65 illustrates an inverter-follower driver circuit operating 50Ω at a gain of 2, using individually compensated AD8021s. The IN 56pF HI 01888-063 vtoatlaule lso oafd f oeef dlebsasc tkh aannd 1 lkoΩad, arensdis tthoers e wquerivea sleelnetc rteedsi sttoa nprcoevs isdeee na Figure 63. Inverting ADC Driver, Gain = −7.5, fC = 65 kHz at each op amp’s inputs were matched to minimize offset voltage Table 7. Summary of ADC Driver Performance (f = 65 kHz, and drift. Figure 67 is a plot of the resulting ac responses of C V = 10 V p-p) driver halves. OUT Parameter Measurement Unit Second Harmonic Distortion −101.3 dBc VIN 249Ω 3 + G = +2 6 Third Harmonic Distortion −109.5 dBc 49.9Ω AD8021 2 5 THD −100.0 dBc – SFDR +100.3 dBc –VS 7pF 499Ω 499Ω VOUT1 Figure 64 shows another ADC driver connection. The circuit 1kΩ was tested with a noninverting gain of 10.1 and an output 232Ω 3 + G =–2 voltage of approximately 20 V p-p for optimum resolution and 6 AD8021 VOUT2 noise performance. No filtering was used. An FFT was 2 – 5 1kΩ performed using Analog Devices evaluation software for the AD7665 16-bit converter. The+ 1r2eVsults are listed in Table 8. 332Ω –VS 656p4FΩ 01888-065 +5V Figure 65. Differential Amplifier 50Ω 3 + 50Ω 6 IN AD8021 50Ω 2 5 HI – CC S –12V 75R0FΩ A57D07kS6P6S5 6 BIT 1 RG ADC 82.5Ω OPTIONAL CF IN LO 01888-064 Figure 64. Noninverting ADC Driver, Gain = 10, fC = 100 kHz Rev. F | Page 22 of 28

AD8021 12 C1 9 +VS AD8021 6 VIN R1 R2 3 6 3 C2 2 5 VOUT N (dB) –30 GG == +–22 –VSCC GAI ––69 Figure 68. Schematic of a SReGcond-OrdeRr,F Low-Pass Ac01888-068tiv e Filter –12 Table 9. Typical Component Values for Second-Order, Low- ––1158 01888-066 PGaasins AcRti1v e FilteRr2 o f FigRuFr e 68 RG C1 C2 CC 100k 1M 10M 100M 1G (Ω) (Ω) (Ω) (Ω) (nF) (nF) (pF) FREQUENCY (Hz) 2 71.5 215 499 499 10 10 7 Figure 66. AC Response of Two Identically Compensated High Speed Op Amps Configured for a Gain of +2 and a Gain of −2 5 44.2 365 365 90.9 10 10 2 12 50 9 40 6 30 3 G =±2 20 G = 5 0 dB) B) 10 GAIN ( ––36 GAIN (d–100 G = 2 –9 –20 –12 –30 ––1158100k 1M 10M 100M 1G01888-067 ––4500 01888-069 1k 10k 100k 1M 10M FREQUENCY (Hz) FREQUENCY (Hz) Figure 67. AC Response of Two Dissimilarly Compensated AD8021 Op Amps Figure 69. Frequency Response of the Filter Circuit of Figure 68 (Figure 66) Configured for a Gain of +2 and a Gain of −2, for Two Different Gains (Note the Close Gain Match) DRIVING CAPACITIVE LOADS USING THE AD8021 IN ACTIVE FILTERS When the AD8021 drives a capacitive load, the high frequency The low noise and high gain bandwidth of the AD8021 make it response can show excessive peaking before it rolls off. Two an excellent choice in active filter circuits. Most active filter techniques can be used to improve stability at high frequency literature provides resistor and capacitor values for various and reduce peaking. The first technique is to increase the filters but neglects the effect of the op amp’s finite bandwidth on compensation capacitor, C , which reduces the peaking while filter performance; ideal filter response with infinite loop gain is C maintaining gain flatness at low frequencies. The second implied. Unfortunately, real filters do not behave in this manner. technique is to add a resistor, R , in series between the output Instead, they exhibit finite limits of attenuation, depending on SNUBB pin of the AD8021 and the capacitive load, C. Figure 70 shows the gain bandwidth of the active device. Good low-pass filter L the response of the AD8021 when both C and R are used to performance requires an op amp with high gain bandwidth for C SNUBB reduce peaking. For a given C, Figure 71 can be used to attenuation at high frequencies, and low noise and high dc gain L determine the value of R that maintains 2 dB of peaking in for low frequency, pass-band performance. SNUBB the frequency response. Note, however, that using R attenuates SNUB Figure 68 shows the schematic of a 2-pole, low-pass active filter the low frequency output by a factor of RLOAD/(RSNUBB + RLOAD). and lists typical component values for filters having a Bessel- type response with a gain of 2 and a gain of 5. Figure 69 is a network analyzer plot of this filter’s performance. Rev. F | Page 23 of 28

AD8021 18 20 +VS PRFOETBE 1164 49.9Ω 5 RSNUB CRCSN =U 7Bp =F 0;Ω 1186 12 49.9Ω –VS CC 6 33pF 1kRΩL CRCSN =U 8Bp =F 0;Ω 14 B) 10 499Ω )Ω12 N (d 8 499Ω (UB10 GAI 6 RSN 8 4 6 2 4 0 CRCSN =U 8Bp =F 1;7.4Ω 01888-070 20 01888-071 0.1 1.0 10 100 1000 0 5 10 15 20 25 30 35 40 45 50 FREQUENCY (MHz) CAPACITIVE LOAD (pF) Figure 70. Peaking vs. RSNUB and CC for CL = 33 pF Figure 71. Relationship of RSNUB Bvs. CL for 2 dB Peaking at a Gain of +2 Rev. F | Page 24 of 28

AD8021 OUTLINE DIMENSIONS 5.00 (0.1968) 4.80 (0.1890) 8 5 4.00 (0.1574) 6.20 (0.2440) 3.80 (0.1497) 1 4 5.80 (0.2284) 1.27 (0.0500) 0.50 (0.0196) BSC 1.75 (0.0688) 0.25 (0.0099)× 45° 0.25 (0.0098) 1.35 (0.0532) 0.10 (0.0040) 0.51 (0.0201) 8° COPL0A.1N0ARITY SEPALTAINNGE 0.31 (0.0122) 00..2157 ((00..00009687))0° 10..2470 ((00..00510507)) COMPLIANT TO JEDEC STANDARDS MS-012-AA CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. Figure 72. 8-Lead Standard Small Outline Package [SOIC] Narrow Body (R-8) Dimensions shown in millimeters and (inches) 3.20 3.00 2.80 8 5 5.15 3.20 4.90 3.00 4.65 2.80 1 4 PIN 1 0.65 BSC 0.95 0.85 1.10 MAX 0.75 0.80 0.15 0.38 0.23 8° 0.60 0.00 0.22 0.08 0° 0.40 COPLANARITY SEATING 0.10 PLANE COMPLIANT TO JEDEC STANDARDS MO-187-AA Figure 73. 8-Lead Mini Small Outline Package [MSOP] (RM-8) Dimensions shown in millimeters ORDERING GUIDE Model Temperature Range Package Description Package Option Branding AD8021AR −40°C to +85°C 8-Lead SOIC R-8 AD8021AR-REEL −40°C to +85°C 8-Lead SOIC R-8 AD8021AR-REEL7 −40°C to +85°C 8-Lead SOIC R-8 AD8021ARZ1 −40°C to +85°C 8-Lead SOIC R-8 AD8021ARZ-REEL1 −40°C to +85°C 8-Lead SOIC R-8 AD8021ARZ-REEL71 −40°C to +85°C 8-Lead SOIC R-8 AD8021ARM −40°C to +85°C 8-Lead MSOP RM-8 HNA AD8021ARM-REEL −40°C to +85°C 8-Lead MSOP RM-8 HNA AD8021ARM-REEL7 −40°C to +85°C 8-Lead MSOP RM-8 HNA AD8021ARMZ1 −40°C to +85°C 8-Lead MSOP RM-8 HNA# AD8021ARMZ-REEL1 −40°C to +85°C 8-Lead MSOP RM-8 HNA# AD8021ARMZ-REEL71 −40°C to +85°C 8-Lead MSOP RM-8 HNA# 1Z = Pb-free part, # denotes lead-free product may be top or bottom marked. Rev. F | Page 25 of 28

AD8021 NOTES Rev. F | Page 26 of 28

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AD8021 NOTES ©2006 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. C01888-0-5/06(F) Rev. F | Page 28 of 28

Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: A nalog Devices Inc.: AD8021ARMZ-REEL7 AD8021ARM-REEL7 AD8021ARM AD8021AR AD8021ARZ AD8021ARMZ AD8021ARZ- REEL AD8021ARZ-REEL7 AD8021ARMZ-REEL