Low Power, High Output Current xDSL Line Driver Data Sheet AD8016 FEATURES PIN CONFIGURATIONS xDSL line driver that features full ADSL central office (CO) +V1 1 24 +V2 Performance on ±12 V supplies VOUT1 2 23 VOUT2 Low power operation VINN1 3 – + + – 22 VINN2 ±5 V to ±12 V voltage supply VINP1 4 21 VINP2 12.5 mA/amp (typical) total supply current AGND 5 20 AGND AD8016 AGND 6 19 AGND Power reduced keep alive current of 4.5 mA/amp TOP VIEW AGND 7 (Not to Scale)18 AGND High output voltage and current drive AGND 8 17 AGND IOUT = 600 mA PWDN0 9 16 PWDN1 40 V p-p differential output voltage RL = 50 Ω, VS = ±12 V DGND 10 15 BIAS Low single-tone distortion –V1 11 14 –V2 MT–P7R5 =d B–7c 5@ d 1B Mc, H2z6 SkFHDzR t,o R 1L .=1 1M0H0z Ω, Z, LVINOEU =T = 1 020 V Ω p,- p NC = NNCO C12ONNECT 13 NC 01019-002 PLINE = 20.4 dBm Figure 1. 24-Lead SOIC_W_BAT (RB-24) High Speed 78 MHz bandwidth (–3 dB), G = +5 NC 1 28 NC 40 MHz gain flatness NC 2 27 NC NC 3 26 NC 1000 V/μs slew rate +VIN2 4 25 NC –VIN2 5 24 PWDN1 VOUT2 6 23 BIAS +V2 7 AD8016ARE 22 –V2 +V1 8 (NToOt Pto V SIEcaWle) 21 –V1 VOUT1 9 20 DGND –VIN1 10 19 NC +VIN1 11 18 PWDN0 NC 12 17 NC NC 13 16 NC NC 14 15 NC NOTES 1. THE EXPOSED PADDLE IS FLOATING, 2 . NNINCOT TE= RENNLOAE CCLOLTYRN.INCEACLTL.Y CONNECTED 01019-003 Figure 2. 28-Lead TSSOP_EP (RE-28-1) GENERAL DESCRIPTION The AD8016 high output current dual amplifier is designed for the xDSL hybrid in Figure 35 and Figure 36. Two digital bits the line drive interface in Digital Subscriber Line systems such (PWDN0, PWDN1) allow the driver to be capable of full as ADSL, HDSL2, and proprietary xDSL systems. The drivers performance, an output keep-alive state, or two intermediate are capable, in full-bias operation, of providing 24.4 dBm bias states. The keep-alive state biases the output transistors output power into low resistance loads, enough to power a enough to provide a low impedance at the amplifier outputs 20.4 dBm line, including hybrid insertion loss. for back termination. The AD8016 is available in a low cost 24-lead SOIC_W_BAT The low power dissipation, high output current, high output and a 28-lead TSSOP_EP with an exposed lead frame (ePAD). voltage swing, flexible power-down, and robust thermal Operating from ±12 V supplies, the AD8016 requires only 1.5 W packaging enable the AD8016 to be used as the central office of total power dissipation (refer to the Power Dissipation section (CO) terminal driver in ADSL, HDSL2, VDSL, and proprietary for details) while driving 20.4 dBm of power downstream using xDSL systems. Rev. C Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Tel: 781.329.4700 www.analog.com Trademarks and registered trademarks are the property of their respective owners. Fax: 781.461.3113 ©2012 Analog Devices, Inc. All rights reserved.

AD8016 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Feedback Resistor Selection ...................................................... 14 Pin Configurations ........................................................................... 1 Bias Pin and PWDN Features ................................................... 14 General Description ......................................................................... 1 Thermal Shutdown .................................................................... 15 Revision History ............................................................................... 2 Applications Information .............................................................. 16 Specifications ..................................................................................... 3 Multitone Power Ratio (MTPR) ............................................... 16 Logic Inputs (CMOS Compatible Logic) .................................. 4 Generating DMT ........................................................................ 17 Absolute Maximum Ratings ............................................................ 5 Power Dissipation....................................................................... 17 Maximum Power Dissipation ..................................................... 5 Thermal Enhancements and PCB Layout ............................... 18 ESD Caution .................................................................................. 5 Thermal Testing .......................................................................... 18 Pin Configurations and Function Descriptions ........................... 6 Air Flow Test Conditions .......................................................... 18 Typical Performance Characteristics ............................................. 7 Experimental Results ................................................................. 19 Test Circuts ...................................................................................... 13 Outline Dimensions ....................................................................... 20 Theory of Operation ...................................................................... 14 Ordering Guide .......................................................................... 20 Power Supply and Decoupling .................................................. 14 REVISION HISTORY 3/12—Rev. B to Rev. C Updated Format .................................................................. Universal Deleted PSOP Package and Evaluation Boards (Throughout) ... 1 Added Pin Configurations and Function Descriptions Sections .. 7 Updated Outline Dimensions ....................................................... 21 Changes to Ordering Guide .......................................................... 19 11/03—Rev. A to Rev. B Changes to Ordering Guide ............................................................ 4 Changes to TPC 21 ........................................................................... 8 Updated Outline Dimensions ..................................................19-20 Rev. C | Page 2 of 20

Data Sheet AD8016 SPECIFICATIONS @ 25°C, V = ±12 V, R = 100 Ω, PWDN0, PWDN1 = (1, 1), T = −40°C, T = +85°C, unless otherwise noted. S L MIN MAX Table 1. Parameter Test Conditions/Comments Min Typ Max Unit DYNAMIC PERFORMANCE −3 dB Bandwidth G = +1, RF = 1.5 kΩ, VOUT = 0.2 V p-p 380 MHz G = +5, RF = 499 Ω, VOUT < 0.5 V p-p 69 78 MHz Bandwidth for 0.1 dB Flatness G = +5, RF = 499 Ω, VOUT = 0.2 V p-p 16 38 MHz Large Signal Bandwidth VOUT = 4 V p-p 90 MHz Peaking VOUT = 0.2 V p-p < 50 MHz 0.1 dB Slew Rate VOUT = 4 V p-p, G = +2 1000 V/μs Rise and Fall Time VOUT = 2 V p-p 2 ns Settling Time 0.1%, VOUT = 2 V p-p 23 ns Input Overdrive Recovery Time VOUT = 12.5 V p-p 350 ns NOISE/DISTORTION PERFORMANCE Distortion, Single-Ended VOUT = 2 V p-p, G = +5, RF = 499 Ω Second Harmonic fC = 1 MHz, RL = 100 Ω/25 Ω −75/−62 −77/−64 dBc Third Harmonic fC = 1 MHz, RL = 100 Ω/25 Ω −88/−74 −93/−76 dBc Multitone Power Ratio1 26 kHz to 1.1 MHz, ZLINE = 100 Ω, PLINE = 20.4 dBm –75 dBc IMD 500 kHz, Δf = 10 kHz, RL = 100 Ω/25 Ω −84/−80 −88/−85 dBc IP3 500 kHz, RL = 100 Ω/25 Ω 42/40 43/41 dBm Voltage Noise (RTI) f = 10 kHz 2.6 4.5 nV/√Hz Input Current Noise f = 10 kHz 18 21 pA√Hz INPUT CHARACTERISTICS RTI Offset Voltage −3.0 1.0 +3.0 mV +Input Bias Current −45 +45 μA –Input Bias Current −75 4 +75 μA Input Resistance 400 kΩ Input Capacitance 2 pF Input Common-Mode Voltage Range −10 +10 V Common-Mode Rejection Ratio 58 64 dB OUTPUT CHARACTERISTICS Output Voltage Swing Single-ended, RL = 100 Ω −11 +11 V Linear Output Current G = 5, RL = 10 Ω, f1 = 100 kHz, −60 dBc SFDR 400 600 mA Short-Circuit Current 2000 mA Capacitive Load Drive 80 pF POWER SUPPLY Operating Range ±3 ±13 V Quiescent Current PWDN1, PWDN0 = (1, 1) 12.5 13.2 mA/Amp PWDN1, PWDN0 = (1, 0) 8 10 mA/Amp PWDN1, PWDN0 = (0, 1) 5 8 mA/Amp PWDN1, PWDN0 = (0, 0) 4 6 mA/Amp Recovery Time To 95% of IQ 25 μs Shutdown Current 250 μA out of bias pin 1.5 4.0 mA/Amp Power Supply Rejection Ratio ΔVS = ±1 V 63 75 dB OPERATING TEMPERATURE RANGE −40 +85 °C 1 See Figure 48, R20, R21 = 0 Ω, R1 = open. Rev. C | Page 3 of 20

AD8016 Data Sheet @ 25°C, V = ±6 V, R = 100 Ω, PWDN0, PWDN1 = (1, 1), T = –40°C, T = +85°C, unless otherwise noted. S L MIN MAX Table 2. Parameter Test Conditions/Comments Min Typ Max Unit DYNAMIC PERFORMANCE –3 dB Bandwidth G = +1, RF = 1.5 kΩ, VOUT = 0.2 V p-p 320 MHz G = +5, RF = 499 Ω, VOUT < 0.5 V p-p 70 71 MHz Bandwidth for 0.1 dB Flatness G = +5, RF = 499 Ω, VOUT = 0.2 V p-p 10 15 MHz Large Signal Bandwidth VOUT = 1 V rms 80 MHz Peaking VOUT = 0.2 V p-p < 50 MHz 0.7 1.0 dB Slew Rate VOUT = 4 V p-p, G = +2 300 V/μs Rise and Fall Time VOUT = 2 V p-p 2 ns Settling Time 0.1%, VOUT = 2 V p-p 39 ns Input Overdrive Recovery Time VOUT = 6.5 V p-p 350 ns NOISE/DISTORTION PERFORMANCE Distortion, Single-Ended G = +5, VOUT = 2 V p-p, RF = 499 Ω Second Harmonic fC = 1 MHz, RL = 100 Ω/25 Ω −73/61 −75/−63 dBc Third Harmonic fC = 1 MHz, RL = 100 Ω/25 Ω −80/−68 −82/−70 dBc Multitone Power Ratio1 26 kHz to 138 kHz, ZLINE = 100 Ω, PLINE = 13 dBm −68 dBc IMD 500 kHz, Δf = 110 kHz, RL = 100 Ω/25 Ω −87/−82 −88/−83 dBc IP3 500 kHz 42/39 42/39 dBm Voltage Noise (RTI) f = 10 kHz 4 5 nV/√Hz Input Current Noise f = 10 kHz 17 20 pA√Hz INPUT CHARACTERISTICS RTI Offset Voltage −3.0 0.2 +3.0 mV +Input Bias Current −25 10 +25 μA −Input Bias Current −30 10 +30 μA Input Resistance 400 kΩ Input Capacitance 2 pF Input Common-Mode Voltage Range −4 +4 V Common-Mode Rejection Ratio 60 66 dB OUTPUT CHARACTERISTICS Output Voltage Swing Single-Ended, RL = 100 Ω −5 +5 V Linear Output Current G = +5, RL = 5 Ω, f = 100 kHz, −60 dBc SFDR 300 420 mA Short-Circuit Current 830 mA Capacitive Load Drive RS = 10 Ω 50 pF POWER SUPPLY Quiescent Current PWDN1, PWDN0 = (1, 1) 8 9.7 mA/Amp PWDN1, PWDN0 = (1, 0) 6 6.9 mA/Amp PWDN1, PWDN0 = (0, 1) 4 5.0 mA/Amp PWDN1, PWDN0 = (0, 0) 3 4.1 mA/Amp Recovery Time To 95% of IQ 23 μs Shutdown Current 250 μA out of bias pin 1.0 2.0 mA/Amp Power Supply Rejection Ratio ΔVS = ±1 V 63 80 dB OPERATING TEMPERATURE RANGE −40 +85 °C 1See Figure 48, R20, R21 = 0 Ω, R1 = open. LOGIC INPUTS (CMOS COMPATIBLE LOGIC) PWDN0, PWDN1, V = ±12 V or ±6 V; full temperature range. CC Table 3. Parameter Min Typ Max Unit Logic 1 Voltage 2.2 VCC V Logic 0 Voltage 0 0.8 V Rev. C | Page 4 of 20

Data Sheet AD8016 ABSOLUTE MAXIMUM RATINGS The output stage of the AD8016 is designed for maximum load Table 4. current capability. As a result, shorting the output to common Parameter Rating can cause the AD8016 to source or sink 2000 mA. To ensure Supply Voltage 26.4 V proper operation, it is necessary to observe the maximum Internal Power Dissipation power derating curves. Direct connection of the output to SOIC_W_BAT Package1 1.4 W either power supply rail can destroy the device. TSSOP_EP Package2 1.4 W Input Voltage (Common-Mode) ±VS 8 Differential Input Voltage ±VS 7 Output Short-Circuit Duration Observe power derating W) curves N ( O 6 Storage Temperature Range −65°C to +125°C TI A Operating Temperature Range −40°C to +85°C SIP 5 S Lead Temperature Range (Soldering 10 sec) 300°C DI ER 4 SOIC_W_BAT 1 Specification is for device on a 4-layer board with 10 inches2 of 1 oz copper W O 2 aStp 8e5c°iCfi c2a4t-iolena dis SfoOrI Cd_eWvic_eB AonT pa a4c-klaaygeer: bθoJAa =rd 2 w8°iCth/W 9 .i nches2 of 1 oz copper at UM P 3 TSSOP-EP 85°C 28-lead (TSSOP_EP) package: θJA = 29°C/W. XIM 2 A Stresses above those listed under Absolute Maximum Ratings M 1 may cause permanent damage to the device. This is a stress roatthienrg c oonnldyi;t fiuonncs taiobnovale othpoersaet iinond iocaf ttehde idne tvhicee o apte trhaetisoen oarl any 00 10 20 AMB30IENT T4E0MPE5R0ATUR6E0 (°C)70 80 90 01019-005 section of this specification is not implied. Exposure to absolute Figure 3. Maximum Power Dissipation vs. Temperature for AD8016 for maximum rating conditions for extended periods may affect TJ = 125 °C device reliability. ESD CAUTION MAXIMUM POWER DISSIPATION The maximum power that can be safely dissipated by the AD8016 is limited by the associated rise in junction temper- ature. The maximum safe junction temperature for a plastic encapsulated device is determined by the glass transition temperature of the plastic, approximately 150°C. Temporarily exceeding this limit may cause a shift in parametric perfor- mance due to a change in the stresses exerted on the die by the package. Rev. C | Page 5 of 20

AD8016 Data Sheet PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS NC 1 28 NC NC 2 27 NC NC 3 26 NC +VIN2 4 25 NC +V1 1 24 +V2 –VIN2 5 24 PWDN1 VOUT1 2 23 VOUT2 VOUT2 6 23 BIAS +V2 7 AD8016ARE 22 –V2 VVIINNNP11 34 – + + – 2221 VVIINNNP22 +V1 8 (NToOt Pto V SIEcaWle) 21 –V1 AGND 5 20 AGND VOUT1 9 20 DGND AGND 6 AD8016 19 AGND –VIN1 10 19 NC AGND 7 (NToOtP t oV ISEcWale)18 AGND +VIN1 11 18 PWDN0 NC 12 17 NC AGND 8 17 AGND NC 13 16 NC PWDN0 9 16 PWDN1 NC 14 15 NC DGND 10 15 BIAS –V1 11 14 –V2 NOTES NC = NNCO C12ONNECT 13 NC 01019-002 1 2 .. NTNINHCOTE TE= ERENXNLOPAE OCCLOLSTYREN.DINC EPACALTLD.YD LCEO INSN FELCOTAETDING,01019-003 Figure 4. 24-Lead SOIC_W_BAT (RB-24) Figure 5. 28-Lead TSSOP_EP (RE-28-1) Table 5. Pin Function Descriptions Pin No. SOIC_W_BAT TSSOP_EP Mnemonic Description 1 8 +V1 Positive Power Supply, Amp 1. 2 9 V 1 Output Signal, Amp 1. OUT 3 V 1 Negative Input Signal, Amp 1. INN 4 V 1 Positive Input Signal, Amp1. INP 5 to 8, 17 to 20 AGND Analog Ground. 9 18 PWDN0 Power-Down Input 0. 10 20 DGND Digital Ground. 11 21 −V1 Negative Power Supply, Amp1. 12, 13 1 to 3, 12 to 17, 19, NC This pin is not connected internally (see Figure 4 and Figure 5). 25 to 28 14 22 −V2 −V Power Supply, Amp 2. 15 23 BIAS Quiescent Current Adjust. 16 24 PWDN1 Power-Down Input 1. 21 V 2 Positive Input Signal, Amp 2. INP 22 V 2 Negative Input Signal, Amp 2. INN 23 6 V 2 Output Signal, Amp 2. OUT 24 7 +V2 Positive Power Supply, Amp 2. 4 +V 2 Positive Input Signal, Amp 2. IN 5 −V 2 Negative Input Signal, Amp 2. IN 10 −V 1 Negative Input Signal, Amp 1. IN 11 +V 1 Positive Input Signal, Amp 1. IN EP EPAD Exposed Pad. The exposed paddle is floating, not electrically connected internally. Rev. C | Page 6 of 20

Data Sheet AD8016 TYPICAL PERFORMANCE CHARACTERISTICS VOUT = 100mV DIV –75dBc TS 10dB/ VOL VIN = 20mV 549.3 550.3 551.3 552.3F5R53E.Q3U5E5N4.C3Y5 (5k5H.3z)556.3 557.3 558.3 559.3 01019-004 TIME (100ns/DIV) 01019-010 Figure 6. Multitone Power Ratio; VS = ±12 V, 20.4 dBm Output Power into Figure 9. 100 mV Step Response; G = +5, VS = ±12 V, RL = 25 Ω, Single-Ended 100 Ω, Downstream VOUT = 100mV VOUT= 4V OLTS OLTS V V VIN = 20mV VIN = 800mV TIME (100ns/DIV) 01019-008 TIME (100ns/DIV) 01019-011 Figure 7. 100 mV Step Response; G = +5, VS = ±6 V, RL = 25 Ω, Single-Ended Figure 10. 4 V Step Response; G = +5, VS = ±12 V, RL = 25 Ω, Single-Ended –30 VOUT= 5V RGF = = + 41909Ω (0,0) –40 VOUT = 4V p-p –50 (0,1) dBc) –60 (1,0) TS N ( VOL RTIO –70 VIN = 800mV TO S –80 DI PWDN1, PWDN0 = (1,1) –90 –100 TIME (100ns/DIV) 01019-009 –1100.01 0.1 FREQUENCY (M1Hz) 10 20 01019-012 Figure 8. 4 V Step Response; G = +5, VS = ±6 V, RL = 25 Ω, Single-Ended Figure 11. Distortion vs. Frequency; Second Harmonic, VS = ±12 V, RL = 50 Ω, Differential Rev. C | Page 7 of 20

AD8016 Data Sheet –30 –30 RF = 499Ω (0,0) RF = 499Ω G = +10 G = +10 –40 VOUT = 4V p-p (0,1) –40 VOUT = 4V p-p (0,0) –50 –50 (1,0) (0,1) (1,0) N (dBc) –60 N (dBc) –60 O O RTI –70 RTI –70 O O PWDN1, PWDN0 = (1,1) ST –80 ST –80 DI PWDN1, PWDN0 = (1,1) DI –90 –90 –100 –100 –1100.01 0.1 FREQUENCY (M1Hz) 10 20 01019-013 –1100.01 0.1 FREQUENCY (M1Hz) 10 20 01019-016 Figure 12. Distortion vs. Frequency; Second Harmonic, VS = ±6 V, RL = 50 Ω Figure 15. Distortion vs. Frequency; Third Harmonic, VS = ±6 V, RL = 50 Ω, Differential –30 –30 RF = 499Ω RF = 499Ω G = +5 G = +5 –35 –40 –40 (1,0) –45 (0,0) c) c) –50 B B N (d –50 N (d (0,1) O O TI –55 TI –60 R (0,0) (0,1) (1,0) R O O T –60 T S S DI DI –70 –65 –70 –80 –75 PWDN1, PWDN0 = (1,1) PWDN1, PWDN0 = (1,1) –800 100 20P0EAK 3O0U0TPU4T0 C0URR5E0N0T (mA6)00 700 800 01019-014 –900 100 P20E0AK OU3T0P0UT CU4R0R0ENT (m50A0) 600 700 01019-017 Figure 13. Distortion vs. Peak Output Current; Second Harmonic, VS = ±12 V, Figure 16. Distortion vs. Peak Output Current, Third Harmonic; VS = ±12 V, RL = 10 Ω, f = 100 kHz, Single-Ended RL = 10 Ω, G = +5, f = 100 kHz, Single-Ended –30 –30 RF = 499Ω (0,0) RF = 499Ω G = +10 G = +5 –40 VOUT = 4V p-p –35 (0,1) –40 –50 –45 N (dBc) –60 (1,0) N (dBc) –50 (0,0) (0,1) O O TI –70 TI –55 R R (1,0) O PWDN1, PWDN0 = (1,1) O ST –80 ST –60 DI DI –65 –90 –70 –100 –75 PWDN1, PWDN0 = (1,1) –1100.01 0.1 FREQUENCY (M1Hz) 10 20 01019-015 –800 100 PEA2K00 OUTPU3T0 C0URREN4T0 (0mA) 500 600 01019-018 Figure 14. Distortion vs. Frequency; Third Harmonic, VS = ±12 V, RL = 50 Ω, Figure 17. Distortion vs. Peak Output Current; Second Harmonic, VS = ±6 V, Differential RL = 5 Ω, f = 100 kHz, Single-Ended Rev. C | Page 8 of 20

Data Sheet AD8016 –30 –30 –40 –40 (0,0) –50 –50 Bc) Bc) d (0,0) d (0,1) N (–60 N (–60 O O ORTI–70 (0,1) ORTI–70 (1,0) ST (1,0) ST DI DI –80 –80 PWDN1, PWDN0 = (1,1) PWDN1, PWDN0 = (1,1) –90 –90 –1000 5 10DIFFE1R5ENTIA2L0 OUTP2U5T (V p3-0p) 35 40 01019-020 –1000 5 10DIFFE1R5ENTIA2L0 OUTP25UT (V p3-0p) 35 40 01019-023 Figure 18. Distortion vs. Output Voltage; Second Harmonic, VS = ±12 V, Figure 21. Distortion vs. Output Voltage; Third Harmonic, VS = ±12 V, G = +10, f = 1 MHz, RL = 50 Ω, Differential G = +10, f = 1 MHz, RL = 50 Ω, Differential –30 –30 –40 –40 (0,0) c)–50 c)–50 B B d d N ( N ( (0,1) O O TI–60 TI–60 OR (0,0) OR (1,0) ST (0,1) ST DI–70 DI–70 (1,0) –80 –80 PWDN1, PWDN0 = (1,1) PWDN1, PWDN0 = (1,1) –900 5DIFFERENTIAL1 0OUTPUT (V p-p1)5 20 01019-021 –900 5DIFFERENTIAL1 0OUTPUT (V p-p1)5 20 01019-024 Figure 19. Distortion vs. Output Voltage; Second Harmonic, VS = ±6 V, Figure 22. Distortion vs. Output Voltage, Third Harmonic, VS = ±6 V, G = +10, G = +10, f = 1 MHz, RL = 50 Ω, Differential f = 1 MHz, RL = 50 Ω, Differential –30 3 –35 dB) 0 E ( –40 NS –3 O (1,1) c) –45 ESP –6 B R ON (d –50 (0,0) NCY –9 (1,0) DISTORTI –––665505 (0,1) (1,0) ED FREQUE–––111258 (0,(10),0) Z –70 ALI–21 M ––87050 100 PEA2K00 OUTPU3T0 C0URRENP4WT0 (D0mNA1), PW5D0N00 = (1,16)00 01019-022 NOR––22471GRVIL N= = =+ 154000mΩV p-p F10REQUENCY (MHz) 100 500 01019-025 Figure 20. Distortion vs. Peak Output Current; Third Harmonic, VS = ±6 V, Figure 23. Frequency Response; VS = ±12 V, @ PWDN1, PWDN0 Codes G = +5, RL = 5 Ω, f = 100 kHz, Single-Ended Rev. C | Page 9 of 20

AD8016 Data Sheet 11 11 G = +5 G = +5 8 RRLF == 140909ΩΩ 8 RRLF == 140909ΩΩ 5 5 V) V) dB 2 dB 2 GE ( –1 GE ( –1 A A T T OL –4 OL –4 V V UT –7 UT –7 P P UT–10 UT–10 O O –13 –13 –16 –16 –191 F1R0EQUENCY (MHz) 100 500 01019-026 –191 F1R0EQUENCY (MHz) 100 500 01019-029 Figure 24. Output Voltage vs. Frequency; VS = ±12 V Figure 27. Output Voltage vs. Frequency; VS = ±6 V 20 –10 VIN= 2V rms RF = 499Ω 10 RF = 602Ω –20 (1,1) 0 (1,0) –30 –10 +PSRR –40 B)–20 B) d d RR (–30 (0,1) RR (–50 CM–40 PS –PSRR –60 (0,0) –50 –70 –60 –80 –70 –800.03 0.1 F1REQUENCY (M10Hz) 100 500 01019-027 –900.01 0.1 FRE1QUENCY (MH1z0) 100 500 01019-030 Figure 25. CMRR vs. Frequency; VS = ±12 V @ PWDN1, PWDN0 Codes Figure 28. PSRR vs. Frequency; VS = ±12 V 6 180 90 B) MALIZED FREQUENCY RESPONSE (d–––111–––25836930 (1,1(1()0,0,(1)0),0) + INPUT CURRENT NOISE (pA/ Hz)111124608640000000 +INOISE VIN NOISE 23456780000000 INPUT VOLTAGE NOISE (nV/ Hz) OR–21 VIN = 40mV p-p 20 10 N G = +5 –241RL = 100Ω F10REQUENCY (MHz) 100 500 01019-028 010 100 1kFREQUE1N0CkY (MHz1)00k 1M 10M0 01019-031 Figure 26. Frequency Response; VS = ±6 V, @ PWDN1, PWDN0 Codes Figure 29. Noise vs. Frequency Rev. C | Page 10 of 20

Data Sheet AD8016 %/DIV)) GRVOF = U= T+ 1 2=k Ω2VSTEP %/DIV)) GRVOF = U= T+ 1 2=k Ω2VSTEP V (0.1 RL = 100Ω V (0.1 RL = 100Ω DI DI mV/ +2mV mV/ OR (2(–0.1%0) OR (2(–+02.1m%V) E ERR(––02.1m%V) E ERR –2mV0 VIN AG VIN VOUT VOUT – VIN AG(–0.1%) VOLT VOLT VOUT VOUT – VIN UT UT P P UT UT O O –5 0 5 10 15TIM2E0 (ns)25 30 35 40 45 01019-032 –5 0 5 10 15TIM2E0 (ns)25 30 35 40 45 01019-035 Figure 30. Settling Time 0.1%; VS = ±12 V Figure 33. Settling Time 0.1%; VS = ±6 V –20 1000 VOUT= 2V p-p RF = 499Ω G = +5 –30 RL = 100Ω 100 B)–40 ΩCE () (0,0) CROSSTALK (d––5600 TPUT IMPEDAN 101 (0,1) (1,1)(1,0) –70 OU 0.1 –80 –900.03 0.1 F1REQUENCY(M10Hz) 100 500 01019-033 0.010.03 0.1 F1REQUENCY (M10Hz) 100 500 01019-036 Figure 31. Output Crosstalk vs. Frequency Figure 34. Output Impedance vs. Frequency @ PWDN1, PWDN0 Codes 1M 360 VIN = 2V/DIV VOUT = 5V/DIV 100k 320 VOUT 10k 280 Ω) CE (k 1k PHASE 240 ees) DAN 100 200 Degr 0V MPE 10 TRANSIMPEDANCE 160 SE ( VIN ANSI 1 120 PHA R T 0.1 80 0V 0.01 40 0.000.10001 0.001 0.01 F0R.1EQUEN1CY (MH10z) 100 1k 10k0 01019-034 –100 0 100 200 300TIM4E0 0(ns)500 600 700 800 900 01019-037 Figure 32. Open-Loop Transimpedance and Phase vs. Frequency Figure 35. Positive Overdrive Recovery; VS = ±12 V, G = +5, RL = 100 Ω Rev. C | Page 11 of 20

AD8016 Data Sheet VIN = 2V/DIV 18 VOUT = 5V/DIV 16 PWDN1, PWDN0 = (1,1) 0V 14 VOUT 12 (1,0) A)10 m I (Q 8 (0,1) 0V (0,0) VIN 6 4 2 –100 0 100 200 300TIM4E0 0(ns)500 600 700 800 900 01019-038 00 50 IBIA1S0 0(µA) 150 200 01019-040 Figure 36. Negative Overdrive Recovery; VS = ±12 V, G = +5, RL = 100 Ω Figure 38. IQ vs. IBIAS Current; VS = ±6 V 25 12 +VOUT, VS = ±12V PWDN1, PWDN0 = (1,1) 8 20 +VOUT, VS = ±6V V) 4 mA)15 (1,0) WING ( (Q T S 0 I (0,1) U 10 P T U O–4 (0,0) –VOUT, VS = ±6V 5 –8 –VOUT, VS = ±12V 00 50 IBIA1S0 0(µA) 150 200 01019-039 –1210 100 RLOAD (Ω) 1k 10k 01019-041 Figure 37. IQ vs. IBIAS Current; VS = ±12 V Figure 39. Output Voltage vs. RLOAD Rev. C | Page 12 of 20

Data Sheet AD8016 TEST CIRCUTS 10µF +VS + 0.1µF 124Ω 499Ω RL VOUT +VIN 49.9Ω +VO 499Ω VIN 111Ω 499Ω RL 49.9Ω +VS 0.1µF +10µF –VO –VIN 0.1µF 49.9Ω 0.1µF +10µF –VS 01019-006 –VS 10µF+ 01019-007 Figure 40. Single-Ended Test Circuit; G = +5 Figure 41. Differential Test Circuit; G = +10 Rev. C | Page 13 of 20

AD8016 Data Sheet THEORY OF OPERATION The AD8016 is a current feedback amplifier with high POWER SUPPLY AND DECOUPLING (500 mA) output current capability. With a current feedback The AD8016 should be powered with a good quality (that is, amplifier, the current into the inverting input is the feedback low noise) dual supply of ±12 V for the best distortion and signal and the open-loop behavior is that of a transimpedance, multitone power ratio (MTPR) performance. Careful attention dV /dI or T . The open-loop transimpedance is analogous OUT IN Z must be paid to decoupling the power supply pins. A 10 μF to the open-loop voltage gain of a voltage feedback amplifier. capacitor located in near proximity to the AD8016 is required Figure 42 shows a simplified model of a current feedback ampli- to provide good decoupling for lower frequency signals. In fier. Because R is proportional to 1/g , the equivalent voltage IN m addition, 0.1 μF decoupling capacitors should be located as gain is just T × g , where g is the transconductance of the Z m m close to each of the four power supply pins as is physically input stage. Basic analysis of the follower with gain circuit yields possible. All ground pins should be connected to a common V T (S) low impedance ground plane. OUT =G× Z V T (S)+G×R +R FEEDBACK RESISTOR SELECTION IN Z IN F where: In current feedback amplifiers, selection of feedback and gain resistors has an impact on the MTPR performance, bandwidth, R G=1+ F and gain flatness. Take care in selecting these resistors so that R G optimum performance is achieved. Table 6 below shows the 1 recommended resistor values for use in a variety of gain R = ≈25Ω IN g settings. These values are suggested as a good starting point m when designing for any application. Recognizing that G × R << R for low gains, the familiar result IN F of constant bandwidth with gain for current feedback amplifiers Table 6. Resistor Selection Guide is evident, the 3 dB point being set when |TZ| = RF. Of course, Gain RF (Ω) RG (Ω) for a real amplifier there are additional poles that contribute +1 1000 ∞ excess phase and there is a value for R below which the ampli- F −1 500 500 fier is unstable. Tolerance for peaking and desired flatness +2 650 650 determines the optimum R in each application. F +5 750 187 +10 1000 111 RF RG – BIAS PIN AND PWDN FEATURES RIN + IIN TZ VOUT The AD8016 is designed to cover both central office (CO) RN + and customer premise equipment (CPE) ends of an xDSL application. It offers full versatility in setting quiescent bias VIN 01019-042 lbeivaesl (si nfo rth trheee psaterptisc)u tloa rf uapllp olficf a(tviioan B fIrAomS p fiunl)l. oTnh tios vreedrsuacteildit y Figure 42. Simplified Block Diagram gives the modem designer the flexibility to maximize efficiency The AD8016 is the first current feedback amplifier capable of while maintaining reasonable levels of MTPR performance. delivering 400 mA of output current while swinging to within Optimizing driver efficiency while delivering the required DMT 2 V of either power supply rail. This enables full CO ADSL power is accomplished with the AD8016 through the use of on- performance on only 12 V rails, an immediate 20% power chip power management features. Two digitally programmable saving. The AD8016 is also unique in that it has a power logic pins, PWDN1 and PWDN0, may be used to select four management system included on-chip. It features four user different bias levels: 100%, 60%, 40%, and 25% of full quiescent programmable power levels (all of which provide a low output power (see Table 7). impedance of the driver), as well as the provision for complete shutdown (high impedance state). Also featured is a thermal Table 7. PWDN Code Selection Guide shutdown with alarm signal. PWDN1 PWDN0 Code Code Quiescent Bias Level 1 1 100% (full on) 1 0 60% 0 1 40% 0 0 25% (low Z but not off) OUT X X Full off (high Z via 250 μA pulled out of OUT BIAS pin) Rev. C | Page 14 of 20

Data Sheet AD8016 The bias level can be controlled with TTL logic levels (high = 1) THERMAL SHUTDOWN applied to the PWDN1 and PWDN0 pins alone or in combina- The AD8016 ARB is designed to incorporate shutdown tion with the BIAS control pin. The DGND or digital ground protection against accidental thermal overload. In the event pin is the logic ground reference for the PWDN1 and PWDN0 of thermal overload, the AD8016 was designed to shut down pins. In typical ADSL applications where ±12 V or ±6 V at a junction temperature of 165°C and return to normal supplies (also single supplies) are used, the DGND pin is operation at a junction temperature 140°C. The AD8016 connected to analog ground. continues to operate, cycling on and off, as long as the thermal The BIAS control pin by itself is a means to continuously adjust overload condition remains. The frequency of the protection the AD8016 internal biasing and, thus, quiescent current IQ. By cycle depends on the ambient environment, severity of the pulling out a current of 0 μA (or open) to approximately200 μA, thermal overload condition, the power being dissipated, and the quiescent current can be adjusted from 100% (full on) to a the thermal mass of the PCB beneath the AD8016. When the full off condition. The full off condition yields a high output AD8016 begins to cycle due to thermal stress, the internal impedance. Because of an on-chip resistor variation of up to shutdown circuitry draws current out of the node connected ±20%, the actual amount of current required to fully shut down in common with the BIAS pin, while the voltage at the BIAS the AD8016 can vary. To institute a full chip shutdown, a pull- pin goes to the negative rail. When the junction temperature down current of 250 μA is recommended. See Figure 43 for the returns to 140°C, current is no longer drawn from this node, logic drive circuit for complete amplifier shutdown. Figure 37 and the BIAS pin voltage returns to the positive rail. Under and Figure 38 show the relationship between current pulled out these circumstances, the BIAS pin can be used to trip an alarm of the BIAS pin (I ) and the supply current (I ). A typical indicating the presence of a thermal overload condition. BIAS Q shutdown I is less than 1 mA total. Alternatively, an external Q Figure 44 also shows three circuits for converting this signal to pull-down resistor to ground or a current sink attached to the a standard logic level. BIAS pin can be used to set I to lower levels (see Figure 44). Q The BIAS pin may be used in combination with the PWDN1 VCC AD8016 and PWDN0 pins; however, diminished MTPR performance 200µA 10kΩ V = VCC–0.2V may result when I is lowered too much. Current pulled away Q SHUT- BIAS OR 0µA – 200µA from the BIAS pin shunts away a portion of the internal bias DOWN current. Setting PWDN1 or PWDN0 to Logic 0 also shunts BIAS VEE away a portion of the internal bias current. The reduction of PWDN0 PWDN1 5V quiescent bias levels due to the use of PWDN1 and PWDN0 is VCC 10kΩ consistent with the percentages established in Table 7. When 5V ALARM PWDN0 alone is set to Logic 0, and no other means of reducing 10kΩ 1MΩ BIAS ALARM OR BIAS MINβ 350 tdhreiv iennte wrnhaille b miaas icnutarrinenintsg irse uassoedn,a fbulell -leravteel sA oDf MSLT sPigRn.a ls may be S1G/4S H–CTFH O40M1S0O9BN 100kΩ 01019-044 3.3V LOGIC R1* Figure 44. Shutdown and Alarm Circuit R2 BIAS 50kΩ 2N3904 *RR11 == 2427kkΩΩ FFOORR ±±61V2VS.S OR +12VS, 01019-043 Figure 43. Logic Drive of BIAS Pin for Complete Amplifier Shutdown Rev. C | Page 15 of 20

AD8016 Data Sheet APPLICATIONS INFORMATION The AD8016 dual amplifier forms an integrated single-channel See Figure 6 for a sample of the ADSL downstream spectrum ADSL line driver. The AD8016 may be applied in driving mod- showing MTPR results while driving 20.4 dBm of power onto ulated signals including discrete multitone (DMT) in either a 100 Ω line. Measurements of MTPR are typically made at direction; upstream from CPE to the CO and downstream the output (line side) of ADSL hybrid circuits. MTPR can be from CO to CPE. The most significant thermal management affected by the components contained in the hybrid circuit, challenge lies in driving downstream information from CO sites including the quality of the capacitor dielectrics, voltage ratings, to the CPE. Driving xDSL information downstream suggests and the turns ratio of the selected transformers. Other compo- the need to locate many xDSL modems in a single CO site. The nents aside, an ADSL driver hybrid containing the AD8016 can implication is that several modems will be placed onto a single be optimized for the best MTPR performance by selecting the printed circuit board residing in a card cage located in a variety turns ratio of the transformers. The voltage and current demands of ambient conditions. Environmental conditioners such as fans from the differential driver changes, depending on the trans- or air conditioning may or may not be available, depending on former turns ratio. The point on the curve indicating maximum the density of modems and the facilities contained at the CO dynamic headroom is achieved when the differential driver site. To achieve long-term reliability and consistent modem delivers both the maximum voltage and current while maintaining performance, designers of CO solutions must consider the wide the lowest possible distortion. Below this point, the driver has array of ambient conditions that exist within various CO sites. reserve current-driving capability and experiences voltage clipping. Above this point, the amplifier runs out of current MULTITONE POWER RATIO (MTPR) drive capability before the maximum voltage drive capability ADSL systems rely on discrete multitone modulation to carry is reached. Because a transformer reflects the secondary load digital data over phone lines. DMT modulation appears in the impedance back to the primary side by the square of the turns frequency domain as power contained in several individual ratio, varying the turns ratio changes the load across the frequency subbands, sometimes referred to as tones or bins, differential driver. The following equation may be used to each of which is uniformly separated in frequency. (See Figure 6 calculate the load impedance across the output of the differen- for an example of downstream DMT signals used in evaluating tial driver, reflected by the transformers, from the line side of MTPR performance.) A uniquely encoded, quadrature ampli- the xDSL driver hybrid. tude modulation (QAM) signal occurs at the center frequency Z of each subband or tone. Difficulties arise when decoding these Z′≡ ( 2 ) subbands if a QAM signal from one subband is corrupted by the 2×N 2 QAM signal(s) from other subbands, regardless of whether the where: corruption comes from an adjacent subband or harmonics of Z' is the primary side impedance as seen by the differential other subbands. Conventional methods of expressing the output driver. signal integrity of line drivers, such as spurious-free dynamic Z is the line impedance. 2 range (SFDR), single-tone harmonic distortion or THD, two- N is the transformer turns ratio. tone intermodulation distortion (IMD), and third-order inter- Figure 45 shows the dynamic headroom in each subband of a cept (IP3) become significantly less meaningful when amplifiers downstream DMT waveform vs. turns ratio running at 100% are required to drive DMT and other heavily modulated and 60% of the quiescent power while maintaining −65 dBc waveforms. A typical xDSL downstream DMT signal may of MTPR at V = ±12 V. contain as many as 256 carriers (subbands or tones) of QAM S signals. MTPR is the relative difference between the measured 4 VS = ±12V PWDN1, PWDN0 = (1,1) power in a typical subband (at one tone or carrier) vs. the power at another subband specifically selected to contain no QAM 3 dopatean. Ionr ovtohider o wf oinrtdesn, tai osnelaelc pteodw seur b(bwainthdo (uotr a t oQnAeM) r esmiganianls) , OM (dB) 2 PVWS =D N±111, .P4WVDN0 = (1,1) O yielding an empty frequency bin. MTPR, sometimes referred ADR 1 PVWS =D N±112, VPWDN0 = (1,0) to as the empty bin test, is typically expressed in dBc, similar E H to expressing the relative difference between single-tone MIC A 0 fundamentals and second or third harmonic distortion YN VS = ±11.4V components. D PWDN1, PWDN0 = (1,0) –1 –21.0 1.1 1.2 D1O.3WNS1T.4REA1M.5 TUR1N.6S RA1T.7IO 1.8 1.9 2.0 01019-045 Figure 45. Dynamic Headroom vs. XFMR Turns Ratio, VS = ±12 V Rev. C | Page 16 of 20

Data Sheet AD8016 Once an optimum turns ratio is determined, the amplifier has The situation is more complicated with a complex modulated an MTPR performance for each setting of the power-down signal. In the case of a DMT signal, taking the equivalent sine pins. Table 8 demonstrates the effects of reducing the total wave power overestimates the power dissipation by ~23%. For power dissipated by using the PWDN pins on MTPR perfor- example: mance when driving 20.4 dBm downstream onto the line with P = 23.4 dBm = 220 mW OUT a transformer turns ratio of 1:1.4. V @ 50 Ω = 3.31 V rms OUT Table 8. Dynamic Power Dissipation of Downstream V = 2.354 V OUT Transmission at each amplifier output, which yields a P of 1.81 W. PWDN1 PWDN0 PD (W) MTPR D 1 1 1.454 −78 dBc Through measurement, a DMT signal of 23.4 dBm requires 1 0 1.262 −75.3 dBc 1.47 W of power to be dissipated by the AD8016. Figure 46 0 1 1.142 −57.2 dBc shows the results of calculation and actual measurements 01 0 0.120 N/A detailing the relationship between the power dissipated by the AD8016 vs. the total output power delivered to the back 1 This mode is quiescent power dissipation. termination resistors and the load combined. A 1:2 transformer GENERATING DMT turns ratio was used in the calculations and measurements. At this time, DMT modulated waveforms are not typically 2.5 menu selectable items contained within arbitrary waveform generators. Even using AWG software to generate DMT signals, 2.0 AWGs that are available today may not deliver DMT signals CALCULATED N sufficient in performance with regard to MTPR due to limita- TIO tions in the DAC and output drivers used by AWG manufacturers. PA1.5 Similar to evaluating single-tone distortion performance of an DISSI MEASSINUERED amplifier, MTPR evaluation requires a DMT signal generator ER 1.0 MEASURED W DMT capable of delivering MTPR performance better than that of O P the driver under evaluation. 0.5 POWER DISSIPATION Tito i sp irmoppeorrltya snitz teo t hcoe nhseiadte sri tnhkei ntogt aarl epao fwoer rt hdeis usispeart’si oanp polfi ctahtei on, 00 1O00UTPUT POWER (m2W00) 300 01019-046 AD8016. The dc power dissipation for VIN = 0 V is IQ (VCC − Figure 46. Power Dissipation vs. Output Power (Including Back V ), or 2 × I × V. Terminations), See Figure 9 for Test Circuit EE Q S For the AD8016 powered on +12 V and −12 V supplies (±V), S the number is 0.6 W. In a differential driver circuit (Figure 41), one can use symmetry to simplify the computation for a dc input signal. V P =2×I ×V +4×(V −V ) OUT D Q S S OUT R L where: V is the peak output voltage of an amplifier. OUT This formula is slightly pessimistic due to the fact that some of the quiescent supply current is commutated during sourcing or sinking current into the load. For a sine wave source, integra- tion over a half cycle yields 4V V V 2 P =2×I ×V +2 OUT S − OUT  D Q S  πRL RL  Rev. C | Page 17 of 20

AD8016 Data Sheet THERMAL ENHANCEMENTS AND PCB LAYOUT AIR FLOW TEST CONDITIONS There are several ways to enhance the thermal capacity of the DUT Power CO solution. Additional thermal capacity can be created using A typical DSL DMT signal produces about 1.5 W of power enhanced PCB layout techniques such as interlacing (some- dissipation in the AD8016 package. The fully biased (PWDN0 times referred to as stitching or interconnection) of the layers and PWDN1 = Logic 1) quiescent current of the AD8016 is immediately beneath the line driver. This technique serves to ~25 mA. A 1 MHz differential sine wave at an amplitude of increase the thermal mass or capacity of the PCB immediately 8 V p-p/amplifier into an R of 100 Ω differential (50 Ω LOAD beneath the driver. The AD8016 in a TSSOP_EP (ARE model) per side) produces the 1.5 W of power typical in the AD8016 package can be designed to operate in the CO solution using device. (See the Power Dissipation section for details.) prudent measures to manage the power dissipation through Thermal Resistance careful PCB design. The ARE package is available for use in designing the highest density CO solutions. Maximum heat The junction-to-case thermal resistance (θJC) of the AD8016 transfer to the PCB can be accomplished using the ARE ARB or SOIC_W_BAT package is 8.6°C/W and for the AD8016 package when the thermal slug is soldered to an exposed ARE or TSSOP_EP it is 5.6°C/W. These package specifications copper pad directly beneath the AD8016. Optimum thermal were used in this study to determine junction temperature performance can be achieved in the ARE package only when based on the measured case temperature. the back of the package is soldered to a PCB designed for PCB Dimensions of a Differential Driver Circuit maximum thermal capacity (see Figure 48). Thermal experi- Several components are required to support the AD8016 in a ments with the ARE package were conducted without soldering differential driver circuit. The PCB area necessary for these the heat slug to the PCB. Heat transfer was through physical components (that is, feedback and gain resistors, ac-coupling contact only. The following offers some insight into the AD8016 and decoupling capacitors, termination and load resistors) power dissipation and relative junction temperature, as well as dictated the area of the smallest PCB in this study, 4.7 square the effects of PCB size and composition on the junction-to-air inches. Further reduction in PCB area, although possible, has thermal resistance or θ . JA consequences in terms of the maximum operating junction THERMAL TESTING temperature method of thermal enhancement.) A cooling fan that draws moving air over the PCB and xDSL drivers, while A wind tunnel study was conducted to determine the relation- not always required, may be useful in reducing the operating ship between thermal capacity (that is, printed circuit board temperature. copper area), air flow, and junction temperature. Junction-to- ambient thermal resistance, θ , was also calculated for the JA AD8016 ARE and AD8016 ARB packages. The AD8016 was operated in a noninverting differential driver configuration, typical of an xDSL application yet isolated from any other modem components. Testing was conducted using a 1 oz. copper board in an ambient temperature of ~24°C over air flows of 200, 150, 100, and 50 linear feet per minute (LFM) (0.200 and 400 for AD8016 ARE) and for the ARB packages as well as in still air. The 4-layer PCB was designed to maximize the area of copper on the outer two layers of the board, while the inner layers were used to configure the AD8016 in a differential driver circuit. The PCB measured 3 inches × 4 inches in the beginning of the study and was progressively reduced in size to approximately 2 inches × 2 inches. The testing was performed in a wind tunnel to control airflow in units of LFM. The tunnel is approximately 11 inches in diameter. Rev. C | Page 18 of 20

Data Sheet AD8016 EXPERIMENTAL RESULTS 35 ARB 0 LFM The experimental data suggests that for both packages, and ARB 50 LFM a PCB as small as 4.7 square inches, reasonable junction 30 ARB 100 LFM temperatures can be maintained even in the absence of air flow. The graph in Figure 47 shows junction temperature vs. W)25 airflow for various dimensions of 1 oz. copper PCBs at an C/ ambient temperature of 24°C in the ARB package. For the (°A ARB 150 LFM ARB 200 LFM θJ20 worst-case package, the AD8016 ARB and the worst-case PCB at 4.7 square inches, the extrapolated junction temperature for an ambient environment of 85°C would be approximately 15 132°C with 0 LFM of airflow. If the target maximum junction temperature of the AD8016 ARB is 125°C, a 4-layer PCB with 1in oczh.e cso ips preeqr uciorveedr iwnigt ht h0e L oFuMte ro lfa ayierr fsl oanwd. measuring 9 square 104 P7CB AREA (SQ-IN) 10 01019-048 Figure 48. Junction-to-Ambient Thermal Resistance vs. PCB Area Note that the AD8016 ARE is targeted at xDSL applications 50 other than full-rate CO ADSL. The AD8016 ARE is targeted 45 at g.lite and other xDSL applications where reduced power dissipation can be achieved through a reduction in output 40 power. Extreme temperatures associated with full-rate ADSL using the AD8016 ARE should be avoided whenever possible. W) 35 ARE 0 LFM 75 ARB 4.7 SQ-IN +24°C AMBIENT θ (°C/JA30 ARE 200 LFM 70 ARB 6 SQ-IN 25 ARE 400 LFM C) E (°65 20 R ATU ARB 7.125 SQ-IN 15 R60 E ARB 9 SQ-IN N TEMP55 100 1 2 3 PC4B ARE5A (SQ6-IN) 7 8 9 10 01019-049 O Figure 49. Junction-to-Ambient Thermal Resistance vs. PCB Area CTI50 N U J 45 400 50 AIR FL1O0W0 (LFM) 150 200 01019-047 Figure 47. Junction Temperature vs. Air Flow Rev. C | Page 19 of 20

AD8016 Data Sheet OUTLINE DIMENSIONS 15.60 15.20 24 13 7.60 7.40 10.65 1 12 10.00 PIN 1 2.65 00..7255 45° 2.35 00..3100 1B.S2C7 00..5313 SPELAANTIENG 00..3223 80°° 10..2470 COMPLIANT WITH JEDEC STANDARDS MS-013-AD Figure 50. 24-Lead Batwing SOIC, Thermally Enhanced w/Fused Leads [SOIC_W_BAT] (RB-24) Dimensions shown in millimeters 9.80 3.55 9.70 3.50 9.60 3.45 28 15 4.50 6.40 EXPOSED 3.05 4.40 BSC PAD 3.00 4.30 (Pins Up) 2.95 1 14 TOP VIEW BOTTOM VIEW 1.05 1.20 MAX 1.00 8° FOR PROPER CONNECTION OF 0.80 0° THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND 00..1055 SEATING 0.65 BSC 0.30 00..2009 0.75 FSUECNCTITOION NO DF ETSHCISR IDPATTIOAN SSHEET. PLANE 0.19 0.60 COPLANARITY 0.45 0.10 COMPLIANTTO JEDEC STANDARDS MO-153-AET 02-23-2012-A Figure 51. 28-Lead Thin Shrink Small Outline With Exposed Pad [TSSOP_EP] (RE-28-1) Dimensions shown in millimeters ORDERING GUIDE Model1 Temperature Range Package Description Package Option AD8016ARBZ −40°C to +85°C 24-Lead SOIC_W_BAT RB-24 AD8016ARBZ-REEL −40°C to +85°C 24-Lead SOIC_W_BAT RB-24 AD8016AREZ −40°C to +85°C 28-Lead TSSOP_EP RE-28-1 AD8016AREZ-REEL −40°C to +85°C 28-Lead TSSOP_EP RE-28-1 AD8016AREZ-REEL7 −40°C to +85°C 28-Lead TSSOP_EP RE-28-1 1 Z = RoHS Compliant Part. ©2012 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D01019-0-3/12(C) Rev. C | Page 20 of 20