Dual 350 MHz Low Power Amplifier AD8012* FEATURES FUNCTIONAL BLOCK DIAGRAM Low Power 1.7 mA/Amplifier Supply Current Fully Specified for (cid:1)5 V and +5 V Supplies OUT1 1 8 +VS High Output Current, 125 mA –IN1 2 7 OUT2 High Speed +IN1 3 6 –IN2 350 MHz, –3 dB Bandwidth (G = +1) 150 MHz, –3 dB Bandwidth (G = +2) –VS 4 AD8012 5 +IN2 2,250 V/(cid:2)s Slew Rate 20 ns Settling Time to 0.1% Low Distortion –72dBc Worst Harmonic @ 500kHz, R = 100(cid:3) L –66dBc Worst Harmonic @ 5MHz, R = 1k(cid:3) L Good Video Specifications (R = 1 k(cid:3), G = +2) L 0.02% Differential Gain Error 0.06(cid:4) Differential Phase Error Gain Flatness 0.1 dB to 40 MHz 60 ns Overdrive Recovery Low Offset Voltage, 1.5 mV –40 Low Voltage Noise, 2.5 nV/√Hz G = +2 Available in 8-Lead SOIC and 8-Lead MSOP VOUT = 2V p-p –50 RF = 750(cid:3) APPLICATIONS XDSL, HDSL Line Drivers Bc ADC Buffers N – d–60 Professional Cameras RTIO THIRD CCD Imaging Systems TO–70 Ultrasound Equipment DIS Digital Cameras –80 SECOND PRODUCT DESCRIPTION The AD8012 is a dual, low power, current feedback amplifier –90 capable of providing 350 MHz bandwidth while using only 10 100 1k 1.7 mA per amplifier. It is intended for use in high frequency, RL – (cid:3) wide dynamic range systems where low distortion and high Figure 1.Distortion vs. Load Resistance, VS = ±5V, speed are essential and low power is critical. Frequency = 500 kHz With only 1.7 mA of supply current, the AD8012 also offers +VS exceptional ac specifications such as 20 ns settling time and 2,250 V/µs slew rate. The video specifications are 0.02% differ- + R1 AMP 1 + ential gain and 0.06 degree differential phase, excellent for such a low power amplifier. In addition, the AD8012 has a low offset of 1.5mV. VIN VREF ROLR = 100(cid:3) VOUT LPIONWEER 135(cid:3) IN dB The AD8012 is well suited for any application that requires high performance with minimal power. R2 – – Np:Ns The product is available in standard 8-lead SOIC or MSOP TRANSFORMER packages and operates over the industrial temperature range –VS –40°C to +85°C. Figure 2.Differential Drive Circuit for XDSL Applications *Protected under U.S. Patent Number 5,537,079. REV.B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. under any patent or patent rights of Analog Devices. Trademarks and Tel: 781/329-4700 www.analog.com registered trademarks are the property of their respective owners. Fax: 781/326-8703 © 2003 Analog Devices, Inc. All rights reserved.

AD8012–SPECIFICATIONS DUAL SUPPLY (@ T = 25(cid:4)C, V = (cid:1)5V, G = +2, R = 100 (cid:3), R = R = 750 (cid:3), unless otherwise noted.) A S L F G Parameter Conditions Min Typ Max Unit DYNAMIC PERFORMANCE –3 dB Small Signal Bandwidth G = +1, V < 0.4 V p-p, R = 1 kΩ 270 350 MHz OUT L G=+2, V < 0.4 V p-p, R = 1 kΩ 95 150 MHz OUT L G=+2, V < 0.4 V p-p, R = 100 Ω 90 MHz OUT L 0.1 dB Bandwidth V < 0.4 V p-p, R = 1 kΩ/100Ω 40/23 MHz OUT L Large Signal Bandwidth V = 4 V p-p 75 MHz OUT Slew Rate V = 4 V p-p 2,250 V/µs OUT Rise and Fall Time V = 2 V p-p 3 ns OUT Settling Time 0.1%, V = 2 V p-p 20 ns OUT 0.02%, V = 2 V p-p 35 ns OUT Overdrive Recovery 2(cid:1) Overdrive 60 ns NOISE/HARMONIC PERFORMANCE Distortion V = 2 V p-p, G = +2 OUT Second Harmonic 500 kHz, R = 1 kΩ/100 Ω –89/–73 dBc L 5 MHz, R = 1 kΩ/100 Ω –78/–62 dBc L Third Harmonic 500 kHz, R = 1 kΩ/100 Ω –84/–72 dBc L 5 MHz, R = 1 kΩ/100 Ω –66/–52 dBc L Output IP3 500 kHz, ∆f = 10 kHz, R = 1 kΩ/100 Ω 30/40 dBm L IMD 500 kHz, ∆f = 10 kHz, R = 1 kΩ/100 Ω –79/–77 dBc L Crosstalk 5 MHz, R = 100 Ω –70 dB L Input Voltage Noise f = 10 kHz 2.5 nV/√Hz Input Current Noise f = 10 kHz,+Input, –Input 15 pA/√Hz Differential Gain f = 3.58 MHz, R = 150 Ω/1kΩ, G = +2 0.02/0.02 % L Differential Phase f = 3.58 MHz, R = 150 Ω/1kΩ, G = +2 0.3/0.06 Degrees L DC PERFORMANCE Input Offset Voltage ±1.5 ±4 mV T –T ±5 mV MIN MAX Open-Loop Transimpedance V = ±2 V, R = 100 Ω 240 500 kΩ OUT L T –T 200 kΩ MIN MAX INPUT CHARACTERISTICS Input Resistance +Input 450 kΩ Input Capacitance +Input 2.3 pF Input Bias Current +Input, –Input ±3 ±12 µA +Input, –Input, T –T ±15 µA MIN MAX Common-Mode Rejection Ratio V = ±2.5 V –56 –60 dB CM Input Common-Mode Voltage Range ±3.8 ±4.1 V OUTPUT CHARACTERISTICS Output Resistance G = +2 0.1 Ω Output Voltage Swing ±3.85 ±4 V Output Current T –T 70 125 mA MIN MAX Short-Circuit Current 500 mA POWER SUPPLY Supply Current/Amp 1.7 1.8 mA T –T 1.9 mA MIN MAX Operating Range Dual Supply ±1.5 ±6.0 V Power Supply Rejection Ratio –58 –60 dB Specifications subject to change without notice. –2– REV. B

AD8012 SINGLE SUPPLY (@ T = 25(cid:4)C, V = +5V, G = +2, R = 100 (cid:3), R = R = 750 (cid:3), unless otherwise noted.) A S L F G Parameter Conditions Min Typ Max Unit DYNAMIC PERFORMANCE –3 dB Small Signal Bandwidth G = +1, V < 0.4 V p-p, R = 1 kΩ 220 300 MHz OUT L G=+2, V < 0.4 V p-p, R = 1 kΩ 90 140 MHz OUT L G=+2, V < 0.4 V p-p, R = 100 Ω 85 MHz OUT L 0.1 dB Bandwidth V < 0.4 V p-p, R = 1 kΩ/100Ω 43/24 MHz OUT L Large Signal Bandwidth V = 2 V p-p 60 MHz OUT Slew Rate V = 3 V p-p 1,200 V/µs OUT Rise and Fall Time V = 2 V p-p 2 ns OUT Settling Time 0.1%, V = 2 V p-p 25 ns OUT 0.02%, V = 2 V p-p 40 ns OUT Overdrive Recovery 2(cid:1) Overdrive 60 ns NOISE/HARMONIC PERFORMANCE Distortion V = 2 V p-p, G = +2 OUT Second Harmonic 500 kHz, R = 1 kΩ/100 Ω –87/–71 dBc L 5 MHz, R = 1 kΩ/100 Ω –77/–61 dBc L Third Harmonic 500 kHz, R = 1 kΩ/100 Ω –89/–72 dBc L 5 MHz, R = 1 kΩ/100 Ω –78/–52 dBc L Output IP3 500 kHz, R = 1 kΩ/100 Ω 30/40 dBm L IMD 500 kHz, R = 1 kΩ/100 Ω –77/–80 dBc L Crosstalk 5 MHz, R = 100 Ω –70 dB L Input Voltage Noise f = 10 kHz 2.5 nV/√Hz Input Current Noise f = 10 kHz,+Input, –Input 15 pA/√Hz Black Level Clamped to +2 V, f = 3.58 MHz Differential Gain R = 150 Ω/1 kΩ 0.03/0.03 % L Differential Phase R = 150 Ω/1 kΩ 0.4/0.08 Degrees L DC PERFORMANCE Input Offset Voltage ±1 ±3 mV T –T ±4 mV MIN MAX Open-Loop Transimpedance V = 2 V p-p, R = 100 Ω 200 400 kΩ OUT L T –T 150 kΩ MIN MAX INPUT CHARACTERISTICS Input Resistance +Input 450 kΩ Input Capacitance +Input 2.3 pF Input Bias Current +Input, –Input ±3 ±12 µA +Input, –Input, T –T ±15 µA MIN MAX Common-Mode Rejection Ratio V = 1.5 V to 3.5 V –56 –60 dB CM Input Common-Mode Voltage Range 1.5 to 3.5 1.2 to 3.8 V OUTPUT CHARACTERISTICS Output Resistance G = +2 0.1 Ω Output Voltage Swing 1 to 4 0.9 to 4.2 V Output Current T –T 50 100 mA MIN MAX Short-Circuit Current 500 mA POWER SUPPLY Supply Current/Amp 1.55 1.75 mA T –T 1.85 mA MIN MAX Operating Range Single Supply 3 12 V Power Supply Rejection Ratio –58 –60 dB Specifications subject to change without notice. REV. B –3–

AD8012 MAXIMUM POWER DISSIPATION 2.0 The maximum power that can be safely dissipated by the AD8012 is limited by the associated rise in junction temperature. The maxi- W TJ = 150(cid:4)C – mum safe junction temperature for plastic encapsulated devices N 1.5 8-LEAD SOIC O is determined by the glass transition temperature of the plastic, TI PACKAGE A approximately +150°C. Temporarily exceeding this limit may SIP S cstaruessese as sehxiefrt tiend poanr atmhee tdriiec bpye rtfhoerm paanckcaeg deu. eE xtoc eae dchinagn gae j uinn cthtieon ER DI1.0 W temperature of +175°C for an extended period can result in O P device failure. M 8-LEAD MU0.5 MSOP The output stage of the AD8012 is designed for maximum load XI A current capability. As a result, shorting the output to common M can cause the AD8012 to source or sink 500 mA. To ensure 0 proper operation, it is necessary to observe the maximum power –50–40–30–20–10 0 10 20 30 40 50 60 70 80 90 AMBIENT TEMPERATURE – (cid:4)C derating curves. Direct connection of the output to either power supply rail can destroy the device. Figure 3.Plot of Maximum Power Dissipation vs. Temperature for AD8012 Test Circuits 750(cid:3) 750(cid:3) 750(cid:3) 750(cid:3) VOUT VIN VOUT RL 53.6(cid:3) RL VIN 49.9(cid:3) 0.1(cid:2)F +10(cid:2)F +VS 0.1(cid:2)F +10(cid:2)F +VS 0.1(cid:2)F +10(cid:2)F 0.1(cid:2)F +10(cid:2)F –VS –VS Test Circuit 1.Gain = +2 Test Circuit 2.Gain = –1 –4– REV. B

AD8012 ABSOLUTE MAXIMUM RATINGS1 NOTES SupplyVoltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.6V 1Stresses above those listed under Absolute Maximum Ratings may cause perma- InternalPowerDissipation2 nent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational SOICPackage (R) . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.8W section of this specification is not implied. Exposure to absolute maximum rating MSOP Package (RM) . . . . . . . . . . . . . . . . . . . . . . . . 0.6 W conditions for extended periods may affect device reliability. Input Voltage (Common Mode) . . . . . . . . . . . . . . . . . . . . ±V 2Specification is for device in free air at +25°C. DifferentialInputVoltage . . . . . . . . . . . . . . . . . . . . . . .±2.5VS 8-Lead SOIC Package: (cid:2)JA = 155°C/W 8-Lead MSOP Package: (cid:2) = 200°C/W Output Short-Circuit Duration JA . . . . . . . . . . . . . . . . . . Observe Power Derating Curves Storage Temperature Range RM, R . . . . . . –65°C to +125°C Operating Temperature Range (A Grade) . . . –40°C to +85°C Lead Temperature Range (Soldering10sec) . . . . . . . . . 300°C CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD8012 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. ORDERING GUIDE Model Temperature Range Package Description Package Options Branding AD8012AR –40°C to +85°C 8-Lead SOIC R-8 AD8012AR-REEL –40°C to +85°C 13” Tape and Reel R-8 AD8012AR-REEL7 –40°C to +85°C 7” Tape and Reel R-8 AD8012ARM –40°C to +85°C 8-Lead MSOP RM-08 H6A AD8012ARM-REEL –40°C to +85°C 13” Tape and Reel RM-08 H6A AD8012ARM-REEL7 –40°C to +85°C 7” Tape and Reel RM-08 H6A AD8012ARMZ* –40°C to +85°C 8-Lead MSOP RM-08 H6A AD8012ARMZ-REEL* –40°C to +85°C 13” Tape and Reel RM-08 H6A AD8012ARMZ-REEL7* –40°C to +85°C 7” Tape and Reel RM-08 H6A *Z = Pb-free product. REV. B –5–

AD8012–Typical Performance Characteristics 20mV 5ns 1V 10ns TPC 1.100 mV Step Response; G = +2, V = ±2.5 V or TPC 4.4 V Step Response; G = –1, V = ±5 V, R = 1kΩ S S L ±5 V, R = 1kΩ* L 1V 10ns 20mV 5ns TPC 2.4 V Step Response; G = +2, V = ±5 V, R = 1kΩ TPC 5.100 mV Step Response; G = +2, V = ±2.5 V or S L S ±5 V, R = 100 Ω* L 20mV 5ns 500mV 10ns TPC 3.100 mV Step Response; G = –1, V = ±2.5 V TPC 6.2 V Step Response; G = +2, V = ±2.5 V, R = 100 Ω S S L or ±5 V, R = 1kΩ* L *V = ±2.5 V operation is identical to V = +5 V single-supply operation. S S –6– REV. B

AD8012 1V 10ns 1V 10ns TPC 7.4 V Step Response; G = +2, VS = ±5 V, RL = 100 Ω TPC 10.4 V Step Response; G = –1, VS = ±5 V, RL = 100 Ω –40 G = +2 VOUT = 2V p-p –50 RF = 750(cid:3) c B – d–60 N O TI TOR–70 THIRD S DI –80 SECOND 20mV 5ns –90 10 100 1k RL – (cid:3) TPC 8.100 mV Step Response; G = –1, V = ±2.5 V TPC 11.Distortion vs. Load Resistance; V = ±5 V, S S or ±5 V, R = 100 Ω* Frequency = 500 kHz L –40 THIRD RL = 100(cid:3) SECOND c–60 RL = 100(cid:3) B d (cid:5) N O ORTI RTHL I=R D1k(cid:3) ST–80 DI SECOND G = +2 RL = 1k(cid:3) VOUT = 2V p-p RF = 750(cid:3) 500mV 10ns –100 1 10 20 FREQUENCY (cid:5) MHz TPC 9.2 V Step Response; G = –1, V = ±2.5 V, R = 100 Ω TPC 12.Distortion vs. Frequency; V = ±5 V S L S REV. B –7–

AD8012 0.5 0.5 0.4 G = +2 0.4 G = +2 VO = 0.3V p-p VO = 0.3V p-p 0.3 RF = 750(cid:3) 0.3 RF = 750(cid:3) B RL = 100(cid:3) B RL = 100(cid:3) (cid:5) d 0.2 VS = (cid:1)5V (cid:5) d 0.2 VS = +5V N N AI 0.1 AI 0.1 G G ED 0 ED 0 Z Z ALI–0.1 ALI –0.1 M M OR–0.2 OR –0.2 N N –0.3 –0.3 –0.4 –0.4 –0.5 –0.5 0.1 1 10 100 0.1 1 10 100 FREQUENCY (cid:5) MHz FREQUENCY (cid:5) MHz TPC 13.Gain Flatness; V = ±5 V TPC 16.Gain Flatness; V = +5 V S S –40 5 GVO =U T+ 2= 2V p-p 4 VROF == 705.30V(cid:3) p-p –50 RF = 750(cid:3) 3 RL = 100(cid:3) SECOND B VS = (cid:1)5V Bc (cid:5) d 2 N – d–60 GAIN 1 TIO ED 0 R Z DISTO–70 THIRD ORMALI ––12 G = +10 G = +1 N G = +2 –80 –3 –4 –90 –5 10 100 1k 1 10 100 500 RL – (cid:3) FREQUENCY (cid:5) MHz TPC 14.Distortion vs. Load Resistance; V = +5 V, TPC 17.Frequency Response; V = ±5 V S S Frequency = 500 kHz –40 9 THIRD G = +2 RL = 100(cid:3) 6 RF = 750(cid:3) V 3 1V RMS VRSL == (cid:1)1050V(cid:3) Bc –60 (cid:5) dB 0 – d SECOND GE –3 DISTORTION –80 RSEL C=O 1Nk(cid:3)D RL = 100(cid:3) TPUT VOLTA–––1962 U O G = +2 –15 THIRD VOUT = 2V p-p RL = 1k(cid:3) RF = 750(cid:3) –18 –100 –21 1 10 20 1 10 100 500 FREQUENCY – MHz FREQUENCY (cid:5) MHz TPC 15.Distortion vs. Frequency; VS = +5 V TGP =C +128,. RO u=t p10u0t VΩoltage vs. Frequency; VS = ±5 V, L –8– REV. B

AD8012 0 0 ––2100 VVISN == (cid:1)05.2VV, p+5-pV ––1200 RVGSF = == + +72550V(cid:3) OR (cid:1)5V –PSRR –30 –30 +PSRR B–40 B –40 (cid:5) R d–50 R – d –50 R R M S C–60 P –60 –70 –70 –80 –80 –90 –90 –100 –100 0.03 0.1 1 10 100 500 100k 1M 10M 100M 500M FREQUENCY – MHz FREQUENCY – Hz TPC 19.CMRR vs. Frequency; VS = ±5 V, +5 V TPC 22.PSRR vs. Frequency; VS = ±5 V, +5 V 5 1k 4 VROF == 705.30V(cid:3) p-p B 3 VRSL == +150V0(cid:3) (cid:3)100 GRF = = + 7250(cid:3) (cid:5) AIN d 21 (cid:5)NCE 10 G A ORMALIZED ––102 G = +10 G = +1 TPUT RESIST 1 VS = +5V VS = (cid:1)5V N G = +2 OU –3 0.1 –4 –5 0.01 1 10 100 500 0.03 0.1 1 10 100 500 FREQUENCY – MHz FREQUENCY – MHz TPC 20.Frequency Response; VS = +5 V TPC 23.Output Resistance vs. Frequency 3 135 0 1VRMS G = +2 –03 RRFL == 715000(cid:3)(cid:3) 115 –40 V VS = +5V dB –6 95 PHASE –80 (cid:5)T VOLTAGE ––1–1592 (cid:5) (cid:3)T dB Z7555 TZ(s) ––112600 ASE – Degrees U H P P UT–18 35 –200 O –21 15 –240 –24 –27 –5 –280 1 10 100 500 1k 10k 100k 1M 10M 100M 1G FREQUENCY (cid:5) MHz FREQUENCY (cid:5) Hz TPC 21.Output Voltage vs. Frequency; VS = +5 V, TPC 24. Open-Loop Transimpedance and G = +2, RL = 100 Ω Phase vs. Frequency REV. B –9–

AD8012 9 V G = +2 8 (cid:1)5V DI RF = 750(cid:3) %/ RL = 100(cid:3) 7 0.1 2V STEP – 6 R p O p- R V 5 R G – +5V E E N 4 G SWI LTA 3 O V T 2 U P T 1 OU 0.1% 5ns 0 10 100 1k 10k LOAD – (cid:3) t = 0 TPC 25.Output Swing vs. Load TPC 28.Settling Time, V = ±5 V S 4.0 30 5 3.8 28 4 RVOF == 705.30V(cid:3) p-p Hz 3.6 26 Hz 3 RL = 1k(cid:3) OISE –nV/ 33..42 2242 OISE – pA/ (cid:5)GAIN dB 21 GE N 3.0 20 NT N ZED 0 G = +1 UT VOLTA 22..86 CURR+IENN/–TI NNOISE 1186 UT CURRE NORMALI ––12 G = +10 G = +2 NP 2.4 14 NP –3 I I 2.2 VOLTAGE NOISE 12 –4 2.0 10 –5 100 1k 10k 100k 1 10 100 500 FREQUENCY – Hz FREQUENCY – MHz TPC 26.Noise vs. Frequency TPC 29.Frequency Response; V = ±5 V S V 9 0.5 (cid:5)D) 8 RL = 1k(cid:3) 0.4 VO = 0.3V p-p H f = 5MHz G = +2 % T 7 G = (cid:6)2 0.3 RF = 750(cid:3) (cid:3)1 RF = 750(cid:3) B RL = 1k(cid:3) UT AT 5MHz ( 654 RL = 100(cid:3) ZED GAIN – d 00..210 TP ALI –0.1 OU 3 RM K O –0.2 A N E 2 P –0.3 O- K-T 1 –0.4 A PE 0 –0.5 3 4 5 6 7 8 9 10 11 0.1 1 10 100 TOTAL SUPPLY VOLTAGE (cid:5) V FREQUENCY – MHz TPC 27.Output Swing vs. Supply TPC 30.Gain Flatness; V = ±5 V S –10– REV. B

AD8012 –20 0.5 –30 DRIVER 0.4 VO = 0.3V p-p dB –40 VROL == 120V0 (cid:3)p-p 0.3 RRFL == 715k(cid:3)0(cid:3) – B OR –50 – d 0.2 R N FERRED ER –––867000 SIDE 1 ALIZED GAI–00..101 T RE –90 SIDE 2 ORM–0.2 U N P N–100 –0.3 I –110 –0.4 –120 –0.5 0.03 0.1 1 10 100 500 0.1 1 10 100 FREQUENCY – MHz FREQUENCY – MHz TPC 31.Crosstalk vs. Frequency TPC 33.Gain Flatness; VS = +5 V 5 4 VROF == 705.30V(cid:3) p-p 3 RL = 1k(cid:3) +3V B VOUT 0V d 2 (cid:5) AIN 1 VIN G 0V D 0 E Z G = +1 0V ALI –1 VIN M G = +10 0V NOR –2 G = +2 VOUT –3 –3V –4 VOUT, 2V/DIV 20ns –5 1 10 100 500 FREQUENCY – MHz TPC 32.Frequency Response; V = +5 V TPC 34.Overdrive Recovery;V = ±5 V, G = +2, S S R = 750Ω, R = 100Ω, V = 3 V p-p (T = 1µs) F L IN REV. B –11–

AD8012 THEORY OF OPERATION traditional single stage complementary devices. In addition, The AD8012 is a dual, high speed CF amplifier that attains new because the AD8012 is a CF amplifier, closed-loop BW variations levels of bandwidth (BW), power, distortion, and signal swing versus external gain variations (varying RN) will be much lower capability. Its wide dynamic performance (including noise) is compared to a VF op amp, where the BW varies inversely with the result of both a new complementary high speed bipolar gain. Another key attribute of this amplifier is its ability to run on process and a new and unique architectural design. The AD8012 a single 5 V supply partially because of its wide common-mode uses a two-gain stage complementary design approach versus input and output voltage range capability. For 5 V supply the traditional single-stage complementary mirror structure operation, the device consumes half the quiescent power (vs. sometimes referred to as the Nelson amplifier. Though twin 10V supply) with little degradation in its ac and dc perfor- stages have been tried before, they typically consumed high mance characteristics. See data sheet comparisons. power since they were of a folded cascade design, similar to that of the AD9617. This design allows for the standing or quiescent DC GAIN CHARACTERISTICS current to add to the high signal or slew current-induced stages. Gain stages A1/A1B and A2/A2B combined provide negative In the time domain, the large signal output rise/fall time and feedforward transresistance gain as shown in Figure 4. Stage A3 slew rate is typically controlled by the small signal BW of the is a unity-gain buffer that provides external load isolation to A2. amplifier and the input signal step amplitude, respectively, and Each stage uses a symmetrical complementary design (A3 is also not the dc quiescent current of the gain stages (with the excep- complementary though not explicitly shown). This is done to tion of input level shift diodes Q1/Q2). Using two stages versus reduce both second-order signal distortion and overall quiescent one also allows for a higher overall gain bandwidth product power as previously described. In the quasi dc to low frequency (GBWP) for the same power, resulting in lower signal distortion region, the closed-loop gain relationship can be approximated as: and the ability to drive heavier external loads. In addition, the G=1+R /R noninvertingoperation second-gain stage also isolates (divides down) A3’s input F N reflected load drive and the nonlinearities created, resulting in G =–RF/RN invertingoperation relatively lower distortion and higher open-loop gain. These basic relationships are common to all traditional opera- Overall, when high external load drive and low ac distortion is a tional amplifiers. requirement, a twin-gain stage integrating amplifier like the AD8012 will provide excellent results for lower power over the A1 CD Z1 = R1 || C1 IPP IPN Z1 –VI A2 IQ1 CP1 Q3 CP2 ICQ + IO IR + IFC Q1 (cid:1)VP (cid:2)VN ZI VOI A3 VO Z2 RL CL Q2 RF IE RN Q4 IR – IFC Z1 ICQ – IO IQ1 A2 –VI INP IPN CP1 AD8012 A1 CD Figure 4.Simplified Block Diagram –12– REV. B

AD8012 APPLICATIONS TO RECEIVER Line Driving for HDSL CIRCUITRY High bitrate digital subscriber line (HDSL) is becoming +5V popular as a means of providing full duplex data communication at 1/2 0.1(cid:2)F UP TO AD8012 12,000 FEET rates up to 1.544 MBPS or 2.048 MBPS over moderate distances + v(Eia1 c ionn Eveunrtoipoen)a lr eteqlueiprheso nreep tewaitsetresd e pveariry w3,i0re0s0. Tfereatd tioti o6n,0a0l 0T f1eet 7R50F(cid:3) 66.5(cid:3) to boost the signal strength and allow transmission over distances of up to 12,000 feet. In order to achieve repeaterless transmission 6V p-p 1.5kR(cid:3)G 7R50F(cid:3) 12V p-p 6V p-p 135(cid:3) over this distance, an HDSL modem requires a transmitted power level of 13.5 dBm (assuming a line impedance of 135 Ω). 66.5(cid:3) HDSL uses the two binary/one quaternary line code (2B1Q). – 0.1(cid:2)F 1:1 1:1 1/2 A sample 2B1Q waveform is shown in Figure 5. The digital bit AD8012 stream is broken up into groups of two bits. Four analog volt- –5V TO GAIN = +2 ages (called quaternary symbols) are used to represent the four RECEIVER CIRCUITRY possible combinations of two bits. These symbols are assigned the arbitrary names +3, +1, –1, and –3. The corresponding Figure 6.Differential for HDSL Applications voltage levels are produced by a DAC that is usually part of an The immediate effect of back-termination is that the signal from analog front end circuit (AFEC). Before being applied to the the amplifier is halved before being applied to the line. This line, the DAC output is low-pass filtered and acquires the sinu- doubles the power the amplifier must deliver. However, the soidal form shown in Figure 5. Finally, the filtered signal is back-termination resistors also play an important second role. applied to the line driver. The line voltages that correspond to Full-duplex data transmission systems like HDSL simulta- the quaternary symbols +3, +1, –1, and –3 are 2.64 V, 0.88 V, neously transmit data in both directions. As a result, the signal –0.88 V, and –2.64 V. This gives a peak-to-peak line voltage of on the line and across the back termination resistors is the 5.28 V. composite of the transmitted and received signal. The termina- tion resistors are used to tap off this signal and feed it to the SYMBOL NAME VOLTAGE DAC receive circuitry. Because the receive circuitry “knows” what is OUTPUT +3 2.64V being transmitted, the transmitted data can be subtracted from FILTERED the digitized composite signal to reveal the received data. OUTPUT TO LINE +1 0.88V DRIVER Driving a line with a differential signal offers a number of advantages compared to a single-ended drive. Because the two outputs are always 180 degrees out of phase relative to one –1 –0.88V another, the differential signal output is double the output amplitude of either of the op amps. As a result, the differential amplifier can have a peak-to-peak swing of 16 V (each op amp –3 –2.64V can swing to ±4 V), even though the power supply is ±5 V. –1 +3 +1 –3 –3 +1 +3 –3 –1 –1 +1 –1 –3 01 10 11 00 00 11 10 00 01 01 11 01 00 In addition, even-order harmonics (second, fourth, sixth, and Figure 5.Time Domain Representation of an HDSL Signal so on.) of the two single-ended outputs tend to cancel out one another, so the total harmonic distortion (quadratic sum of all Many of the elements of a classic differential line driver are harmonics) decreases compared to the single-ended case, even shown in the HDSL line driver in Figure 6. A 6 V peak-to-peak as the signal amplitude is doubled. This is particularly advan- differential signal is applied to the input. The differential gain of tageous in the case of the second harmonic. Because it is very the amplifier (1+2 R /R ) is set to +2, so the resulting differen- F G close to the fundamental, filtering becomes difficult. In this tial output signal is 12 V p-p. application, the THD is dominated by the third harmonic, As is normal in telephony applications, a transformer galvani- which is 65dB below the carrier (i.e., spurious-free dynamic cally isolates the differential amplifier from the line. In this case, range = –65dBc). a 1:1 turns ratio is used. In order to correctly terminate the line, Differential line driving also helps to preserve the integrity of the it is necessary to set the output impedance of the amplifier to be transmitted signal in the presence of electromagnetic interfer- equal to the impedance of the line being driven (135 Ω in this ence (EMI). EMI tends to induce itself equally onto both the case). Because the transformer has a turns ratio of 1:1, the positive and negative signal lines. As a result, a receiver with impedance reflected from the line is equal to the line impedance good common-mode rejection will amplify the original signal of 135 Ω (R = R /Turns Ratio2). As a result, two 66.5 Ω REFL LINE while rejecting induced (common-mode) EMI. resistors correctly terminate the line. REV. B –13–

AD8012 Choosing the Appropriate Turns Ratio for the Transformer The PCB should have a ground plane covering all unused Increasing the peak-to-peak output signal of the amplifier in the portions of the component side of the board to provide a low previous example and adding a variation in the turns ratio of the impedance ground path. The ground plane should be removed transformer can yield further enhancements to the circuit. The from the area near the input pins to reduce stray capacitance. output signal swing of the AD8012 can be increased to about Chip capacitors should be used for supply bypassing (see Figure 7). ±3.9 V before clipping occurs. This increases the peak-to-peak One end should be connected to the ground plane and the other output of the differential amplifier to 15.6 V. Because the signal within 1/8 inch of each power pin. An additional (4.7 µF to 10 µF) applied to the primary winding is now bigger, the transformer tantalum electrolytic capacitor should be connected in parallel. turns ratio of 1:1 can be replaced with a (step-down) turns ratio The feedback resistor should be located close to the inverting of about 1.3:1 (from amplifier to line). This steps the 7.8 V input pin in order to keep the stray capacitance at this node to peak-to-peak primary voltage down to 6 V. This is the same a minimum. Capacitance greater than 1.5 pF at the inverting secondary voltage of the earlier examples, so the resulting power input will significantly affect high speed performance when delivered to the line is the same. operating at low noninverting gains. The received signal, which is small relative to the transmitted Stripline design techniques should be used for long signal traces signal, will, however, be stepped up by a factor of 1.3. Amplifying (greater than about 1 inch). They should be designed with the the received signal in this manner enhances its signal-to-noise proper system characteristic impedance and be properly termi- ratio and is useful when the received signal is small compared to nated at each end. the to-be-transmitted signal. The impedance reflected from the 135 Ω line now becomes INVERTING CONFIGURATION 228 Ω (1.32 (cid:1) 135 Ω). With a correctly terminated line, the RG RF RO* amplifier must now drive a total load of 456 Ω (114 Ω + 114 Ω VIN VOUT + 228 Ω), considerably more than the original 270 Ω load. This RT +VS 10(cid:2)F reduces the drive current from the op amps by about 40%. + More significant, however, is the reduction in dynamic power 0.1(cid:2)F consumption—that is, the power the amplifier must consume in order to deliver the load power. Increasing the output signal so that it is as close as possible to the power rails minimizes the power consumed in the amplifier. There is, however, a price to pay in terms of increased signal *RO CHOSEN FOR CHARACTERISTIC IMPEDANCE. distortion. Increasing the output signal of each op amp from the original ±3 V to ±3.9 V reduces the spurious-free dynamic NONINVERTING CONFIGURATION range (SFDR) from –65 dB to –50 dB (measured at 500 kHz), RG RF RO* even though the overall load impedance has increased from VOUT 270Ω to 456Ω. LAYOUT CONSIDERATIONS VIN 0.1(cid:2)F The specified high speed performance of the AD8012 requires RT careful attention to board layout and component selection. 10(cid:2)F Table I shows recommended component values for the AD8012 + and Figures 8–13 show recommended layouts for the 8-lead –VS SOIC and MSOP packages for a positive gain. Proper RF design techniques and low parasitic component selections *RO CHOSEN FOR CHARACTERISTIC IMPEDANCE. are mandatory. Figure 7.Inverting and Noninverting Configurations Table I. Typical Bandwidth vs. Gain Setting Resistors Small Signal –3 dB BW (MHz), Gain R R R V = (cid:1)5 V, R = 1 k(cid:3) F G T S L –1 750 Ω 750 Ω 53.6 Ω 110 +1 750 Ω 49.9 Ω 350 +2 750 Ω 750 Ω 49.9 Ω 150 +10 750 Ω 82.5 Ω 49.9 Ω 40 RT chosen for 50 Ω characteristic input impedance. –14– REV. B

AD8012 Figure 8.Universal SOIC Noninverter Top Silkscreen Figure 11.Universal MSOP Noninverter Top Silkscreen Figure 9.Universal SOIC Noninverter Top Figure 12.Universal MSOP Noninverter Top Figure 10.Universal SOIC Noninverter Bottom Figure 13.Universal MSOP Noninverter Bottom REV. B –15–

AD8012 OUTLINE DIMENSIONS 8-Lead Standard Small Outline Package [SOIC] Narrow Body (R-8) Dimensions shown in millimeters and (inches) B) 5.00 (0.1968) 3( 0 4.80 (0.1890) 2/ 1 – 0 4.00 (0.1574) 8 5 6.20 (0.2440) 9– 3.80 (0.1497) 1 4 5.80 (0.2284) 04 1 0 C 1.27B (0S.C0500) 1.75 (0.0688) 00..5205 ((00..00109969))(cid:7) 45(cid:4) 0.25 (0.0098) 1.35 (0.0532) 0.10 (0.0040) 0.51 (0.0201) 8(cid:4) COPLANARITY 0.31 (0.0122) 0.25 (0.0098)0(cid:4) 1.27 (0.0500) 0.10 SEPALTAINNGE 0.17 (0.0067) 0.40 (0.0157) COMPLIANT TO JEDEC STANDARDS MS-012AA CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN 8-Lead Mini Small Outline Package [MSOP] (RM-8) Dimensions shown in millimeters 3.00 BSC 8 5 3.00 4.90 BSC BSC 1 4 PIN 1 0.65 BSC 0.15 1.10 MAX 0.00 0.80 0.38 0.23 80(cid:4)(cid:4) 0.60 0.22 0.08 0.40 COPLANARITY SEATING 0.10 PLANE COMPLIANT TO JEDEC STANDARDS MO-187AA Revision History Location Page 12/03—Data Sheet changed from REV. A to REV. B. Renumbered figures and TPCs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Universal Updated ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 Updated OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 –16– REV. B

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