Ultralow Distortion, High Speed Amplifiers AD8007/AD8008 FEATURES CONNECTION DIAGRAMS Extremely low distortion AD8007 Second harmonic NC 1 (Top View) 8 NC −88 dBc @ 5 MHz –IN 2 7 +VS −83 dBc @ 20 MHz (AD8007) +IN 3 6 VOUT −77 dBc @ 20 MHz (AD8008) –VS 4 5 NC Third harmonic −−9120 1d dBBc c@ @ 2 05 MMHHzz (AD8007) NC = NO CONNECT 02866-001 Figure 1. 8-Lead SOIC (R) −98 dBc @ 20 MHz (AD8008) High speed AD8007 VOUT 1 (Top View) 5 +VS 650 MHz, −3 dB bandwidth (G = +1) 1000 V/μs slew rate –VS 2 Lo2w. 7n noVis/e√ Hz input voltage noise +IN 3 4 –IN 02866-002 22.5 pA/√Hz input inverting current noise Figure 2. 5-Lead SC70 (KS) Low power: 9 mA/amplifier typical supply current AD8008 Wide supply voltage range: 5 V to 12 V VOUT1 1 (Top View) 8 +VS 0.5 mV typical input offset voltage –IN1 2 7 VOUT2 Small packaging: 8-lead SOIC, 8-lead MSOP, and 5-lead SC70 +IN1 3 6 –IN2 APPLICATIONS Instrumentation –VS 4 5 +IN2 02866-003 IF and baseband amplifiers Figure 3. 8-Lead SOIC (R) and 8-Lead MSOP (RM) Filters A/D drivers DAC buffers GENERAL DESCRIPTION The AD8007 is available in a tiny SC70 package as well as a standard 8-lead SOIC. The dual AD8008 is available in both an The AD8007 (single) and AD8008 (dual) are high performance 8-lead SOIC and an 8-lead MSOP. These amplifiers are rated to current feedback amplifiers with ultralow distortion and noise. work over the industrial temperature range of −40°C to +85°C. Unlike other high performance amplifiers, the low price and low quiescent current allow these amplifiers to be used in a –30 G = +2 wide range of applications. Analog Devices, Inc., proprietary –40 RVSL == ±155V0Ω second-generation eXtra-Fast Complementary Bipolar (XFCB) VOUT = 2V p-p process enables such high performance amplifiers with low power –50 consumption. Bc) –60 d Tvohleta AgeD n8o0i0s7e/, A−D838 d00B8 S hFaDvRe 6a5t 02 0M MHHz bz a(nAdDw8i0d0th7,) ,2 a.7n dn V−7/√7H dzB c RTION ( –70 O SECOND SFDR at 20 MHz (AD8008). ST –80 DI With the wide supply voltage range (5 V to 12 V) and wide –90 bandwidth, the AD8007/AD8008 are designed to work in a THIRD –100 variety of applications. The AD8007/AD8008 amplifiers have a low power supply current of 9 mA/amplifier. –1101 FREQUEN10CY (MHz) 10002866-004 Figure 4. AD8007 Second and Third Harmonic Distortion vs. Frequency Rev. E Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Tel: 781.329.4700 www.analog.com Trademarks and registered trademarks are the property of their respective owners. Fax: 781.461.3113 ©2002–2009 Analog Devices, Inc. All rights reserved.

AD8007/AD8008 TABLE OF CONTENTS Features .............................................................................................. 1  Typical Performance Characteristics ..............................................7  Applications ....................................................................................... 1  Theory of Operation ...................................................................... 15  Connection Diagrams ...................................................................... 1  Using the AD8007/AD8008 ...................................................... 15  General Description ......................................................................... 1  Layout Considerations ............................................................... 16  Revision History ............................................................................... 2  Layout And Grounding Considerations ...................................... 17  Specifications ..................................................................................... 3  Grounding ................................................................................... 17  V = ±5 V ....................................................................................... 3  Input Capacitance ...................................................................... 17  S V = 5 V .......................................................................................... 4  Output Capacitance ................................................................... 17  S Absolute Maximum Ratings ............................................................ 6  Input-to-Output Coupling ........................................................ 17  Maximum Power Dissipation ......................................................... 6  External Components and Stability ......................................... 17  Output Short Circuit ........................................................................ 6  Outline Dimensions ....................................................................... 18  ESD Caution .................................................................................. 6  Ordering Guide .......................................................................... 19  REVISION HISTORY 11/09—Rev. D to Rev. E 9/02—Rev. A to Rev. B Change to Output Capacitance Section ....................................... 17 Updated Outline Dimensions ....................................................... 19 Updated Outline Dimensions ....................................................... 18 Changes to Ordering Guide .......................................................... 19 8/02—Rev. 0 to Rev. A Added AD8008 .................................................................. Universal 6/03—Rev. C to Rev. D Added SOIC-8 (RN) and MSOP-8 (RM) ...................................... 1 Change to Layout Considerations Section .................................. 15 Changes to Features .......................................................................... 1 Deleted Figure 7 .............................................................................. 16 Changes to General Description .................................................... 1 Deleted Evaluation Board Section ................................................ 16 Changes to Specifications ................................................................ 2 Updated Outline Dimensions ....................................................... 16 Edits to Maximum Power Dissipation Section ............................. 4 New Figure 2 ..................................................................................... 4 10/02—Rev. B to Rev. C Changes to Ordering Guide ............................................................ 5 Connection Diagrams Captions Updated .................................... 1 New TPCs 19 to 24 and TPCs 27, 29, 30, and 35 .......................... 9 Ordering Guide Updated ................................................................ 5 Changes to Evaluation Board Section ......................................... 16 Figure 5 Edited ............................................................................... 14 MSOP-8 (RM) Added ................................................................... 19 Updated Outline Dimensions ....................................................... 19 Rev. E | Page 2 of 20

AD8007/AD8008 SPECIFICATIONS V = ±5 V S T = 25°C, R = 200 Ω, R = 150 Ω, R = 499 Ω, Gain = +2, unless otherwise noted. A S L F Table 1. AD8007/AD8008 Parameter Conditions Min Typ Max Unit DYNAMIC PERFORMANCE −3 dB Bandwidth G = +1, V = 0.2 V p-p, R = 1 kΩ 540 650 MHz O L G = +1, V = 0.2 V p-p, R = 150 Ω 250 500 MHz O L G = +2, V = 0.2 V p-p, R = 150 Ω 180 230 MHz O L G = +1, V = 2 V p-p, R = 1 kΩ 200 235 MHz O L Bandwidth for 0.1 dB Flatness V = 0.2 V p-p, G = +2, R = 150 Ω 50 90 MHz O L Overdrive Recovery Time ±2.5 V input step, G = +2, R = 1 kΩ 30 ns L Slew Rate G = +1, V = 2 V step 900 1000 V/μs O Settling Time to 0.1% G = +2, V = 2 V step 18 ns O Settling Time to 0.01% G = +2, V = 2 V step 35 ns O NOISE/HARMONIC PERFORMANCE Second Harmonic f = 5 MHz, V = 2 V p-p −88 dBc C O f = 20 MHz, V = 2 V p-p −83/−77 dBc C O Third Harmonic f = 5 MHz, V = 2 V p-p −101 dBc C O IMD f = 20 MHz, V = 2 V p-p −92/−98 dBc C O f = 19.5 MHz to 20.5 MHz, R = 1 kΩ, V = 2 V p-p −77 dBc C L O Third-Order Intercept f = 5 MHz, R = 1 kΩ 43.0/42.5 dBm C L f = 20 MHz, R = 1 kΩ 42.5 dBm C L Crosstalk (AD8008) f = 5 MHz, G = +2 −68 dB Input Voltage Noise f = 100 kHz 2.7 nV/√Hz Input Current Noise −Input, f = 100 kHz 22.5 pA/√Hz +Input, f = 100 kHz 2 pA/√Hz Differential Gain Error NTSC, G = +2, R = 150 Ω 0.015 % L Differential Phase Error NTSC, G = +2, R = 150 Ω 0.010 Degree L DC PERFORMANCE Input Offset Voltage 0.5 4 mV Input Offset Voltage Drift 3 μV/°C Input Bias Current +Input 4 8 μA −Input 0.4 6 μA Input Bias Current Drift +Input 16 nA/°C −Input 9 nA/°C Transimpedance V = ±2.5 V, R = 1 kΩ 1.0 1.5 MΩ O L R = 150 Ω 0.4 0.8 MΩ L INPUT CHARACTERISTICS Input Resistance +Input 4 MΩ Input Capacitance +Input 1 pF Input Common-Mode Voltage Range −3.9 to +3.9 V Common-Mode Rejection Ratio V = ±2.5 V 56 59 dB CM OUTPUT CHARACTERISTICS Output Saturation Voltage V − V , V − V , R = 1 kΩ 1.1 1.2 V CC OH OL EE L Short-Circuit Current, Source 130 mA Short-Circuit Current, Sink 90 mA Capacitive Load Drive 30% overshoot 8 pF Rev. E | Page 3 of 20

AD8007/AD8008 AD8007/AD8008 Parameter Conditions Min Typ Max Unit POWER SUPPLY Operating Range 5 12 V Quiescent Current per Amplifier 9 10.2 mA Power Supply Rejection Ratio +PSRR 59 64 dB −PSRR 59 65 dB V = 5 V S T = 25°C, R = 200 Ω, R = 150 Ω, R = 499 Ω, Gain = +2, unless otherwise noted. A S L F Table 2. AD8007/AD8008 Unit Parameter Conditions Min Typ Max DYNAMIC PERFORMANCE −3 dB Bandwidth G = +1, V = 0.2 V p-p, R = 1 kΩ 520 580 MHz O L G = +1, V = 0.2 V p-p, R = 150 Ω 350 490 MHz O L G = +2, V = 0.2 V p-p, R = 150 Ω 190 260 MHz O L G = +1, V = 1 V p-p, R = 1 kΩ 270 320 MHz O L Bandwidth for 0.1 dB Flatness V = 0.2 V p-p, G = +2, R = 150 Ω 72 120 MHz O L Overdrive Recovery Time 2.5 V input step, G = +2, R = 1 kΩ 30 ns L Slew Rate G = +1, V = 2 V step 665 740 V/μs O Settling Time to 0.1% G = +2, V = 2 V step 18 ns O Settling Time to 0.01% G = +2, V = 2 V step 35 ns O NOISE/HARMONIC PERFORMANCE Second Harmonic f = 5 MHz, V = 1 V p-p −96/−95 dBc C O f = 20 MHz, V = 1 V p-p −83/−80 dBc C O Third Harmonic f = 5 MHz, V = 1 V p-p −100 dBc C O f = 20 MHz, V = 1 V p-p −85/−88 dBc C O IMD f = 19.5 MHz to 20.5 MHz, R = 1 kΩ, −89/−87 dBc C L V = 1 V p-p O Third-Order Intercept f = 5 MHz, R = 1 kΩ 43.0 dBm C L f = 20 MHz, R = 1 kΩ 42.5/41.5 dBm C L Crosstalk (AD8008) Output-to-output, f = 5 MHz, G = +2 −68 dB Input Voltage Noise f = 100 kHz 2.7 nV/√Hz Input Current Noise −Input, f = 100 kHz 22.5 pA/√Hz +Input, f = 100 kHz 2 pA/√Hz DC PERFORMANCE Input Offset Voltage 0.5 4 mV Input Offset Voltage Drift 3 μV/°C Input Bias Current +Input 4 8 μA −Input 0.7 6 μA Input Bias Current Drift +Input 15 nA/°C −Input 8 nA/°C Transimpedance V = 1.5 V to 3.5 V, R = 1 kΩ 0.5 1.3 MΩ O L R = 150 Ω 0.4 0.6 MΩ L INPUT CHARACTERISTICS Input Resistance +Input 4 MΩ Input Capacitance +Input 1 pF Input Common-Mode Voltage Range 1.1 to 3.9 V Common-Mode Rejection Ratio V = 1.75 V to 3.25 V 54 56 dB CM Rev. E | Page 4 of 20

AD8007/AD8008 AD8007/AD8008 Unit Parameter Conditions Min Typ Max OUTPUT CHARACTERISTICS Output Saturation Voltage V − V , V − V , R = 1 kΩ 1.05 1.15 V CC OH OL EE L Short-Circuit Current, Source 70 mA Short-Circuit Current, Sink 50 mA Capacitive Load Drive 30% overshoot 8 pF POWER SUPPLY Operating Range 5 12 V Quiescent Current per Amplifier 8.1 9 mA Power Supply Rejection Ratio +PSRR 59 62 dB −PSRR 59 63 dB Rev. E | Page 5 of 20

AD8007/AD8008 ABSOLUTE MAXIMUM RATINGS RMS output voltages should be considered. If R is referenced to L Table 3. V, as in single-supply operation, then the total drive power is S Parameter Rating V × I . S OUT Supply Voltage 12.6 V If the rms signal levels are indeterminate, then consider the Power Dissipation See Figure 5 worst case, when V = V/4 for R to midsupply Common-Mode Input Voltage ±V OUT S L S Differential Input Voltage ±1.0 V ⎛V ⎞2 ⎜ S ⎟ Output Short-Circuit Duration See Figure 5 ⎝ 4 ⎠ P =(V ×I )+ Storage Temperature Range −65°C to +125°C D S S R L Operating Temperature Range −40°C to +85°C In single-supply operation, with R referenced to V, worst case is Lead Temperature (Soldering, 10 sec) 300°C L S V = V/2. OUT S Stresses above those listed under Absolute Maximum Ratings Airflow increases heat dissipation, effectively reducing θ . In may cause permanent damage to the device. This is a stress JA addition, more metal directly in contact with the package leads rating only; functional operation of the device at these or any from metal traces, through-holes, ground, and power planes other conditions above those indicated in the operational reduces the θ . Care must be taken to minimize parasitic section of this specification is not implied. Exposure to absolute JA capacitances at the input leads of high speed op amps, see the maximum rating conditions for extended periods may affect Layout Considerations section. device reliability. Figure 5 shows the maximum safe power dissipation in the MAXIMUM POWER DISSIPATION package vs. the ambient temperature for the SOIC-8 (125°C/W), The maximum safe power dissipation in the AD8007/AD8008 MSOP-8 (150°C/W), and SC70-5 (210°C/W) packages on a packages is limited by the associated rise in junction temperature JEDEC standard 4-layer board. θ values are approximations. JA (T) on the die. The plastic encapsulating the die locally reaches J 2.0 the junction temperature. At approximately 150°C, which is the glass transition temperature, the plastic changes its properties. W) Ethvee nst rteemssepso trhaaritl yth eex pceaecdkiangge tehxiesr ttesm onp etrhaet udriee ,l ipmeritm caanne cnhtlayn ge ATION ( 1.5 MSOP-8 P shifting the parametric performance of the AD8007/AD8008. SI SOIC-8 S Exceeding a junction temperature of 175°C for an extended DI R 1.0 time can result in changes in the silicon devices, potentially WE O causing failure. P M SC70-5 U The still-air thermal properties of the package and PCB (θJA), XIM 0.5 ambient temperature (TA), and the total power dissipated in the MA package (P ) determine the junction temperature of the die. D The jTuJn =c tTioAn + t e(PmDp ×er θaJtAu)r e can be calculated as 0–60 –40 –20AMBIE0NTTEM2P0ERATU4R0E (°C)60 80 100 02866-005 Figure 5. Maximum Power Dissipation vs. Temperature for a 4-Layer Board The power dissipated in the package (P ) is the sum of the D quiescent power dissipation and the power dissipated in the OUTPUT SHORT CIRCUIT package due to the load drive for all outputs. The quiescent Shorting the output to ground or drawing excessive current for power is the voltage between the supply pins (VS) times the the AD8007/AD8008 will likely cause catastrophic failure. quiescent current (I). Assuming the load (R ) is referenced to S L ESD CAUTION midsupply, the total drive power is V/2 × I , some of which is S OUT dissipated in the package and some in the load (V × I ). OUT OUT The difference between the total drive power and the load power is the drive power dissipated in the package. PD = Quiescent Power + (Total Drive Power − Load Power) ⎛V V ⎞ V 2 P =(V ×I )+⎜ S × OUT ⎟− OUT D S S ⎜⎝ 2 RL ⎟⎠ RL Rev. E | Page 6 of 20

AD8007/AD8008 TYPICAL PERFORMANCE CHARACTERISTICS V = ±5 V, R = 150 Ω, R = 200 Ω, R = 499 Ω, unless otherwise noted. S L S F 3 6.4 G = +2 2 6.3 1 G = +1 6.2 dB) 0 6.1 N ( G = +2 GAI –1 B)6.0 ED –2 N (d5.9 VS = +5V ALIZ –3 GAI5.8 M OR –4 5.7 VS = ±5V N G = +10 –5 5.6 G = –1 –6 5.5 –71 10FREQUENCY (MHz)100 1000 02866-006 5.410 FREQUE1N0C0Y (MHz) 1000 02866-009 Figure 6. Small Signal Frequency Response for Various Gains Figure 9. 0.1 dB Gain Flatness; VS = +5, VS = ±5 V 3 9 G = +1 G = +2 2 8 1 RL = 1kΩ, VS = ±5V 7 RL = 1kΩ, VS = +5V 0 6 –1 5 B) B) AIN (d –2 RL = 150kΩ, VS = ±5V AIN (d 4 RVSL == 1+550VkΩ, G –3 G 3 –4 2 RL = 150kΩ, VS = ±5V –5 RL = 150kΩ, VS = 5V 1 RL = 1kΩ, VS = ±5V –6 0 –710 FREQUE1N0C0Y (MHz) 1000 02866-007 –110 FREQUE1N0C0Y (MHz) 1000 02866-010 Figure 7. Small Signal Frequency Response for VS and RL Figure 10. Small Signal Frequency Response for VS and RL 3 9 G = +1 G = +2 2 RL = 1kΩ 8 RF = RG = 324Ω 1 RS = 200Ω 7 RF = RG = 249Ω 0 6 –1 5 B) B) d d N ( –2 N ( 4 GAI –3 RS = 301Ω GAI 3 RF = RG = 499Ω RS = 249Ω –4 2 –5 1 RF = RG = 649Ω –6 0 –710 FREQUE1N0C0Y (MHz) 1000 02866-008 –110 FREQUE1N0C0Y (MHz) 1000 02866-011 Figure 8. Small Signal Frequency Response for Various RS Values Figure 11. Small Signal Frequency Response for Various Feedback Resistors, RF = RG Rev. E | Page 7 of 20

AD8007/AD8008 10 10M 90 G = +2 20pF 9 20pF AND 20pF AND 10Ω SNUB 1M 30 8 20Ω SNUB TRANSIMPEDANCE 0 7 Ω)100k –30 GAIN (dB) 654 499Ω SIMPEDANCE ( 101kk PHASE ––91050ASE (Degrees) 499Ω 0pF AN –180PH 3 RSNUB TR 100 –210 200Ω 2 CLOAD 49.9Ω 10 –270 1 0 1 10FREQUENCY (MHz)100 1000 02866-012 110k 100k F1MREQUENC1Y0 M(Hz) 100M 1G2G–330 02866-015 Figure 12. Small Signal Frequency Response for Figure 15. Transimpedance and Phase vs. Frequency Capacitive Load and Snub Resistor 3 9 G = +1 VS = +5V, +85°C G = +2 2 VS = ±5V, +85°C 8 1 7 VS = +5V, +85°C 0 6 N (dB) ––12 VS = +5V, –40°C N (dB) 54 VS = +5V, –40°C VS = ±5V, +85°C GAI –3 VS = ±5V, –40°C GAI 3 VS = ±5V, –40°C –4 2 –5 1 –6 0 –710 FREQUE1N0C0Y (MHz) 1000 02866-013 –110 FREQUE1N0C0Y (MHz) 1000 02866-016 Figure 13. Small Signal Frequency Response over Temperature, Figure 16. Small Signal Frequency Response over Temperature, VS = +5 V, VS = ±5 V VS = +5 V, VS = ±5 V 3 9 VOUT = 2V p-p G = +2 2 8 1 G = +1 G = +2 7 dB) 0 6 N ( GAI –1 B) 5 ED –2 G = +10 N (d 4 ALIZ –3 G = –1 GAI 3 RL = 150Ω,VS = ±5V,VO = 2V p-p M R RL = 1kΩ,VS = ±5V,VO = 2V p-p O –4 2 N RL = 150Ω,VS = +5V,VO = 1V p-p –5 1 RL = 1kΩ,VS = +5V,VO = 1V p-p –6 0 –71 10FREQUENCY (MHz)100 1000 02866-014 –110 FREQUE1N0C0Y (MHz) 1000 02866-017 Figure 14. Large Signal Frequency Response for Various Gains Figure 17. Large Signal Frequency Response for VS and RL Rev. E | Page 8 of 20

AD8007/AD8008 –40 –40 G = +1 G = +2 –50 VVSO == 51VV p-p HD2, RL = 150Ω –50 VVSO == 51VV p-p HD3, RL = 150Ω –60 –60 HD2, RL = 1kΩ DISTORTION (dBc) ––7800 HD3, RL = H1kDΩ2, RL = 1kΩ DISTORTION (dBc) ––7800 HD2, RL = 150Ω –90 –90 –100 –100 HD3, RL = 150Ω HD3, RL = 1kΩ –110 –1101 FREQUEN10CY (MHz) 100 02866-018 1 FREQUEN10CY (MHz) 100 02866-021 Figure 18. AD8007 Second and Third Harmonic Distortion vs. Frequency and RL Figure 21. AD8007 Second and Third Harmonic Distortion vs. Frequency and RL –40 –40 G = +1 G = +2 –50 VVSO == ±25VV p-p –50 VVSO == ±25VV p-p –60 –60 DISTORTION (dBc) ––7800 HD2, RL = 1kΩ HD3, RHL D=2 1, 5R0LΩ = 150Ω DISTORTION (dBc) ––7800 HD2, RL =H D1520, ΩRL = 1kΩ –90 –90 HD3, RL = 150Ω –100 HD3, RL = 1kΩ –100 HD3, RL = 1kΩ –1101 FREQUEN10CY (MHz) 100 02866-019 –1101 FREQUEN10CY (MHz) 100 02866-022 Figure 19. AD8007 Second and Third Harmonic Distortion vs. Frequency and RL Figure 22. AD8007 Second and Third Harmonic Distortion vs. Frequency and RL –30 –30 VS = ±5V G = +2 –40 VROL == 125V0 pΩ-p –40 VRSL == ±155V0Ω –50 HD2, G = +10 –50 HD3, VO = 4V p-p N (dBc) –60 HD3, G = +10 N (dBc) –60 HD2, VO = 4V p-p DISTORTIO ––7800 DISTORTIO ––7800 HD2, VO = 2V p-p HD3, G = +1 –90 –90 HD2, G = +1 –100 –100 HD3, VO = 2V p-p –1101 FREQUEN10CY (MHz) 100 02866-020 –1101 FREQUEN10CY (MHz) 100 02866-023 Figure 20. AD8007 Second and Third Harmonic Distortion vs. Frequency and Gain Figure 23. AD8007 Second and Third Harmonic Distortion vs. Frequency and VO Rev. E | Page 9 of 20

AD8007/AD8008 V = ±5 V, R = 200 Ω, R = 499 Ω, R = 150 Ω, @ 25°C, unless otherwise noted. S S F L –40 –40 G = 1 G = 2 –50 VVSO == 51VV p-p –50 VVSO == 51VV p-p –60 –60 N (dBc) –70 HD2, RL = 150Ω N (dBc) –70 HD2, RL = 150Ω O O ORTI –80 HD2, RL = 1kΩ ORTI –80 HD2, RL = 1kΩ T T S S DI DI –90 –90 HD3, RL = 1kΩ HD3, RL = 1kΩ –100 –100 HD3, RL = 150Ω HD3,RL = 150Ω –1101 FREQUE1N0CY (MHz) 100 02866-024 –1101 FREQUE1N0CY (MHz) 100 02866-027 Figure 24. AD8008 Second and Third Harmonic Distortion vs. Frequency and RL Figure 27. AD8008 Second and Third Harmonic Distortion vs. Frequency and RL –40 –40 G = 2 G = 1 –50 VVSO == 51VV p-p –50 VVSO == ±25VV p-p –60 –60 HD2, RL = 1kΩ DISTORTION (dBc) ––8700 HD2, RL =H 1Dk2Ω, RL = 150Ω DISTORTION (dBc) ––8700 HD2, RL = 150Ω –90 –90 HD3, RL = 1kΩ –100 –100 HD3, RL = 1kΩ HD3, RL = 150Ω HD3,RL = 150Ω –1101 FREQUE1N0CY (MHz) 100 02866-025 –1101 FREQUE1N0CY (MHz) 10002866-028 Figure 25. AD8008 Second and Third Harmonic Distortion vs. Frequency and RL Figure 28. AD8008 Second and Third Harmonic Distortion vs. Frequency and RL –30 –30 VS = ±5V G = 2 –40 RVOL == 125V0 pΩ-p –40 VRSL == ±155V0Ω –50 –50 Bc)–60 HD2, G = 10 Bc)–60 N (d N (d HD2, VO = 4V p-p RTIO–70 RTIO–70 HD2, VO = 2V p-p O O ST–80 ST–80 DI HD2, G = 1 DI –90 –90 HD3, VO = 4V p-p –100 –100 HD3, G = 10 HD3, G = 1 HD3, VO = 2V p-p –1101 FREQUE1N0CY (MHz) 100 02866-026 –1101 FREQUE1N0CY (MHz) 100 02866-029 Figure 26. AD8008 Second and Third Harmonic Distortion vs. Frequency and Gain Figure 29. AD8008 Second and Third Harmonic Distortion vs. Frequency and VO Rev. E | Page 10 of 20

AD8007/AD8008 –60 –65 G = +2 G = +2 –65 VFOS == 52V0MHz HD3, RL = 1kΩ –70 VFOS == ±250VMHz HD3, RL = 1kΩ –75 HD2, RL = 1kΩ HD2, RL = 150Ω Bc) –70 Bc) –80 d d RTION ( –75 HD3, RL = 150Ω RTION ( ––9805 HD2, RL = 1kΩ O O T T DIS –80 DIS –95 HD3, RL = 150Ω HD2, RL = 150Ω –100 –85 –105 –90 –110 1.0 1.5 VOUT (V p-p) 2.0 2.5 02866-030 1 2 3VOUT(V p-p4) 5 6 02866-033 Figure 30. AD8007 Second and Third Harmonic Distortion vs. VOUT and RL Figure 33. AD8007 Second and Third Harmonic Distortion vs. VOUT and RL 44 44 G = +2 G = +2 43 VS = ±5V 43 VS = ±5V VO = 2V p-p VO = 2V p-p Bm) 42 RL = 1kΩ Bm) 42 RL = 1kΩ d d PT ( 41 PT ( 41 E E C C ER 40 ER 40 T T N N R I 39 R I 39 E E D D OR 38 OR 38 D D- HIR 37 HIR 37 T T 36 36 35 5 10 15 20 25FR3E0QU3E5NC4Y0 (MH45z) 50 55 60 65 7002866-031 355 10 15 20 25 FR30EQU3E5NC4Y0 (M4H5z) 50 55 60 65 70 02866-034 Figure 31. AD8007 Third-Order Intercept vs. Frequency Figure 34. AD8008 Third-Order Intercept vs. Frequency –65 –65 G = +2 VS = 5V –70 HD2, RL = 1kΩ FO = 20MHz HD2, RL = 150Ω –70 HD2, RL = 1kΩ –75 HD2, RL = 150Ω Bc) Bc) –80 N (d –75 N (d –85 HD3, RL = 150Ω O O RTI RTI –90 HD3, RL = 1kΩ DISTO –80 HD3, RL = 150Ω DISTO –95 HD3, RL = 1kΩ –100 –85 G = +2 –105 VS = 5V FO = 20MHz –901.0 1.5 VOUT (V p-p) 2.0 2.5 02866-032 –1101 2 3VOUT (V p-p)4 5 6 02866-035 Figure 32. AD8008 Second and Third Harmonic Distortion vs. VOUT and RL Figure 35. AD8008 Second and Third Harmonic Distortion vs. VOUT and RL Rev. E | Page 11 of 20

AD8007/AD8008 V = ±5 V, R = 150 Ω, R = 200 Ω, R = 499 Ω, unless otherwise noted. S L S F 100 1000 SE (nV/Hz) SE (pA/ Hz) 100 INVERTING CURRENT NOISE 22.5pA/ Hz OI 10 OI N N GE NT LTA 2.7nV/ Hz RRE 10 O U V C NONINVERTING CURRENT NOISE 2.0pA/ Hz 110 100 FR1kEQUENCY 1(H0zk) 100k 1M 02866-036 110 100 1kFREQUE10NkCY (Hz)100k 1M 10M 02866-039 Figure 36. Input Voltage Noise vs. Frequency Figure 39. Input Current Noise vs. Frequency 1k –20 G = +2 G = +2 R = 150Ω –30 VS = ±5V 100 VM = 1V p-p –40 Ω) PEDANCE ( 10 TALK (dB) ––6500 SIDE B DRIVEN M S UT I 1 ROS –70 SIDE A DRIVEN P C T U O –80 0.1 –90 0.01 –100 100k 1M FREQU1E0NMCY (Hz) 100M 1G 02866-037 100k 1M FREQU1E0NMCY (Hz) 100M 1G 02866-040 Figure 37. Output Impedance vs. Frequency Figure 40. AD8008 Crosstalk vs. Frequency (Output to Output) 0 20 VS = ±5V, +5V 10 –10 0 –20 –10 B)–30 B)–20 MRR (d–40 SRR (d–30 +PSRR C P–40 –50 –50 –60 –PSRR –60 –70 –71000k 1M FREQU1E0NMCY (Hz) 100M 1G 02866-038 –8010k 100k F1RMEQUENCY 1(H0Mz) 100M 1G 02866-041 Figure 38. CMRR vs. Frequency Figure 41. PSRR vs. Frequency Rev. E | Page 12 of 20

AD8007/AD8008 G = +1 RL = 150Ω,VS = +5V AND ±5V G = +2 RL = 150Ω,VS = +5V AND ±5V RL = 150Ω,VS = +5V AND ±5V RL = 1kΩ,VS = +5V AND ±5V 50mV/DIV 50mV/DIV 0 10 20TIME (ns)30 40 5002866-042 0 10 20TIME (ns)30 40 5002866-045 Figure 42. Small Signal Transient Response for Figure 45. Small Signal Transient Response for RL = 150 Ω, RL = 1 kΩ and VS = +5 V, VS = ±5 V RL = 150 Ω, RL = 1 kΩ and VS = +5 V, VS = ±5 V G = +1 G = –1 RL = 150Ω INPUT RL = 1kΩ OUTPUT 1V/DIV 1V/DIV 0 10 20TIME (ns)30 40 5002866-043 0 10 20TIME (ns)30 40 50 02866-046 Figure 43. Large Signal Transient Response for RL = 150 Ω, RL = 1 kΩ Figure 46. Large Signal Transient Response, G = −1, RL = 150 Ω G = +2 CLOAD = 0pF G = +2 CL = 0pF CLOAD = 10pF CL = 20pF CL = 20pF RSNUB = 10Ω CLOAD = 20pF 499Ω 499Ω – RSNUB 200Ω + CLOAD 49.9Ω 1V/DIV 50mV/DIV 0 10 20TIME (ns)30 40 5002866-044 0 10 20TIME (ns)30 40 50 02866-047 Figure 44. Large Signal Transient Response for Figure 47. Small Signal Transient Response, Effect of Series Snub Resistor CLOAD = 0 pF, CLOAD = 10 pF, and CLOAD = 20 pF when Driving Capacitive Load Rev. E | Page 13 of 20

AD8007/AD8008 4 G = +2 G = +10 +VS 3 VS= ±5V RL = 1kΩ VIN= ±0.75V 2 RL = 150Ω 1 V) (UT 0 O V OUTPUT (2V/DIV) –1 INPUT (1V/DIV) –VS –2 –3 Figure 408. Outpu1t 0O0verdrive2 0R0TecIMoEv e(nrys,3) R00L = 1 kΩ, 410500 Ω, VIN =50 ±0202866-048.5 V –40 200 400 RL (Ω) 600 800 1000 02866-050 Figure 50. VOUT Swing vs. RL, VS = ±5 V, G = +10, VIN = ±0.75 V 0.5 G = +2 0.4 0.3 0.2 %) E ( 0.1 M GTI 0 N TLI –0.1 ET 18ns S –0.2 –0.3 –0.4 –0.50 5 10 15 T20IME (n2s5) 30 35 40 45 02866-049 Figure 49. 0.1% Settling Time, 2 V Step Rev. E | Page 14 of 20

AD8007/AD8008 THEORY OF OPERATION USING THE AD8007/AD8008 The AD8007 (single) and AD8008 (dual) are current feedback amplifiers optimized for low distortion performance. A simplified Supply Decoupling for Low Distortion conceptual diagram of the AD8007 is shown in Figure 51. It Decoupling for low distortion performance requires careful closely resembles a classic current feedback amplifier comprised consideration. The commonly adopted practice of returning the of a complementary emitter-follower input stage, a pair of signal high frequency supply decoupling capacitors to physically separate mirrors, and a diamond output stage. However, in the case of (and possibly distant) grounds can lead to degraded even-order the AD8007/AD8008, several modifications were made to improve harmonic performance. This situation is shown in Figure 52 using the distortion performance over that of a classic current feedback the AD8007 as an example; however, it is not recommended. For a topology. sinusoidal input, each decoupling capacitor returns to its ground a +VS quasi-rectified current carrying high even-order harmonics. M1 RF I1 – – I3 499Ω GND 1 CJ1 Q5 Q1 +VS Q3 0.1µF +10µF D1 IN– HIGH-Z IDO RG +VS IN+ IDI OUT 499Ω D2 Q2 –VS Q4 20R0SΩ AD8007 OUT IN CJ2 Q6 –VS I2 – – I4 0.1µF +10µF M2 RF –VS GND 2 02866-052 Figure 52. High Frequency Capacitors Returned to Physically Separate Grounds (Not Recommended) RG 02866-051 The decoupling scheme shown in Figure 53 is recommended. Figure 51. Simplified Schematic of AD8007 In Figure 53, the two high frequency decoupling capacitors are The signal mirrors were replaced with low distortion, high first tied together at a common node and are then returned to precision mirrors. In Figure 51, they are shown as M1 and M2. the ground plane through a single connection. By first adding Their primary function from a distortion standpoint is to reduce the two currents flowing through each high frequency decoupling the effect of highly nonlinear distortion caused by capacitances, capacitor, this ensures that the current returned into the ground CJ1 and CJ2. These capacitors represent the collector-to-base plane is only at the fundamental frequency. capacitances of the output devices of the mirrors. RF 499Ω A voltage imbalance arises across the output stage, as measured from the high impedance node, high-Z, to the output node, OUT. This imbalance is a result of delivering high output currents and 10µF is the primary cause of output distortion. Circuitry is included + to sense this output voltage imbalance and generate a compensating RG +VS 499Ω 0.1µF current, I . When injected into the circuit, I reduces the DO DO RS AD8007 OUT distortion that could be generated at the output stage. Similarly, the 200Ω nonlinear voltage imbalance across the input stage (measured from IN 0.1µF the noninverting to the inverting input) is sensed, and a current, –VS ITDhI,e i sd iensjiegcnt eadn dto l acyoomupt eanres astter ifcotrly i ntoppu-tt-og-ebnoetrtaotmed sdyimstmoretitorinc. to 10µF + 02866-053 minimize the presence of even-order harmonics. Figure 53. High Frequency Capacitors Returned to Ground at a Single Point (Recommended) Rev. E | Page 15 of 20

AD8007/AD8008 Whenever physical layout considerations prevent the decoupling LAYOUT CONSIDERATIONS scheme shown in Figure 53, the user can connect one of the The standard noninverting configuration with recommended high frequency decoupling capacitors directly across the supplies power supply bypassing is shown in Figure 54. The 0.1 μF high and connect the other high frequency decoupling capacitor to frequency decoupling capacitors should be X7R or NPO chip ground (see Figure 54). components. Connect C2 from the +V pin to the −V pin. S S 49R9FΩ Connect C1 from the +VS pin to signal ground. The length of the high frequency bypass capacitor leads is critical. 10µF Parasitic inductance due to long leads works against the low + +VS impedance created by the bypass capacitor. The ground for the C1 0.1µF load impedance should be at the same physical location as the RG bypass capacitor grounds. For larger value capacitors, which are 499Ω intended to be effective at lower frequencies, the current return RS AD8007 OUT path distance is less critical. 200Ω IN C2 0.1µF –VS 10µF+ 02866-054 Figure 54. High Frequency Capacitors Connected Across the Supplies (Recommended) Rev. E | Page 16 of 20

AD8007/AD8008 LAYOUT AND GROUNDING CONSIDERATIONS GROUNDING EXTERNAL COMPONENTS AND STABILITY A ground plane layer is important in densely packed printed The AD8007/AD8008 are current feedback amplifiers and, to a circuit boards (PCB) to minimize parasitic inductances. However, first order, the feedback resistor determines the bandwidth and an understanding of where the current flows in a circuit is critical stability. The gain, load impedance, supply voltage, and input impedances also have an effect. to implementing effective high speed circuit design. The length of the current path is directly proportional to the magnitude of Figure 11 shows the effect of changing R on the bandwidth and F parasitic inductances and thus the high frequency impedance of peaking for a gain of 2. Increasing R reduces peaking but also F the path. High speed currents in an inductive ground return reduces bandwidth. Figure 6 shows that for a given R increasing F create unwanted voltage noise. Broad ground plane areas reduce the gain also reduces peaking and bandwidth. Table 4 shows the parasitic inductance. recommended R and R values that optimize bandwidth with F G INPUT CAPACITANCE minimal peaking. Along with bypassing and ground, high speed amplifiers can be Table 4. Recommended Component Values sensitive to parasitic capacitance between the inputs and ground. Gain R (Ω) R (Ω) R (Ω) F G S Even 1 pF or 2 pF of capacitance reduces the input impedance at −1 499 499 200 high frequencies, in turn increasing the gain of the amplifier, which +1 499 Not applicable 200 causes peaking of the frequency response or even oscillations if +2 499 499 200 severe enough. Place the external passive components that are +5 499 124 200 connected to the input pins as close as possible to the inputs to +10 499 54.9 200 avoid parasitic capacitance. The ground and power planes must The load resistor also affects bandwidth, as shown in Figure 7 and be kept at a distance of at least 0.05 mm from the input pins on Figure 10. A comparison between Figure 7 and Figure 10 also all layers of the board. demonstrates the effect of gain and supply voltage. OUTPUT CAPACITANCE When driving loads with a capacitive component, stability To a lesser extent, parasitic capacitances on the output can cause improves by using a series snub resistor, R , at the output. SNUB peaking of the frequency response. The following two methods The frequency and pulse responses for various capacitive minimize its effect: loads are illustrated in Figure 12 and Figure 47, respectively. • Put a small value resistor in series with the output to isolate For noninverting configurations, a resistor in series with the the load capacitance from the output stage of the amplifier input, R, is needed to optimize stability for a gain of 1, as S (see Figure 12). illustrated in Figure 8. For larger noninverting gains, the effect • Increase the phase margin by increasing the gain of the of a series resistor is reduced. amplifier or by increasing the value of the feedback resistor. INPUT-TO-OUTPUT COUPLING To minimize capacitive coupling, the input and output signal traces should not be parallel. When they are not parallel, they help reduce unwanted positive feedback. Rev. E | Page 17 of 20

AD8007/AD8008 OUTLINE DIMENSIONS 5.00(0.1968) 4.80(0.1890) 8 5 4.00 (0.1574) 6.20 (0.2441) 3.80 (0.1497) 1 4 5.80 (0.2284) 1.27 (0.0500) 0.50 (0.0196) BSC 1.75 (0.0688) 0.25 (0.0099) 45° 0.25 (0.0098) 1.35 (0.0532) 8° 0.10 (0.0040) 0° COPLANARITY 0.51 (0.0201) 0.10 SEATING 0.31 (0.0122) 0.25 (0.0098) 10..2470 ((00..00510507)) PLANE 0.17 (0.0067) COMPLIANTTO JEDEC STANDARDS MS-012-AA C(RINOEFNPETARRREOENNLCLTEIHN EOGSN DELSIYM)AEANNRDSEI AORRNOESU NANORDEET DAIN-PO MPFRIFLO LMPIIMRLELIATIMTEEER TFSEO; RIRN ECUQHSU EDI VIINMA LEDENENSSTIIOGSN NFS.OR 012407-A Figure 55. 8-Lead Standard Small Outline Package [SOIC_N] Narrow Body (R-8) Dimensions shown in millimeters and (inches) 3.20 3.00 2.80 8 5 5.15 3.20 4.90 3.00 4.65 2.80 1 4 PIN1 IDENTIFIER 0.65BSC 0.95 15°MAX 0.85 1.10MAX 0.75 0.70 0.15 0.40 6° 0.23 0.55 CO0P.0L5ANARITY 0.25 0° 0.13 0.40 0.10 COMPLIANTTOJEDECSTANDARDSMO-187-AA 091709-A Figure 56. 8-Lead Mini Small Outline Package [MSOP] (RM-8) Dimensions shown in millimeters Rev. E | Page 18 of 20

AD8007/AD8008 2.20 2.00 1.80 1.35 5 4 2.40 1.25 2.10 1.15 1 2 3 1.80 0.65BSC 1.00 1.10 0.40 0.90 0.80 0.10 0.70 0.46 0.10MAX 0.30 SPELAATNIENG 00..2028 0.36 COPLANARITY 0.15 0.26 0.10 COMPLIANTTOJEDECSTANDARDSMO-203-AA 072809-A Figure 57. 5-Lead Thin Shrink Small Outline Transistor Package [SC70] (KS-5) Dimensions shown in millimeters ORDERING GUIDE Model Temperature Range Package Description Package Outline Branding AD8007AKS-R2 −40°C to +85°C 5-Lead SC70 KS-5 HTA AD8007AKSZ-R21 −40°C to +85°C 5-Lead SC70 KS-5 HTC AD8007AKSZ-REEL1 −40°C to +85°C 5-Lead SC70 KS-5 HTC AD8007AKSZ-REEL71 −40°C to +85°C 5-Lead SC70 KS-5 HTC AD8007AR −40°C to +85°C 8-Lead SOIC R-8 AD8007AR-REEL −40°C to +85°C 8-Lead SOIC R-8 AD8007AR-REEL7 −40°C to +85°C 8-Lead SOIC R-8 AD8007ARZ1 −40°C to +85°C 8-Lead SOIC R-8 AD8007ARZ-REEL1 −40°C to +85°C 8-Lead SOIC R-8 AD8007ARZ-REEL71 −40°C to +85°C 8-Lead SOIC R-8 AD8008AR −40°C to +85°C 8-Lead SOIC R-8 AD8008AR-REEL7 −40°C to +85°C 8-Lead SOIC R-8 AD8008AR-REEL −40°C to +85°C 8-Lead SOIC R-8 AD8008ARZ1 −40°C to +85°C 8-Lead SOIC R-8 AD8008ARZ-REEL71 −40°C to +85°C 8-Lead SOIC R-8 AD8008ARZ-REEL1 −40°C to +85°C 8-Lead SOIC R-8 AD8008ARM −40°C to +85°C 8-Lead MSOP RM-8 H2B AD8008ARM-REEL −40°C to +85°C 8-Lead MSOP RM-8 H2B AD8008ARM-REEL7 −40°C to +85°C 8-Lead MSOP RM-8 H2B AD8008ARMZ1 −40°C to +85°C 8-Lead MSOP RM-8 H2B# AD8008ARMZ-REEL1 −40°C to +85°C 8-Lead MSOP RM-8 H2B# AD8008ARMZ-REEL71 −40°C to +85°C 8-Lead MSOP RM-8 H2B# 1 Z = RoHS Compliant Part, # denotes RoHS compliant part may be top or bottom marked. Rev. E | Page 19 of 20

AD8007/AD8008 NOTES ©2002–2009 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D02866-0-11/09(E) Rev. E | Page 20 of 20