a 800 MHz, 50 mW Current Feedback Amplifier AD8001 FEATURES FUNCTIONAL BLOCK DIAGRAMS Excellent Video Specifications (R = 150 (cid:1), G = +2) L Gain Flatness 0.1 dB to 100 MHz 8-Lead PDIP (N-8), 5-Lead SOT-23-5 0.01% Differential Gain Error CERDIP (Q-8) and SOIC (R-8) (RT-5) 0.025(cid:2) Differential Phase Error Low Power AD8001 NC 1 8 NC 5.5 mA Max Power Supply Current (55 mW) VOUT 1 5 +VS High Speed and Fast Settling –IN 2 7 V+ 880 MHz, –3 dB Bandwidth (G = +1) +IN 3 6 OUT –VS 2 440 MHz, –3 dB Bandwidth (G = +2) +IN 3 4 –IN 1200 V/(cid:3)s Slew Rate V– 4 AD8001 5 NC 10 ns Settling Time to 0.1% NC = NO CONNECT Low Distortion transimpedance linearization circuitry. This allows it to drive –65 dBc THD, f = 5 MHz C video loads with excellent differential gain and phase perfor- 33 dBm Third Order Intercept, F = 10 MHz 1 –66 dB SFDR, f = 5 MHz mance ononly 50mW of power. The AD8001 is a current High Output Drive feedback amplifier and features gain flatness of 0.1 dB to 100 MHz 70 mA Output Current while offering differential gain and phase error of 0.01% and Drives Up to 4 Back-Terminated Loads (75 (cid:1) Each) 0.025°. This makes the AD8001 ideal for professional video While Maintaining Good Differential Gain/Phase electronics such as cameras and video switchers. Additionally, Performance (0.05%/0.25(cid:2)) the AD8001’s low distortion and fast settling make it ideal for buffer high speed A-to-D converters. APPLICATIONS A-to-D Drivers The AD8001 offers low power of 5.5 mA max (VS = ±5 V) and Video Line Drivers can run on a single +12 V power supply, while being capable of Professional Cameras delivering over 70 mA of load current. These features make this Video Switchers amplifier ideal for portable and battery-powered applications Special Effects where size and power are critical. RF Receivers The outstanding bandwidth of 800 MHz along with 1200 V/µs of slew rate make the AD8001 useful in many general-purpose GENERAL DESCRIPTION high speed applications where dual power supplies of up to ±6 V The AD8001 is a low power, high speed amplifier designed to operate on±5V supplies. The AD8001 features unique andsinglesuppliesfrom6Vto12Vareneeded.TheAD8001is availableintheindustrialtemperaturerangeof–40°C to +85°C. 9 VS = (cid:4)5V 6 RFB = 820(cid:1) G = +2 3 RL = 100(cid:1) dB 0 – GAIN –3 VRSF B= =(cid:4) 15kV(cid:1) –6 –9 –12 10M 100M 1G FREQUENCY – Hz Figure 1.Frequency Response of AD8001 Figure 2.Transient Response of AD8001; 2 V Step, G = +2 REV. D Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. under any patent or patent rights of Analog Devices. Trademarks and Tel: 781/329-4700 www.analog.com registered trademarks are the property of their respective companies. Fax: 781/326-8703 © 2003 Analog Devices, Inc. All rights reserved.

AD8001–SPECIFICATIONS (@ T = + 25(cid:2)C, V = (cid:4)5 V, R = 100 (cid:1), unless otherwise noted.) A S L AD8001A Model Conditions Min Typ Max Unit DYNAMIC PERFORMANCE –3 dB Small Signal Bandwidth, N Package G=+2, < 0.1 dB Peaking, R = 750 Ω 350 440 MHz F G=+1, < 1 dB Peaking, R = 1 kΩ 650 880 MHz F R Package G=+2, < 0.1 dB Peaking, R = 681 Ω 350 440 MHz F G=+1, < 0.1 dB Peaking, R = 845 Ω 575 715 MHz F RT Package G=+2, < 0.1 dB Peaking, R = 768 Ω 300 380 MHz F G=+1, < 0.1 dB Peaking, R = 1 kΩ 575 795 MHz F Bandwidth for 0.1 dB Flatness N Package G = +2, R = 750 Ω 85 110 MHz F R Package G = +2, R = 681 Ω 100 125 MHz F RT Package G = +2, R = 768 Ω 120 145 MHz F Slew Rate G = +2, V = 2 V Step 800 1000 V/µs O G = –1, V = 2 V Step 960 1200 V/µs O Settling Time to 0.1% G = –1, V = 2 V Step 10 ns O Rise and Fall Time G = +2, V = 2 V Step, R = 649 Ω 1.4 ns O F NOISE/HARMONIC PERFORMANCE Total Harmonic Distortion f = 5 MHz, V = 2 V p-p –65 dBc C O G = +2, R = 100 Ω L Input Voltage Noise f = 10kHz 2.0 nV/√Hz Input Current Noise f = 10 kHz,+In 2.0 pA/√Hz –In 18 pA/√Hz Differential Gain Error NTSC, G = +2, R = 150 Ω 0.01 0.025 % L Differential Phase Error NTSC, G = +2, R = 150 Ω 0.025 0.04 Degree L Third Order Intercept f = 10 MHz 33 dBm 1 dB Gain Compression f = 10 MHz 14 dBm SFDR f = 5 MHz –66 dB DC PERFORMANCE Input Offset Voltage 2.0 5.5 mV T –T 2.0 9.0 mV MIN MAX Offset Drift 10 µV/°C –Input Bias Current 5.0 25 ±µA T –T 35 ±µA MIN MAX +Input Bias Current 3.0 6.0 ±µA T –T 10 ±µA MIN MAX Open-Loop Transresistance V = ±2.5 V 250 900 kΩ O T –T 175 kΩ MIN MAX INPUT CHARACTERISTICS Input Resistance +Input 10 MΩ –Input 50 Ω Input Capacitance +Input 1.5 pF Input Common-Mode Voltage Range 3.2 ±V Common-Mode Rejection Ratio Offset Voltage V = ±2.5 V 50 54 dB CM –Input Current V = ±2.5 V, T –T 0.3 1.0 µA/V CM MIN MAX +Input Current V = ±2.5 V, T –T 0.2 0.7 µA/V CM MIN MAX OUTPUT CHARACTERISTICS Output Voltage Swing R = 150 Ω 2.7 3.1 ±V L Output Current R = 37.5 Ω 50 70 mA L Short Circuit Current 85 110 mA POWER SUPPLY Operating Range ±3.0 ±6.0 V Quiescent Current T –T 5.0 5.5 mA MIN MAX Power Supply Rejection Ratio +V = +4 V to +6V, –V = –5 V 60 75 dB S S –V = –4 V to –6 V, +V = +5 V 50 56 dB S S –Input Current T –T 0.5 2.5 µA/V MIN MAX +Input Current T –T 0.1 0.5 µA/V MIN MAX Specifications subject to change without notice. –2– REV. D

AD8001 ABSOLUTE MAXIMUM RATINGS1 MAXIMUM POWER DISSIPATION SupplyVoltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.6V The maximum power that can be safely dissipated by the InternalPowerDissipation @ 25°C2 AD8001 is limited by the associated rise in junction tempera- PDIP Package (N) . . . . . . . . . . . . . . . . . . . . . . . . . . . .1.3W ture. The maximum safe junction temperature for plastic SOIC (R) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0.8W encapsulated devices is determined by the glass transition tem- 8-Lead CERDIP . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1.1W perature of the plastic, approximately 150°C. Exceeding this SOT-23-5 Package (RT) . . . . . . . . . . . . . . . . . . . . . . .0.5 W limit temporarily may cause a shift in parametric performance Input Voltage (Common Mode) . . . . . . . . . . . . . . . . . . . . ±V due to a change in the stresses exerted on the die by the package. S DifferentialInputVoltage . . . . . . . . . . . . . . . . . . . . . . . ±1.2V Exceeding a junction temperature of 175°C for an extended Output Short Circuit Duration period can result in device failure. . . . . . . . . . . . . . . . . . . . . . . Observe Power Derating Curves While the AD8001 is internally short circuit protected, this Storage Temperature Range N, R . . . . . . . . .–65°C to +125°C may not be sufficient to guarantee that the maximum junction Operating Temperature Range (A Grade) . . . –40°C to +85°C temperature (150°C) is not exceeded under all conditions. To Lead Temperature Range (Soldering10sec) . . . . . . . . . 300°C ensure proper operation, it is necessary to observe the maximum NOTES power derating curves. 1Stresses above those listed under Absolute Maximum Ratings may cause perma- nent damage to the device. This is a stress rating only; functional operation of the 2.0 device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating 8-LEAD TJ = +150(cid:2)C conditions for extended periods may affect device reliability. W PDIP PACKAGE 2S8885p----LLLLeceeeeiaaaafiddddc aPSCStOODiEoITnRICP -Di 2 sPP I3fPaao-cc5 rPkk dPaaagegcaevkec:i:ak c gaθθeegJJ AAi:en :=θ= fJθ Ar91Je A0=5e °=5 aC1° i21Cr/W:60/0W°C°C/W/W DISSIPATION – 1.5 SOIC8 -PLAECAKDAGE CERD8IP-L PEAACDKAGE R 1.0 E W O P M U M0.5 XI MA 5-LEAD SOT-23-5 PACKAGE 0 –50 –40 –30–20–10 0 10 20 30 40 50 60 70 80 90 AMBIENT TEMPERATURE – (cid:2)C Figure 3.Plot of Maximum Power Dissipation vs. Temperature ORDERING GUIDE Temperature Package Package Model Range Description Option Branding AD8001AN –40°C to +85°C 8-Lead PDIP N-8 AD8001AQ –55°C to +125°C 8-Lead CERDIP Q-8 AD8001AR –40°C to +85°C 8-Lead SOIC R-8 AD8001AR-REEL –40°C to +85°C 13" Tape and REEL R-8 AD8001AR-REEL7 –40°C to +85°C 7" Tape and REEL R-8 AD8001ART-REEL –40°C to +85°C 13" Tape and REEL RT-5 HEA AD8001ART-REEL7 –40°C to +85°C 7" Tape and REEL RT-5 HEA AD8001ACHIPS –40°C to +85°C Die Form 5962-9459301MPA* –55°C to +125°C 8-Lead CERDIP Q-8 *Standard Military Drawing Device. CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily WARNING! accumulate on the human body and test equipment and can discharge without detection. Although the AD8001 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD ESD SENSITIVE DEVICE precautions are recommended to avoid performance degradation or loss of functionality. REV. D –3–

AD8001–Typical Performance Characteristics 806(cid:1) +VS 0.001(cid:3)F VOUT TO 0.1(cid:3)F TEKTRONIX CSA 404 COMM. 806(cid:1) SIGNAL ANALYZER AD8001 VIN 0.1(cid:3)F RL = 100(cid:1) HP8133A 50(cid:1) PULSE 0.001(cid:3)F GENERATOR TR/TF = 50ps –VS 400mV 5ns TPC 1.Test Circuit , Gain = +2 TPC 4.2 V Step Response, G = +2 909(cid:1) +VS 0.001(cid:3)F VOUT TO 0.1(cid:3)F TEKTRONIX CSA 404 COMM. SIGNAL ANALYZER AD8001 VIN 0.1(cid:3)F RL = 100(cid:1) LeCROY 9210 50(cid:1) PULSE 0.001(cid:3)F GENERATOR TR/TF = 350ps –VS TPC 2.1 V Step Response, G = +2 TPC 5.Test Circuit, Gain = +1 0.5V 5ns TPC 3.2 V Step Response, G = +1 TPC 6.100 mV Step Response, G = +1 –4– REV. D

AD8001 1000 9 6 RVSF B= =(cid:4) 852V0(cid:1) 800 VRSL == (cid:4)1050V(cid:1) 3 RGL = = + 1200(cid:1) – MHz G = +2 GAIN – dB –03 RVSF B= =(cid:4) 15kV(cid:1) BANDWIDTH 640000 PACKNAGE B –6 –3d PACKRAGE 200 –9 –12 0 10M 100M 1G 500 600 700 800 900 1000 FREQUENCY – Hz VALUE OF FEEDBACK RESISTOR (RF) – (cid:1) TPC 7.Frequency Response, G = +2 TPC 10.–3 dB Bandwidth vs. R F 0.1 –50 R64F9 =(cid:1) (cid:4)5V SUPPLIES 0 RF = 698(cid:1) –0.1 Bc –60 VOUT = 2V p-p –0.2 RF = 750(cid:1) N – d RGL = = + 1200(cid:1) dB–0.3 TIO –70 OUTPUT – ––00..45 RVGIL N= = =+ 125000m(cid:1)V NIC DISTOR –80 SECOND HARMONIC –0.6 MO THIRD HARMONIC R –0.7 HA –90 –0.8 –0.9 –100 1M 10M 100M 10k 100k 1M 10M 100M FREQUENCY – Hz FREQUENCY – Hz TPC 8.0.1 dB Flatness, R Package (for N Package Add TPC 11.Distortion vs. Frequency, R = 100 Ω L 50 Ω to R) F –50 es 0.08 e Bc –60 VRGOL = U= T+ 1 2=k (cid:1)2V p-p (cid:4)5V SUPPLIES SE – Degr 00..0046 GRF = = + 8206(cid:1) 2 BALCOKA TDESR (M75IN(cid:1)A)TED d A TORTION – ––8700 SECOND HARMONIC DIFF PH 00..0002 1 BALCOKA TDE (R1M50IN(cid:1)A)TED S DI C 0.02 RMONI –90 THIRD HARMONIC N – % 0.01 1 ALONDA D2S B (A1C50K(cid:1) T EARNMDI N7A5(cid:1)TE)D HA GAI 0.00 –100 F DIF–0.01 –110 –0.02 10k 100k 1M 10M 100M 0 100 IRE FREQUENCY – Hz TPC 9.Distortion vs. Frequency, R = 1 kΩ TPC 12.Differential Gain and Differential Phase L REV. D –5–

AD8001 5 1000 0 N PACKAGE 900 –5 Hz M AIN – dB ––1105 VRIFN == 9 –0296(cid:1)dBm NDWIDTH – 800 R PACKAGE G –20 BA 700 –25 –3dB VRILN == 15000m(cid:1)V 600 G = +1 –30 –35 500 100M 1G 3G 600 700 800 900 1000 1100 FREQUENCY – Hz VALUE OF FEEDBACK RESISTOR (RF) – (cid:1) TPC 13.Frequency Response, G = +1 TPC 16.–3 dB Bandwidth vs. R, G = +1 F 1 –40 0 RF = 649(cid:1) –50 RL = 100(cid:1) –1 G = +1 –2 RF = 953(cid:1) VOUT = 2V p-p Bc –60 dB–3 – d – N SECOND HARMONIC OUTPUT –––465 GRVIL N= = =+ 115000m(cid:1)V DISTORTIO ––7800 THIRD HARMONIC –7 –90 –8 –9 –100 2M 10M 100M 1G 10k 100k 1M 10M 100M FREQUENCY – Hz FREQUENCY – Hz TPC 14.Flatness, R Package, G = +1 (for N Package Add TPC 17.Distortion vs. Frequency, R = 100 Ω L 100 Ω to R) F –40 3 G = +1 0 –50 RL = 1k(cid:1) VOUT = 2V p-p –3 –60 –6 c B V STORTION – d ––8700 SECOND HARMONIC OUTPUT – dB–––11925 DI THIRD HARMONIC –18 –90 –21 RL = 100(cid:1) G = +1 –100 –24 –110 –27 10k 100k 1M 10M 100M 1M 10M 100M FREQUENCY – Hz FREQUENCY – Hz TPC 15. Distortion vs. Frequency, R = 1 kΩ TPC 18.Large Signal Frequency Response, G = +1 L –6– REV. D

AD8001 45 2.2 40 35 G = +100 2.0 DEVICE NO. 1 30 RF = 1000(cid:1) mV1.8 25 – 20 AGE 1.6 DEVICE NO. 2 GAIN – dB 11055 G = +10 RF = 470(cid:1) SET VOLT11..24 F 0 F O1.0 –5 RL = 100(cid:1) UT –10 NP0.8 DEVICE NO. 3 I –15 0.6 –20 –25 0.4 1M 10M 100M 1G –60 –40 –20 0 20 40 60 80 100 FREQUENCY – Hz JUNCTION TEMPERATURE – (cid:2)C TPC 19.Frequency Response, G = +10, G = +100 TPC 22.Input Offset vs. Temperature 3.35 5.8 3.25 5.6 T SWING – Volts233...901555 +VOUT | –VOUT | VRSL == (cid:4)1550V(cid:1) Y CURRENT– mA 555...240 VS = (cid:4)5V PU2.85 +VOUT PL T P U U 4.8 O2.75 RL = 50(cid:1) S VS = (cid:4)5V 2.65 | –VOUT | 4.6 2.55 4.4 –60 –40 –20 0 20 40 60 80 100 –60 –40 –20 0 20 40 60 80 100 120 140 JUNCTION TEMPERATURE – (cid:2)C JUNCTION TEMPERATURE – (cid:2)C TPC 20.Output Swing vs. Temperature TPC 23.Supply Current vs. Temperature 5 125 4 120 A (cid:3)CURRENT– A 213 –IN T CURRENT – m111011505 | SINK ISC |SOURCE ISC S 0 UI A C NPUT BI–1 +IN ORT CIR19050 I–2 H S –3 90 –4 85 –60 –40 –20 0 20 40 60 80 100 120 140 –60 –40 –20 0 20 40 60 80 100 JUNCTION TEMPERATURE – (cid:2)C JUNCTION TEMPERATURE – (cid:2)C TPC 21.Input Bias Current vs. Temperature TPC 24.Short Circuit Current vs. Temperature REV. D –7–

AD8001 6 1k 5 (cid:1)k RVSL == (cid:4)1550V(cid:1) 100 E– 4 VOUT = (cid:4)2.5V C AN (cid:1) 10 SIST 3 – UT SRE –TZ RO 1 N 2 A R T 1 +TZ 0.1 GRF = = + 9209(cid:1) 0 0.01 –60 –40 –20 0 20 40 60 80 100 120 140 10k 100k 1M 10M 100M JUNCTION TEMPERATURE – (cid:2)C FREQUENCY – Hz TPC 25.Transresistance vs. Temperature TPC 28.Output Resistance vs. Frequency 100 100 1 RF = 576(cid:1) 0 –1 √NOISE VOLTAGE – nV/Hz 10 NINOVNEIRNTVIENRGT CINUGR CRUENRRT EVNST = V(cid:4)S5 =V (cid:4)5V 10√NOISE CURRENT – pA/Hz OUTPUT – dB–––––45632 VGRIL N= = =– 115000m(cid:1)V RF =R F6 4=9 7(cid:1)50(cid:1) –7 –8 VOLTAGE NOISE VS = (cid:4)5V 1 1 –9 10 100 1k 10k 100k 1M 10M 100M 1G FREQUENCY – Hz FREQUENCY – Hz TPC 26.Noise vs. Frequency TPC 29.–3 dB Bandwidth vs. Frequency, G = –1 –48 –52.5 –55.0 –49 –PSRR –CMRR –57.5 –50 –60.0 3V SPAN –51 B B–62.5 R– d –52 +CMRR R– d –65.0 CCAUSREV ECSO ANRDEIT FIOONR W WHOERRSET- R R M S ONE SUPPLY IS VARIED C–53 P–67.5 WHILE THE OTHER IS 2.5V SPAN –70.0 HELD CONSTANT. –54 –72.5 +PSRR –55 –75.0 –56 –77.5 –60 –40 –20 0 20 40 60 80 100 120 140 –60 –40 –20 0 20 40 60 80 100 JUNCTION TEMPERATURE – (cid:2)C JUNCTION TEMPERATURE – (cid:2)C TPC 27.CMRR vs. Temperature TPC 30.PSRR vs. Temperature –8– REV. D

AD8001 30 –10 910(cid:1) 20 CURVES ARE FOR WORST- VIN 910(cid:1) 51(cid:1) 10 COANSEE S CUOPPNLDYIT IISO NVA WRHIEEDRE +PSRR 150(cid:1) WHILE THE OTHER IS –20 VOUT 0 HELD CONSTANT. 62(cid:1) 150(cid:1) B B R – d–30 R – d–10 MR SR–20 –PSRR C P –40 –30 –PSRR +PSRR –40 RF = 909(cid:1) G = +2 –50 –50 –60 300k 1M 10M 100M 1G 1M 10M 100M 1G FREQUENCY – Hz FREQUENCY – Hz TPC 31.CMRR vs. Frequency TPC 34.PSRR vs. Frequency 1 RF = 549(cid:1) 0 –1 –2 RF = 649(cid:1) dB–3 – G = –2 UT –4 RL = 100(cid:1) TP VIN = 50mVrms RF = 750(cid:1) U–5 O –6 –7 –8 –9 1M 10M 100M 1G FREQUENCY – Hz TPC 32.–3 dB Bandwidth vs. Frequency, G = –2 TPC 35.2 V Step Response, G = –1 100 100 90 3 WAFER LOTS 90 COUNT = 895 80 MEAN = 1.37 80 STD DEV = 1.13 CUMULATIVE 70 MIN = –2.45 70 MAX = +4.69 60 60 T T N N E U 50 50 C CO FREQ DIST ER 40 40 P 30 30 20 20 10 10 0 0 –5 –4 –3 –2 –1 0 1 2 3 4 5 INPUT OFFSET VOLTAGE – mV TPC 33.100 mV Step Response, G = –1 TPC 36.Input Offset Voltage Distribution REV. D –9–

AD8001 THEORY OF OPERATION Considering that additional poles contribute excess phase at A very simple analysis can put the operation of the AD8001, a high frequencies, there is a minimum feedback resistance below current feedback amplifier, in familiar terms. Being a current which peaking or oscillation may result. This fact is used to feedback amplifier, the AD8001’s open-loop behavior is expressed determine the optimum feedback resistance, RF. In practice, as transimpedance, ∆V /∆I , or T . The open-loop transimped- parasitic capacitance at Pin 2 will also add phase in the feedback O –IN Z ance behaves just as the open-loop voltage gain of a voltage loop, so picking an optimum value for RF can be difficult. feedback amplifier, that is, it has a large dc value and decreases Figure 6 illustrates this problem. Here the fine scale (0.1 dB/ at roughly 6 dB/octave in frequency. div) flatness is plotted versus feedback resistance. These plots were taken using an evaluation card which is available to cus- Since the R is proportional to 1/g , the equivalent voltage IN M tomers so that these results may readily be duplicated. gain is just T × g , where the g in question is the trans- Z M M conductance of the input stage. This results in a low open-loop Achieving and maintaining gain flatness of better than 0.1 dB at input impedance at the inverting input, a now familiar result. frequencies above 10 MHz requires careful consideration of Using this amplifier as a follower with gain, Figure 4, basic several issues. analysis yields the following result. V T (S) 0.1 O = G × Z RF = V T (S)+G × R + R1 0 649(cid:1) IN Z IN RF = 698(cid:1) –0.1 R1 G =1+ R =1/g ≈ 50 Ω R2 IN M B –0.2 G = +2 RF = 750(cid:1) d –0.3 – T R1 U –0.4 P T OU –0.5 R2 –0.6 RIN VOUT –0.7 –0.8 VIN –0.9 1M 10M 100M FREQUENCY – Hz Figure 4. Follower with Gain Figure 6.0.1 dB Flatness vs. Frequency Recognizing that G × R << R1 for low gains, it can be seen to Choice of Feedback and Gain Resistors IN the first order that bandwidth for this amplifier is independent Because of the above-mentioned relationship between the band- of gain (G). This simple analysis in conjunction with Figure 5 width and feedback resistor, the fine scale gain flatness will, to can, in fact, predict the behavior of the AD8001 over a wide some extent, vary with feedback resistance. It, therefore, is range of conditions. recommended that once optimum resistor values have been determined, 1% tolerance values should be used if it is desired to 1M maintain flatness over a wide range of production lots. In addition, resistors of different construction have different associated parasitic capacitance and inductance. Surface-mount resistors were used 100k for the bulk of the characterization for this data sheet. It is not recommended that leaded components be used with the AD8001. 10k (cid:1) – Z T 1k 100 10 100k 1M 10M 100M 1G FREQUENCY – Hz Figure 5.Transimpedance vs. Frequency –10– REV. D

AD8001 Printed Circuit Board Layout Considerations Driving Capacitive Loads As to be expected for a wideband amplifier, PC board parasitics The AD8001 was designed primarily to drive nonreactive loads. can affect the overall closed-loop performance. Of concern are If driving loads with a capacitive component is desired, best stray capacitances at the output and the inverting input nodes. If frequency response is obtained by the addition of a small series a ground plane is to be used on the same side of the board as resistance, as shown in Figure 8. The accompanying graph the signal traces, a space (5 mm min) should be left around the shows the optimum value for R versus capacitive load. It is SERIES signal lines to minimize coupling. Additionally, signal lines worth noting that the frequency response of the circuit when connecting the feedback and gain resistors should be short driving large capacitive loads will be dominated by the passive enough so that their associated inductance does not cause high roll-off of R and C . SERIES L frequency gain errors. Line lengths on the order of less than 5 mm are recommended. If long runs of coaxial cable are being 909(cid:1) driven, dispersion and loss must be considered. Power Supply Bypassing Adequate power supply bypassing can be critical when optimiz- RSERIES ing the performance of a high frequency circuit. Inductance in IN the power supply leads can form resonant circuits that produce 500R(cid:1)L CL peaking in the amplifier’s response. In addition, if large current transients must be delivered to the load, then bypass capacitors (typically greater than 1 µF) will be required to provide the best Figure 8.Driving Capacitive Loads settling time and lowest distortion. A parallel combination of 4.7 µF and 0.1 µF is recommended. Some brands of electrolytic capacitors will require a small series damping resistor ≈4.7 Ω for 40 optimum results. G = +1 DC Errors and Noise There are three major noise and offset terms to consider in a 30 current feedback amplifier. For offset errors, refer to the equation below. For noise error the terms are root-sum-squared to give a (cid:1) – net output error. In the circuit in Figure 7 they are input offset ES20 RI (V ), which appears at the output multiplied by the noise gain E of ItOhe circuit (1 + R /R), noninverting input current (I × R ) RS F I BN N also multiplied by the noise gain, and the inverting input current, 10 which when divided between R and R and subsequently F I multiplied by the noise gain always appears at the output as I × R . The input voltage noise of the AD8001 is a low 2 nV/ BN F √Hz. At low gains though the inverting input current noise times 00 5 10 15 20 25 RF is the dominant noise source. Careful layout and device CL – pF matching contribute to better offset and drift specifications for Figure 9.Recommended R vs. Capacitive Load SERIES the AD8001 compared to many other current feedback ampli- fiers. The typical performance curves in conjunction with the following equations can be used to predict the performance of the AD8001 in any application.     R R V =V ×1+ F ± I × R ×1+ F ± I × R OUT IO BN N BI F  R   R  I I RF RI IBI RN IBN VOUT Figure 7.Output Offset Voltage REV. D –11–

AD8001 Communications Operation as a Video Line Driver Distortion is a key specification in communications applications. The AD8001 has been designed to offer outstanding perfor- Intermodulation distortion (IMD) is a measure of the ability of mance as a video line driver. The important specifications of an amplifier to pass complex signals without the generation of differential gain (0.01%) and differential phase (0.025°) meet spurious harmonics. The third order products are usually the the most exacting HDTV demands for driving one video load. most problematic since several of them fall near the fundamentals The AD8001 also drives up to two back terminated loads as and do not lend themselves to filtering. Theory predicts that the shown in Figure 11, with equally impressive performance (0.01%, third order harmonic distortion components increase in power at 0.07°). Another important consideration is isolation between three times the rate of the fundamental tones. The specification loads in a multiple load application. The AD8001 has more of third order intercept as the virtual point where fundamental and than 40 dB of isolation at 5 MHz when driving two 75 Ω back harmonic power are equal is one standard measure of distortion terminated loads. performance. Op amps used in closed-loop applications do not always obey this simple theory. At a gain of +2, the AD8001 75(cid:1) has performance summarized in Figure 10. Here the worst third 909(cid:1) 909(cid:1) 75(cid:1) CABLE VOUT NO. 1 order products are plotted versus input power. The third order 75(cid:1) intercept of the AD8001 is +33 dBm at 10 MHz. +VS 0.001(cid:3)F + 0.1(cid:3)F –45 75(cid:1) –50 GF1 = = + 120MHz 75(cid:1) AD8001 75(cid:1) CABLE VOUT NO. 2 Bc–55 F2 = 12MHz 2F2 – F1 VIN CABLE 0.1(cid:3)F 75(cid:1) – d 75(cid:1) D M–60 R I 0.001(cid:3)F DE 2F1 – F2 OR–65 –VS D R Figure 11.Video Line Driver HI–70 T –75 –80 –8 –7 –6 –5 –4 –3 –2 –1 0 1 2 3 4 5 6 INPUT POWER – dBm Figure 10.Third Order IMD; F = 10 MHz, F = 12 MHz 1 2 –12– REV. D

AD8001 Driving A-to-D Converters ADC. Using the AD9058’s internal +2 V reference connected The AD8001 is well suited for driving high speed analog-to- to both ADCs as shown in Figure 12 reduces the number of digital converters such as the AD9058. The AD9058 is a dual external components required to create a complete data 8-bit 50 MSPS ADC. In the circuit below, the AD8001 is acquisition system. The 20 Ω resistors in series with ADC inputs shown driving the inputs of the AD9058, which are configured are used to help the AD8001s drive the 10 pF ADC input for 0 V to 2 V ranges. Bipolar input signals are buffered, amplified capacitance. The AD8001 only adds 100 mW to the power (–2×), and offset (by +1.0 V) into the proper input range of the consumption while not limiting the performance of the circuit. 1k(cid:1) ENCODE 74ACT04 50(cid:1) 10pF 10 36 ENCODE A ENCODE B ANALOG 324(cid:1) 649(cid:1) 388 ––VVRREEFF AB AD9058 +VS 52,4 ,9 ,3 27,2 ,41 0.1(cid:3)F +5V (cid:4)0IN.5 AV 1.3k(cid:1) AD8001 20(cid:1) 6 AIN A (J-LEAD)D0A (LSB) 1187 RZ1 16 0.1(cid:3)F –2V AD707 20k(cid:1) 23 ++VVIRNETF A 111543 4ACT 273 8 7 20k(cid:1) 0.1(cid:3)F 43 +VREF B 12 11 1.3k(cid:1) D7A (MSB) 649(cid:1) 28 RZ2 D0B (LSB) 29 ANALOG 324(cid:1) 30 (cid:4)0IN.5 BV AD8001 20(cid:1) 40 AIN B 3312 CT 273 8 33 4A 1 7 COMP 34 0.1(cid:3)F D7B (MSB) 35 7, 20, CLOCK –VS 26, 39 –5V RZ1, RZ2 = 2,000(cid:1) SIP (8-PKG) 0.1(cid:3)F 1N4001 4,19, 21 25, 27, 42 Figure 12.AD8001 Driving a Dual A-to-D Converter REV. D –13–

AD8001 Layout Considerations (4.7 µF–10 µF) tantalum electrolytic capacitor should be con- The specified high speed performance of the AD8001 requires nected in parallel, but not necessarily so close, to supply current careful attention to board layout and component selection. Proper for fast, large-signal changes at the output. R design techniques and low parasitic component selection F The feedback resistor should be located close to the inverting are mandatory. input pin in order to keep the stray capacitance at this node to a The PCB should have a ground plane covering all unused portions minimum. Capacitance variations of less than 1 pF at the invert- of the component side of the board to provide a low impedance ing input will significantly affect high speed performance. ground path. The ground plane should be removed from the area Stripline design techniques should be used for long signal traces near the input pins to reduce stray capacitance. (greater than about 1 inch). These should be designed with a Chip capacitors should be used for supply bypassing (see Figure 13). characteristic impedance of 50 Ω or 75 Ω and be properly termi- One end should be connected to the ground plane and the other nated at each end. within 1/8 inch of each power pin. An additional large RF RF +VS +VS +VS IN RG RO C0.11(cid:3)F C103(cid:3)F RG RO RT OUT IN OUT C2 C4 RS 0.1(cid:3)F 10(cid:3)F RT –VS –VS –VS Inverting Configuration Supply Bypassing Noninverting Configuration Figure 13. Inverting and Noninverting Configurations for Evaluation Boards Table I. Recommended Component Values AD8001AN (PDIP) AD8001AR (SOIC) AD8001ART (SOT-23-5) Gain Gain Gain Component –1 +1 +2 +10 +100 –1 +1 +2 +10 +100 –1 +1 +2 +10 +100 R (Ω) 649 1050 750 470 1000 604 953 681 470 1000 845 1000 768 470 1000 F R (Ω) 649 750 51 10 604 681 51 10 845 768 51 10 G R (Nominal) (Ω) 49.9 49.9 49.9 49.9 49.9 49.9 49.9 49.9 49.9 49.9 49.9 49.9 49.9 49.9 49.9 O R (Ω) 0 0 0 S R (Nominal) (Ω) 54.9 49.9 49.9 49.9 49.9 54.9 49.9 49.9 49.9 49.9 54.9 49.9 49.9 49.9 49.9 T Small Signal 340 880 460 260 20 370 710 440 260 20 240 795 380 260 20 BW (MHz) 0.1 dB Flatness 105 70 105 130 100 120 110 300 145 (MHz) –14– REV. D

AD8001 OUTLINE DIMENSIONS 8-Lead Plastic Dual In-Line Package [PDIP] 8-Lead Ceramic Dual In-Line Package [CERDIP] (N-8) (Q-8) Dimensions shown in inches and (millimeters) Dimensions shown in inches and (millimeters) 0.375 (9.53) 0.005 (0.13) 0.055 (1.40) 0.365 (9.27) MIN MAX 0.355 (9.02) 8 5 8 5 0.295 (7.49) 0.310 (7.87) 0.285 (7.24) PIN 1 0.220 (5.59) 1 4 0.275 (6.98) 1 4 0.325 (8.26) 0.310 (7.87) 0.100 (2.54) BSC 0.10B0S (C2.54) 0.300 (7.62) 0.150 (3.81) 0.405 (10.29) MAX 0.320 (8.13) 0.135 (3.43) 0.290 (7.37) 0.060 (1.52) (04..15870) 0(M0.I0.N3185) 0.120 (3.05) 0.200 (5M.0A8X) 0.015 (0.38) MAX 0.015 (0.38) 0.200 (5.08) 0.150 (3.81) 0.150 (3.81) SEATING 0.010 (0.25) 0.125 (3.18) MIN 0.130 (3.30) PLANE 0.008 (0.20) 0.023 (0.58) SEATING 0.015 (0.38) 00.1.01202 ( 2(0.7.596)) 00..006500 ((11..5227)) 0.014 (0.36) 00..007300 ((10..7786)) PLANE 1 05 0.008 (0.20) 0.018 (0.46) 0.045 (1.14) CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETERS DIMENSIONS 0.014 (0.36) (IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN COMPLIANT TO JEDEC STANDARDS MO-095AA CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN 8-Lead Standard Small Outline Package [SOIC] 5-Lead Small Outline Transistor Package [SOT-23] (R-8) (RT-5) Dimensions shown in millimeters and (inches) Dimensions shown in millimeters 5.00 (0.1968) 2.90 BSC 4.80 (0.1890) 4.00 (0.1574) 8 5 6.20 (0.2440) 5 4 3.80 (0.1497) 1 4 5.80 (0.2284) 1.60 BSC 2.80 BSC 1 2 3 1.27B (0S.C0500) 1.75 (0.0688) 00..5205 ((00..00109969))(cid:1) 45(cid:2) PIN 1 0.95 BSC 0.25 (0.0098) 1.35 (0.0532) 1.90 0.10 (0.0040) 1.30 BSC COPLANARITY 00..5311 ((00..00210212)) 0.25 (0.0098)80(cid:2)(cid:2) 1.27 (0.0500) 10..1950 0.10 SEPALTAINNGE 0.17 (0.0067) 0.40 (0.0157) 1.45 MAX 0.22 0.08 COMPLIANT TO JEDEC STANDARDS MS-012AA CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS 10(cid:2) (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR 0.15 MAX 0.50 SEATING 5(cid:2) 0.60 REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN 0.30 PLANE 0(cid:2) 0.45 0.30 COMPLIANT TO JEDEC STANDARDS MO-178AA REV. D –15–

AD8001 Revision History Location Page D) 7/03—Data Sheet changed from REV. C to REV. D 3( 0 7/ Renumbered figures and TPCs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Universal – 0 – Changes to ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 43 0 1 Updated OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 0 C –16– REV. D