14-Bit, 1 MSPS, Unipolar/Bipolar Programmable Input PulSAR® ADC Data Sheet AD7951 FEATURES FUNCTIONAL BLOCK DIAGRAM Multiple pins/software programmable input ranges: 5 V, 10 V, ±5 V, ±10 V TEMP REFBUFIN REF REFGND VCC VEE DVDD DGND Pins or serial SPI® compatible input ranges/mode selection OVDD AGND AD7951 Throughput REF OGND AVDD AMP 1 MSPS (warp mode) PDREF REF SERPIAOLR DTATA 800 kSPS (normal mode) PDBUF SERIAL CONFIGURATION 670 kSPS (impulse mode) IN+ SWITCHED PORT 14 D[13:0] 14-bit resolution with no missing codes IN– CAP DAC SER/PAR INL: ±0.3 LSB typ, ±1 LSB max (±61 ppm of FSR) BYTESWAP SNR: 85 dB @ 2 kHz CLOCK IPNATREARLFLAECLE OB/2C CNVST iCMOS® process technology BUSY PD CONTROL LOGIC AND 5 V internal reference: typical drift 3 ppm/°C; TEMP output CALIBRATION CIRCUITRY RD RESET No pipeline delay (SAR architecture) CS PSParI-a/lQleSlP (1I™4--/ MorI C8-RbOitW bIuRsE)™ a-n/DdS sPe-rciaolm 5p Va/t3i.b3l eV interface WARP IMPULSE BIPOLAR TEN 06396-001 Figure 1. Power dissipation: 10 mW @ 100 kSPS Table 1. 48-Lead 14-/16-/18-Bit PulSAR Selection 235 mW @ 1 MSPS 100 kSPS to 500 kSPS to 570 kSPS to >1000 48-lead LQFP and LFCSP (7 mm × 7 mm) packages Type 250 kSPS 570 kSPS 1000 kSPS kSPS Pseudo AD7651 AD7650 AD7653 APPLICATIONS Differential AD7660 AD7652 AD7667 Process control AD7661 AD7664 AD7666 Medical instruments True Bipolar AD7610 AD7665 AD7951 High speed data acquisition AD7663 AD7612 Digital signal processing AD7671 Instrumentation True AD7675 AD7676 AD7677 AD7621 Spectrum analysis Differential AD7622 AD7623 ATE 18-Bit, True AD7678 AD7679 AD7674 AD7641 GENERAL DESCRIPTION Differential AD7643 Multichannel/ AD7654 The AD7951 is a 14-bit, charge redistribution, successive Simultaneous AD7655 approximation register (SAR) architecture analog-to-digital converter (ADC) fabricated on Analog Devices, Inc.’s iCMOS high voltage process. The device is configured through hardware or via a dedicated write only serial configuration port for input range and operating mode. The AD7951 contains a high speed 14-bit sampling ADC, an internal conversion clock, an internal reference (and buffer), error correction circuits, and both serial and parallel system interface ports. A falling edge on CNVST samples the analog input on IN+ with respect to a ground sense, IN−. The AD7951 features four different analog input ranges and three different sampling modes: warp mode for the fastest throughput, normal mode for the fastest asynchronous throughput, and impulse mode where power is scaled with throughput. Operation is specified from −40°C to +85°C. Rev. B Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Tel: 781.329.4700 ©2006–2015 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com

AD7951 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Analog Inputs.............................................................................. 20 Applications ....................................................................................... 1 Voltage Reference Input/Output .............................................. 21 General Description ......................................................................... 1 Power Supplies ............................................................................ 22 Functional Block Diagram .............................................................. 1 Conversion Control ................................................................... 23 Revision History ............................................................................... 2 Interfaces.......................................................................................... 24 Specifications ..................................................................................... 3 Digital Interface .......................................................................... 24 Timing Specifications .................................................................. 5 Parallel Interface ......................................................................... 24 Absolute Maximum Ratings ............................................................ 7 Serial Interface ............................................................................ 25 ESD Caution .................................................................................. 7 Master Serial Interface ............................................................... 25 Pin Configuration and Function Descriptions ............................. 8 Slave Serial Interface .................................................................. 27 Typical Performance Characteristics ........................................... 12 Hardware Configuration ........................................................... 29 Terminology .................................................................................... 16 Software Configuration ............................................................. 29 Theory of Operation ...................................................................... 17 Microprocessor Interfacing ....................................................... 30 Overview ...................................................................................... 17 Application Information ................................................................ 31 Converter Operation .................................................................. 17 Layout Guidelines....................................................................... 31 Modes of Operation ................................................................... 18 Outline Dimensions ....................................................................... 32 Transfer Functions...................................................................... 18 Ordering Guide .......................................................................... 32 Typical Connection Diagram.................................................... 19 REVISION HISTORY 5/15—Rev. A to Rev. B Change to Acquisition Time Parameter, Table 3 .......................... 5 Deleted Evaluating Performance Section .................................... 31 Changes to Ordering Guide .......................................................... 32 12/12—Rev. 0 to Rev. A Added Exposed Pad Note ................................................................ 8 Changes to Power Sequencing Section ........................................ 23 Updated Outline Dimensions ....................................................... 32 Changes to Ordering Guide .......................................................... 32 10/06—Revision 0: Initial Version Rev. B | Page 2 of 32

Data Sheet AD7951 SPECIFICATIONS AVDD = DVDD = 5 V; OVDD = 2.7 V to 5.5 V; VCC = 15 V; VEE = −15 V; V = 5 V; all specifications T to T , unless otherwise noted. REF MIN MAX Table 2. Parameter Conditions/Comments Min Typ Max Unit RESOLUTION 14 Bits ANALOG INPUT Voltage Range, V V − V = 0 V to 5 V −0.1 +5.1 V IN IN+ IN− V − V = 0 V to 10 V −0.1 +10.1 V IN+ IN− V − V = ±5 V −5.1 +5.1 V IN+ IN− V − V = ±10 V −10.1 +10.1 V IN+ IN− V to AGND −0.1 +0.1 V IN− Analog Input CMRR f = 100 kHz 75 dB IN Input Current V = ±5 V, ±10 V @ 1 MSPS 3001 µA IN Input Impedance See the Analog Inputs section THROUGHPUT SPEED Complete Cycle In warp mode 1 μs Throughput Rate In warp mode 1 1 MSPS Time Between Conversions In warp mode 1 ms Complete Cycle In normal mode 1.25 μs Throughput Rate In normal mode 0 800 kSPS Complete Cycle In impulse mode 1.49 μs Throughput Rate In impulse mode 0 670 kSPS DC ACCURACY Integral Linearity Error2 −1 ±0.3 +1 LSB3 No Missing Codes2 14 Bits Differential Linearity Error2 −1 +1 LSB Transition Noise 0.55 LSB Zero Error (Unipolar or Bipolar) −15 +15 LSB Zero Error Temperature Drift ±1 ppm/°C Full-Scale Error (Unipolar or Bipolar) −20 +20 LSB Full-Scale Error Temperature Drift ±1 ppm/°C Power Supply Sensitivity AVDD = 5 V ± 5% ±0.8 LSB AC ACCURACY Dynamic Range f = 2 kHz, −60 dB 84.5 85.5 dB4 IN Signal-to-Noise Ratio f = 2 kHz 84.5 85.5 dB IN f = 20 kHz 85.5 dB IN Signal-to-(Noise + Distortion) (SINAD) f = 2 kHz 83 85.4 dB IN Total Harmonic Distortion f = 2 kHz −105 dB IN Spurious-Free Dynamic Range f = 2 kHz 102 dB IN –3 dB Input Bandwidth V = 0 V to 5 V 45 MHz IN Aperture Delay 2 ns Aperture Jitter 5 ps rms Transient Response Full-scale step 500 ns INTERNAL REFERENCE PDREF = PDBUF = low Output Voltage REF @ 25°C 4.965 5.000 5.035 V Temperature Drift –40°C to +85°C ±3 ppm/°C Line Regulation AVDD = 5 V ± 5% ±15 ppm/V Long-Term Drift 1000 hours 50 ppm Turn-On Settling Time C = 22 µF 10 ms REF Rev. B | Page 3 of 32

AD7951 Data Sheet Parameter Conditions/Comments Min Typ Max Unit REFERENCE BUFFER PDREF = high REFBUFIN Input Voltage Range 2.4 2.5 2.6 V EXTERNAL REFERENCE PDREF = PDBUF = high Voltage Range REF 4.75 5 AVDD + 0.1 V Current Drain 1 MSPS throughput 200 µA TEMPERATURE PIN Voltage Output @ 25°C 311 mV Temperature Sensitivity 1 mV/°C Output Resistance 4.33 kΩ DIGITAL INPUTS Logic Levels V −0.3 +0.6 V IL V 2.1 OVDD + 0.3 V IH I −1 +1 µA IL I −1 +1 µA IH DIGITAL OUTPUTS Data Format Parallel or serial 14-bit Pipeline Delay5 V I = 500 µA 0.4 V OL SINK V I = –500 µA OVDD − 0.6 V OH SOURCE POWER SUPPLIES Specified Performance AVDD 4.756 5 5.25 V DVDD 4.75 5 5.25 V OVDD 2.7 5.25 V VCC 7 15 15.75 V VEE −15.75 −15 0 V Operating Current7, 8 @ 1 MSPS throughput AVDD With Internal Reference 20 mA With Internal Reference Disabled 18.5 mA DVDD 7 mA OVDD 0.5 mA VCC VCC = 15 V, with internal reference buffer 4 mA VCC = 15 V 3 mA VEE VEE = −15 V 2 mA Power Dissipation @ 1 MSPS throughput With Internal Reference PDREF = PDBUF = low 235 260 mW With Internal Reference Disabled PDREF = PDBUF = high 215 240 mW In Power-Down Mode9 PD = high 10 µW TEMPERATURE RANGE10 Specified Performance T to T −40 +85 °C MIN MAX 1 With VIN = 0 V to 5 V or 0 V to 10 V ranges, the input current is typically 100 μA. In all input ranges, the input current scales with throughput. See the Analog Inputs section. 2 Linearity is tested using endpoints, not best fit. All linearity is tested with an external 5 V reference. 3 LSB means least significant bit. All specifications in LSB do not include the error contributed by the reference. 4 All specifications in dB are referred to a full-scale range input, FSR. Tested with an input signal at 0.5 dB below full-scale, unless otherwise specified. 5 Conversion results are available immediately after completed conversion. 6 4.75 V or VREF – 0.1 V, whichever is larger. 7 Tested in parallel reading mode. 8 With internal reference, PDREF = PDBUF = low; with internal reference disabled, PDREF = PDBUF = high. With internal reference buffer, PDBUF = low. 9 With all digital inputs forced to OVDD. 10 Consult sales for extended temperature range. Rev. B | Page 4 of 32

Data Sheet AD7951 TIMING SPECIFICATIONS AVDD = DVDD = 5 V; OVDD = 2.7 V to 5.5 V; VCC = 15 V; VEE = −15 V; V = 5 V; all specifications T to T , unless otherwise noted. REF MIN MAX Table 3. Parameter Symbol Min Typ Max Unit CONVERSION AND RESET (See Figure 33 and Figure 34) Convert Pulse Width t 10 ns 1 Time Between Conversions t 2 Warp Mode/Normal Mode/Impulse Mode1 1/1.25/1.49 μs CNVST Low to BUSY High Delay t3 35 ns BUSY High All Modes (Except Master Serial Read After Convert) t 4 Warp Mode/Normal Mode/Impulse Mode 850/1100/1350 ns Aperture Delay t 2 ns 5 End of Conversion to BUSY Low Delay t 10 ns 6 Conversion Time t 7 Warp Mode/Normal Mode/Impulse Mode 850/1100/1350 ns Acquisition Time t 8 Warp Mode/Normal Mode/Impulse Mode 148 ns RESET Pulse Width t 10 ns 9 PARALLEL INTERFACE MODES (See Figure 35 and Figure 37) CNVST Low to DATA Valid Delay t10 Warp Mode/Normal Mode/Impulse Mode 850/1100/1350 ns DATA Valid to BUSY Low Delay t 20 ns 11 Bus Access Request to DATA Valid t 40 ns 12 Bus Relinquish Time t 2 15 ns 13 MASTER SERIAL INTERFACE MODES2 (See Figure 39 and Figure 40) CS Low to SYNC Valid Delay t14 10 ns CS Low to Internal SDCLK Valid Delay2 t15 10 ns CS Low to SDOUT Delay t16 10 ns CNVST Low to SYNC Delay, Read During Convert t17 Warp Mode/Normal Mode/Impulse Mode 50/290/530 ns SYNC Asserted to SDCLK First Edge Delay t 3 ns 18 Internal SDCLK Period3 t 30 45 ns 19 Internal SDCLK High3 t 15 ns 20 Internal SDCLK Low3 t 10 ns 21 SDOUT Valid Setup Time3 t 4 ns 22 SDOUT Valid Hold Time3 t 5 ns 23 SDCLK Last Edge to SYNC Delay3 t 5 ns 24 CS High to SYNC High-Z t25 10 ns CS High to Internal SDCLK High-Z t26 10 ns CS High to SDOUT High-Z t27 10 ns BUSY High in Master Serial Read After Convert3 t See Table 4 28 CNVST Low to SYNC Delay, Read After Convert t29 Warp Mode/Normal Mode/Impulse Mode 710/950/1190 ns SYNC Deasserted to BUSY Low Delay t 25 ns 30 Rev. B | Page 5 of 32

AD7951 Data Sheet Parameter Symbol Min Typ Max Unit SLAVE SERIAL/SERIAL CONFIGURATION INTERFACE MODES2 (See Figure 42, Figure 43, and Figure 45) External SDCLK, SCCLK Setup Time t 5 ns 31 External SDCLK Active Edge to SDOUT Delay t 2 18 ns 32 SDIN/SCIN Setup Time t 5 ns 33 SDIN/SCIN Hold Time t 5 ns 34 External SDCLK/SCCLK Period t 25 ns 35 External SDCLK/SCCLK High t 10 ns 36 External SDCLK/SCCLK Low t 10 ns 37 1 In warp mode only, the time between conversions is 1 ms; otherwise, there is no required maximum time. 2 In serial interface modes, the SDSYNC, SDSCLK, and SDOUT timings are defined with a maximum load CL of 10 pF; otherwise, the load is 60 pF maximum. 3 In serial master read during convert mode. See Table 4 for serial master read after convert mode. Table 4. Serial Clock Timings in Master Read After Convert Mode DIVSCLK[1] 0 0 1 1 DIVSCLK[0] Symbol 0 1 0 1 Unit SYNC to SDCLK First Edge Delay Minimum t 3 20 20 20 ns 18 Internal SDCLK Period Minimum t 30 60 120 240 ns 19 Internal SDCLK Period Maximum t 45 90 180 360 ns 19 Internal SDCLK High Minimum t 12 30 60 120 ns 20 Internal SDCLK Low Minimum t 10 25 55 115 ns 21 SDOUT Valid Setup Time Minimum t 4 20 20 20 ns 22 SDOUT Valid Hold Time Minimum t 5 8 35 90 ns 23 SDCLK Last Edge to SYNC Delay Minimum t 5 7 35 90 ns 24 BUSY High Width Maximum t 28 Warp Mode 1.60 2.35 3.75 6.75 µs Normal Mode 1.85 2.60 4.00 7.00 µs Impulse Mode 2.10 2.85 4.25 7.25 µs 1.6mA IOL TO OUTPUT 1.4V PIN CL 2V 60pF 0.8V tDELAY tDELAY N1 . O ISCNTLDE SOOSEUFRT 1I A0ApLRF EIN; ODTEETRFHIFEN5AR0ECW0DµE IAWS MEIOT, HTD HEAES IMO ,L HTAOHXAEIMD S UIYSMN 6 CL0,Op SFAC DMLAKX, IAMNUDM. 06396-002 20V.8V 02.V8V 06396-003 Figure 2. Load Circuit for Digital Interface Timing, Figure 3. Voltage Reference Levels for Timing SDOUT, SYNC, and SCLK Outputs, CL = 10 pF Rev. B | Page 6 of 32

Data Sheet AD7951 ABSOLUTE MAXIMUM RATINGS Stresses at or above those listed under Absolute Maximum Table 5. Ratings may cause permanent damage to the product. This is a Parameter Rating stress rating only; functional operation of the product at these Analog Inputs/Outputs or any other conditions above those indicated in the operational IN+1, IN−1 to AGND VEE − 0.3 V to VCC + 0.3 V section of this specification is not implied. Operation beyond REF, REFBUFIN, TEMP, AVDD + 0.3 V to REFGND to AGND AGND − 0.3 V the maximum operating conditions for extended periods may affect product reliability. Ground Voltage Differences AGND, DGND, OGND ±0.3 V ESD CAUTION Supply Voltages AVDD, DVDD, OVDD −0.3 V to +7 V AVDD to DVDD, AVDD to OVDD ±7 V DVDD to OVDD ±7 V VCC to AGND, DGND –0.3 V to +16.5 V VEE to GND +0.3 V to −16.5 V Digital Inputs −0.3 V to OVDD + 0.3 V PDREF, PDBUF2 ±20 mA Internal Power Dissipation3 700 mW Internal Power Dissipation4 2.5 W Junction Temperature 125°C Storage Temperature Range −65°C to +125°C 1 See the Analog Inputs section. 2 See the Voltage Reference Input section. 3 Specification is for the device in free air: 48-Lead LQFP; θJA = 91°C/W, θJC = 30°C/W. 4 Specification is for the device in free air: 48-Lead LFCSP; θJA = 26°C/W. Rev. B | Page 7 of 32

AD7951 Data Sheet PIN CONFIGURATION AND FUNCTION DESCRIPTIONS N FI D PDBUF PDREF REFBU TEMP AVDD IN+ AGND VEE VCC IN– REFGN REF 48 47 46 45 44 43 42 41 40 39 38 37 AGND 1 36 BIPOLAR AVDD 2 PIN 1 35 CNVST AGND 3 34 PD BYTESWAP 4 33 RESET OB/2C 5 32 CS AD7951 WARP 6 31 RD TOP VIEW IMPULSE 7 (Not to Scale) 30 TEN SER/PAR 8 29 BUSY NC 9 28 D13/SCCS NC 10 27 D12/SCCLK D0/DIVSCLK[0] 11 26 D11/SCIN D1/DIVSCLK[1] 12 25 D10/HW/SW 13 14 15 16 17 18 19 20 21 22 23 24 T C K N D D D D T K C R D2/EXT/IN D3/INVSYN D4/INVSCL D5/RDC/SDI OGN OVD DVD DGN D6/SDOU D7/SDCL D8/SYN D9/RDERRO NOTES 1.NC = NO CONNECT. 2.FPROAEDQR USTIHHROEE DUL LETDAO DB M EFE RCEAOTMN TENH ECECH ETIPLEE DSC CTTAORL IVCEE APELA. PCTEKHRAISFG OCEOR (MLNFNACENSCCPTE)IS,O T.NH IES ENXOPTOSED 06396-004 Figure 4. Pin Configuration Table 6. Pin Function Descriptions Pin No. Mnemonic Type1 Description 1, 3, 42 AGND P Analog Power Ground Pins. Ground reference point for all analog I/O. All analog I/O should be referenced to AGND and should be connected to the analog ground plane of the system. In addition, the AGND, DGND, and OGND voltages should be at the same potential. 2, 44 AVDD P Analog Power Pins. Nominally 4.75 V to 5.25 V and decoupled with 10 μF and 100 nF capacitors. 4 BYTESWAP DI Parallel Mode Selection (8-Bit/14-Bit). When high, the LSB is output on D[15:8] and the MSB is output on D[7:0]; when low, the LSB is output on D[7:0] and the MSB is output on D[15:8]. 5 OB/2C DI2 Straight Binary/Binary Twos Complement Output. When high, the digital output is straight binary. When low, the MSB is inverted resulting in a twos complement output from its internal shift register. 6 WARP DI2 Conversion Mode Selection. Used in conjunction with the IMPULSE input per the following: Conversion Mode WARP IMPULSE Normal Low Low Impulse Low High Warp High Low Normal High High See the Modes of Operation section for a more detailed description. 7 IMPULSE DI2 Conversion Mode Selection. See the WARP pin description in the previous row of this table. See the Modes of Operation section for a more detailed description. 8 SER/PAR DI Serial/Parallel Selection Input. When SER/PAR = low, the parallel mode is selected. When SER/PAR = high, the serial modes are selected. Some bits of the data bus are used as a serial port and the remaining data bits are high impedance outputs. 9, 10 NC DO No Connect. Do not connect. Rev. B | Page 8 of 32

Data Sheet AD7951 Pin No. Mnemonic Type1 Description 11, 12 D[0:1] or DI/O In parallel mode, these outputs are used as Bit 0 and Bit 1 of the parallel port data output bus. DIVSCLK[0:1] Serial Data Division Clock Selection. In serial master read after convert mode (SER/PAR = high, EXT/INT = low, RDC/SDIN = low) these inputs can be used to slow down the internally generated serial data clock that clocks the data output. In other serial modes, these pins are high impedance outputs. 13 D2 or DI/O In parallel mode, this output is used as Bit 2 of the parallel port data output bus. EXT/INT Serial Data Clock Source Select. In serial mode, this input is used to select the internally generated (master) or external (slave) serial data clock for the AD7951 output data. When EXT/INT = low, master mode; the internal serial data clock is selected on SDCLK output. When EXT/INT = high, slave mode; the output data is synchronized to an external clock signal (gated by CS) connected to the SDCLK input. 14 D3 or DI/O In parallel mode, this output is used as Bit 3 of the parallel port data output bus. INVSYNC Serial Data Invert Sync Select. In serial master mode (SER/PAR = high, EXT/INT = low). This input is used to select the active state of the SYNC signal. When INVSYNC = low, SYNC is active high. When INVSYNC = high, SYNC is active low. 15 D4 or DI/O In parallel mode, this output is used as Bit 4 of the parallel port data output bus. INVSCLK In all serial modes, invert SDCLK/SCCLK select. This input is used to invert both SDCLK and SCCLK. When INVSCLK = low, the rising edge of SDCLK/SCCLK are used. When INVSCLK = high, the falling edge of SDCLK/SCCLK are used. 16 D5 or DI/O In parallel mode, this output is used as Bit 5 of the parallel port data output bus. RDC or Serial Data Read During Convert. In serial master mode (SER/PAR = high, EXT/INT = low) RDC is used to select the read mode. Refer to the Master Serial Interface section. When RDC = low, the current result is read after conversion. Note the maximum throughput is not attainable in this mode. When RDC = high, the previous conversion result is read during the current conversion. SDIN Serial Data In. In serial slave mode (SER/PAR = high EXT/INT = high) SDIN can be used as a data input to daisy-chain the conversion results from two or more ADCs onto a single SDOUT line. The digital data level on SDIN is output on SDOUT with a delay of 16 SDCLK periods after the initiation of the read sequence. 17 OGND P Input/Output Interface Digital Power Ground. Ground reference point for digital outputs. Should be connected to the system digital ground ideally at the same potential as AGND and DGND. 18 OVDD P Input/Output Interface Digital Power. Nominally at the same supply as the supply of the host interface 2.5 V, 3 V, or 5 V and decoupled with 10 μF and 100 nF capacitors. 19 DVDD P Digital Power. Nominally at 4.75 V to 5.25 V and decoupled with 10 μF and 100 nF capacitors. Can be supplied from AVDD. 20 DGND P Digital Power Ground. Ground reference point for digital outputs. Should be connected to system digital ground ideally at the same potential as AGND and OGND. 21 D6 or DO In parallel mode, this output is used as Bit 6 of the parallel port data output bus. SDOUT Serial Data output. In all serial modes this pin is used as the serial data output synchronized to SDCLK. Conversion results are stored in an on-chip register. The AD7951 provides the conversion result, MSB first, from its internal shift register. The data format is determined by the logic level of OB/2C. When EXT/INT = low (master mode), SDOUT is valid on both edges of SDCLK. When EXT/INT = high (slave mode): When INVSCLK = low, SDOUT is updated on SDCLK rising edge. When INVSCLK = high, SDOUT is updated on SDCLK falling edge. 22 D7 or DI/O In parallel mode, this output is used as Bit 7 of the parallel port data output bus. SDCLK Serial Data Clock. In all serial modes, this pin is used as the serial data clock input or output, dependent on the logic state of the EXT/INT pin. The active edge where the data SDOUT is updated depends on the logic state of the INVSCLK pin. Rev. B | Page 9 of 32

AD7951 Data Sheet Pin No. Mnemonic Type1 Description 23 D8 or DO In parallel mode, this output is used as Bit 8 of the parallel port data output bus. SYNC Serial Data Frame Synchronization. In serial master mode (SER/PAR = high, EXT/INT= low), this output is used as a digital output frame synchronization for use with the internal data clock. When a read sequence is initiated and INVSYNC = low, SYNC is driven high and remains high while the SDOUT output is valid. When a read sequence is initiated and INVSYNC = high, SYNC is driven low and remains low while the SDOUT output is valid. 24 D9 or DO In parallel mode, this output is used as Bit 9 of the parallel port data output bus. RDERROR Serial Data Read Error. In serial slave mode (SER/PAR = high, EXT/INT = high), this output is used as an incomplete data read error flag. If a data read is started and not completed when the current conversion is complete, the current data is lost and RDERROR is pulsed high. 25 D10 or DI/O In parallel mode, this output is used as Bit 10 of the parallel port data output bus. HW/SW Serial Configuration Hardware/Software Select. In serial mode, this input is used to configure the AD7951 by hardware or software. See the Hardware Configuration section and Software Configuration section. When HW/SW = low, the AD7951 is configured through software using the serial configuration register. When HW/SW = high, the AD7951 is configured through dedicated hardware input pins. 26 D11 or DI/O In parallel mode, this output is used as Bit 11 of the parallel port data output bus. SCIN Serial Configuration Data Input. In serial software configuration mode (SER/PAR = high, HW/SW = low) this input is used to serially write in, MSB first, the configuration data into the serial configuration register. The data on this input is latched with SCCLK. See the Software Configuration section. 27 D12 or DI/O In parallel mode, this output is used as Bit 12 of the parallel port data output bus. SCCLK Serial Configuration Clock. In serial software configuration mode (SER/PAR = high, HW/SW = low) this input is used to clock in the data on SCIN. The active edge where the data SCIN is updated depends on the logic state of the INVSCLK pin. See the Software Configuration section. 28 D13 or DI/O In parallel mode, this output is used as Bit 13 of the parallel port data output bus. SCCS Serial Configuration Chip Select. In serial software configuration mode (SER/PAR = high, HW/SW = low) this input enables the serial configuration port. See the Software Configuration section. 29 BUSY DO Busy Output. Transitions high when a conversion is started, and remains high until the conversion is complete and the data is latched into the on-chip shift register. The falling edge of BUSY can be used as a data ready clock signal. Note that in master read after convert mode (SER/PAR = high, EXT/INT = low, RDC = low), the busy time changes according to Table 4. 30 TEN DI2 Input Range Select. Used in conjunction with BIPOLAR per the following: Input Range BIPOLAR TEN 0 V to 5 V Low Low 0 V to 10 V Low High ±5 V High Low ±10 V High High 31 RD DI Read Data. When CS and RD are both low, the interface parallel or serial output bus is enabled. 32 CS DI Chip Select. When CS and RD are both low, the interface parallel or serial output bus is enabled. CS is also used to gate the external clock in slave serial mode (not used for serial programmable port). 33 RESET DI Reset Input. When high, reset the AD7951. Current conversion, if any, is aborted. The falling edge of RESET resets the data outputs to all zeros (with OB/2C = high) and clears the configuration register. See the Digital Interface section. If not used, this pin can be tied to OGND. 34 PD DI2 Power-Down Input. When PD = high, powers down the ADC. Power consumption is reduced and conversions are inhibited after the current one is completed. The digital interface remains active during power-down. 35 CNVST DI Conversion Start. A falling edge on CNVST puts the internal sample-and-hold into the hold state and initiates a conversion. 36 BIPOLAR DI2 Input Range Select. See description for Pin 30. Rev. B | Page 10 of 32

Data Sheet AD7951 Pin No. Mnemonic Type1 Description 37 REF AI/O Reference Input/Output. When PDREF/PDBUF = low, the internal reference and buffer are enabled, producing 5 V on this pin. When PDREF/PDBUF = high, the internal reference and buffer are disabled, allowing an externally supplied voltage reference up to AVDD volts. Decoupling with at least a 22 μF is required with or without the internal reference and buffer. See the Reference Decoupling section. 38 REFGND AI Reference Input Analog Ground. Connected to analog ground plane. 39 IN− AI Analog Input Ground Sense. Should be connected to the analog ground plane or to a remote sense ground. 40 VCC P High Voltage Positive Supply. Normally +7 V to +15 V. 41 VEE P High Voltage Negative Supply. Normally 0 V to −15 V (0 V in unipolar ranges). 43 IN+ AI Analog Input. Referenced to IN−. 45 TEMP AO Temperature Sensor Analog Output. Enabled when the internal reference is turned on (PDREF = PDBUF = low). See the Temperature Sensor section. 46 REFBUFIN AI Reference Buffer Input. When using an external reference with the internal reference buffer (PDBUF = low, PDREF = high), applying 2.5 V on this pin produces 5 V on the REF pin. See the Voltage Reference Input section. 47 PDREF DI Internal Reference Power-Down Input. When low, the internal reference is enabled. When high, the internal reference is powered down, and an external reference must be used. 48 PDBUF DI Internal Reference Buffer Power-Down Input. When low, the buffer is enabled (must be low when using internal reference). When high, the buffer is powered-down. 49 EPAD3 NC Exposed Pad. The exposed pad is not connected internally. It is recommended that the pad be soldered to VEE. 1 AI = analog input; AI/O = bidirectional analog; AO = analog output; DI = digital input; DI/O = bidirectional digital; DO = digital output; P = power. 2 In serial configuration mode (SER/PAR = high, HW/SW = low), this input is programmed with the serial configuration register and this pin is a don’t care. See the Hardware Configuration section and Software Configuration section. 3 LFCSP_VQ package only. Rev. B | Page 11 of 32

AD7951 Data Sheet TYPICAL PERFORMANCE CHARACTERISTICS AVDD = DVDD = 5 V; OVDD = 5 V; VCC = 15 V; VEE = −15 V; V = 5 V; T = 25°C. REF A 1.0 1.0 POSITIVE INL = +0.15 POSITIVE DNL = +0.27 NEGATIVE INL = –0.15 NEGATIVE DNL = –0.27 0.5 0.5 B) B) S S NL (L 0 NL (L 0 I D –0.5 –0.5 –1.0 –1.0 0 4096 C8O19D2E 12288 16384 06396-005 0 4096 C8O19D2E 12288 16384 06396-008 Figure 5. Integral Nonlinearity vs. Code Figure 8. Differential Nonlinearity vs. Code 250 200 NEGATIVE INL NEGATIVE DNL POSITIVE INL POSITIVE DNL 180 200 160 S S 140 T T UNI 150 UNI 120 F F R O R O 100 E E MB 100 MB 80 U U N N 60 50 40 20 0 0 –1.0 –0.8 –0.6 –0I.N4L D–I0S.2TRIB0UTION0. 2(LSB0).4 0.6 0.8 1.006396-006 –1.0 –0.8 –0.6 –0D.N4L D–0IS.2TRIB0UTIO0N. 2(LSB0).4 0.6 0.8 1.006396-009 Figure 6. Integral Nonlinearity Distribution (239 Devices) Figure 9. Differential Nonlinearity Distribution (239 Devices) 300000 140000 132052 129068 261120 250000 120000 100000 200000 S S 80000 UNT150000 UNT O O C C 60000 100000 40000 50000 20000 0 1F0FF 20000 COD2E0 I0N1 HEX 20002 20003 06396-007 0 81092 81093 8C1O94DE IN H81E9X5 81096 81097 06396-010 Figure 7. Histogram of 261,120 Conversions of a DC Input Figure 10. Histogram of 261,120 Conversions of a DC Input at the Code Center at the Code Transition Rev. B | Page 12 of 32

Data Sheet AD7951 0 86.5 ffSIN == 11090.09k4SkHPzS dB) E) –20 STHNDR == –8150.47ddBB LE ( ULL SCAL ––6400 SSFINDARD = = 1 8156.d4BdB FULL SCA86.0 SNR F F TO B O –80 ED d R SINAD DE (–100 FER U E85.5 T R PLI–120 AD M N A SI –140 R, N S –160 85.0 0 100 FR20E0QUENCY (3k0H0z) 400 500 06396-011 –60 –50 –40INPUT L–E3V0EL (dB)–20 –10 0 06396-014 Figure 11. FFT 20 kHz Figure 14. SNR and SINAD vs. Input Level (Referred to Full Scale) 88 14.5 –70 120 –80 110 86 14.3 SFDR SNR B) SNR, SINAD (dB) 8824 ENOB SINAD 1134..91 ENOB (Bits) D, HARMONICS (d––11–109000 TTHHHADIRRMDONIC 8910000 SFDR (dB) H T SECOND 80 13.7 HARMONIC –120 70 781 FREQUE1N0CY (kHz) 10013.5 06396-012 –1301 FREQUE1N0CY (kHz) 10060 06396-015 Figure 12. SNR, SINAD, and ENOB vs. Frequency Figure 15. THD, Harmonics, and SFDR vs. Frequency 86.0 86.0 0V TO 5V 0V TO 5V 0V TO 10V 0V TO 10V ±5V ±5V ±10V ±10V 85.5 85.5 SNR (dB)85.0 SINAD (dB)85.0 84.5 84.5 84.0–55 –35 –15 5TEMP2E5RATU4R5E (°C)65 85 105 125 06396-013 84.0–55 –35 –15 5TEMP2E5RATU4R5E (°C6)5 85 105 125 06396-016 Figure 13. SNR vs. Temperature Figure 16. SINAD vs. Temperature Rev. B | Page 13 of 32

AD7951 Data Sheet –96 124 0V TO 5V 0V TO 5V 0V TO 10V 0V TO 10V ±5V 122 ±5V –100 ±10V ±10V 120 –104 118 THD (dB)–108 SFDR (dB) 111146 –112 112 110 –116 108 –120 106 –55 –35 –15 5TEMP2E5RATU4R5E (°C6)5 85 105 125 06396-017 –55 –35 –15 5TEMP2E5RATU4R5E (°C6)5 85 105 125 06396-020 Figure 17. THD vs. Temperature Figure 20. SFDR vs. Temperature (Excludes Harmonics) 1.5 5.008 B) ZERO ERROR S POSITIVE FS ERROR R (L 1.0 NEGATIVE FS ERROR 5.006 O R R E 0.5 5.004 E L LL SCA 0 REF (V)5.002 U V F OR, –0.5 5.000 R R E RO –1.0 4.998 E Z –1.5–55 –35 –15 5TEMP2E5RATU4R5E (°C6)5 85 105 125 06396-018 4.996–55 –35 –15 5TEMP2E5RATU4R5E (°C6)5 85 105 125 06396-021 Figure 18. Zero Error, Positive and Negative Full Scale vs. Temperature Figure 21. Typical Reference Voltage Output vs. Temperature (3 Devices) 60 100000 AVDD, WARP/NORMAL 10000 50 DVDD, ALL MODES µA) 1000 TS 40 TS ( F UNI RREN 100 R O 30 CU 10 AVDD, IMPULSE NUMBE 20 RATING 1 VVACELELC M–+11O55DVVES E P 0.1 O OVDD, ALL MODES 10 0.01 PDREF = PDBUF = HIGH 0 0 1 2REFER3ENCE D4RIFT (p5pm/°C)6 7 8 06396-019 0.00110 100 SAM10P0L0ING RAT1E00 (0S0PS) 100000 1000000 06396-022 Figure 19. Reference Voltage Temperature Coefficient Distribution (247 Devices) Figure 22. Operating Currents vs. Sample Rate Rev. B | Page 14 of 32

Data Sheet AD7951 700 50 nA) PD V=E PED =B –U1F5 V= PDREF = HIGH 45 OVDD = 2.7V @ 85°C S ( 600 VCC = +15V OVDD = 2.7V @ 25°C T DVDD 40 EN OVDD RR 500 AVDD 35 U C s) NG 400 Y(n 30 N OPERATI 300 tDELA12 2205 OVDD = 5V @ 25°C OVDD = 5V @ 85°C W 15 O 200 D – 10 R WE 100 5 O P 0 0 –55 –35 –15 TE5MPERA25TURE (4°5C) 65 85 105 06396-023 0 50 CL1 (0p0F) 150 200 06396-024 Figure 23. Power-Down Operating Currents vs. Temperature Figure 24. Typical Delay vs. Load Capacitance CL Rev. B | Page 15 of 32

AD7951 Data Sheet TERMINOLOGY Least Significant Bit (LSB) Total Harmonic Distortion (THD) The least significant bit, or LSB, is the smallest increment that THD is the ratio of the rms sum of the first five harmonic can be represented by a converter. For an analog-to-digital components to the rms value of a full-scale input signal and is converter with N bits of resolution, the LSB expressed in volts is expressed in decibels. V (max) Signal-to-(Noise + Distortion) Ratio (SINAD) LSB(V)= INp−2pN SINAD is the ratio of the rms value of the actual input signal to the rms sum of all other spectral components below the Nyquist Integral Nonlinearity Error (INL) frequency, including harmonics but excluding dc. The value for Linearity error refers to the deviation of each individual code SINAD is expressed in decibels. from a line drawn from negative full-scale through positive full- Spurious-Free Dynamic Range (SFDR) scale. The point used as negative full-scale occurs a ½ LSB The difference, in decibels (dB), between the rms amplitude of before the first code transition. Positive full-scale is defined as a the input signal and the peak spurious signal. level 1½ LSBs beyond the last code transition. The deviation is measured from the middle of each code to the true straight line. Effective Number of Bits (ENOB) ENOB is a measurement of the resolution with a sine wave Differential Nonlinearity Error (DNL) input. It is related to SINAD and is expressed in bits by In an ideal ADC, code transitions are 1 LSB apart. Differential nonlinearity is the maximum deviation from this ideal value. It ENOB = [(SINADdB − 1.76)/6.02] is often specified in terms of resolution for which no missing Aperture Delay codes are guaranteed. Aperture delay is a measure of the acquisition performance Bipolar Zero Error measured from the falling edge of the CNVST input to when The difference between the ideal midscale input voltage (0 V) the input signal is held for a conversion. and the actual voltage producing the midscale output code. Transient Response Unipolar Offset Error The time required for the AD7951 to achieve its rated accuracy The first transition should occur at a level ½ LSB above analog after a full-scale step function is applied to its input. ground. The unipolar offset error is the deviation of the actual Reference Voltage Temperature Coefficient transition from that point. Reference voltage temperature coefficient is derived from the Full-Scale Error typical shift of output voltage at 25°C on a sample of parts at the The last transition (from 111…10 to 111…11) should occur for maximum and minimum reference output voltage (V ) REF an analog voltage 1½ LSB below the nominal full-scale. The measured at T , T(25°C), and T . It is expressed in ppm/°C as MIN MAX full-scale error is the deviation in LSB (or % of full-scale range) V (Max)–V (Min) of the actual level of the last transition from the ideal level and TCV (ppm/°C)= REF REF ×106 REF V (25°C) × (T –T ) includes the effect of the offset error. Closely related is the gain REF MAX MIN error (also in LSB or % of full-scale range), which does not where: include the effects of the offset error. V (Max) = maximum V at T , T(25°C), or T . REF REF MIN MAX V (Min) = minimum V at T , T(25°C), or T . Dynamic Range REF REF MIN MAX V (25°C) = V at 25°C. Dynamic range is the ratio of the rms value of the full-scale to REF REF T = +85°C. the rms noise measured for an input typically at −60 dB. The MAX T = –40°C. value for dynamic range is expressed in decibels. MIN Signal-to-Noise Ratio (SNR) SNR is the ratio of the rms value of the actual input signal to the rms sum of all other spectral components below the Nyquist frequency, excluding harmonics and dc. The value for SNR is expressed in decibels. Rev. B | Page 16 of 32

Data Sheet AD7951 THEORY OF OPERATION IN+ REF REFGND SWITCHES CONTROL MSB LSB SWA 8,192C 4,096C 4C 2C C C BUSY CONTROL COMP LOGIC IN– OUTPUT 16,384C CODE SWB CNVST 06396-025 Figure 25. ADC Simplified Schematic OVERVIEW CONVERTER OPERATION The AD7951 is a very fast, low power, precise, 14-bit analog-to- The AD7951 is a successive approximation ADC based on a digital converter (ADC) using successive approximation capacitive charge redistribution DAC. Figure 25 shows the simplified digital-to-analog (CDAC) converter architecture. schematic of the ADC. The CDAC consists of two identical arrays of 16 binary weighted capacitors, which are connected to The AD7951 can be configured at any time for one of four input the two comparator inputs. ranges and conversion mode with inputs in parallel and serial hardware modes or by a dedicated write only, SPI-compatible During the acquisition phase, terminals of the array tied to the interface via a configuration register in serial software mode. comparator’s input are connected to AGND via SW+ and SW−. The AD7951 uses Analog Devices’ patented iCMOS high All independent switches are connected to the analog inputs. voltage process to accommodate 0 to 5 V, 0 to 10 V, ±5 V, and Thus, the capacitor arrays are used as sampling capacitors and ±10 V input ranges without the use of conventional thin films. acquire the analog signal on IN+ and IN− inputs. A conversion Only one acquisition cycle, t, is required for the inputs to latch to phase is initiated once the acquisition phase is complete and the 8 the correct configuration. Resetting or power cycling is not CNVST input goes low. When the conversion phase begins, required for reconfiguring the ADC. SW+ and SW− are opened first. The two capacitor arrays are The AD7951 features different modes to optimize performance then disconnected from the inputs and connected to the REFGND according to the applications. It is capable of converting input. Therefore, the differential voltage between the inputs 1,000,000 samples per second (1 MSPS) in warp mode, 800 kSPS (IN+ and IN−) captured at the end of the acquisition phase is in normal mode, and 670 kSPS in impulse mode. applied to the comparator inputs, causing the comparator to become unbalanced. By switching each element of the capacitor The AD7951 provides the user with an on-chip track-and-hold, array between REFGND and REF, the comparator input varies successive approximation ADC that does not exhibit any pipe- by binary weighted voltage steps (V /2, V /4 through V / REF REF REF line or latency, making it ideal for multiple, multiplexed channel 16,384). The control logic toggles these switches, starting with applications. the MSB first, in order to bring the comparator back into a For unipolar input ranges, the AD7951 typically requires three balanced condition. supplies; VCC, AVDD (which can supply DVDD), and OVDD After the completion of this process, the control logic generates which can be interfaced to either 5 V, 3.3 V, or 2.5 V digital the ADC output code and brings the BUSY output low. logic. For bipolar input ranges, the AD7951 requires the use of the additional VEE supply. The device is housed in Pb-free, 48-lead LQFP or tiny LFCSP 7 mm × 7 mm packages that combine space savings with flexibility. In addition, the AD7951 can be configured as either a parallel or a serial SPI-compatible interface. Rev. B | Page 17 of 32

AD7951 Data Sheet MODES OF OPERATION Impulse Mode Setting WARP = low and IMPULSE = high uses the lowest power The AD7951 features three modes of operation: warp, normal, dissipation mode and allows power saving between conversions. and impulse. Each of these modes is more suitable to specific The maximum throughput in this mode is 670 kSPS and in this applications. The mode is configured with the input pins, WARP mode, the ADC powers down circuits after conversion making and IMPULSE, or via the configuration register. See Table 6 for the AD7951 ideal for battery-powered applications. the pin details and the Hardware Configuration section and Software Configuration section for programming the mode TRANSFER FUNCTIONS selection with either pins or configuration register. Note that Using the OB/2C digital input or via the configuration register, when using the configuration register, the WARP and IMPULSE the AD7951 offers two output codings: straight binary and twos inputs are don’t cares and should be tied to either high or low. complement. See Figure 26 and Table 7 for the ideal transfer Warp Mode characteristic and digital output codes for the different analog Setting WARP = high and IMPULSE = low allows the fastest input ranges, VIN. Note that when using the configuration conversion rate up to 1 MSPS. However, in this mode, the full register, the OB/2C input is a don’t care and should be tied to specified accuracy is guaranteed only when the time between either high or low. conversions does not exceed 1 ms. If the time between two consecutive conversions is longer than 1 ms (after power-up), 111...111 the first conversion result should be ignored since in warp mode, y) 111...110 the ADC performs a background calibration during the SAR nar 111...101 Bi conversion process. This calibration can drift if the time between ht g conversions exceeds 1 ms thus causing the first conversion to Strai appear offset. This mode makes the AD7951 ideal for applications E ( D where both high accuracy and fast sample rate are required. CO C Normal Mode AD 000...010 Setting WARP = IMPULSE = low or WARP = IMPULSE = high 000...001 allows the fastest mode (800 kSPS) without any limitation on 000...000 tfoimr ea sbyentcwhereonn ocouns vaeprpsliiocnasti. oTnhsi ssu mcho daes dmaatak easc tqhuei sAitDio7n9 s5y1s tiedmeasl, ––FFSSRR +0.–5FLSSRB +1LSBANALOGINPU+TFSR –1.5+LFSSBR –1LSB 06396-026 where both high accuracy and fast sample rate are required. Figure 26. ADC Ideal Transfer Function Table 7. Output Codes and Ideal Input Voltages V = 5 V Digital Output Code REF Description V = 5 V V = 10 V V = ±5 V V = ±10 V Straight Binary Twos Complement IN IN IN IN FSR − 1 LSB 4.999695 V 9.999389 V +4.999389 V +9.998779 V 0x3FFF1 0x1FFF1 FSR − 2 LSB 4.999390 V 9.998779 V +4.998779 V +9.997558 V 0x3FFE 0x1FFE Midscale + 1 LSB 2.500305 V 5.000610 V +610.4 μV +1.221 mV 0x2001 0x0001 Midscale 2.5 V 5.000000 V 0 V 0 V 0x2000 0x0000 Midscale − 1 LSB 2.499695 V 4.999389 V −610.4 μV −1.221 mV 0x1FFF 0x3FFF −FSR + 1 LSB 305.2 μV 610.4 μV −4.999389 V −9.998779 V 0x0001 0x2001 −FSR 0 V 0 V −5 V −10 V 0x00002 0x20002 1 This is also the code for overrange analog input (VIN+ − VIN− above VREF − VREFGND). 2 This is also the code for overrange analog input (VIN+ − VIN− below VREF − VREFGND). Rev. B | Page 18 of 32

Data Sheet AD7951 TYPICAL CONNECTION DIAGRAM Figure 27 shows a typical connection diagram for the AD7951 using the internal reference, serial data and serial configuration interfaces. Different circuitry from that shown in Figure 27 is optional and is discussed in the following sections. DIGITAL NOTE 5 SUPPLY (5V) DIGITAL ANALOG 10Ω INTERFACE SUPPLY (5V) SUPPLY (2.5V, 3.3V, OR 5V) 10µF 100nF 10µF 100nF 100nF 10µF AVDD AGND DGND DVDD OVDD OGND +7V TO +15.75V SUPPLY VCC BUSY MICROCONVERTER/ 10µF 100nF MICROPROCESSOR/ DSP SDCLK SERIAL 10µF 100nF SDOUT PORT 1 SCCLK –7V TO –15.75V VEE SERIAL SUPPLY SCIN PORT 2 NOTE 6 REF NOTE 3 SCCS NOTE 4 C22RµEFF 100nF REFBUFIN 50ΩNOTE 7 REFGND CNVST D AD7951 OB/2C NOTE 2 SER/PAR OVDD 15Ω ANALOG U1 IN+ HW/SW INPUT+ BIPOLAR CC 2.7nF TEN CLOCK WARP ANALOG IMPULSE INPUT– IN– NOTE 3 NOTE 1 PDREF PDBUF PD RD CS RESET NOTES 1. SEE ANALOG INPUT SECTION. ANALOG INPUT(–) IS REFERENCED TO AGND ±0.1V. 2. THE AD8021 IS RECOMMENDED. SEE DRIVER AMPLIFIER CHOICE SECTION. 3. THE CONFIGURATION SHOWN IS USING THE INTERNAL REFERENCE. SEE VOLTAGE REFERENCE INPUT SECTION. 4.A 22µF CERAMIC CAPACITOR (X5R, 1206 SIZE) IS RECOMMENDED (FOR EXAMPLE, PANASONIC ECJ4YB1A226M). SEE VOLTAGE REFERENCE INPUT SECTION. 5. OPTION, SEE POWER SUPPLY SECTION. 6 7 .. OTFHOPETR I VOUCNNCAIP LAO NLLODA WRV E IJNEITP STUUETPR RP CALNNIEVGSSE TSS,H ,S OVEEUEEL C DCO ABNNEV EVBRCESC 0I VO=. N[SV ECINEO( MPNOTARWXO)E L+R 2S VSE]U CAPTNPIODLY NV .SEEEC =T [IOVINN.(MIN) –2V] FOR BIPOLAR INPUT RANGES. 06396-027 Figure 27. Typical Connection Diagram Shown with Serial Interface and Serial Programmable Port Rev. B | Page 19 of 32

AD7951 Data Sheet ANALOG INPUTS For instance, by using IN− to sense a remote signal ground, Input Range Selection ground potential differences between the sensor and the local ADC ground are eliminated. In parallel mode and serial hardware mode, the input range is selected by using the BIPOLAR (bipolar) and TEN (10 Volt 100 range) inputs. See Table 6 for pin details and the Hardware 90 Configuration section and Software Configuration section for 80 programming the mode selection with either pins or configuration 70 register. Note that when using the configuration register, the B) 60 BIPOLAR and TEN inputs are don’t cares and should be tied to d R ( 50 either high or low. R M C 40 Input Structure 30 Figure 28 shows an equivalent circuit for the input structure of 20 the AD7951. 10 0VTO 5V RANGE ONLY 0 VCC AVDD 1 10 FREQUE1N00CY (kHz) 1000 10000 06396-029 D1 D3 RIN CIN Figure 29. Analog Input CMRR vs. Frequency IN+ OR IN– During the acquisition phase for ac signals, the impedance of CPIN D2 D4 the analog inputs, IN+ and IN−, can be modeled as a parallel VEE AGND 06396-028 cseormiebsi cnoantinoenc otifo Cn aopfa RciINto arn CdP CINI Na.n Cd PtINh eis n pertiwmoarrki lfyo trhmee pdi nb y the Figure 28. AD7951 Simplified Analog Input capacitance. R is typically 70 Ω and is a lumped component IN The four diodes, D1 to D4, provide ESD protection for the analog comprised of serial resistors and the on resistance of the switches. inputs, IN+ and IN−. Care must be taken to ensure that the analog C is primarily the ADC sampling capacitor and depending on the IN input signal never exceeds the supply rails by more than 0.3 V, input range selected is typically 48 pF in the 0 V to 5 V range, because this causes the diodes to become forward-biased and to typically 24 pF in the 0 V to 10 V and ±5 V ranges and typically start conducting current. These diodes can handle a forward- 12 pF in the ±10 V range. During the conversion phase, when the biased current of 120 mA maximum. For instance, these conditions switches are opened, the input impedance is limited to C . PIN could eventually occur when the input buffer’s U1 supplies are Since the input impedance of the AD7951 is very high, it can be different from AVDD, VCC, and VEE. In such a case, an input directly driven by a low impedance source without gain error. buffer with a short-circuit current limitation can be used to protect To further improve the noise filtering achieved by the AD7951 the part although most op amps’ short circuit current is <100 mA. analog input circuit, an external, one-pole RC filter between the Note that D3 and D4 are only used in the 0 V to 5 V range to amplifier’s outputs and the ADC analog inputs can be used, as allow for additional protection in applications that are switching shown in Figure 27. However, large source impedances signifi- from the higher voltage ranges. cantly affect the ac performance, especially total harmonic This analog input structure allows the sampling of the differential distortion (THD). The maximum source impedance depends on signal between IN+ and IN−. By using this differential input, the amount of THD that can be tolerated. The THD degrades as small signals common to both inputs are rejected as shown in a function of the source impedance and the maximum input Figure 29, which represents the typical CMRR over frequency. frequency. Rev. B | Page 20 of 32

Data Sheet AD7951 DRIVER AMPLIFIER CHOICE The AD8021 meets these requirements and is appropriate for almost all applications. The AD8021 needs a 10 pF external Although the AD7951 is easy to drive, the driver amplifier must compensation capacitor that should have good linearity as an meet the following requirements: NPO ceramic or mica type. Moreover, the use of a noninverting  For multichannel, multiplexed applications, the driver +1 gain arrangement is recommended and helps to obtain the amplifier and the AD7951 analog input circuit must be best signal-to-noise ratio. able to settle for a full-scale step of the capacitor array at a The AD8022 can also be used when a dual version is needed 14-bit level (0.006%). For the amplifier, settling at 0.1% to and a gain of 1 is present. The AD829 is an alternative in applica- 0.01% is more commonly specified. This differs significantly tions where high frequency (above 100 kHz) performance is not from the settling time at a 14-bit level and should be required. In applications with a gain of 1, an 82 pF compensation verified prior to driver selection. The AD8021 op amp com- capacitor is required. The AD8610 is an option when low bias bines ultralow noise and high gain bandwidth and meets current is needed in low frequency applications. this settling time requirement even when used with gains of up to 13. Since the AD7951 uses a large geometry, high voltage input switch, the best linearity performance is obtained when using  The noise generated by the driver amplifier needs to be the amplifier at its maximum full power bandwidth. Gaining kept as low as possible to preserve the SNR and transition the amplifier to make use of the more dynamic range of the noise performance of the AD7951. The noise coming from ADC results in increased linearity errors. For applications the driver is filtered by the external one-pole low-pass filter requiring more resolution, the use of an additional amplifier as shown in Figure 27. The SNR degradation due to the with gain should precede a unity follower driving the AD7951. amplifier is See Table 8 for a list of recommended op amps.     Table 8. Recommended Driver Amplifiers  V  SNRLOSS 20log NADC  Amplifier Typical Application  V 2  f Ne 2 ADA4841-1/ 12 V supply, very low noise, low distortion,  NADC 2 3dB N  ADA4841-2 low power, low frequency AD829 ±15 V supplies, very low noise, low frequency where: AD8021 ±12 V supplies, very low noise, high frequency V is the noise of the ADC, which is: NADC AD8022 ±12 V supplies, very low noise, high V frequency, dual INp-p AD8610/ ±13 V supplies, low bias current, low 2 2 V  AD8620 frequency, single/dual NADC SNR 10 20 VOLTAGE REFERENCE INPUT/OUTPUT f is the cutoff frequency of the input filter (3.9 MHz). –3dB The AD7951 allows the choice of either a very low temperature N is the noise factor of the amplifier (+1 in buffer drift internal voltage reference, an external reference, or an configuration). external buffered reference. e is the equivalent input voltage noise density of the op N The internal reference of the AD7951 provides excellent perform- amp, in nV/√Hz. ance and can be used in almost all applications. However, the  The driver needs to have a THD performance suitable to linearity performance is guaranteed only with an external reference. that of the AD7951. Figure 15 shows the THD vs. frequency that the driver should exceed. Rev. B | Page 21 of 32

AD7951 Data Sheet Internal Reference (REF = 5 V) Temperature Sensor (PDREF = Low, PDBUF = Low) When the internal reference is enabled (PDREF = PDBUF = To use the internal reference, the PDREF and PDBUF inputs low), the on-chip temperature sensor output (TEMP) is enabled must be low. This enables the on-chip band gap reference, buffer, and can be use to measure the temperature of the AD7951. To and TEMP sensor resulting in a 5.00 V reference on the REF pin. improve the calibration accuracy over the temperature range, the output of the TEMP pin is applied to one of the inputs of the The internal reference is temperature-compensated to 5.000 V analog switch (such as ADG779), and the ADC itself is used to ±35 mV. The reference is trimmed to provide a typical drift of measure its own temperature. This configuration is shown 3 ppm/°C. This typical drift characteristic is shown in Figure 19. in Figure 30. External 2.5 V Reference and Internal Buffer (REF = 5 V) (PDREF = High, PDBUF = Low) TEMP ADG779 To use an external reference with the internal buffer, PDREF should be high and PDBUF should be low. This powers down ANALOG INPUT IN+ TSEEMNSPOERRATURE tthoe R iEntFeBrnUaFl rIeNfe prernocdeu acnindg a 5ll oVw os nth teh 2e. 5R VEF r epfeinre. nTchee t oin btee ranpapll ied CC AD7951 06396-030 reference buffer is useful in multiconverter applications because Figure 30. Use of the Temperature Sensor a buffer is typically required in these applications. POWER SUPPLIES External 5 V Reference (PDREF = High, PDBUF = High) The AD7951 uses five sets of power supply pins: To use an external reference directly on the REF pin, PDREF  AVDD: analog 5 V core supply and PDBUF should both be high. PDREF and PDBUF power  VCC: analog high voltage positive supply down the internal reference and the internal reference buffer,  VEE: high voltage negative supply respectively. For improved drift performance, an external  DVDD: digital 5 V core supply reference such as the ADR445 or ADR435 is recommended.  OVDD: digital input/output interface supply Reference Decoupling Core Supplies Whether using an internal or external reference, the AD7951 The AVDD and DVDD supply the AD7951 analog and digital voltage reference input (REF) has a dynamic input impedance; cores respectively. Sufficient decoupling of these supplies is therefore, it should be driven by a low impedance source with required consisting of at least a 10 μF capacitor and 100 nF on efficient decoupling between the REF and REFGND inputs. This each supply. The 100 nF capacitors should be placed as close as decoupling depends on the choice of the voltage reference, but possible to the AD7951. To reduce the number of supplies needed, usually consists of a low ESR capacitor connected to REF and the DVDD can be supplied through a simple RC filter from the REFGND with minimum parasitic inductance. A 22 μF (X5R, analog supply, as shown in Figure 27. 1206 size) ceramic chip capacitor (or 47 μF tantalum capacitor) is appropriate when using either the internal reference or the High Voltage Supplies ADR445/ADR435 external reference. The high voltage bipolar supplies, VCC and VEE are required The placement of the reference decoupling is also important to and must be at least 2 V larger than the maximum input, V . IN the performance of the AD7951. The decoupling capacitor should For example, if using the bipolar 10 V range, the supplies should be mounted on the same side as the ADC, right at the REF pin be ±12 V minimum. Sufficient decoupling of these supplies is with a thick PCB trace. The REFGND should also connect to also required consisting of at least a 10 μF capacitor and 100 nF the reference decoupling capacitor with the shortest distance on each supply. For unipolar operation, the VEE supply can be and to the analog ground plane with several vias. grounded with some slight THD performance degradation. For applications that use multiple AD7951 or other PulSAR Digital Output Supply devices, it is more effective to use the internal reference buffer The OVDD supplies the digital outputs and allows direct interface to buffer the external 2.5 V reference voltage. with any logic working between 2.3 V and 5.25 V. OVDD should The voltage reference temperature coefficient (TC) directly impacts be set to the same level as the system interface. Sufficient full scale; therefore, in applications where full-scale accuracy decoupling is required, consisting of at least a 10 μF capacitor and matters, care must be taken with the TC. For instance, a 100 nF with the 100 nF placed as close as possible to the AD7951. ±15 ppm/°C TC of the reference changes full-scale by ±1 LSB/°C. Rev. B | Page 22 of 32

Data Sheet AD7951 Power Sequencing Power Down The AD7951 requires sequencing of the AVDD and DVDD Setting PD = high powers down the AD7951, thus reducing supplies. AVDD should come up prior to or simultaneously supply currents to their minimums as shown in Figure 23. When with DVDD. This can be achieved using the configuration in the ADC is in power down, the current conversion (if any) is Figure 27 or sequencing the supplies in that manner. The completed and the digital bus remains active. To further reduce the digital supply currents, drive the inputs to OVDD or OGND. other supplies can be sequenced as desired as long as absolute maximum ratings are observed. The AD7951 is very insensitive Power down can also be programmed with the configuration to power supply variations on AVDD over a wide frequency register. See the Software Configuration section for details. Note range, as shown in Figure 31. that when using the configuration register, the PD input is a 80 don’t care and should be tied to either high or low. EXT REF 75 INT REF CONVERSION CONTROL 70 65 The AD7951 is controlled by the CNVST input. A falling edge B) 60 on CNVST is all that is necessary to initiate a conversion. Detailed (d timing diagrams of the conversion process are shown in Figure 33. R 55 R S Once initiated, it cannot be restarted or aborted, even by the P 50 power-down input, PD, until the conversion is complete. The 45 CNVST signal operates independently of CS and RD signals. 40 35 t2 30 t1 1 10 FREQUE1N0C0Y (kHz) 1000 10000 06396-031 CNVST Figure 31. AVDD PSRR vs. Frequency Power Dissipation vs. Throughput BUSY t4 In impulse mode, the AD7951 automatically reduces its power t3 t6 consumption at the end of each conversion phase. During the t5 acquisition phase, the operating currents are very low, which allows MODE ACQUIRE CONVERT ACQUIRE CONVERT a(s seieg Fniigfiucraen 3t 2p)o. wTehri ss afveiantgusr ew mheank eths et hcoe nAvDer7si9o5n1 r iadtee aisl rfoedr uvceerdy Figutr7e 33. Basic Conversiont8 Timing 06396-033 low power, battery-operated applications. Although CNVST is a digital signal, it should be designed with It should be noted that the digital interface remains active even special care with fast, clean edges, and levels with minimum during the acquisition phase. To reduce the operating digital supply overshoot, undershoot, or ringing. currents even further, drive the digital inputs close to the power The CNVST trace should be shielded with ground and a low value rails (that is, OVDD and OGND). (such as 50 Ω) serial resistor termination should be added close 1000 to the output of the component that drives this line. For applications where SNR is critical, the CNVST signal should W) have very low jitter. This can be achieved by using a dedicated N (m 100 WARP MODE POWER oscillator for CNVST generation, or by clocking CNVST with a O ATI high frequency, low jitter clock, as shown in Figure 27. P SI S DI R IMPULSE MODE POWER WE 10 O P 110 100 1000 100P0D0REF = 1P0D0B00U0F = HI1G0H00000 06396-032 Figure 32. Power Dissipation vs. Sample Rate Rev. B | Page 23 of 32

AD7951 Data Sheet INTERFACES DIGITAL INTERFACE CS = RD = 0 t1 The AD7951 has a versatile digital interface that can be set up CNVST as either a serial or a parallel interface with the host system. The serial interface is multiplexed on the parallel data bus. The AD7951 t10 digital interface also accommodates 2.5 V, 3.3 V, or 5 V logic. In BUSY t4 most applications, the OVDD supply pin is connected to the host t3 t11 system interface 2.5 V to 5.25 V digital supply. Finally, by using cthoed iOnBg /c2aCn ibnep uust epdi.n , both twos complement or straight binary DBAUTSA PREVIOUS CONVERSION DATA NEW DATA 06396-035 Figure 35. Master Parallel Data Timing for Reading (Continuous Read) Two signals, CS and RD, control the interface. When at least Slave Parallel Interface one of these signals is high, the interface outputs are in high In slave parallel reading mode, the data can be read either after impedance. Usually, CS allows the selection of each AD7951 in each conversion, which is during the next acquisition phase, or multicircuit applications and is held low in a single AD7951 during the following conversion, as shown in Figure 36 and design. RD is generally used to enable the conversion result on Figure 37, respectively. When the data is read during the conver- the data bus. sion, it is recommended that it is read only during the first half RESET of the conversion phase. This avoids any potential feedthrough The RESET input is used to reset the AD7951. A rising edge on between voltage transients on the digital interface and the most RESET aborts the current conversion (if any) and tristates the critical analog conversion circuitry. data bus. The falling edge of RESET resets the AD7951 and clears the data bus and configuration register. See Figure 34 for CS the RESET timing details. t9 RD RESET BUSY BUSY DATA BUS t8 DATA CURRENT BUS CONVERSION CNVST 06396-034 t12 t13 06396-036 Figure 34. RESET Timing Figure 36. Slave Parallel Data Timing for Reading (Read After Convert) PARALLEL INTERFACE CS = 0 The AD7951 is configured to use the parallel interface when SER/PAR is held low. CNVSRTD, t1 Master Parallel Interface Data can be continuously read by tying CS and RD low, thus requiring minimal microprocessor connections. However, in BUSY t4 this mode, the data bus is always driven and cannot be used in t3 shared bus applications (unless the device is held in RESET). Figure 35 details the timing for this mode. DATA PREVIOUS BUS t12 CONVERSIOt1N3 06396-037 Figure 37. Slave Parallel Data Timing for Reading (Read During Convert) Rev. B | Page 24 of 32

Data Sheet AD7951 8-Bit Interface (Master or Slave) MASTER SERIAL INTERFACE The BYTESWAP pin allows a glueless interface to an 8-bit bus. The pins multiplexed on D[8:0] and used for master serial As shown in Figure 38, when BYTESWAP is low, the LSB byte is interface are: DIVSCLK[0], DIVSCLK[1], EXT/INT, INVSYNC, output on D[7:0] and the MSB is output on D[13:8]. When INVSCLK, RDC, SDOUT, SDCLK and SYNC. BYTESWAP is high, the LSB and MSB bytes are swapped; the Internal Clock (SER/PAR = High, EXT/INT = Low) LSB is output on D[13:8] and the MSB is output on D[7:0]. By connecting BYTESWAP to an address line, the 14-bit data can The AD7951 is configured to generate and provide the serial be read in two bytes on either D[13:8] or D[7:0]. This interface data clock, SDCLK, when the EXT/INT pin is held low. The can be used in both master and slave parallel reading modes. AD7951 also generates a SYNC signal to indicate to the host when the serial data is valid. The SDCLK, and the SYNC signals can be inverted, if desired using the INVSCLK and INVSYNC CS inputs, respectively. Depending on the input, RDC, the data can be read during the following conversion or after each conversion. RD Figure 39 and Figure 40 show detailed timing diagrams of these two modes. BYTESWAP Read During Convert (RDC = High) HI-Z HI-Z Setting RDC = high, allows the master read (previous PINS D[13:8] HIGH BYTE LOW BYTE conversion result) during conversion mode. Usually, because PINS D[7:0] HI-Z t12LOW BYTE t12HIGH BYTt1E3 HI-Z 06396-038 tmhoe sAt Dre7c9o5m1m ise unsdeedd wseitrhia la m faosdt eth. Irno uthgihs pmuot,d teh, itsh me soedriea li sc ltohcek Figure 38. 8-Bit and 14-Bit Parallel Interface and data toggle at appropriate instances, minimizing potential feedthrough between digital activity and critical conversion SERIAL INTERFACE decisions. In this mode, the SDCLK period changes since the The AD7951 has a serial interface (SPI-compatible) multiplexed LSBs require more time to settle and the SDCLK is derived on the data pins D[13:0]. The AD7951 is configured to use the from the SAR conversion cycle. In this mode, the AD7951 serial interface when SER/PAR is held high. generates a discontinuous SDCLK of two different periods and Data Interface the host should use an SPI interface. The AD7951 outputs 14 bits of data, MSB first, on the SDOUT Read After Convert (RDC = Low, DIVSCLK[1:0] = [0 to 3]) pin. This data is synchronized with the 14 clock pulses provided Setting RDC = low allows the read after conversion mode. on the SDCLK pin. The output data is valid on both the rising Unlike the other serial modes, the BUSY signal returns low and falling edge of the data clock. after the 14 data bits are pulsed out and not at the end of the Serial Configuration Interface conversion phase, resulting in a longer BUSY width (refer to Table 4 for BUSY timing specifications). The DIVSCLK[1:0] The AD7951 can be configured through the serial configuration inputs control the SDCLK period and SDOUT data rate. As a register only in serial mode, as the serial configuration pins are result, the maximum throughput cannot be achieved in this also multiplexed on the data pins D[13:10]. Refer to the Hardware mode. In this mode, the AD7951 also generates a discontinuous Configuration section and Software Configuration section for SDCLK; however, a fixed period and hosts supporting both SPI more information. and serial ports can also be used. Rev. B | Page 25 of 32

AD7951 Data Sheet EXT/INT = 0 RDC/SDIN = 0 INVSCLK = INVSYNC = 0 CS, RD t3 CNVST BUSY t28 t30 t29 t25 SYNC t14 t18 t19 t20 t21 t24 t26 SDCLK 1 2 3 12 13 14 t15 t27 SDOUT X D13 D12 D2 D1 D0 t16 t22 t23 06396-039 Figure 39. Master Serial Data Timing for Reading (Read After Convert) EXT/INT = 0 RDC/SDIN = 1 INVSCLK = INVSYNC = 0 CS, RD t1 CNVST t3 BUSY t17 t25 SYNC t14 t19 t20 t21 t24 SDCLK t15 1 2 3 12 13 14 t26 t18 t27 SDOUT X D13 D12 D2 D1 D0 t16 t22 t23 06396-040 Figure 40. Master Serial Data Timing for Reading (Read Previous Conversion During Convert) Rev. B | Page 26 of 32

Data Sheet AD7951 SLAVE SERIAL INTERFACE Simultaneous sampling is possible by using a common CNVST signal. Note that the SDIN input is latched on the opposite edge The pins multiplexed on D[19:2] used for slave serial of SDCLK used to shift out the data on SDOUT (SDCLK falling interface are: EXT/INT, INVSCLK, SDIN, SDOUT, edge when INVSCLK = low). Therefore, the MSB of the SDCLK and RDERROR. upstream converter follows the LSB of the downstream External Clock (SER/PAR = High, EXT/INT = High) converter on the next SDCLK cycle. In this mode, the 40 MHz Setting the EXT/INT = high allows the AD7951 to accept an SDCLK rate cannot be used since the SDIN to SDCLK setup externally supplied serial data clock on the SDCLK pin. In this time, t33, is less than the minimum time specified. (SDCLK to mode, several methods can be used to read the data. The SDOUT delay, t32, is the same for all converters when external serial clock is gated by CS. When CS and RD are both simultaneously sampled). For proper operation, the SDCLK edge low, the data can be read after each conversion or during the for latching SDIN (or ½ period of SDCLK) needs to be: following conversion. A clock can be either normally high or t =t +t 1/2SDCLK 32 33 normally low when inactive. For detailed timing diagrams, see Or the max SDCLK frequency needs to be: Figure 42 and Figure 43. 1 While the AD7951 is performing a bit decision, it is important fSDCLK = 2(t +t ) that voltage transients be avoided on digital input/output pins, 32 33 or degradation of the conversion result may occur. This is If not using the daisy-chain feature, the SDIN input should particularly important during the last 450 ns of the conversion always be tied either high or low. phase because the AD7951 provides error correction circuitry BUSY that can correct for an improper bit decision made during the OUT first part of the conversion phase. For this reason, it is recom- BUSY BUSY mended that any external clock provided is a discontinuous AD7951 AD7951 clock that transitions only when BUSY is low or, more importantly, #2 #1 (UPSTREAM) (DOWNSTREAM) that it does not transition during the last 450 ns of BUSY high. RDC/SDIN SDOUT RDC/SDIN SDOUT DOAUTTA External Discontinuous Clock Data Read After Conversion CNVST CNVST CS CS Though the maximum throughput cannot be achieved using SCLK SCLK this mode, it is the most recommended of the serial slave modes. Figure 42 shows the detailed timing diagrams for this method. SCLK IN Athfete cro an cvoenrsvieornsi ornes iusl ct ocmanp lbeete r, einadd iwcahteilde bbyo BthU CSYS arentdu rRnDin ga rloe wlo, w. CNVCSST IINN 06396-041 Figure 41. Two AD7951 Devices in a Daisy-Chain Configuration Data is shifted out MSB first with 14 clock pulses and, depending on the SDCLK frequency, can be valid on the falling and rising External Clock Data Read During Previous Conversion edges of the clock. Figure 43 shows the detailed timing diagrams for this method. One advantage of this method is that conversion performance is During a conversion, while both CS and RD are low, the result not degraded because there are no voltage transients on the digital of the previous conversion can be read. The data is shifted out, interface during the conversion process. Another advantage is MSB first, with 14 clock pulses, and depending on the SDCLK the ability to read the data at any speed up to 40 MHz, which frequency, can be valid on both the falling and rising edges of accommodates both the slow digital host interface and the fastest the clock. The 14 bits have to be read before the current serial reading. conversion is complete; otherwise, RDERROR is pulsed high Daisy-Chain Feature and can be used to interrupt the host interface to prevent incomplete data reading. Also in the read after convert mode, the AD7951 provides a daisy-chain feature for cascading multiple converters together To reduce performance degradation due to digital activity, a fast using the serial data input pin, SDIN. This feature is useful for discontinuous clock of at least 40 MHz is recommended to ensure reducing component count and wiring connections when that all the bits are read during the first half of the SAR desired, for instance, in isolated multiconverter applications. conversion phase. See Figure 42 for the timing details. The daisy-chain feature should not be used in this mode since An example of the concatenation of two devices is shown in digital activity occurs during the second half of the SAR Figure 41. conversion phase, likely resulting in performance degradation. Rev. B | Page 27 of 32

AD7951 Data Sheet External Clock Data Read After/During Conversion discontinuous SDCLK whenever possible to minimize potential incorrect bit decisions. For the different modes, the use of a slower It is also possible to begin to read data after conversion and SDCLK such as 20 MHz in warp mode, 15 MHz in normal mode continue to read the last bits after a new conversion has been and 13 MHz in impulse mode can be used. initiated. This method allows the full throughput and the use of a slower SDCLK frequency. Again, it is recommended to use a SER/PAR = 1 EXT/INT = 1 INVSCLK = 0 RD = 0 CS BUSY t31 t31 t35 t36 SDCLK X* 1 2 3 4 12 13 14 15 16 17 t32 t37 SDOUT D13 D12 D11 D2 D1 D0 X13 X12 t16 SDIN X13 X12 X11 X2 X1 X0 Y13 Y12 *A DISCONTINUOUS SDCLK IS RtE33COMMENDED. t34 06396-042 Figure 42. Slave Serial Data Timing for Reading (Read After Convert) SER/PAR = 1 EXT/INT = 1 INVSCLK = 0 RD = 0 CS CNVST BUSY t31 t31 t35 t36 SDCLK X* 1 2 3 13 14 X* X* X* X* X* t32 t37 SDOUT D13 D12 D1 D0 DATA = SDIN *A DISCONTINUtO16US SDCLK IS RECOMMENDED. t27 06396-043 Figure 43. Slave Serial Data Timing for Reading (Read Previous Conversion During Convert) Rev. B | Page 28 of 32

Data Sheet AD7951 HARDWARE CONFIGURATION it is not recommended to write to the SCP during the last 450 ns of conversion (BUSY = high), or performance degradation can The AD7951 can be configured at any time with the dedicated result. In addition, the SCP can be accessed in both serial master hardware pins WARP, IMPULSE, BIPOLAR, TEN, OB/2C, and and serial slave read during and read after convert modes. PD for parallel mode (SER/PAR = low) or serial hardware mode (SER/ PAR = high, HW/SW = high). Programming the AD7951 Note that at power up, the configuration register is undefined. The RESET input clears the configuration register (sets all bits for mode selection and input range configuration can be done to 0), thus placing the configuration to 0 V to 5 V input, normal before or during conversion. Like the RESET input, the ADC mode, and twos complemented output. requires at least one acquisition time to settle as indicated in Figure 44. See Table 6 for pin descriptions. Note that these Table 9. Configuration Register Description inputs are high impedance when using the software Bit Name Description configuration mode. 8 START START bit. With the SCP enabled (SCCS = low), SOFTWARE CONFIGURATION when START is high, the first rising edge of SCCLK (INVSCLK = low) begins to load the register with The pins multiplexed on D[13:10] used for software configura- the new configuration. tion are: HW/SW, SCIN, SCCLK, and SCCS. The AD7951 is 7 BIPOLAR Input Range Select. Used in conjunction with programmed using the dedicated write-only serial configurable Bit 6, TEN, per the following: port (SCP) for conversion mode, input range selection, output Input Range BIPOLAR TEN coding, and power-down using the serial configuration register. 0 V to 5 V Low Low See Table 9 for details of each bit in the configuration register. 0 V to 10 V Low 1 ±5 V High Low The SCP can only be used in serial software mode selected with ±10 V High High SER/PAR = high and HW/SW = low since the port is multiplexed 6 TEN Input Range Select. See Bit 7, BIPOLAR. on the parallel interface. 5 PD Power Down. The SCP is accessed by asserting the port’s chip select, SCCS, PD = low, normal operation. and then writing SCIN synchronized with SCCLK, which (like PD = high power down the ADC. The SCP is accessible while in power down. To power up the SDCLK) is edge sensitive depending on the state of INVSCLK. ADC, write PD = low on the next configuration See Figure 45 for timing details. SCIN is clocked into the con- setting. figuration register MSB first. The configuration register is an 4 IMPULSE Mode Select. Used in conjunction with Bit 3, internal shift register that begins with Bit 8, the start bit. The 9th WARP, per the following: SPPCLK edge updates the register and allows the new settings to be Mode WARP IMPULSE used. As indicated in the timing diagram, at least one acquisition Normal Low Low time is required from the 9th SCCLK edge. Bits [1:0] are reserved Impulse Low High bits and are not written to while the SCP is being updated. Warp High Low Normal High High The SCP can be written to at any time, up to 40 MHz, and it is 3 WARP Mode Select. See Bit 4, IMPULSE. recommended to write to while the AD7951 is not busy 2 OB/2C Output Coding converting, as detailed in Figure 45. In this mode, the full OB/2C = low, use twos complement output. 1 MSPS is not attainable because the time required for SCP access OB/2C = high, use straight binary output. is (t31 + 9 × 1/SCCLK + t8) minimum. If the full throughput is 1 RSV Reserved. required, the SCP can be written to during conversion, however, 0 RSV Reserved. HW/SW = 0 PD = 0 SER/PAR = 0, 1 t8 t8 CNVST BUSY BIPOLAR, TEN IMPWUALRSPE, 06396-044 Figure 44. Hardware Configuration Timing Rev. B | Page 29 of 32

AD7951 Data Sheet WARP = 0 OR 1 BIP = 0 OR 1 SER/PAR = 1 INVSCLK = 0 IMPULSE = 0 OR 1 TEN = 0 OR 1 HW/SW = 0 PD = 0 t8 CNVST BUSY t31 SCCS t31 t35 t36 SCCLK 1 2 3 4 5 6 7 8 9 t37 SCIN X START BIPOLAR TEN PD IMPULSE WARP OB/2C X t33 t34 Figure 45. Serial Configuration Port Timing 06396-045 MICROPROCESSOR INTERFACING the DSP. The serial peripheral interface (SPI) on the ADSP-219x is configured for master mode (MSTR) = 1, clock polarity bit The AD7951 is ideally suited for traditional dc measurement (CPOL) = 0, clock phase bit (CPHA) = 1, and SPI interrupt enable applications supporting a microprocessor, and ac signal (TIMOD) = 0 by writing to the SPI control register (SPICLTx). processing applications interfacing to a digital signal processor. The AD7951 is designed to interface with a parallel 8-bit or It should be noted that to meet all timing requirements, the SPI 14-bit wide interface, or with a general-purpose serial port or clock should be limited to 17 Mbps, allowing it to read an ADC I/O ports on a microcontroller. A variety of external buffers can result in less than 1 μs. When a higher sampling rate is desired, be used with the AD7951 to prevent digital noise from coupling use one of the parallel interface modes. into the ADC. DVDD SPI Interface AD7951* ADSP-219x* The AD7951 is compatible with SPI and QSPI digital hosts and SER/PAR DSPs such as Blackfin® ADSP-BF53x and ADSP-218x/ADSP-219x. BUSY PFx EXT/INT Figure 46 shows an interface diagram between the AD7951 and CS SPIxSEL (PFx) SDOUT MISOx the SPI-equipped ADSP-219x. To accommodate the slower RD SCLK SCKx speed of the DSP, the AD7951 acts as a slave device, and data must INVSCLK CNVST PFx OR TFSx bfeea trueared. aTfhteer ccoonnvveerrts cioonm. mThainsd m coodueld a blseo ianliltoiawtse dth ien draeisspyo-nchsea itno *ADDITIONAL PINS OMITTED FOR CLARITY. 06396-046 an internal timer interrupt. Figure 46. Interfacing the AD7951 to SPI Interface The reading process can be initiated in response to the end-of- conversion signal (BUSY going low) using an interrupt line of Rev. B | Page 30 of 32

Data Sheet AD7951 APPLICATION INFORMATION LAYOUT GUIDELINES The DVDD supply of the AD7951 can either be a separate supply or come from the analog supply, AVDD, or from the digital While the AD7951 has very good immunity to noise on the interface supply, OVDD. When the system digital supply is noisy, power supplies, exercise care with the grounding layout. To or fast switching digital signals are present, and no separate supply facilitate the use of ground planes that can be easily separated, is available, it is recommended to connect the DVDD digital supply design the printed circuit board that houses the AD7951 so that to the analog supply AVDD through an RC filter, and to connect the analog and digital sections are separated and confined to the system supply to the interface digital supply OVDD and the certain areas of the board. Digital and analog ground planes remaining digital circuitry. See Figure 27 for an example of this should be joined in only one place, preferably underneath the configuration. When DVDD is powered from the system supply, AD7951, or as close as possible to the AD7951. If the AD7951 is it is useful to insert a bead to further reduce high frequency spikes. in a system where multiple devices require analog-to-digital ground connections, the connections should still be made at one The AD7951 has four different ground pins: REFGND, AGND, point only, a star ground point, established as close as possible to DGND, and OGND. the AD7951. • REFGND senses the reference voltage and, because it carries To prevent coupling noise onto the die, avoid radiating noise, pulsed currents, should be a low impedance return to the and to reduce feedthrough: reference. • Do not run digital lines under the device. • AGND is the ground to which most internal ADC analog signals are referenced; it must be connected with the least • Do run the analog ground plane under the AD7951. resistance to the analog ground plane. • Shield fast switching signals, like CNVST or clocks, with • DGND must be tied to the analog or digital ground plane digital ground to avoid radiating noise to other sections of depending on the configuration. the board, and never run them near analog signal paths. • OGND is connected to the digital system ground. • Avoid crossover of digital and analog signals. The layout of the decoupling of the reference voltage is important. • Run traces on different but close layers of the board, at right To minimize parasitic inductances, place the decoupling capacitor angles to each other, to reduce the effect of feedthrough through close to the ADC and connect it with short, thick traces. the board. The power supply lines to the AD7951 should use as large a trace as possible to provide low impedance paths and reduce the effect of glitches on the power supply lines. Good decoupling is also important to lower the impedance of the supplies presented to the AD7951, and to reduce the magnitude of the supply spikes. Decoupled ceramic capacitors, typically 100 nF, should be placed on each of the power supplies pins, AVDD, DVDD, and OVDD, VCC, and VEE. The capacitors should be placed close to, and ideally right up against, these pins and their corresponding ground pins. Additionally, low ESR 10 µF capacitors should be located in the vicinity of the ADC to further reduce low frequency ripple. Rev. B | Page 31 of 32

AD7951 Data Sheet OUTLINE DIMENSIONS 9.20 0.75 9.00 SQ 1.60 0.60 MAX 8.80 0.45 48 37 1 36 PIN 1 7.20 1.45 TOP VIEW 7.00 SQ 1.40 0.20 (PINS DOWN) 6.80 0.09 1.35 7° 3.5° 12 25 0.15 0° 13 24 0.05 SPELAANTEING 0C.O08PLANARITY VIEW A 0.50 0.27 BSC 0.22 LEAD PITCH 0.17 VIEW A ROTATED 90° CCW COMPLIANTTO JEDEC STANDARDS MS-026-BBC 051706-A Figure 47. 48-Lead Low Profile Quad Flat Package [LQFP] (ST-48) Dimensions shown in millimeters 7.10 0.30 7.00 SQ 0.60 MAX 0.23 6.90 0.60 MAX 0.18 PIN 1 37 48 INDICATOR 36 1 PIN 1 INDICATOR 0.50 66..8755 SQ REF EXPOSED 5.25 6.65 PAD 5.10 SQ 4.95 25 12 0.50 24 13 0.25 MIN TOP VIEW 0.40 5.50 REF 0.30 12° MAX 0.80 MAX 1.00 0.85 0.65 TYP FOR PROPER CONNECTION OF 0.80 0.05 MAX TTHHEE EPXINP COOSENDFI GPAUDR,A RTEIOFNE RA NTOD 0.02 NOM FUNCTION DESCRIPTIONS SEATING COPL0A.0N8ARITY SECTION OF THIS DATA SHEET. PLANE 0.20 REF COMPLIANT TO JEDEC STANDARDS MO-220-VKKD-2 06-05-2012-A Figure 48. 48-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 7 mm × 7 mm Body, Very Thin Quad (CP-48-1) Dimensions shown in millimeters ORDERING GUIDE Model1 Temperature Range Package Description Package Option AD7951BCPZ −40°C to +85°C 48-Lead Lead Frame Chip Scale Package [LFCSP_VQ] CP-48-1 AD7951BCPZRL −40°C to +85°C 48-Lead Lead Frame Chip Scale Package [LFCSP_VQ] CP-48-1 AD7951BSTZ −40°C to +85°C 48-Lead Low Profile Quad Flat Package [LQFP] ST-48 AD7951BSTZRL −40°C to +85°C 48-Lead Low Profile Quad Flat Package [LQFP] ST-48 1 Z = RoHS Compliant Part. ©2006–2015 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D06396-0-5/15(B) Rev. B | Page 32 of 32

Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: A nalog Devices Inc.: AD7951BSTZ AD7951BCPZRL AD7951BSTZRL AD7951BCPZ