14-Bit, 8-Channel, 250 kSPS PulSAR ADC Enhanced Product AD7949-EP FEATURES FUNCTIONAL BLOCK DIAGRAM 14-bit resolution with no missing codes 0.5V TO VDD – 0.5V 0.5V TO VDD 2.3V TO 5.5V 0.1µF 10µF 8-channel multiplexer with choice of inputs Unipolar single-ended REFIN REF VDD Differential (GND sense) BAND GAP 1.8V Pseudobipolar REF AD7949-EP VIOTVODD Throughput: 250 kSPS TEMP INL/DNL: ±0.5/±0.25 LSB typical SENSOR SINAD: 85 dB at 20 kHz IN0 CNV IN1 THD: −100 dB at 20 kHz IN2 MUX 14-BIT SAR SPI SERIAL SCK Analog input range: 0 V to V with V up to VDD IN3 ADC INTERFACE SDO REF REF IN4 Multiple reference types IN5 ONE-POLE DIN IN6 LPF Internal selectable 2.5 V or 4.096 V IN7 SEQUENCER External buffered (up to 4.096 V) COM External (up to VDD) GND 09822-001 Internal temperature sensor (TEMP) Figure 1. Channel sequencer, selectable 1-pole filter, busy indicator No pipeline delay, SAR architecture GENERAL DESCRIPTION Single-supply 2.3 V to 5.5 V operation with The AD7949-EP is an 8-channel, 14-bit, charge redistribution 1.8 V to 5.5 V logic interface successive approximation register (SAR) analog-to-digital Serial interface compatible with SPI, MICROWIRE, converter (ADC) that operates from a single power supply, VDD. QSPI, and DSP Power dissipation The AD7949-EP contains all components for use in a multi- 2.9 mW at 2.5 V/200 kSPS channel, low power data acquisition system, including a true 10.8 mW at 5 V/250 kSPS 14-bit SAR ADC with no missing codes; an 8-channel, low Standby current: 50 nA crosstalk multiplexer that is useful for configuring the inputs as 20-lead 4 mm × 4 mm LFCSP package single-ended (with or without ground sense), differential, or Supports defense and aerospace applications (AQEC bipolar; an internal low drift reference (selectable 2.5 V or 4.096 V) standard) and buffer; a temperature sensor; a selectable one-pole filter; Military temperature range (−55°C to +125°C) and a sequencer that is useful when channels are continuously Controlled manufacturing baseline scanned in order. Enhanced product change notification The AD7949-EP uses a simple SPI interface for writing to the Qualification data available on request configuration register and receiving conversion results. The SPI APPLICATIONS interface uses a separate supply, VIO, which is set to the host logic level. Power dissipation scales with throughput. Multichannel system monitoring Battery-powered equipment The AD7949-EP is housed in a tiny 20-lead LFCSP with operation Medical instruments: ECG/EKG specified from −55°C to +125°C. Full details about this enhanced Mobile communications: GPS product are available in the AD7949 data sheet, which should Power line monitoring be consulted in conjunction with this data sheet. Data acquisition Table 1. Multichannel 14-/16-Bit PulSAR® ADCs Seismic data acquisition systems Type Channels 250 kSPS 500 kSPS ADC Driver Instrumentation 14-Bit 8 AD7949 ADA4841-1 Process control 16-Bit 4 AD7682 ADA4841-1 16-Bit 8 AD7689 AD7699 ADA4841-1 Rev. B Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Tel: 781.329.4700 ©2011–2018 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com

AD7949-EP Enhanced Product TABLE OF CONTENTS Features .............................................................................................. 1 Absolute Maximum Ratings ............................................................7 Applications ....................................................................................... 1 ESD Caution...................................................................................7 Functional Block Diagram .............................................................. 1 Pin Configuration and Function Descriptions ..............................8 General Description ......................................................................... 1 Typical Performance Characteristics ..............................................9 Revision History ............................................................................... 2 Outline Dimensions ....................................................................... 12 Specifications ..................................................................................... 3 Ordering Guide .......................................................................... 12 Timing Specifications .................................................................. 5 REVISION HISTORY 5/2018—Rev. A to Rev. B Updated Outline Dimensions ....................................................... 12 Changes to Ordering Guide .......................................................... 12 5/2015—Rev. 0 to Rev. A Changes to Table 1 ............................................................................ 1 Updated Outline Dimensions ....................................................... 12 Changes to Ordering Guide .......................................................... 12 4/2011—Revision 0: Initial Version Rev. B | Page 2 of 12

Enhanced Product AD7949-EP SPECIFICATIONS VDD = 2.3 V to 5.5 V, VIO = 1.8 V to VDD, V = VDD, all specifications −55°C to +125°C, unless otherwise noted. REF Table 2. Parameter Test Conditions/Comments Min Typ Max Unit RESOLUTION 14 Bits ANALOG INPUT Voltage Range Unipolar mode 0 +V V REF Bipolar mode −V /2 +V /2 REF REF Absolute Input Voltage Positive input, unipolar and bipolar modes −0.1 V + 0.1 V REF Negative or COM input, unipolar mode −0.1 +0.1 Negative or COM input, bipolar mode V /2 − 0.1 V /2 V /2 + 0.1 REF REF REF Analog Input CMRR f = 250 kHz 68 dB IN Leakage Current at 25°C Acquisition phase 1 nA Input Impedance1 THROUGHPUT Conversion Rate Full Bandwidth2 VDD = 4.5 V to 5.5 V 0 250 kSPS VDD = 2.3 V to 4.5 V 0 200 kSPS ¼ Bandwidth2 VDD = 4.5 V to 5.5 V 0 62.5 kSPS VDD = 2.3 V to 4.5 V 0 50 kSPS Transient Response Full-scale step, full bandwidth 1.8 μs Full-scale step, ¼ bandwidth 14.5 μs ACCURACY No Missing Codes 14 Bits Integral Linearity Error −1 ±0.5 +1 LSB3 Differential Linearity Error −1 ±0.25 +1 LSB Transition Noise REF = VDD = 5 V 0.1 LSB Gain Error4 −5 ±0.5 +5 LSB Gain Error Match −1 ±0.2 +1 LSB Gain Error Temperature Drift ±1 ppm/°C Offset Error4 ±0.5 LSB Offset Error Match −1 ±0.2 +1 LSB Offset Error Temperature Drift ±1 ppm/°C Power Supply Sensitivity VDD = 5 V ± 5% ±0.2 LSB AC ACCURACY5 Dynamic Range 85.6 dB6 Signal-to-Noise f = 20 kHz, V = 5 V 84.5 85.5 dB IN REF f = 20 kHz, V = 4.096 V internal REF 85 dB IN REF f = 20 kHz, V = 2.5 V internal REF 84 dB IN REF SINAD f = 20 kHz, V = 5 V 84 85 dB IN REF f = 20 kHz, V = 5 V, −60 dB input 33.5 dB IN REF f = 20 kHz, V = 4.096 V internal REF 85 dB IN REF f = 20 kHz, V = 2.5 V internal REF 84 dB IN REF Total Harmonic Distortion f = 20 kHz −100 dB IN Spurious-Free Dynamic Range f = 20 kHz 108 dB IN Channel-to-Channel Crosstalk f = 100 kHz on adjacent channel(s) −125 dB IN SAMPLING DYNAMICS −3 dB Input Bandwidth Full bandwidth 1.7 MHz ¼ bandwidth 0.425 MHz Aperture Delay VDD = 5 V 2.5 ns Rev. B | Page 3 of 12

AD7949-EP Enhanced Product Parameter Test Conditions/Comments Min Typ Max Unit INTERNAL REFERENCE REF Output Voltage 2.5 V, at 25°C 2.490 2.500 2.510 V 4.096 V, at 25°C 4.086 4.096 4.106 V REFIN Output Voltage7 2.5 V, at 25°C 1.2 V 4.096 V, at 25°C 2.3 V REF Output Current ±300 µA Temperature Drift ±10 ppm/°C Line Regulation VDD = 5 V ± 5% ±15 ppm/V Long-Term Drift 1000 hours 50 ppm Turn-On Settling Time CREF = 10 µF 5 ms EXTERNAL REFERENCE Voltage Range REF input 0.5 VDD + 0.3 V REFIN input (buffered) 0.5 VDD − 0.5 V Current Drain 250 kSPS, REF = 5 V 50 µA TEMPERATURE SENSOR Output Voltage8 At 25°C 283 mV Temperature Sensitivity 1 mV/°C DIGITAL INPUTS Logic Levels V −0.3 +0.3 × VIO V IL V 0.7 × VIO VIO + 0.3 V IH I −1 +1 µA IL I −1 +1 µA IH DIGITAL OUTPUTS Data Format9 Pipeline Delay10 V I = +500 µA 0.4 V OL SINK V I = −500 µA VIO − 0.3 V OH SOURCE POWER SUPPLIES VDD Specified performance 2.3 5.5 V VIO Specified performance 2.3 VDD + 0.3 V Operating range 1.8 VDD + 0.3 V Standby Current11, 12 VDD and VIO = 5 V, at 25°C 50 nA Power Dissipation VDD = 2.5 V, 100 SPS throughput 1.5 µW VDD = 2.5 V, 100 kSPS throughput 1.45 2.0 mW VDD = 2.5 V, 200 kSPS throughput 2.9 4.0 mW VDD = 5 V, 250 kSPS throughput 10.8 12.5 mW VDD = 5 V, 250 kSPS throughput with internal 13.5 15.5 mW reference Energy per Conversion 50 nJ TEMPERATURE RANGE13 Specified Performance T to T −55 +125 °C MIN MAX 1 See the AD7949 data sheet. 2 The bandwidth is set in the configuration register. 3 LSB means least significant bit. With the 5 V input range, one LSB = 305 µV. 4 See the AD7949 data sheet. These specifications include full temperature range variation but not the error contribution from the external reference. 5 With VDD = 5 V, unless otherwise noted. 6 All specifications expressed in decibels are referred to a full-scale input FSR and tested with an input signal at 0.5 dB below full scale, unless otherwise specified. 7 This is the output from the internal band gap. 8 The output voltage is internal and present on a dedicated multiplexer input. 9 Unipolar mode: serial 14-bit straight binary. Bipolar mode: serial 14-bit twos complement. 10 Conversion results available immediately after completed conversion. 11 With all digital inputs forced to VIO or GND as required. 12 During acquisition phase. 13 Contact an Analog Devices, Inc., sales representative for the extended temperature range. Rev. B | Page 4 of 12

Enhanced Product AD7949-EP TIMING SPECIFICATIONS VDD = 4.5 V to 5.5 V, VIO = 1.8 V to VDD, all specifications −55°C to +125°C, unless otherwise noted. Table 3. Parameter1 Symbol Min Typ Max Unit Conversion Time: CNV Rising Edge to Data Available t 2.2 µs CONV Acquisition Time t 1.8 µs ACQ Time Between Conversions t 4.0 µs CYC Data Write/Read During Conversion t 1.0 µs DATA CNV Pulse Width t 10 ns CNVH SCK Period t t + 2 ns SCK DSDO SCK Low Time t 11 ns SCKL SCK High Time t 11 ns SCKH SCK Falling Edge to Data Remains Valid t 4 ns HSDO SCK Falling Edge to Data Valid Delay t DSDO VIO Above 2.7 V 18 ns VIO Above 2.3 V 23 ns VIO Above 1.8 V 28 ns CNV Low to SDO D15 MSB Valid t EN VIO Above 2.7 V 18 ns VIO Above 2.3 V 22 ns VIO Above 1.8 V 25 ns CNV High or Last SCK Falling Edge to SDO High Impedance t 32 ns DIS CNV Low to SCK Rising Edge t 10 ns CLSCK DIN Valid Setup Time from SCK Rising Edge t 5 ns SDIN DIN Valid Hold Time from SCK Rising Edge t 5 ns HDIN 1 See Figure 2 and Figure 3 for load conditions. Rev. B | Page 5 of 12

AD7949-EP Enhanced Product VDD = 2.3 V to 4.5 V, VIO = 1.8 V to VDD, all specifications −55°C to +125°C, unless otherwise noted. Table 4. Parameter1 Symbol Min Typ Max Unit Conversion Time: CNV Rising Edge to Data Available t 3.2 µs CONV Acquisition Time t 1.8 µs ACQ Time Between Conversions t 5 µs CYC Data Write/Read During Conversion t 1.2 µs DATA CNV Pulse Width t 10 ns CNVH SCK Period t t + 2 ns SCK DSDO SCK Low Time t 12 ns SCKL SCK High Time t 12 ns SCKH SCK Falling Edge to Data Remains Valid t 5 ns HSDO SCK Falling Edge to Data Valid Delay t DSDO VIO Above 3 V 24 ns VIO Above 2.7 V 30 ns VIO Above 2.3 V 38 ns VIO Above 1.8 V 48 ns CNV Low to SDO D15 MSB Valid t EN VIO Above 3 V 21 ns VIO Above 2.7 V 27 ns VIO Above 2.3 V 35 ns VIO Above 1.8 V 45 ns CNV High or Last SCK Falling Edge to SDO High Impedance t 50 ns DIS CNV Low to SCK Rising Edge t 10 ns CLSCK DIN Valid Setup Time from SCK Rising Edge t 5 ns SDIN DIN Valid Hold Time from SCK Rising Edge t 5 ns HDIN 1 See Figure 2 and Figure 3 for load conditions. 500µA IOL TOSDO 1.4V CL 50pF 500µA IOH 09822-002 Figure 2. Load Circuit for Digital Interface Timing 70% VIO 30% VIO tDELAY tDELAY 2V OR VIO – 0.5V1 2V OR VIO – 0.5V1 0.8V OR 0.5V2 0.8V OR 0.5V2 12 20V.8 VIF I FV IVOI OA BAOBVOEV E2. 52V.5,V V, I0O.5 –V 0I.F5 VV IIOF VBIEOL OBEWL 2O.W5V .2.5V. 09822-003 Figure 3. Voltage Levels for Timing Rev. B | Page 6 of 12

Enhanced Product AD7949-EP ABSOLUTE MAXIMUM RATINGS Table 5. Stresses at or above those listed under Absolute Maximum Parameter Rating Ratings may cause permanent damage to the product. This is a Analog Inputs stress rating only; functional operation of the product at these INx, COM1 GND − 0.3 V to VDD + 0.3 V or any other conditions above those indicated in the operational or VDD ± 130 mA section of this specification is not implied. Operation beyond REF, REFIN GND − 0.3 V to VDD + 0.3 V the maximum operating conditions for extended periods may Supply Voltages affect product reliability. VDD, VIO to GND −0.3 V to +7 V ESD CAUTION VIO to VDD −0.3 V to VDD + 0.3 V DIN, CNV, SCK to GND −0.3 V to VIO + 0.3 V SDO to GND −0.3 V to VIO + 0.3 V Storage Temperature Range −65°C to +150°C Junction Temperature 150°C θJA Thermal Impedance (LFCSP) 47.6°C/W θ Thermal Impedance (LFCSP) 4.4°C/W JC 1 See the AD7949 data sheet. Rev. B | Page 7 of 12

AD7949-EP Enhanced Product PIN CONFIGURATION AND FUNCTION DESCRIPTIONS D DV3NI2NI1NI0NI 09876 21111 VDD 1 15 VIO REF 2 AD7949-EP 14 SDO REFIN 3 TOP VIEW 13 SCK GND 4 (Not to Scale) 12 DIN GND 5 11 CNV 67890 1 4 567 M NI NININI OC NOTES 1. THE EXPOSEDPAD IS NOT CONNECTED INTERNALLY. FOR INCREASED RELIABILITY OF THE SOLDER JOINTS, IT ISGSOR RLOEDUCENORDME PDMLTEAONND ETEH.DE TSHYASTT ETHMEPAD BE 09822-004 Figure 4. Pin Configuration Table 6. Pin Function Descriptions Pin No. Mnemonic Type1 Description 1, 20 VDD P Power Supply. Nominally 2.5 V to 5.5 V when using an external reference and decoupled with 10 μF and 100 nF capacitors. When using the internal reference for 2.5 V output, the minimum should be 3.0 V. When using the internal reference for 4.096 V output, the minimum should be 4.5 V. 2 REF AI/O Reference Input/Output. See the AD7949 data sheet. When the internal reference is enabled, this pin produces a selectable system reference = 2.5 V or 4.096 V. When the internal reference is disabled and the buffer is enabled, REF produces a buffered version of the voltage present on the REFIN pin (4.096 V maximum), useful when using low cost, low power references. For improved drift performance, connect a precision reference to REF (0.5 V to VDD). For any reference method, this pin needs decoupling with an external 10 μF capacitor connected as close to REF as possible. See the AD7949 data sheet. 3 REFIN AI/O Internal Reference Output/Reference Buffer Input. See the AD7949 data sheet. When using the internal reference, the internal unbuffered reference voltage is present and needs decoupling with a 0.1 μF capacitor. When using the internal reference buffer, apply a source between 0.5 V and 4.096 V that is buffered to the REF pin as described above. 4, 5 GND P Power Supply Ground. 6 to 9 IN4 to IN7 AI Channel 4 through Channel 7 Analog Inputs. 10 COM AI Common Channel Input. All input channels, IN[7:0], can be referenced to a common-mode point of 0 V or V /2 V. REF 11 CNV DI Convert Input. On the rising edge, CNV initiates the conversion. During conversion, if CNV is held high, the busy indictor is enabled. 12 DIN DI Data Input. This input is used for writing to the 14-bit configuration register. The configuration register can be written to during and after conversion. 13 SCK DI Serial Data Clock Input. This input is used to clock out the data on SDO and clock in data on DIN in an MSB first fashion. 14 SDO DO Serial Data Output. The conversion result is output on this pin, synchronized to SCK. In unipolar modes, conversion results are straight binary; in bipolar modes, conversion results are twos complement. 15 VIO P Input/Output Interface Digital Power. Nominally at the same supply as the host interface (1.8 V, 2.5 V, 3 V, or 5 V). 16 to 19 IN0 to IN3 AI Channel 0 through Channel 3 Analog Inputs. 21 Exposed Pad NC The exposed pad is not connected internally. For increased reliability of the solder joints, it is (EPAD) (EPAD) recommended that the pad be soldered to the system ground plane. 1 AI = analog input, AI/O = analog input/output, DI = digital input, DO = digital output, and P = power. Rev. B | Page 8 of 12

Enhanced Product AD7949-EP TYPICAL PERFORMANCE CHARACTERISTICS VDD = 2.5 V to 5.5 V, V = 2.5 V to 5 V, VIO = 2.3 V to VDD, unless otherwise noted. REF 1.0 1.0 0.5 0.5 B) B) NL (LS 0 NL (LS 0 I D –0.5 –0.5 –1.00 4,096 C8O,1D9E2S 12,288 16,384 09822-005 –1.00 4,096 C8O,1D9E2S 12,288 16,384 09822-008 Figure 5. Integral Nonlinearity vs. Code, VREF = VDD = 5 V Figure 8. Differential Nonlinearity vs. Code, VREF = VDD = 5 V 300k 300k 261,120 VREF = VDD = 5V 259,473 VREF = VDD = 2.5V 250k 250k 200k 200k S S T T N N U 150k U150k O O C C 100k 100k 50k 50k 0 0 0 1 0 0 0 0 0 0 0 955 693 0 0 0 0 1FFC 1FFD 1FFE C1FOFDFE IN2 0H0E0X 2001 2002 2003 09822-006 0 1FFC 1FFD 1FFE 1FFCFOD2E0 0IN0 HE2X001 2002 2003 2004 09822-009 Figure 6. Histogram of a DC Input at Code Center Figure 9. Histogram of a DC Input at Code Center 0 0 VREF= VDD = 5V VREF= VDD = 2.5V –20 fS= 250kSPS –20 fs= 200kSPS fIN = 19.9kHz fIN = 19.9kHz cale) –40 SSNINRA D= 8=5 8.35d.2BdB cale) –40 SSNINRA D= 8=4 8.22d.4BdB S THD = –100dB S THD = –84dB dB of Full- ––6800 SSTHFEDICRROD N= HD 1A 0HR3AMdRBOMNOICN I=C – =1 0–31d1B0dB dB of Full- ––6800 SSTHFEDICRROD N= HD 8A 5HRdAMBROMNOICN I=C – =8 5–d1B00dB E ( E ( –100 D D U –100 U LIT LIT –120 P P M –120 M A A –140 –140 –160 –1600 25 FR5E0QUENCY (k7H5z) 100 125 09822-007 –1800 25 FREQUE5N0CY (kHz) 75 100 09822-010 Figure 7. 20 kHz FFT, VREF = VDD = 5 V Figure 10. 20 kHz FFT, VREF = VDD = 2.5 V Rev. B | Page 9 of 12

AD7949-EP Enhanced Product 90 90 85 85 80 80 NR (dB) 75 NAD (dB) 75 S SI 70 70 VDD = VREF = 5V, –0.5dB VDD = VREF = 5V, –0.5dB VDD = VREF = 5V, –10dB VDD = VREF = 5V, –10dB 65 VDD = VREF = 2.5V, –0.5dB 65 VDD = VREF = 2.5V, –0.5dB VDD = VREF = 2.5V, –10dB VDD = VREF = 2.5V, –10dB 600 50 FREQUE10N0CY (kHz) 150 200 09822-011 600 50 FREQUE10N0CY (kHz) 150 200 09822-014 Figure 11. SNR vs. Frequency Figure 14. SINAD vs. Frequency 88 15.5 130 –60 SNR 125 –65 SINAD ENOB 120 –70 86 15.0 115 –75 NR, SINAD (dB)8842 1144..50 ENOB (Bits) SFDR (dB)11110090505 SFDR ––––88990505 THD (dB) S 90 THD –100 85 –105 80 13.5 80 –110 75 –115 781.0 1.5 2.0 RE2.F5ERE3N.C0E VO3L.5TAGE4. 0(V) 4.5 5.0 5.513.0 09822-012 701.0 1.5 2.0 R2E.F5ERE3N.C0E VO3L.5TAG4E. 0(V) 4.5 5.0 5.5–120 09822-015 Figure 12. SNR, SINAD, and ENOB vs. Reference Voltage Figure 15. SFDR and THD vs. Reference Voltage 90 –90 fIN = 20kHz fIN = 20kHz VDD= VREF = 5V 85 –95 80 VDD= VREF = 2.5V VDD= VREF = 5V dB) dB) VDD= VREF = 2.5V R (75 D (–100 N H S T 70 –105 65 60–55 –35 –15 5TEMP2E5RATU4R5E (°C6)5 85 105 125 09822-013 –110–55 –35 –15 5TEMP2E5RATU4R5E (°C6)5 85 105 125 09822-016 Figure 13. SNR vs. Temperature Figure 16. THD vs. Temperature Rev. B | Page 10 of 12

Enhanced Product AD7949-EP –60 2750 100 2.5VINTERNALREF fS = 200kSPS 2500 4.096VINTERNALREF 90 –70 INTERNALBUFFER,TEMPON INTERNALBUFFER,TEMPOFF 2250 EXTERNALREF,TEMPON 80 –80 A) EXTERNALREF,TEMPOFF A) B) NT (µ2000 VIO 70 NT (µ THD (d –90 CURRE1750 60 CURRE D 1500 50 O –100 VD VI VDD = VREF = 5V, –0.5dB 1250 40 –110 VDD = VREF = 2.5V, –0.5dB VDD = VREF = 2.5V, –10dB 1000 30 VDD = VREF = 5V, –10dB –1200 50 FREQUE10N0CY (kHz) 150 200 09822-017 7502.5 3.0 3.5VDD SU4.P0PLY (V)4.5 5.0 5.520 09822-020 Figure 17. THD vs. Frequency Figure 20. Operating Currents vs. Supply 90 3000 180 89 fIN = 20kHz fS = 200kSPS 2750 160 88 87 2500 140 B) 8865 VDD= VREF = 5V NT (µA) 2250 VDD=5V,INTERNAL4.096VREF 120 NT (µA) SNR (d 8843 VDD= VREF = 2.5V CURRE 2000 VDD=5V,EXTERNALREF 100 CURRE D 1750 80 O 82 VD VI 81 1500 VDD=2.5,EXTERNALREF VIO 60 80 1250 40 79 78–10 –8 IN–P6UT LEVEL –(d4B) –2 0 09822-018 1000–55 –35 –15 5TEMP2E5RATU4R5E (°C6)5 85 105 12520 09822-021 Figure 18. SNR vs. Input Level Figure 21. Operating Currents vs. Temperature 2 B) S L R ( O 1 R R E N AI G D 0 N A R O R R E T –1 UNIPOLARZERO E S UNIPOLARGAIN FF BIPOLARZERO O BIPOLARGAIN –2–55 –35 –15 5TEMP2E5RATU4R5E (°C6)5 85 105 125 09822-019 Figure 19. Offset and Gain Errors vs. Temperature Rev. B | Page 11 of 12

AD7949-EP Enhanced Product OUTLINE DIMENSIONS DETAIL A (JEDEC 95) 4.10 0.30 4.00 SQ 0.25 PIN 1 3.90 0.20 INDICATOR PIN 1 0.50 16 20 I(NSDEEIC DAETTAOIRL AAR)EA OPTIONS BSC 15 1 2.65 EXPPAODSED 2.50 SQ 2.35 11 5 0.50 10 6 0.20 MIN TOP VIEW BOTTOM VIEW 0.40 0.30 0.80 FOR PROPER CONNECTION OF 0.75 SIDE VIEW THE EXPOSED PAD, REFER TO 0.05 MAX THE PIN CONFIGURATION AND 0.70 0.02 NOM FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. COPLANARITY SEATING 0.08 PKG-003578 PLANE COMPLIANTTOJEDE0C.2 S0T RAENFDARDS MO-220-WGGD-11. 10-12-2017-C Figure 22. 20-Lead Lead Frame Chip Scale Package (LFCSP) 4 mm × 4 mm Body and 0.75 mm Package Height (CP-20-10) Dimensions shown in millimeters ORDERING GUIDE Temperature Package Ordering Model1 Range Package Description Option Quantity AD7949SCPZ-EP-RL7 –55°C to +125°C 20-Lead LFCSP, 7” Tape and Reel CP-20-10 1,500 AD7949SCPZ-EP-R2 –55°C to +125°C 20-Lead LFCSP, 7” Tape and Reel CP-20-10 1,500 1 Z = RoHS Compliant Part. ©2011–2018 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D09822-0-5/18(B) Rev. B | Page 12 of 12

Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: A nalog Devices Inc.: AD7949BCPZRL7 AD7949SCPZ-EP-RL7 AD7949BCPZ EVAL-AD7949EDZ AD7949SCPZ-EP-R2