a +3.3 V/+5 V Multiplying 12-Bit DACs AD7943/AD7945/AD7948 FEATURES FUNCTIONAL BLOCK DIAGRAMS 12-Bit Multiplying DACs Guaranteed Specifications with +3.3 V/+5 V Supply VDD RFB 0.5 LSBs INL and DNL AD7943 Low Power: 5 (cid:109)W typ VREF 12-BIT DAC IIOOUUTT12 Fast Interface 40 ns Strobe Pulsewidth (AD7943) CLLDR1 DAC REGISTER AGND 40 ns Write Pulsewidth (AD7945, AD7948) LD2 Low Glitch: 60 nV-s with Amplifier Connected Fast Settling: 600 ns to 0.01% with AD843 SRI INPUT SHIFT REGISTER SRO APPLICATIONS Battery-Powered Instrumentation Laptop Computers Upgrades for All 754x Series DACs (5 V Designs) STB1 STB2 STB3 STB4 DGND VDD RFB GENERAL DESCRIPTION AD7945 The AD7943, AD7945 and AD7948 are fast 12-bit multiplying IOUT1 DACs that operate from a single +5 V supply (Normal Mode) VREF 12-BIT DAC AGND and a single +3.3 V to +5 V supply (Biased Mode). The 12 AD7943 has a serial interface, the AD7945 has a 12-bit parallel CS INPUT LATCH WR interface, and the AD7948 has an 8-bit byte interface. They will 12 replace the industry-standard AD7543, AD7545 and AD7548 in many applications, and they offer superior speed and power DB11–DB0 DGND consumption performance. VDD RFB The AD7943 is available in 16-lead DIP, 16-lead SOP (Small OPauctkliangee )P.ackage) and 20-lead SSOP (Shrink Small Outline VREF 12-BIT DAC AIOGUNT1D 12 AD7948 The AD7945 is available in 20-lead DIP, 20-lead SOP and 20- DF/DOR lead SSOP. DATA OVERRIDE LOGIC CTRL The AD7948 is available in 20-lead DIP, 20-lead SOP and 20- 12 lead SSOP. DAC REGISTER LDAC 12 WR CONTROL INPUT REGISTERS LOGIC CSLSB 12 DATA STEERING LOGIC CSMSB 8 DB7–DB0 DGND REV.B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. which may result from its use. No license is granted by implication or Tel: 781/329-4700 World Wide Web Site: http://www.analog.com otherwise under any patent or patent rights of Analog Devices. Fax: 781/326-8703 © Analog Devices, Inc., 1998

AD7943/AD7945/AD7948–SPECIFICATIONS1 NORMAL MODE (AD7943: V = +4.5 V to +5.5 V; V = V = AGND = 0 V; V = +10 V; T = T to T , unless otherwise noted. DD IOUT1 IOUT2 REF A MIN MAX AD7945, AD7948: V = +4.5 V to +5.5 V; V = AGND = 0 V; V = +10 V; T = T to T , unless otherwise noted.) DD IOUT1 REF A MIN MAX Parameter B Grades2 T Grade2, 3 Units Test Conditions/Comments ACCURACY Resolution 12 12 Bits 1LSB=V /212=2.44mVwhenV =10V REF REF Relative Accuracy – 0.5 – 0.5 LSB max Differential Nonlinearity – 0.5 – 0.5 LSB max All Grades Guaranteed Monotonic over Temperature Gain Error T to T – 2 – 2 LSB max MIN MAX Gain Temperature Coefficient4 2 2 ppm FSR/(cid:176) C typ 5 5 ppm FSR/(cid:176) C max Output Leakage Current I OUT1 @ +25(cid:176) C 10 10 nA max See Terminology Section T to T 100 100 nA max Typically 20 nA over Temperature MIN MAX REFERENCE INPUT Input Resistance 6 6 kW min Typical Input Resistance = 9 kW 12 12 kW max DIGITAL INPUTS V , Input High Voltage 2.4 2.4 V min INH V , Input Low Voltage 0.8 0.8 V max INL I , Input Current – 1 – 1 m A max INH C , Input Capacitance4 10 10 pF max IN DIGITAL OUTPUT (AD7943 SRO) For 1 CMOS Load Output Low Voltage (V ) 0.2 0.2 V max OL Output High Voltage (V ) V – 0.2 V – 0.2 V min OH DD DD POWER REQUIREMENTS V Range 4.5/5.5 4.5/5.5 V min/V max DD Power Supply Sensitivity4 D Gain/D V –75 –75 dB typ DD I (AD7943) 5 5 m A max V = V – 0.1 V min, V = 0.1 V max. DD INH DD INL SRO Open Circuit. No STB Signal. Typically 1 m A. Typically 100 m A with a 1 MHz STB Frequency. At Input Levels of 0.8 V and 2.4 V, I Is Typically 2.5 mA. DD I (AD7945, AD7948) 5 5 m A max V = V – 0.1 V min, V = 0.1 V max. DD INH DD INL Typically 1 m A. At Input Levels of 0.8 V and 2.4 V, I Is Typically 2.5 mA. DD NOTES 1The AD7943, AD7945 and AD7948 are specified in the normal current mode configuration and in the biased current mode for single-supply applications. Figures 14 and 15 are examples of normal mode operation. 2Temperature ranges as follows: B Grades: –40(cid:176) C to +85(cid:176)C; T Grade: –55(cid:176) C to +125(cid:176)C. 3The T Grade applies to the AD7945 only. 4Guaranteed by design. Specifications subject to change without notice. –2– REV. B

AD7943/AD7945/AD7948 SPECIFICATIONS1 BIASED MODE (AD7943: V =+3 V to +5.5V; V =V = AGND =1.23V; V = +0V to 2.45V; T = T toT , unlessother- DD IOUT1 IOUT2 REF A MIN MAX wise noted. AD7945, AD7948:V = +3 V to +5.5 V; V = AGND = 1.23 V; V = +0 V to 2.45 V; T = T to T , unless otherwise noted.) DD IOUT1 REF A MIN MAX Parameter A Grades2 Units Test Conditions/Comments ACCURACY Resolution 12 Bits 1 LSB = (V – V /212 = 300 m V When IOUT1 REF) V = 1.23 V and V = 0 V IOUT1 REF Relative Accuracy – 1 LSB max Differential Nonlinearity – 0.9 LSB max All Grades Guaranteed Monotonic over Temperature Gain Error @ +25(cid:176) C – 3 LSB max T to T – 4 LSB max MIN MAX Gain Temperature Coefficient3 2 ppm FSR/(cid:176) C typ 5 ppm FSR/(cid:176) C max Output Leakage Current See Terminology Section I OUT1 @ +25(cid:176) C 10 nA max T to T 100 nA max Typically 20 nA over Temperature MIN MAX Input Resistance This Varies with DAC Input Code @ I Pin (AD7943) 6 kW min OUT2 @ AGND Pin (AD7945, AD7948) 6 kW min DIGITAL INPUTS V , Input High Voltage @ V = +5 V 2.4 V min INH DD V , Input High Voltage @ V = +3.3 V 2.1 V min INH DD V , Input Low Voltage @ V = +5 V 0.8 V max INL DD V , Input Low Voltage @ V = +3.3 V 0.6 V max INL DD I , Input Current – 1 m A max INH C , Input Capacitance3 10 pF max IN DIGITAL OUTPUT (SRO) For 1 CMOS Load Output Low Voltage (V ) 0.2 V max OL Output High Voltage (V ) V – 0.2 V min OH DD POWER REQUIREMENTS V Range 3.0/5.5 V min/V max DD Power Supply Sensitivity3 D Gain/D V –75 dB typ DD I (AD7943) 5 m A max V = V – 0.1 V min, V = 0.1 V max. DD INH DD INL SRO Open Circuit; No STB Signal; Typically 1 m A. Typically 100 m A with 1 MHz STB Frequency. I (AD7945, AD7948) 5 m A max V = V – 0.1 V min, V = 0.1 V max. DD INH DD INL Typically 1 m A. NOTES 1These specifications apply with the devices biased up at 1.23 V for single supply applications. The model numbering reflects this by means of a “–B” suffix (for example: AD7943AN-B). Figure 16 is an example of Biased Mode Operation. 2Temperature ranges as follows: A Versions: –40(cid:176) C to +85(cid:176) C. 3Guaranteed by design. Specifications subject to change without notice. REV. B –3–

AD7943/AD7945/AD7948 AC PERFORMANCE CHARACTERISTICS NORMAL MODE (AD7943: V = +4.5 V to +5.5 V; V = V = AGND = 0 V. AD7945, AD7948: V = +4.5 V to +5.5 V; V =AGND = DD IOUT1 IOUT2 DD IOUT1 0 V. V = 6 V rms, 1 kHz sine wave; T = T to T ; DAC output op amp is AD843; unless otherwise noted.) These characteristics are in- REF A MIN MAX cluded for Design Guidance and are not subject to test. Parameter B Grades T Grade Units Test Conditions/Comments DYNAMIC PERFORMANCE Output Voltage Settling Time 600 700 ns typ To 0.01% of Full-Scale Range. V = REF +10 V; DAC Latch Alternately Loaded with All 0s and All 1s Digital to Analog Glitch Impulse 60 60 nV-s typ Measured with V = 0 V. DAC Latch REF Alternately Loaded with All 0s and All 1s Multiplying Feedthrough Error –75 –75 dB max DAC Latch Loaded with All 0s Output Capacitance 60 60 pF max All 1s Loaded to DAC 30 30 pF max All 0s Loaded to DAC Digital Feedthrough (AD7943) 5 5 nV-s typ Feedthrough to the DAC Output with LD1, LD2 High and Alternate Loading of All 0s and All 1s into the Input Shift Register Digital Feedthrough (AD7945, AD7948) 5 5 nV-s typ Feedthrough to the DAC Output with CS High and Alternate Loading of All 0s and All 1s to the DAC Bus Total Harmonic Distortion –83 –83 dB typ Output Noise Spectral Density @ 1 kHz 35 35 nV/(cid:214) Hz typ All 1s Loaded to DAC. V = 0 V. Output REF Op Amp Is OP07 Specifications subject to change without notice. AC PERFORMANCE CHARACTERISTICS BIASED MODE (AD7943: V = +3 V to +5.5 V; V = V = AGND = 1.23 V. AD7945, AD7948: V = +3 V to +5.5 V; V = AGND = DD IOUT1 IOUT2 DD IOUT1 1.23 V. V = 1 kHz, 2.45 V p-p, sine wave biased at 1.23 V; DAC output op amp is AD820; T = T to T ; unless otherwise noted.) These REF A MIN MAX characteristics are included for Design Guidance and are not subject to test. Parameter A Grades Units Test Conditions/Comments DYNAMIC PERFORMANCE Output Voltage Settling Time 5 m s typ To 0.01% of Full-Scale Range. V = 0 V REF DAC Latch Alternately Loaded with All 0s and All 1s Digital to Analog Glitch Impulse 60 nV-s typ V = 1.23 V. DAC Register Alternately Loaded REF with All 0s and All 1s Multiplying Feedthrough Error –75 dB max DAC Latch Loaded with All 0s Output Capacitance 60 pF max All 1s Loaded to DAC 30 pF max All 0s Loaded to DAC Digital Feedthrough 5 nV-s typ Feedthrough to the DAC Output with LD1, LD2 High and Alternate Loading of All 0s and All 1s into the Input Shift Register Digital Feedthrough (AD7945, AD7948) 5 nV-s typ Feedthrough to the DAC Output with CS High and Alternate Loading of All 0s and All 1s to the DAC Bus Total Harmonic Distortion –83 dB typ Output Noise Spectral Density @ 1 kHz 25 nV/(cid:214) Hz typ All 1s Loaded to DAC. V = 1.23 V REF Specifications subject to change without notice. –4– REV. B

AD7943/AD7945/AD7948 AD7943 TIMING SPECIFICATIONS1 (T = T to T , unless otherwise noted) A MIN MAX Limit @ Limit @ Parameter V = +3 V to +3.6 V V = +4.5 V to +5.5 V Units Description DD DD t 2 60 40 ns min STB Pulsewidth STB t 15 10 ns min Data Setup Time DS t 35 25 ns min Data Hold Time DH t 55 35 ns min SRI Data Pulsewidth SRI t 55 35 ns min Load Pulsewidth LD t 55 35 ns min CLR Pulsewidth CLR t 0 0 ns min Min Time Between Strobing Input Shift ASB Register and Loading DAC Register t 3 60 35 ns max STB Clocking Edge to SRO Data Valid Delay SV NOTES 1All input signals are specified with tr = tf = 5 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V. tr and tf should not exceed 1 m s on any digital input. 2STB mark/space ratio range is 60/40 to 40/60. 3t is measured with the load circuit of Figure 2 and defined as the time required for the output to cross 0.8 V or 2.4 V. SV Specifications subject to change without notice. t STB STB1, STB2, STB4 STB3 t DH t DS t SRI SRI DB11(N) DB10(N) DB0(N) (MSB) tLD, tCLR t ASB LD1, LD2, CLR t SV SRO DB10(N–1) DB0(N–1) Figure 1.AD7943 Timing Diagram 1.6mA IOL TO OUTPUT +2.1V PIN CL 50pF 200mA IOH Figure 2.Load Circuit for Digital Output Timing Specifications REV. B –5–

AD7943/AD7945/AD7948 AD7945 TIMING SPECIFICATIONS1 (T = T to T , unless otherwise noted) A MIN MAX Limit @ Limit @ Parameter V = +3 V to +3.6 V V = +4.5 V to +5.5 V Units Description DD DD t 35 20 ns min Data Setup Time DS t 10 10 ns min Data Hold Time DH t 60 40 ns min Chip Select Setup Time CS t 0 0 ns min Chip Select Hold Time CH t 60 40 ns min Write Pulsewidth WR NOTES 1All input signals are specified with tr = tf = 5 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V. Specifications subject to change without notice. t CS t CH CS t WR WR t t DS DH DB11–DB0 DATA VALID Figure 3.AD7945 Timing Diagram AD7948 TIMING SPECIFICATIONS1 (T = T to T , unless otherwise noted) A MIN MAX Limit @ Limit @ Parameter V = +3 V to +3.6 V V = +4.5 V to +5.5 V Units Description DD DD t 45 30 ns min Data Setup Time DS t 10 10 ns min Data Hold Time DH t 0 0 ns min CSMSB or CSLSB to WR Setup Time CWS t 0 0 ns min CSMSB or CSLSB to WR Hold Time CWH t 0 0 ns min LDAC to WR Setup Time LWS t 0 0 ns min LDAC to WR Hold Time LWH t 60 40 ns min Write Pulsewidth WR NOTES 1All input signals are specified with tr = tf = 5 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V. Specifications subject to change without notice. t t CWH CWS CSMSB t t CWH CWS CSLSB t t LWH LWS LDAC t t WR WR WR t t t DH t DH DS DS DB7–DB0 DATA DATA VALID VALID Figure 4.AD7948 Timing Diagram –6– REV. B

AD7943/AD7945/AD7948 ABSOLUTE MAXIMUM RATINGS1 SOP Package, Power Dissipation . . . . . . . . . . . . . . . . .450 mW (T = +25(cid:176) C unless otherwise noted) q Thermal Impedance . . . . . . . . . . . . . . . . . . . . . . 75(cid:176) C/W A JA V to DGND . . . . . . . . . . . . . . . . . . . . . . . . . .–0.3 V to +6 V Lead Temperature, Soldering DD I to DGND . . . . . . . . . . . . . . . . . . .–0.3 V to V + 0.3 V Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . +215(cid:176) C OUT1 DD I to DGND . . . . . . . . . . . . . . . . . . .–0.3 V to V + 0.3 V Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . +220(cid:176) C OUT2 DD AGND to DGND . . . . . . . . . . . . . . . . .–0.3 V to V + 0.3 V SSOP Package, Power Dissipation . . . . . . . . . . . . . . . .875 mW DD Digital Input Voltage to DGND . . . . . .–0.3 V to VDD + 0.3 V q JA Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 132(cid:176) C/W V , V to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . – 15 V Lead Temperature, Soldering RFB REF Input Current to Any Pin Except Supplies2 . . . . . . . .– 10 mA Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . +215(cid:176) C Operating Temperature Range Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . +220(cid:176) C Industrial (A, B Versions) . . . . . . . . . . . . . –40(cid:176) C to +85(cid:176) C Extended (T Version) . . . . . . . . . . . . . . . –55(cid:176) C to +125(cid:176) C NOTES 1Stresses above those listed under Absolute Maximum Ratings may cause perma- Storage Temperature Range . . . . . . . . . . . . –65(cid:176) C to +150(cid:176) C nent damage to the device. This is a stress rating only; functional operation of the Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . .+150(cid:176) C device at these or any other conditions above those listed in the operational sections DIP Package, Power Dissipation . . . . . . . . . . . . . . . . 670 mW of this specification is not implied. Exposure to absolute maximum rating q Thermal Impedance . . . . . . . . . . . . . . . . . . . . .116(cid:176) C/W conditions for extended periods may affect device reliability. JA 2Transient currents of up to 100 mA will not cause SCR latch-up. Lead Temperature, Soldering, (10 sec) . . . . . . . . . . +260(cid:176) C CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily (cid:87)(cid:65)(cid:82)(cid:78)(cid:73)(cid:78)(cid:71)(cid:33) accumulate on the human body and test equipment and can discharge without detection. Although the AD7943/AD7945/AD7948 feature proprietary ESD protection circuitry, perma- nent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, ESD SENSITIVE DEVICE proper ESD precautions are recommended to avoid performance degradation or loss of functionality. ORDERING GUIDE Temperature Linearity Nominal Package Model Range Error (LSBs) Supply Voltage Option1 AD7943BN –40(cid:176) C to +85(cid:176) C – 0.5 +5 V N-16 AD7943BR –40(cid:176) C to +85(cid:176) C – 0.5 +5 V R-16 AD7943BRS –40(cid:176) C to +85(cid:176) C – 0.5 +5 V RS-20 AD7943AN-B –40(cid:176) C to +85(cid:176) C – 1 +3.3 V to +5 V N-16 AD7943ARS-B –40(cid:176) C to +85(cid:176) C – 1 +3.3 V to +5 V RS-20 AD7945BN –40(cid:176) C to +85(cid:176) C – 0.5 +5 V N-20 AD7945BR –40(cid:176) C to +85(cid:176) C – 0.5 +5 V R-20 AD7945BRS –40(cid:176) C to +85(cid:176) C – 0.5 +5 V RS-20 AD7945AN-B –40(cid:176) C to +85(cid:176) C – 1 +3.3 V to +5 V N-20 AD7945ARS-B –40(cid:176) C to +85(cid:176) C – 1 +3.3 V to +5 V RS-20 AD7945TQ –55(cid:176) C to +125(cid:176) C – 1 +5 V Q-20 AD7948BN –40(cid:176) C to +85(cid:176) C – 0.5 +5 V N-20 AD7948BR –40(cid:176) C to +85(cid:176) C – 0.5 +5 V R-20 AD7948BRS –40(cid:176) C to +85(cid:176) C – 0.5 +5 V RS-20 AD7948AN-B –40(cid:176) C to +85(cid:176) C – 1 +3.3 V to +5 V N-20 AD7948ARS-B –40(cid:176) C to +85(cid:176) C – 1 +3.3 V to +5 V RS-20 NOTE 1N = Plastic DIP; R = SOP (Small Outline Package); RS = SSOP (Shrink Small Outline Package); Q = Cerdip. REV. B –7–

AD7943/AD7945/AD7948 TERMINOLOGY Output Capacitance Relative Accuracy This is the capacitance from the I pin to AGND. OUT1 Relative Accuracyorendpointlinearityisameasureofthe Output Voltage Settling Time maximumdeviation from a straight line passing through the This is the amount of time it takes for the output to settle to a endpoints of the DAC transfer function. It is measured after specified level for a full-scale input change. For these devices, it adjusting for zero error and full-scale error and is normally is specified both with the AD843 as the output op amp in the expressed in Least Significant Bits or as a percentage of full- normal current mode and with the AD820 in the biased current scale reading. mode. Differential Nonlinearity Digital to Analog Glitch Impulse Differential nonlinearity is the difference between the measured This is the amount of charge injected into the analog output change and the ideal 1 LSB change between any two adjacent when the inputs change state. It is specified as the area of the codes. A specified differential nonlinearity of 1 LSB maximum glitch in nV-s. It is measured with the reference input connected ensures monotonicity. to AGND and the digital inputs toggled between all 1s and all Gain Error 0s. As with Settling Time, it is specified with both the AD817 Gain Error is a measure of the output error between an ideal and the AD820. DAC and the actual device output. It is measured with all 1s AC Feedthrough Error in the DAC after offset error has been adjusted out and is ex- This is the error due to capacitive feedthrough from the DAC pressed in Least Significant Bits. Gain error is adjustable to reference input to the DAC I terminal, when all 0s are zero with an external potentiometer. OUT1 loaded in the DAC. Output Leakage Current Digital Feedthrough Output leakage current is current which flows in the DAC lad- When the device is not selected, high frequency logic activity on der switches when these are turned off. For the I terminal, OUT1 the device digital inputs is capacitively coupled through the it can be measured by loading all 0s to the DAC and measuring device to show up as noise on the I pin and subsequently on the I current. Minimum current will flow in the I line OUT1 OUT1 OUT2 the op amp output. This noise is digital feedthrough. when the DAC is loaded with all 1s. PIN CONFIGURATIONS DIP/SOP SSOP DIP/SOP/SSOP DIP/SOP/SSOP IOUT1 1 16 RFB IOUT1 1 20 RFB IOUT1 1 20 RFB IOUT1 1 20 RFB IOUT2 2 15 VREF IOUT2 2 19 VREF AGND 2 19 VREF AGND 2 19 VREF AGND 3 AD7943 14 VDD AGND 3 AD7943 18 VDD DGND 3 AD7945 18 VDD DGND 3 AD7948 18 VDD STB1 4 TOP VIEW 13 CLR STB1 4 TOP VIEW 17 CLR DB11 4 TOP VIEW 17 WR CSMSB 4 TOP VIEW 17 WR (Not to Scale) (Not to Scale) (Not to Scale) (Not to Scale) LD1 5 12 DGND NC 5 16 NC DB10 5 16 CS DF/DOR 5 16 CSLSB SRO 6 11 STB4 NC 6 15 NC DB9 6 15 DB0 CTRL 6 15 LDAC SRI 7 10 STB3 LD1 7 14 DGND DB8 7 14 DB1 DB7 (MSB) 7 14 DB0 (LSB) STB2 8 9 LD2 SRO 8 13 STB4 DB7 8 13 DB2 DB6 8 13 DB1 SRI 9 12 STB3 DB6 9 12 DB3 DB5 9 12 DB2 STB2 10 11 LD2 DB5 10 11 DB4 DB4 10 11 DB3 NC = NO CONNECT –8– REV. B

AD7943/AD7945/AD7948 AD7943 PIN FUNCTION DESCRIPTIONS Pin Mnemonic Description I DAC current output terminal 1. OUT1 I DAC current output terminal 2. This should be connected to the AGND pin. OUT2 AGND This pin connects to the back gates of the current steering switches. In normal operation, it should be connected to the signal ground of the system. In biased single-supply operation it may be biased to some voltage between 0 V and the 1.23 V. See Figure 11 for more details. STB1 This is the Strobe 1 input. Data is clocked into the input shift register on the rising edge of this signal. STB3 must be high. STB2, STB4 must be low. LD1, LD2 Active low inputs. When both of these are low, the DAC register is updated and the output will change to reflect this. SRI Serial Data Input. Data on this line will be clocked into the input shift register on one of the Strobe inputs, when they are enabled. STB2 This is the Strobe 2 input. Data is clocked into the input shift register on the rising edge of this signal. STB3 must be high. STB1, STB4 must be low. STB3 This is the Strobe 3 input. Data is clocked into the input shift register on the falling edge of this signal. STB1, STB2, STB4, must be low. STB4 This is the Strobe 4 input. Data is clocked into the input shift register on the rising edge of this signal. STB3 must be high. STB1, STB2 must be low. DGND Digital Ground. CLR Asynchronous CLR input. When this input is taken low, all 0s are loaded to the DAC latch. V Power supply input. This is nominally +5 V for Normal Mode Operation and +3.3 V to +5 V for Biased DD Mode Operation. V DAC reference input. REF R DAC feedback resistor pin. FB AD7945 PIN FUNCTION DESCRIPTIONS Pin Mnemonic Description I DAC current output terminal 1. OUT1 AGND This pin connects to the back gates of the current steering switches. The DAC I terminal is also connected OUT2 internally to this point. DGND Digital Ground. DB11–DB0 Digital Data Inputs. CS Active Low, Chip Select Input. WR Active Low, Write Input. V Power supply input. This is nominally +5 V for Normal Mode Operation and +3.3 V to +5 V for Biased Mode DD Operation. V DAC reference input. REF R DAC feedback resistor pin. FB REV. B –9–

AD7943/AD7945/AD7948 AD7948 PIN FUNCTION DESCRIPTIONS Pin Mnemonic Description I DAC current output terminal 1. Normally terminated at the virtual ground of output amplifier. OUT1 AGND Analog Ground Pin. This pin connects to the back gates of the current steering switches. The DAC I OUT2 terminal is also connected internally to this point. DGND Digital Ground Pin. CSMSB Chip Select Most Significant Byte. Active Low Input. Used in combination with WR to load external data into the input register or in combination with LDAC and WR to load external data into both input and DAC registers. DF/DOR Data Format/Data Override. When this input is low, data in the DAC register is forced to one of two override codes selected by CTRL. When the override signal is removed, the DAC output returns to reflect the value in the DAC register. With DF/DOR high, CTRL selects either a left or right justified input data format. For normal operation, DF/DOR is held high. See Table I. Table I. Truth Table for DF/DOR CTRL DF/DOR CTRL Function 0 0 DAC Register Contents Overridden by All 0s 0 1 DAC Register Contents Overridden by All 1s 1 0 Left-Justified Input Data Selected 1 1 Right-Justified Input Data Selected CTRL Control Input. See DF/DOR description. DB7–DB0 Digital Data Inputs. LDAC Load DAC input, active low. This signal, in combination with others, is used to load the DAC register from either the input register or the external data bus. CSLSB Chip Select Least Significant (LS) Byte. Active Low Input. Used in combination with WR to load external data into the input register or in combination with WR and LDAC to load external data into both input and DAC registers. Table II. Truth Table for AD7948 Write Operation WR CSMSB CSLSB LDAC Function 0 1 0 1 Load LS Byte to Input Register 0 1 0 0 Load LS Byte to Input Register and DAC Register 0 0 1 1 Load MS Byte to Input Register 0 0 1 0 Load MS Byte to Input Register and DAC Register 0 1 1 0 Load Input Register to DAC Register 1 X X X No Data Transfer WR Write input, active low. This active low signal, in combination with others is used in loading external data into the AD7948 input register and in transferring data from the input register to the DAC register. V Power supply input. This is nominally +5 V for Normal Mode Operation and +3.3 V to +5 V for Biased Mode DD Operation. V DAC reference input. REF R DAC feedback resistor pin. FB –10– REV. B

AD7943/AD7945/AD7948 Typical Performance Curves 0.5 0.50 VDD = +5V VTAD D= =+ 2+558VC VORPE AF M= P+ 1=0 AVD843 0.4 OP AMP = AD843 TA = +258C S 0.25 B S L – LSBS0.3 ROR NL – Y ER 0.00 D0.2 RIT A E N LI–0.25 0.1 0 –0.50 2 4 6 8 10 0 1024 2048 3072 4095 VREF – Volts INPUT CODE Figure 5.Differential Nonlinearity Error vs. Figure 7.All Codes Linearity In Normal Mode (V = +5 V) DD V (Normal Mode) REF 1.0 6 VDD = +5V 0.9 TOAP =A +M2P5 8=C AD843 5 VTAD D= =+ 2+538.C3V 0.8 OP AMP = AD820 0.7 S 4 S 0.6 SB B L L – LS 0.5 DNL – 3 IN 0.4 L, N I 2 0.3 0.2 1 0.1 0 0 2 4 6 8 10 0.2 0.4 0.6 0.8 1.0 1.2 1.4 VREF – Volts |VREF – VBIAS| – Volts Figure 6.Integral Nonlinearity Error vs. Figure 8. Linearity Error vs. V (Biased Mode) REF V (Normal Mode) REF REV. B –11–

AD7943/AD7945/AD7948 1.00 VDD = +3.3V VREF = 0V VBIAS = 1.23V OP AMP = AD820 5V 200ns BS 0.50 TA = +258C S 100 L – 90 R Y ERRO 0.00 VTVADR DE=F = += 2+ 055V8VC T OP AMP = AD711 RI EA AD711 OUTPUT N 10 LI–0.50 0% 50mV 200ns –1.00 0 1024 2048 3072 4095 INPUT CODE Figure 9.All Codes Linearity in Biased Mode Figure 11.Digital-to-Analog Glitch Impulse (V = +3.3 V) DD –50 0 –55 VDD = +5V –10 VDD = +5V TA = +258C TA = +258C –60 VIN = 6V rms –20 VIN = 20V p-p DAC LOADED WITH ALL 1S OP AMP = AD711 OP AMP = AD711 –65 –30 s–70 –40 B d – –75 –50 D H T–80 –60 –85 –70 DAC LOADED WITH ALL 0S –90 –80 –95 –90 –100 –100 100 1k 10k 100k 1k 10k 100k 1M 10M FREQUERCY – Hz FREQUENCY – Hz Figure 10.Total Harmonic Distortion vs. Frequency Figure 12.Multiplying Frequency Response vs. Digital Code –12– REV. B

AD7943/AD7945/AD7948 GENERAL DESCRIPTION UNIPOLAR BINARY OPERATION D/A Section (Two-Quadrant Multiplication) The AD7943, AD7945 and AD7948 are 12-bit current-output Figure 14 shows the standard unipolar binary connection dia- D/A converters. A simplified circuit diagram is shown in Fig- gram for the AD7943, AD7945 and AD7948. When V is an IN ure 13. The DAC architecture is segmented. This means that ac signal, the circuit performs two-quadrant multiplication. the 2 MSBs of the 12-bit data word are decoded to drive the Resistors R1 and R2 allow the user to adjust the DAC gain three switches A, B and C. The remaining 10 bits of the data error. With a specified gain error of 2 LSBs over temperature, word drive the switches S0 to S9 in a standard inverting R-2R these are not necessary in many applications. Circuit offset is ladder configuration. due completely to the output amplifier offset. It can be re- moved by adjusting the amplifier offset voltage. Alternatively, Each of the switches A to C steers 1/4 of the total reference choosing a low offset amplifier makes this unnecessary. current into either I or I with the remaining 1/4 of the OUT1 OUT2 total current passing through the R-2R section. Switches S9 to A1 should be chosen to suit the application. For example, the S0 steer binarily weighted currents into either I or I . If OP07 is ideal for very low bandwidth applications (10 kHz or OUT1 OUT2 I and I are kept at the same potential, a constant cur- OUT1 OUT2 rent flows in each ladder leg, regardless of digital input code. R2 10V Thus, the input resistance seen at V is always constant. It is REF RFB C1 equal to R/2. The V input may be driven by any reference voltage or current, acR EoFr dc that is within the Absolute Maxi- VREF IOUT1 mum Ratings. VIN R1 20V DAC IOUT2 A1A1: OP07VOUT AD7943/45/48 AD711 The device provides access to the VREF, RFB, and IOUT1 termi- AGND AADD884435 nals of the DAC. This makes the device extremely versatile and SIGNAL GROUND allows it to be configured in several different operating modes. NOTES Examples of these are shown in the following sections. The 1. ONLY ONE DAC IS SHOWN FOR CLAIRITY. AD7943 also has a separate I pin. In the AD7945 and 2. DIGITAL INPUT CONNECTIONS ARE OMITTED. OUT2 AD7948 this is internally tied to AGND. 3. C1 PHASE COMPENSATION (5 – 15pF) MAY BE REQUIRED WHEN USING HIGH SPEED AMPLIFIER. When an output amplifier is connected in the standard configu- Figure 14.Unipolar Binary Operation ration of Figure 14, the output voltage is given by: lower) while the AD711 is suitable for medium bandwidth ap- VOUT = –D · VREF plications (200 kHz or lower). For high bandwidth applications where D is the fractional representation of the digital word of greater than 200 kHz, the AD843 and AD847 offer very fast loaded to the DAC. D can be set from 0 to 4095/4096, since it settling times. has 12-bit resolution. The code table for Figure 14 is shown in Table III. VREF Table III. Unipolar Binary Code R R R Digital Input Analog Output 2R 2R 2R 2R 2R 2R 2R MSB LSB (V as Shown in Figure 14) OUT C B A S9 S8 S0 1111 1111 1111 –V (4095/4096) R/2 REF RFB 1000 0000 0001 –VREF (2049/4096) IOUT1 1000 0000 0000 –VREF (2048/4096) IOUT2 0111 1111 1111 –V (2047/4096) SHOWN FOR ALL 1S ON DAC REF 0000 0000 0001 –V (1/4096) REF Figure 13.Simplified D/A Circuit Diagram 0000 0000 0000 –V (0/4096) = 0 REF NOTE Nominal LSB size for the circuit of Figure 14 is given by: V (1/4096). REF REV. B –13–

AD7943/AD7945/AD7948 BIPOLAR OPERATION SINGLE SUPPLY APPLICATIONS (Four-Quadrant Multiplication) The “-B” versions of the devices are specified and tested for Figure 15 shows the standard connection diagram for bipolar single supply applications. Figure 16 shows the recommended operation of the AD7943, AD7945 and AD7948. The coding is circuit for operation with a single +5 V to +3.3 V supply. The offset binary as shown in Table IV. When V is an ac signal, I andAGND terminalsarebiased to 1.23V. Thus, with 0V IN OUT2 the circuit performs four-quadrant multiplication. Resistors R1 applied to the V terminal, the output will go from 1.23 V (all REF and R2 are for gain error adjustment and are not needed in 0s loaded to the DAC) to 2.46 V (all 1s loaded). With 2.45 V many applications where the device gain error specifications are applied to the V terminal, the output will go from 1.23 V (all REF adequate. To maintain the gain error specifications, resistors 0s loaded) to 0.01 V (all 1s loaded). It is important when con- R3, R4 and R5 should be ratio matched to 0.01%. sidering INL in a single-supply system to realize that most single-supply amplifiers cannot sink current and maintain zero R4 20kV volts at the output. In Figure 16, with V = 2.45 V the re- REF R2 10V R5 quired sink current is 200 m A. The minimum output voltage level is 10 mV. Op amps like the OP295 are capable of main- RFB C1 20kV taining this level while sinking 200 m A. VIN VREF IOUT1 R3 R1 20V AD7D9A4C3/45/48 IOUT2 A1 10kV A2 VOUT Fbyig aunre a 1m6p slihfioewr.s Tthhei sI OisU Tto2 amnadi nAtaGinN tDhe t ebrimasi nvaollst abgeei nagt 1d.r2iv3e nV as the impedance seen looking into the I terminal changes. AGND OUT2 SIGNAL GROUND This impedance is code dependent and varies from infinity (all NOTES 0s loaded in the DAC) to about 6 kW minimum. The AD589 1. ONLY ONE DAC IS SHOWN FOR CLAIRITY. has a typical output resistance of 0.6 W and it can be used to 2. DIGITAL INPUT CONNECTIONS ARE OMITTED. drive the terminals directly. However, this will cause a typical 3. C1 PHASE COMPENSATION (5 – 15pF) MAY BE REQUIRED linearity degradation of 0.2 LSBs. If this is unacceptable then WHEN USING HIGH SPEED AMPLIFIER, A1. the buffer amplifier is necessary. Figure 9 shows the typical Figure 15.Bipolar Operation (Four-Quadrant linearity performance of the AD7943/AD7945/AD7948 when Multiplication) used as in Figure 16 with V set at +3.3 V and V = 0 V. DD REF Suitable dual amplifiers for use with Figure 15 are the OP270 (low noise, low bandwidth, 15 kHz), the AD712 (medium +3.3V bandwidth, 200 kHz) or the AD827 (wide bandwidth, 1 MHz). Table IV. Bipolar (Offset Binary) Code VDD RFB C1 IOUT1 VREF Table Digital Input Analog Output VIN DAC IOUT2 A1 VOUT A1: OP295 MSB LSB (V as Shown in Figure 15) OUT AD7943/45/48 AD822 AGND OP283 1111 1111 1111 +VREF (2047/2048) DGND 1000 0000 0001 +V (1/2048) REF +5V 1000 0000 0000 +V (0/2048) = 0 REF 5.6kV A1 0111 1111 1111 –V (1/2048) REF AD589 0000 0000 0001 –V (2047/2048) REF SIGNAL GROUND 0000 0000 0000 –V (2048/2048) = –V REF REF Figure 16.Single Supply System NOTE Nominal LSB size for the circuit of Figure 15 is given by: V (1/2048). REF –14– REV. B

AD7943/AD7945/AD7948 MICROPROCESSOR INTERFACING AD7945 to MC68000 Interface AD7943 to ADSP-2101 Interface Figure 19 shows the MC68000 interface to the AD7945. The Figure 17 shows the AD7943 to ADSP-2101 interface diagram. appropriate data is written into the DAC in one MOVE instruc- The DSP is set up for alternate inverted framing with an inter- tion to the appropriate memory location. nally generated SCLK. TFS from the ADSP-2101 drives the STB1 input on the AD7943. The serial word length should be set at 12. This is done by making SLEN = 11 (1011 binary). A1 – A23 The SLEN field is Bits 3–0 in the SPORT control register (0x3FF6 for SPORT0 and 0x3FF2 for SPORT1). MC68000 ADDRESS With the 16 MHz version of the ADSP-2101, the maximum AS DECODE CS AD7945 output SCLK is 8 MHz. The AD7943 setup and hold time of DTACK 10 ns and 25 ns mean that it is compatible with the DSP when running at this speed. WR R/W The OUTPUT FLAG drives both LD1 and LD2 and is brought low to update the DAC register and change the analog output. D15 – D0 DB11 – DB0 +5V ADSP-2101 AD7943 CLR Figure 19.AD7945 to MC68000 Interface TFS STB1 AD7948 to Z80 Interface SCLK STB3 Figure 20 is the interface between the AD7948 and the 8-bit DT SRI bus of the Z80 processor. Three write operations are needed to OUTPUT FLAG LD1 load the DAC. The first two load the MS byte and the LS byte LD2 and the third brings the LDAC low to update the output. STB2 STB4 A0 – A15 ADDRESS BUS Figure 17.AD7943 to ADSP-2101 Interface Z80 CSMSB AD7943 to DSP56001 Interface MREQ ADDRESS CSLSB Figure 18 shows the interface diagram for the AD7943 to the DECODE LDAC DSP56001. The DSP56001 is configured for normal mode AD7948 synchronous operation with gated clock. The serial clock, SCK, WR WR is set up as an output from the DSP and the serial word length is set for 12 bits (WL0 = 1, WL1 = 0, in Control Register A). SCK from the DSP56001 is applied to the AD7943 STB3 in- D7 – D0 DB7 – DB0 put. Data from the DSP56000 is valid on the falling edge of SCK and this is the edge which clocks the data into the AD7943 shift register. STB1, STB2 and STB4 are tied low on the DATA BUS AD7943 to permanently enable the STB3 input. When the 12-bit serial word has been written to the AD7943, Figure 20.AD7948 to Z80 Interface the LD1, LD2 inputs are brought low to update the DAC register. +5V DSP56001 AD7943 CLR SCK STB3 STD SRI OUTPUT FLAG LD1 LD2 STB1 STB2 STB4 Figure 18.AD7943 to DSP56001 Interface REV. B –15–

AD7943/AD7945/AD7948 OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 16-Lead Plastic DIP (N-16) 16-Lead SOP (R-16) 0.4133 (10.50) 0.3977 (10.00) 0.840 (21.34) 0.745 (18.92) 16 9 98 161 PIN 1 89 000...022684000 (((176...511210))) 00..332050 ((87..2662))00..119155 ((42..9953)) 1 8 0.2992 (7.60)0.2914 (7.40)0.4193 (10.65)0.3937 (10.00) 1901b–0–5/ C 0.015 (0.38) 0.210 (5.33) MAX 0.130 PIN 1 0.1043 (2.65) 0.0291 (0.74) 0.160 (4.06) (3.30) x 45° 0.115 (2.93) MIN 0.015 (0.381) 00..00101480 ((00..3100)) 0.0926 (2.35) 0.0098 (0.25) 0.022 (0.558) 0.100 0.070 (1.77) SEATING 0.008 (0.204) 0.014 (0.356) (B2.S5C4) 0.045 (1.15) PLANE 8° 0.0500 (1.27) 0(B.10.S52C070) 00..00119328 ((00..4395)) SPELAANTIENG 00..00102951 ((00..3223))0° 0.0157 (0.40) 20-Lead Plastic DIP (N-20) 20-Lead Cerdip (Q-20) 1.060 (26.90) 0.005 (0.13) MIN 0.098 (2.49) MAX 0.925 (23.50) 20 11 20 11 0.310 (7.87) 0.280 (7.11) 1 10 0.240 (6.10) 0.325 (8.25) 1 10 0.220 (5.59) PIN 1 0.060 (1.52) 0.300 (7.62)00..119155 ((42..9953)) PIN 1 1.060 (26.92) MAX 0.060 (1.52) 00..322900 ((87..1337)) 0.210 (5.33) 0.015 (0.38) 0.200 (5.08) 0.015 (0.38) MAX 0.130 MAX 0.150 0.160 (4.06) (3.30) 0.200 (5.08) (3.81) 0.115 (2.93) 00..002124 ((00..535586)) (0B2.1.S50C40) 00..007405 ((11..7175))SPELAAMNTIIENNG 00..001058 ((00..328014)) 0.125 (3.18) 00..002134 ((00..5386)) (0B2.1.S50C40) 00..007300 ((10..7786)) SPELAANTMIEINNG 105°° 00..001058 ((00..3280)) 20-Lead SOP (R-20) 20-Lead SSOP (RS-20) 0.5118 (13.00) 0.295 (7.50) 0.4961 (12.60) 0.271 (6.90) 20 11 20 11 1 10 0.2992 (7.60)0.2914 (7.40) 0.4193 (10.65)0.3937 (10.00) 0.311 (7.9)0.301 (7.64) 1 10 0.212 (5.38)0.205 (5.21) A. S. PIN 1 0.1043 (2.65) 0.0291 (0.74) U. 0.0926 (2.35) 0.0098 (0.25)x 45° 0.078 (1.98)PIN 1 0.07 (1.78) N 0.068 (1.73) 0.066 (1.67) D I E T 8° 0.0500 (1.27) N 00..00101480 ((00..3100)) 0(B.10.S52C070) 00..00119328 ((00..4395)) SPELAANTIENG 00..00102951 ((00..3223))0° 0.0157 (0.40) 00..000082 ((00..200530)) 0(B.00.S26C556) SEPALTAINNGE 00..000095 ((00..212297)) 80°° 00..002327 ((00..59549)) PRI –16– REV. B

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