2-Channel, 2.35 V to 5.25 V, 1 MSPS, 10-/12-Bit ADCs AD7912/AD7922 FUNCTIONAL BLOCK DIAGRAM FEATURES Fast throughput rate: 1 MSPS VDD Specified for V of 2.35 V to 5.25 V DD Low power: 4.8 mW typ at 1 MSPS with 3 V supplies VIN0 10-/12-BIT MUX T/H SUCCESSIVE 15.5mW typ at 1 MSPS with 5 V supplies VIN1 APPROAXDIMCATION Wide input bandwidth: 71 dB minimum SNR at 100 kHz input frequency Flexible power/serial clock speed management No pipeline delays SCLK High speed serial interface: CS SPI®/QSPI™/MICROWIRE™/DSP compatible AD7912/AD7922 CONTROL LOGIC DOUT Standby mode: 1 µA maximum D8-aleisayd-c ThSaOinT mpaocdkea ge DIN 04351-0-001 GND 8-lead MSOP package Figure 1. APPLICATIONS Several AD7912/AD7922 can be connected together in a daisy Battery-powered systems: chain. The AD7912/AD7922 feature a daisy-chain mode that Personal digital assistants allows the user to read the conversion results from the ADCs Medical instruments contained in the chain. The AD7912/AD7922 use advanced Mobile communications design techniques to achieve very low power dissipation at high Instrumentation and control systems throughput rates. The reference for the part is taken internally Data acquisition systems from V , thereby allowing the widest dynamic input range to DD High speed modems the ADC. Optical sensors PRODUCT HIGHLIGHTS GENERAL DESCRIPTION 1. 2-channel, 1 MSPS, 10-/12-bit ADCs in TSOT package. The AD7912/AD79221 are 10-bit and 12-bit, high speed, low 2. High throughput with low power consumption. power, 2-channel successive approximation ADCs, respectively. 3. Flexible power/serial clock speed management. The parts operate from a single 2.35 V to 5.25 V power supply The conversion rate is determined by the serial clock. The and feature throughput rates of up to 1 MSPS. The parts contain parts also feature a power-down mode to maximize power a low noise, wide bandwidth track-and-hold amplifier, which efficiency at lower throughput rates. Average power can handle input frequencies in excess of 6 MHz. consumption is reduced when the power-down mode is used while not converting. Current consumption is 1 µA The conversion process and data acquisition are controlled maximum and 50 nA typically when in power-down mode. using CS and the serial clock, allowing the devices to interface 4. Daisy-chain mode. with microprocessors or DSPs. The conversion rate is 5. No pipeline delay. determined by the SCLK signal. The input signal is sampled on The parts feature a standard successive approximation ADC the falling edge of CS and the conversion is also initiated at this with accurate control of the sampling instant via a CS input point. The channel to be converted is selected through the DIN and once-off conversion control. pin, and the mode of operation is controlled by CS. The serial data stream from the DOUT pin has a channel identifier bit and mode identifier bit, which provide information about the converted channel and the current mode of operation. 1 Protected by U.S. Patent Number 6,681,332. Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and Tel: 781.329.4700 www.analog.com registered trademarks are the property of their respective owners. Fax: 781.326.8703 © 2004 Analog Devices, Inc. All rights reserved.

AD7912/AD7922 TABLE OF CONTENTS Specifications.....................................................................................3 DIN Input....................................................................................17 AD7912 Specifications.................................................................3 DOUT Output............................................................................17 AD7922 Specifications.................................................................5 Modes of Operation.......................................................................18 Timing Specifications..................................................................7 Normal Mode..............................................................................18 Timing Diagrams..........................................................................7 Power-Down Mode....................................................................18 Timing Examples..........................................................................8 Power-Up Time..........................................................................20 Absolute Maximum Ratings............................................................9 Daisy-Chain Mode.....................................................................20 ESD Caution..................................................................................9 Daisy-Chain Example................................................................22 Pin Configurations and Function Descriptions.........................10 Power vs. Throughput Rate...........................................................24 Terminology....................................................................................11 Serial Interface................................................................................25 Typical Performance Characteristics...........................................13 Microprocessor Interfacing.......................................................26 Circuit Information........................................................................15 Application Hints...........................................................................28 Converter Operation..................................................................15 Grounding and Layout..............................................................28 ADC Transfer Function.............................................................15 Evaluating AD7912/AD7922 Performance.................................29 Typical Connection Diagram...................................................16 Outline Dimensions.......................................................................30 Analog Input...............................................................................16 Ordering Guide..........................................................................30 Digital Inputs..............................................................................17 REVISION HISTORY Revision 0: Initial Version Rev. 0 | Page 2 of 32

AD7912/AD7922 SPECIFICATIONS AD7912 SPECIFICATIONS Temperature range for A Grade from −40°C to +85°C. V = 2.35 V to 5.25 V, f = 18 MHz, f = 1 MSPS; T = T to T , unless otherwise noted. DD SCLK SAMPLE A MIN MAX Table 1. Parameter A Grade1 Unit Test Conditions/Comments DYNAMIC PERFORMANCE f = 100 kHz sine wave IN Signal-to- Noise + Distortion (SINAD)2 61 dB min Total Harmonic Distortion (THD)2 −71 dB max Peak Harmonic or Spurious Noise (SFDR)2 −72 dB max Intermodulation Distortion (IMD)2 Second-Order Terms −82 dB typ fa = 100.73 kHz, fb = 90.7 kHz Third-Order Terms −83 dB typ fa = 100.73 kHz, fb = 90.7 kHz Aperture Delay 10 ns typ Aperture Jitter 30 ps typ Channel-to-Channel Isolation2 90 dB typ Full Power Bandwidth 8.5 MHz typ @ 3 dB 1.5 MHz typ @ 0.1 dB DC ACCURACY Resolution 10 Bits Integral Nonlinearity2 ±0.5 LSB max Differential Nonlinearity2 ±0.5 LSB max Guaranteed no missed codes to 10 bits Offset Error2 ±0.5 LSB max Offset Error Match2, 3 ±0.3 LSB max Gain Error2 ±0.5 LSB max Gain Error Match2, 3 ±0.3 LSB max Total Unadjusted Error (TUE)2 ±0.5 LSB max ANALOG INPUT Input Voltage Ranges 0 to V V DD DC Leakage Current ±0.3 µA max Input Capacitance 20 pF typ LOGIC INPUTS Input High Voltage, V 0.7 (V ) V min 2.35 V ≤ V ≤ 2.7 V INH DD DD 2 V min 2.7 V < V ≤ 5.25 V DD Input Low Voltage, V 0.3 V max V = 2.35 V INL DD 0.2 (V ) V max 2.35 V < V ≤ 2.7 V DD DD 0.8 V max 2.7 V < V ≤ 5.25 V DD Input Current, I , SCLK Pin ±0.3 µA max Typically 8 nA, V = 0 V or V IN IN DD Input Current, I , CS Pin ±0.3 µA max IN Input Current, I , DIN Pin ±0.3 µA max IN Input Capacitance, C 3 5 pF max IN LOGIC OUTPUTS Output High Voltage, V V − 0.2 V min I = 200 µA, V = 2.35 V to 5.25 V OH DD SOURCE DD Output Low Voltage, V 0.2 V max I = 200 µA OL SINK Floating-State Leakage Current ±0.3 µA max Floating-State Output Capacitance3 5 pF max Output Coding Straight (natural) binary Rev. 0 | Page 3 of 32

AD7912/AD7922 Parameter A Grade1 Unit Test Conditions/Comments CONVERSION RATE Conversion Time 777 ns max 14 SCLK cycles with SCLK at 18 MHz Track-and-Hold Acquisition Time2 290 ns max Throughput Rate 1 MSPS max POWER REQUIREMENTS V 2.35/5.25 V min/max DD I Digital I/Ps = 0 V or V DD DD Normal Mode (Static) 3 mA typ V = 4.75 V to 5.25 V, SCLK on or off DD 1.5 mA typ V = 2.35 V to 3.6 V, SCLK on or off DD Normal Mode (Operational) 4 mA max V = 4.75 V to 5.25 V, f = 1 MSPS DD SAMPLE 2 mA max V = 2.35 V to 3.6 V, f = 1 MSPS DD SAMPLE Full Power-Down Mode (Static) 1 µA max SCLK on or off, typically 50 nA Full Power-Down Mode (Dynamic) 0.48 mA typ V = 5 V, f = 18 MHz, f = 100 kSPS DD SCLK SAMPLE 0.26 mA typ V = 3 V, f = 18 MHz, f = 100 kSPS DD SCLK SAMPLE Power Dissipation4 Normal Mode (Operational) 20 mW max V = 5 V, f = 1 MSPS DD SAMPLE 6 mW max V = 3 V, f = 1 MSPS DD SAMPLE Full Power-Down 5 µW max V = 5 V DD 1 Operational from VDD = 2 V, with VIH = 1.9 V minimum and VIL = 0.1 V maximum. 2 See the Terminology section. 3 Guaranteed by characterization. 4 See the Power vs. Throughput Rate section. Rev. 0 | Page 4 of 32

AD7912/AD7922 AD7922 SPECIFICATIONS Temperature range for A Grade from −40°C to +85°C. V = 2.35 V to 5.25 V, f = 18 MHz, f = 1 MSPS; T = T to T , unless otherwise noted. DD SCLK SAMPLE A MIN MAX Table 2. Parameter A Grade1 Unit Test Conditions/Comments DYNAMIC PERFORMANCE f = 100 kHz sine wave IN Signal-to-Noise + Distortion (SINAD)2 70 dB min 72 dB typ Signal-to-Noise Ratio (SNR)2 71 dB min 72.5 dB typ Total Harmonic Distortion (THD)2 −81 dB typ Peak Harmonic or Spurious Noise (SFDR)2 −84 dB typ Intermodulation Distortion (IMD)2 Second-Order Terms −84 dB typ fa = 100.73 kHz, fb = 90.72 kHz Third-Order Terms −86 dB typ fa = 100.73 kHz, fb = 90.72 kHz Aperture Delay 10 ns typ Aperture Jitter 30 ps typ Channel-to-Channel Isolation2 90 dB typ Full Power Bandwidth 8.5 MHz typ @ 3 dB 1.5 MHz typ @ 0.1dB DC ACCURACY Resolution 12 Bits Integral Nonlinearity2 ±1.5 LSB max V = 2.35 V to 3.6V DD ±0.7 LSB typ V = 4.75 V to 5.25V DD Differential Nonlinearity2 Guaranteed no missed codes to 12 bits −0.9/+1.5 LSB max V = 2.35 V to 3.6V DD −0.7/+1.2 LSB typ V = 4.75 V to 5.25V DD Offset Error2 ±1 LSB max V = 2.35 V to 3.6V DD ±0.1 LSB typ V = 4.75 V to 5.25V DD Offset Error Match2, 3 ±0.5 LSB max V = 2.35 V to 3.6V DD ±0.02 LSB typ V = 4.75 V to 5.25V DD Gain Error2 ±2 LSB max V = 2.35 V to 3.6V DD ±0.5 LSB typ V = 4.75 V to 5.25V DD Gain Error Match2, 3 ±1 LSB max V = 2.35 V to 3.6V DD ±0.2 LSB typ V = 4.75 V to 5.25V DD Total Unadjusted Error (TUE)2 ±1.5 LSB max V = 2.35 V to 3.6V DD ±0.5 LSB typ V = 4.75 V to 5.25V DD ANALOG INPUT Input Voltage Ranges 0 to V V DD DC Leakage Current ±0.3 µA max Input Capacitance 20 pF typ LOGIC INPUTS Input High Voltage, V 0.7 (V ) V min 2.35 V ≤ V ≤ 2.7 V INH DD DD 2 V min 2.7 V < V ≤ 5.25 V DD Input Low Voltage, V 0.3 V max V = 2.35 V INL DD 0.2 (V ) V max 2.35 V < V ≤ 2.7 V DD DD 0.8 V max 2.7 V < V ≤ 5.25 V DD Input Current, I , SCLK Pin ±0.3 µA max Typically 8 nA, V = 0 V or V IN IN DD Input Current, I , CS Pin ±0.3 µA max IN Input Current, I , DIN Pin ±0.3 µA max IN Input Capacitance, C 3 5 pF max IN Rev. 0 | Page 5 of 32

AD7912/AD7922 Parameter A Grade1 Unit Test Conditions/Comments LOGIC OUTPUTS Output High Voltage, V V − 0.2 V min I = 200 µA; V = 2.35 V to 5.25 V OH DD SOURCE DD Output Low Voltage, V 0.2 V max I = 200 µA OL SINK Floating-State Leakage Current ±0.3 µA max Floating-State Output Capacitance3 5 pF max Output Coding Straight (natural) binary CONVERSION RATE Conversion Time 888 ns max 16 SCLK cycles with SCLK at 18 MHz Track-and-Hold Acquisition Time2 290 ns max Throughput Rate 1 MSPS max See the Serial Interface section POWER REQUIREMENTS V 2.35/5.25 V min/max DD I Digital I/Ps = 0 V or V DD DD Normal Mode (Static) 3 mA typ V = 4.75 V to 5.25 V, SCLK on or off DD 1.5 mA typ V = 2.35 V to 3.6 V, SCLK on or off DD Normal Mode (Operational) 4 mA max V = 4.75 V to 5.25 V, f = 1 MSPS DD SAMPLE 2 mA max V = 2.35 V to 3.6 V, f = 1 MSPS DD SAMPLE Full Power-Down Mode (Static) 1 µA max SCLK on or off, typically 50 nA Full Power-Down Mode (Dynamic) 0.5 mA typ V = 5 V, f = 18 MHz, f = 100 kSPS DD SCLK SAMPLE 0.28 mA typ V = 3 V, f = 18 MHz, f = 100 kSPS DD SCLK SAMPLE Power Dissipation4 Normal Mode (Operational) 20 mW max V = 5 V, f = 1 MSPS DD SAMPLE 6 mW max V = 3 V, f = 1 MSPS DD SAMPLE Full Power-Down 5 µW max V = 5 V DD 3 µW max V = 3 V DD 1 Operational from VDD = 2 V, with VIH = 1.9 V minimum and VIL = 0.1 V maximum. 2 See the Terminology section. 3 Guaranteed by characterization. 4 See the Power vs. Throughput Rate section. Rev. 0 | Page 6 of 32

AD7912/AD7922 TIMING SPECIFICATIONS Guaranteed by characterization. All input signals are specified with tr = tf = 5 ns (10% to 90% of V ) and timed from a voltage level of 1.6 V. DD V = 2.35 V to 5.25 V; T = T to T , unless otherwise noted. DD A MIN MAX Table 3. Parameter Limit at T , Unit Description MIN T MAX f 1 10 kHz min2 SCLK 18 MHz max t 16 × t AD7922 CONVERT SCLK 14 × t AD7912 SCLK t 30 ns min Minimum quiet time required between bus relinquish and start of next conversion QUIET t 15 ns min Minimum CS pulse width 1 t 10 ns min CS to SCLK setup time 2 t3 30 ns max Delay from CS until DOUT three-state is disabled 3 t3 45 ns max DOUT access time after SCLK falling edge 4 t 0.4 t ns min SCLK low pulse width 5 SCLK t 0.4 t ns min SCLK high pulse width 6 SCLK t4 10 ns min SCLK to DOUT valid hold time 7 t 5 ns min DIN setup time prior to SCLK falling edge 8 t 6 ns min DIN hold time after SCLK falling edge 9 t 5 30 ns max SCLK falling edge to DOUT three-state 10 10 ns min SCLK falling edge to DOUT three-state t 6 1 µs max Power-up time from full power-down POWER-UP 1 Mark/space ratio for SCLK input is 40/60 to 60/40. 2 Minimum fSCLK at which specifications are guaranteed. 3 Measured with the load circuit in Figure 2 and defined as the time required for the output to cross VIH or VIL voltage. 4 Measured with a 50 pF load capacitor. 5 T10 is derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit in Figure 2. The measured number is then extrapolated back to remove the effects of charging or discharging the 50 pF capacitor. This means that the time, t10, quoted in the timing characteristics is the true bus relinquish time of the part and is independent of the bus loading. 6 See the Power-Up Time section. TIMING DIAGRAMS t 7 200µA IOL SCLK TO OUTPUT 1.6V PIN 50CpFL 200µA IOH 04351-0-002 DOUT VVIIHL 04351-0-004 Figure 2. Load Circuit for Digital Output Timing Specifications Figure 4. Hold Time after SCLK Falling Edge t4 t10 SCLK SCLK DOUT VVIIHL 04351-0-003 DOUT 1.6V 04351-0-005 Figure 3. Access Time after SCLK Falling Edge Figure 5. SCLK Falling Edge to DOUT Three-State Rev. 0 | Page 7 of 32

AD7912/AD7922 TIMING EXAMPLES Timing Example 2 Figure 6 and Figure 7 show some of the timing parameters from The AD7922 can also operate with slower clock frequencies. As the Timing Specifications section. shown in Figure 7, when fSCLK = 5 MHz and the throughput rate is 315 kSPS, the cycle time is Timing Example 1 As shown in Figure 7, when fSCLK = 18 MHz and the throughput t2 + 12.5(1/fSCLK) + tACQ = 3.17 µs is 1 MSPS, the cycle time is With t = 10 ns minimum, then t is 664 ns, which satisfies the 2 ACQ t2 + 12.5(1/fSCLK) + tACQ = 1 µs requirement of 290 ns for tACQ. With t2 = 10 ns minimum, then tACQ is 295 ns, which satisfies the In Figure 7, tACQ is comprised of 2.5(1/fSCLK) + t10 + tQUIET, where requirement of 290 ns for tACQ. t10 = 30 ns maximum. This allows a value of 134 ns for tQUIET, satisfying the minimum requirement of 30 ns. In Figure 7, t is comprised of 2.5(1/f ) + t + t , where ACQ SCLK 10 QUIET t = 30 ns maximum. This allows a value of 126 ns for t , In this example, as with other slower clock values, the signal 10 QUIET satisfying the minimum requirement of 30 ns. might already be acquired before the conversion is complete, but it is still necessary to leave 30 ns minimum t between QUIET conversions. In this example, the signal should be fully acquired at approximately point C in Figure 7. t 1 CS t CONVERT t2 t6 B SCLK 1 2 3 4 5 13 14 15 16 t3 t4 t7 t5 t10 tQUIET DOUT Z ZERO CHN MOD DB11 DB10 DB2 DB1 DB0 DIN THREE-SXTATE X tC8HN STYt9 X X X X X THREE-STATE 04351-0-006 Figure 6. AD7922 Serial Interface Timing Diagram CS t CONVERT t B C 2 SCLK 1 2 3 4 5 13 14 15 16 t 10 t QUIET 12.5(1/fSCLK) 1/THROUGHPUT tACQUISITION 04351-0-007 Figure 7. Serial Interface Timing Example Rev. 0 | Page 8 of 32

AD7912/AD7922 ABSOLUTE MAXIMUM RATINGS T = 25°C, unless otherwise noted. A Table 4. Stresses above those listed under Absolute Maximum Ratings Parameter Rating may cause permanent damage to the device. This is a stress VDD to GND −0.3 V to +7 V rating only and functional operation of the device at these or Analog Input Voltage to GND −0.3 V to VDD + 0.3 V any other conditions above those indicated in the operational Digital Input Voltage to GND −0.3 V to +7 V section of this specification is not implied. Exposure to absolute Digital Output Voltage to GND −0.3 V to VDD + 0.3 V maximum rating conditions for extended periods may affect Input Current to Any Pin except Supplies1 ±10 mA device reliability. Operating Temperature Range Commercial (A Grade) −40°C to +85°C Storage Temperature Range −65°C to +150°C Junction Temperature 150°C TSOT Package θ Thermal Impedance 207°C/W JA MSOP Package θ Thermal Impedance 205.9°C/W JA θ Thermal Impedance 43.74°C/W JC Lead Temperature Soldering Reflow (10 s to 30 s) 235 (0/+5)°C ESD 1.5 kV 1 Transient currents of up to 100 mA do not cause SCR latch-up. ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. Rev. 0 | Page 9 of 32

AD7912/AD7922 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS 8-LEAD MSOP 8-LEAD TSOT DOUT 1 AD7912/ 8 VDD DIN 1 AD7912/ 8 VIN1 CS 2 AD7922 7 GND SCLK 2 AD7922 7 VIN0 SCDLIKN 34 (NToOt Pto V SIEcaWle) 65 VVIINN01 04351-0-008 DOCUST 34 (NToOt Pto V SIEcaWle) 65 GVDNDD 04351-0-009 Figure 8. 8-Lead MSOP Pin Configuration Figure 9. 8-Lead TSOT Pin Configuration Table 5. Pin Function Descriptions MSOP TSOT Pin No. Pin No. Mnemonic Function 1 4 DOUT Data Out. Logic output. The conversion result from the AD7912/AD7922 is provided on this output as a serial data stream. The bits are clocked out on the falling edge of the SCLK signal. For the AD7922, the data stream consists of two leading zeros, the channel identifier bit that identifies which channel the conversion result corresponds to, followed by the mode bit that indicates the current mode of operation, followed by the 12 bits of conversion data with MSB first. For the AD7912, the data stream consists of two leading zeros, the channel identifier bit that identifies which channel the conversion result corresponds to, followed by the mode bit that indicates the current mode of operation, followed by the 10 bits of conversion data with MSB first and two trailing zeros. 2 3 CS Chip Select. Active low logic input. This input provides the dual function of initiating conversions on the AD7912/AD7922 and framing the serial data transfer. 3 2 SCLK Serial Clock. Logic input. SCLK provides the serial clock for accessing data from the part. This clock input is also used as the clock source for the AD7912/AD7922’s conversion process. 4 1 DIN Data In. Logic input. The channel to be converted is provided on this input and is clocked into an internal register on the falling edge of SCLK. 6, 5 7, 8 V , V Analog Inputs. These two single-ended analog input channels are multiplexed into the on-chip IN0 IN1 track-and-hold amplifier. The analog input channel to be converted is selected by writing to the third MSB on the DIN pin. The input range is 0 to V . DD 7 6 GND Analog Ground. Ground reference point for all circuitry on the AD7912/AD7922. All analog input signals should be referred to this GND voltage. 8 5 V Power Supply Input. The V range for the AD7912/AD7922 is from 2.35 V to 5.25 V. DD DD Rev. 0 | Page 10 of 32

AD7912/AD7922 TERMINOLOGY Integral Nonlinearity Signal-to-Noise + Distortion Ratio (SINAD) The maximum deviation from a straight line passing through The measured ratio of signal-to-noise and distortion at the the endpoints of the ADC transfer function. For the AD7912/ output of the A/D converter. The signal is the rms value of the AD7922, the endpoints of the transfer function are zero scale, a sine wave, and noise is the rms sum of all nonfundamental point 1 LSB below the first code transition, and full scale, a signals up to half the sampling frequency (fs/2), including point 1 LSB above the last code transition. harmonics but excluding dc. Differential Nonlinearity Signal-to-Noise Ratio (SNR) The difference between the measured and the ideal 1 LSB The measured ratio of signal to noise at the output to the A/D change between any two adjacent codes in the ADC. converter. The signal is the rms value of the sine wave input. Noise is the rms quantization error within the Nyquist Offset Error bandwidth (fs/2). The rms value of a sine wave is one-half its peak-to-peak value divided by √2, and the rms value for the The deviation of the first code transition (00…000) to quantization noise is q/√12. The ratio is dependent on the (00… 001) from the ideal, that is, AGND + 1 LSB. number of quantization levels in the digitization process; the Offset Error Match more levels, the smaller the quantization noise. For an ideal N-bit converter, the SNR is defined as The difference in offset error between any two channels. SNR = 6.02N +1.76dB Gain Error Therefore, for a 12-bit converter, SNR is 74 dB; for a 10-bit The deviation of the last code transition (111…110) to converter, SNR is 62 dB. (111…111) from the ideal, that is, V − 1 LSB after the offset DD error has been adjusted out. However, various error sources in the ADC cause the measured SNR to be less than the theoretical value. These errors occur due Gain Error Match to integral and differential nonlinearities, internal ac noise The difference in gain error between any two channels. sources, and so on. Total Unadjusted Error Total Harmonic Distortion (THD) A comprehensive specification that includes gain error, linearity The ratio of the rms sum of harmonics to the fundamental, error, and offset error. which is defined as Channel-to-Channel Isolation V 2 +V 2 +V 2 +V 2 +V 2 2 3 4 5 6 THD(dB)=20log A measure of the level of crosstalk between channels. It is V 1 measured by applying a full-scale sine wave signal of 20 kHz to where: 500 kHz to the nonselected input channel and determining how much that signal is attenuated in the selected channel with a V is the rms amplitude of the fundamental. 1 10 kHz signal. The figure is given worst case across both V, V, V, V, and V are the rms amplitudes of the second 2 3 4 5 6 channels for the AD7912/AD7922. through the sixth harmonics. Track-and-Hold Acquisition Time Peak Harmonic or Spurious Noise The time required for the output of the track-and-hold The ratio of the rms value of the next largest component in the amplifier to reach its final value within ±1 LSB after the end of ADC output spectrum (up to fs /2 and excluding dc) to the rms conversion. The track-and-hold amplifier returns to track mode value of the fundamental. Normally, the value of this specifica- at the end of conversion. See the Serial Interface section for tion is determined by the largest harmonic in the spectrum, but more details. for ADCs where the harmonics are buried in the noise floor, it is a noise peak. Rev. 0 | Page 11 of 32

AD7912/AD7922 Intermodulation Distortion The AD7912/AD7922 are tested using the CCIF standard, where two input frequencies are used (see fa and fb in the With inputs consisting of sine waves at two frequencies, fa and Specifications section). In this case, the second-order terms are fb, any active device with nonlinearities creates distortion usually distanced in frequency from the original sine waves, products at sum and difference frequencies of mfa ± nfb, where while the third-order terms are usually at a frequency close to m, n = 0, 1, 2, 3, and so on. Intermodulation distortion terms are the input frequencies. As a result, the second-order and third- those for which neither m nor n is equal to zero. For example, order terms are specified separately. The calculation of the the second-order terms include (fa + fb) and (fa − fb), while the intermodulation distortion is as in the THD specification, third-order terms include (2fa + fb), (2fa − fb), (fa + 2fb), and where it is defined as the ratio of the rms sum of the individual (fa − 2fb). distortion products to the rms amplitude of the sum of the fundamentals expressed in dB. Rev. 0 | Page 12 of 32

AD7912/AD7922 TYPICAL PERFORMANCE CHARACTERISTICS Figure 10 and Figure 11 show typical FFT plots for the AD7922 Figure 14 and Figure 15 show INL and DNL performance for and AD7912, respectively, at a 1 MSPS sample rate and 100 kHz the AD7922. input frequency. Figure 16 shows a graph of the THD versus the analog input Figure 12 shows the SINAD performance versus the input frequency for different source impedances when using a supply frequency for various supply voltages while sampling at 1 MSPS voltage of 3.6 V and a sampling rate of 1 MSPS. See the Analog with a SCLK frequency of 18 MHz for the AD7922. Input section. Figure 13 shows the SNR performance versus the input fre- Figure 17 shows a graph of the THD versus the analog input quency for various supply voltages while sampling at 1 MSPS frequency for various supply voltages while sampling at 1 MSPS with an SCLK frequency of 18 MHz for the AD7922. with an SCLK frequency of 18 MHz. Figure 18 shows the shutdown current versus the voltage supply for different operating temperatures. 5 –67 8V1D9D2 = P 2O.7INVT FFT VDD = 2.35V –15 FSAMP = 1MSPS –68 FSINNR = =1 0703k.1HdzB VDD = 4.75V SINAD = 72.55dB –69 –35 THD =–81.78dB VDD = 5.25V SNR (dB) –55 SFDR =–83.03dB SINAD (dB) ––7710 –75 VDD = 2.7V –72 –95 –115 04351-0-040 ––7743 VDD = 3.6V 04351-0-043 0 50 100 150 200 250 300 350 400 450 500 10 100 1000 FREQUENCY (kHz) FREQUENCY (kHz) Figure 10. AD7922 Dynamic Performance at 1 MSPS Figure 12. AD7922 SINAD vs. Input Frequency at 1 MSPS –71.6 8192 POINT FFT –10 VDD = 2.7V –71.8 VDD = 2.35V FSAMP = 1MSPS FSINNR = =1 0601k.8H8zdB –72.0 –30 SINAD = 61.83dB VDD = 5.25V THD =–81.12dB –72.2 SFDR =–84.92dB SNR (dB) ––5700 SNR (dB)–––777222...468 VDD = 4.75V –73.0 VDD = 3.6V –90 –73.2 –1100 50 100 150 200 250 300 350 400 450 50004351-0-041 ––7733..4610 VDD = 2.7V 100 100004351-0-044 FREQUENCY (kHz) FREQUENCY (kHz) Figure 11. AD7912 Dynamic Performance at 1 MSPS Figure 13. AD7922 SNR vs. Input Frequency at 1 MSPS Rev. 0 | Page 13 of 32

AD7912/AD7922 1.0 –68 VDD = 2.7V 0.8 FSAMP = 1MSPS –70 TEMPERATURE = 25°C VDD = 4.75V 0.6 –72 VDD = 2.35V 0.4 –74 B) VDD = 2.7V R (LS 0.2 dB) –76 RO 0 D ( –78 R H NL E–0.2 T –80 VDD = 3.6V I–0.4 –82 –0.6 –84 ––10..08 04351-0-045 ––8886 VDD = 5.25V 04351-0-048 0 512 1024 1536 2048 2560 3072 3584 4096 10 100 1000 CODE FREQUENCY (kHz) Figure 14. AD7922 INL Performance Figure 17. THD vs. Analog Input Frequency for Various Supply Voltages 1.0 180 VDD = 2.7V 0.8 FSAMP = 1MSPS 160 TEMPERATURE = 25°C 0.6 A) 140 R (LSB) 00..24 RRENT (n 112000 TEMP = +85°C RO 0 CU R N 80 L E–0.2 OW DN–0.4 UTD 60 H S 40 –0.6 TEMP = +25°C ––10..08 04351-0-046 200 TEMP =–40°C 04351-0-049 0 512 1024 1536 2048 2560 3072 3584 4096 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 CODE SUPPLY VOLTAGE (V) Figure 15. AD7922 DNL Performance Figure 18. Shutdown Current vs. Supply Voltage –20 VDD = 3.6V –30 –40 RIN = 1kΩ B) –50 d D ( TH –60 RIN = 100Ω RIN = 500Ω RIN = 50Ω –70 RIN = 10Ω ––8900 RIN = 0Ω 04351-0-047 10 100 1000 FREQUENCY (kHz) Figure 16. THD vs. Analog Input Frequency for Various Source Impedances Rev. 0 | Page 14 of 32

AD7912/AD7922 CIRCUIT INFORMATION The AD7912/AD7922 are fast, 2-channel, 10-/12-bit, single When the ADC starts a conversion (see Figure 20), SW2 opens supply, analog-to-digital converters (ADCs), respectively. The and SW1 moves to Position B, causing the comparator to parts can be operated from a 2.35 V to 5.25 V supply. When become unbalanced. The control logic and the charge redistri- operated from either a 5 V supply or a 3 V supply, the bution DAC are used to add and subtract fixed amounts of AD7912/AD7922 are capable of throughput rates of 1 MSPS charge from the sampling capacitor to bring the comparator when provided with an 18 MHz clock. back into a balanced condition. When the comparator is rebalanced, the conversion is complete. The control logic The AD7912/AD7922 provide the user with an on-chip track- generates the ADC output code. Figure 21 shows the ADC and-hold, an ADC, and a serial interface, all housed in a tiny transfer function. 8-lead TSOT package or 8-lead MSOP package, which offer the user considerable space-saving advantages over alternative CHARGE solutions. The serial clock input accesses data from the parts, REDISTRIBUTION DAC controls the transfer of data written to the ADC, and provides the clock source for the successive approximation ADC. The SAMPLING A CAPACITOR analog input range is 0 to VDD. An external reference is not VIN0 CONTROL required for the ADC, and neither is there a reference on-chip. VIN1 SW1 CONVERSION SW2 LOGIC B PHASE Tpraohnweg eerre. fseurpenpclye afonrd ,t hthee AreDfo7r9e1, 2g/iAveDs 7th9e2 2w iisd desetr idvyenda fmroicm i nthpeu t AGND VDD/2 COMPARATOR 04351-0-017 Figure 20. ADC Conversion Phase The AD7912/AD7922 feature a power-down option that allows power saving between conversions. The power-down feature is ADC TRANSFER FUNCTION implemented across the standard serial interface as described in The output coding of the AD7912/AD7922 is straight binary. the Modes of Operation section. The AD7912/AD7922 can also The designed code transitions occur at the successive integer be used in daisy-chain mode when several AD7912/AD7922 are LSB values, that is, 1 LSB, 2 LSBs, and so on. The LSB size is connected in a daisy chain. This mode of operation is selected V /4096 for the AD7922 and V /1024 for the AD7912. The DD DD by controlling the logic state of the CS signal. The fourth MSB ideal transfer characteristic for the AD7912/AD7922 is shown on the DOUT pin indicates if the ADC is in normal mode or in Figure 21. daisy-chain mode. CONVERTER OPERATION 111...111 111...110 The AD7912/AD7922 are 10-/12-bit successive approximation ADCs based around a charge redistribution DAC. Figure 19 and ODE 111...000 Figure 20 show simplified schematics of the ADC. Figure 19 C shows the ADC during its acquisition phase. SW2 is closed and ADC 011...111 1LSB = VREF/4096 (AD7922) SW1 is in Position A, the comparator is held in a balanced 1LSB = VREF/1024 (AD7912) 000...010 condition, and the sampling capacitor acquires the signal on the 000...001 selected VIN channel. 000...0000V1LSB ANALOG INPUT +VDD– 1LSB 04351-0-018 CHARGE REDISTRIBUTION DAC Figure 21. AD7912/AD7922 Transfer Characteristic SAMPLING A CAPACITOR VIN0 CONTROL VIN1 SW1 ACQUISITION SW2 LOGIC B PHASE AGND VDD/2 COMPARATOR 04351-0-016 Figure 19. ADC Acquisition Phase Rev. 0 | Page 15 of 32

AD7912/AD7922 TYPICAL CONNECTION DIAGRAM Figure 22 shows a typical connection diagram for the AD7912/ Table 6 provides some typical performance data with various AD7922. V is taken internally from V and as such V references used as a V source and a 50 kHz input tone under REF DD DD DD should be well decoupled. This provides an analog input range the same setup conditions. of 0 V to V . The conversion result is output in a 16-bit word DD Table 6. AD7922 Performance for Various Voltage with two leading zeros, followed by the channel identifier bit References IC that identifies the channel converted, followed by the mode bit Reference Tied to V AD7922 SNR Performance (dB) DD that indicates the current mode of operation, and by the MSB of AD780 at 3 V −73 the 12-bit or 10-bit result. For the AD7912, the 10-bit result is REF193 −72.42 followed by two trailing zeros. See the Serial Interface section. ADR433 −72.9 Alternatively, because the supply current required by the AD780 at 2.5 V −72.86 AD7912/AD7922 is so low, a precision reference can be used as REF192 −72.27 the supply source to the AD7912/AD7922. A REF19x voltage ADR421 −72.75 reference (REF195 for 5 V or REF193 for 3 V) can be used to supply the required voltage to the ADC (see Figure 22). This ANALOG INPUT configuration is especially useful, if the power supply is quite noisy or if the system supply voltages are at some value other Figure 23 shows an equivalent circuit of the analog input than 5 V or 3 V (for example, 15 V). The REF19x outputs a structure of the AD7912/AD7922. The two diodes, D1 and D2, steady voltage to the AD7912/AD7922. If the low dropout provide ESD protection for the analog input. Care must be REF193 is used, the current it needs to supply to the AD7912/ taken to ensure that the analog input signal never exceeds the AD7922 is typically1.5 mA. When the ADC is converting at a supply rails by more than 300 mV, because this would cause rate of 1 MSPS, the REF193 needs to supply a maximum of these diodes to become forward biased and start conducting 2 mA to the AD7912/AD7922. The load regulation of the current into the substrate. The maximum current these diodes REF193 is typically 10 ppm/mA (REF193, VS = 5 V), which can conduct without causing irreversible damage to the part is results in an error of 20 ppm (60 µV) for the 2 mA drawn from 10 mA. it. This corresponds to a 0.082 LSB error for the AD7922 with V = 3 V from the REF193 and a 0.061 LSB error for the VDD DD AD7912. D1 R1 2C0p2F For applications where power consumption is a concern, the VIN C1 power-down mode of the ADC and the sleep mode of the 6pF D2 RanEcFe1. 9Sxee r ethfeer eMnoced essh oouf lOd pbeer autsieodn tsoe cimtiopnro. ve power perform- 04351-0-020 Figure 23. Equivalent Analog Input Circuit 3V 5V REF193 SUPPLY The capacitor C1 in Figure 23 is typically about 6 pF and can 1.5mA 1µF 0.1µF TANT 10µF 0.1µF primarily be attributed to pin capacitance. The resistor R1 is 680nF a lumped component made up of the on resistance of the VDD track-and-hold switch and also includes the on resistance of 0VI NTPOU VTDD VIN0 AD7912/ SCLK the input multiplexer. This resistor is typically about 100 Ω. VIN1 AD7922 DCINS µC/µP The capacitor C2 is the ADC sampling capacitor and has a GND DOUT 04351-0-019 cFaopra acci taapnpclei coaft i2o0n ps,F r etmypoicvainllgy. h igh frequency components from SERIAL the analog input signal is recommended using a band-pass filter INTERFACE on the relevant analog input pin. In applications where har- Figure 22. REF193 as Power Supply to AD7912/AD7922 monic distortion and signal-to-noise ratio are critical, the analog input should be driven from a low impedance source. Large source impedances can significantly affect the ac performance of the ADC. This might necessitate the use of an input buffer amplifier. The choice of the op amp is a function of the particular application. Rev. 0 | Page 16 of 32

AD7912/AD7922 The fourth MSB, STY, is related to the mode of operation of the Table 7 provides some typical performance data with various device. To keep the AD7912/ AD7922 in daisy-chain mode, the op amps used as the input buffer, and a 50 kHz input tone under CHN and STY bits have to be inverted during the conversions the same setup conditions. (STY ≠ CHN). A conversion with STY = CHN on the input Table 7. AD7922 Performance for Various Input Buffers forces the device to normal mode in the next cycle. See the Op Amp in the Input AD7922 SNR Performance (dB) Daisy-Chain Mode section for more details. Buffer 50 kHz Input , V = 3.6 V DD Single op amps If the AD7912/AD7922 are not going to be used in daisy-chain AD8038 −72.79 mode, it is recommended to keep STY and CHN the same AD8510 −72.35 (STY = CHN). In that case, the channel can be selected by tying AD8021 −72.2 DIN either high or low during a conversion cycle. Dual op amps To summarize: AD712 −72.68 AD8022 −72.88 CHN = 0, Channel 0 selected for next conversion. When no amplifier is used to drive the analog input, the source CHN = 1, Channel 1 selected for next conversion. impedance should be limited to low values. The maximum source impedance depends on the amount of total harmonic CHN = STY, forces normal mode in the next cycle. distortion (THD) that can be tolerated. The THD increases as the source impedance increases and performance degrades (see CHN ≠ STY, keeps the AD7912/AD7922 in daisy-chain mode. Figure 16). DIGITAL INPUTS MSXB X CHN STY DON'T CARE LSB 04351-0-021 The digital inputs applied to the AD7912/AD7922 are not Figure 24. AD7912/AD7922 DIN Word limited by the maximum ratings that limit the analog input. DOUT OUTPUT Instead, the digital inputs applied can go to 7 V and are not The conversion result from the AD7912/AD7922 is provided on restricted by the V + 0.3 V limit as on the analog input. For DD this output as a serial data stream. The bits are clocked out on example, if the AD7912/AD7922 are operated with a V of 3 V, DD the SCLK falling edge at the same time that the conversion is then 5 V logic levels could be used on the digital inputs. How- taking place. ever, it is important to note that the data output on DOUT still has 3 V logic levels when V = 3 V. Another advantage of DD The serial data stream for the AD7922 consists of two leading SCLK, DIN, and CS not being restricted by the V + 0.3 V limit DD zeros followed by the bit that identifies the channel converted, is that power supply sequencing issues are avoided. If CS, DIN, the bit that indicates the current mode of operation, and the or SCLK are applied before VDD, then there is no risk of latch-up 12-bit conversion result with MSB provided first. as there would be on the analog inputs if a signal greater than 0.3 V were applied prior to V . For the AD7912, the serial data stream consists of two leading DD zeros followed by the bit that identifies the channel converted, DIN INPUT the bit that indicates the current mode of operation, and the The channel to be converted on in the next conversion is 10-bit conversion result with MSB provided first, followed by selected by writing to the DIN pin. Data on the DIN pin is two trailing zeros. loaded into the AD7912/AD7922 on the falling edge of SCLK. The CHN and MOD bits on DOUT indicate to the user the The data is transferred into the part on the DIN pin at the same current mode of operation of the ADC. If CHN = MOD, time that the conversion result is read from the part. Only the the AD7912/AD7922 are in normal mode. Otherwise, if third and fourth bits of the DIN word are used; the rest are CHN ≠ MOD, the AD7912/AD7922 are in daisy-chain mode. ignored by the ADC. MSB LSB The third MSB is the channel identifier bit, which identifies the 0 0 CHN MOD CONVERSION RESULT 0 0 AD7912 cVhINa0n (nCeHl tNo b=e 0c)o onrv eVrItNe1d ( ConH iNn t=h 1e )n. ext conversion, 0 0 CHN MOD CONVERSION RESULT AD7922 04351-0-022 Figure 25. AD7912/AD7922 DOUT Word Rev. 0 | Page 17 of 32

AD7912/AD7922 MODES OF OPERATION The three modes of operation of the AD7912/AD7922 are CS can idle high until the next conversion or can idle low until normal mode, power-down mode, and daisy-chain mode. The CS returns high sometime prior to the next conversion mode of operation is selected by controlling the logic state of (effectively idling CS low). Once a data transfer is complete the CS signal. The point at which CS is pulled high after the (DOUT has returned to three-state), another conversion can be conversion has been initiated determines whether the initiated after the quiet time, t , has elapsed by bringing CS QUIET AD7912/AD7922 enter power-down mode or change to daisy- low again. chain mode. Similarly, if already in daisy-chain mode, CS can POWER-DOWN MODE control whether the device returns to normal operation or enters power-down mode. The user can also change from daisy- Power-down mode is intended for use in applications where chain mode to normal mode by writing to the DIN pin, as slower throughput rates are required. Either the ADC is outlined in the DIN Input section. powered down between each conversion, or a series of conversions can be performed at a high throughput rate and Power-down mode is designed to provide flexible power then the ADC is powered down for a relatively long duration management options and to optimize the ratio of power between these bursts of several conversions. When the AD7912/ dissipation to throughput rate for different application AD7922 are in power-down mode, all analog circuitry is requirements. powered down. Daisy-chain mode is intended for applications where fast To enter power-down mode, the conversion process must be throughput rate is not required and more than one interrupted by bringing CS high any time after the second AD7912/AD7922 have been connected in a daisy chain, as falling edge of SCLK and before the 10th falling edge of SCLK, shown in Figure 33. as shown in Figure 28. Once CS has been brought high in this NORMAL MODE window of SCLKs, then the part enters power-down mode, the conversion that was initiated by the falling edge of CS is termi- Normal mode is intended for the fastest throughput rate performance. The user does not have to worry about any nated, and DOUT goes back into three-state. If CS is brought power-up time, because the AD7912/AD7922 remain fully high before the second SCLK falling edge, then the part remains powered all the time. Figure 26 shows the operation of the in normal mode and does not power down. This helps to avoid AD7912/AD7922 in this mode. accidental power-down due to glitches on the CS line. The conversion is initiated on the falling edge of CS as To exit this mode of operation and power the AD7912/AD7922 described in the Serial Interface section. To ensure that the part up again, a dummy conversion is performed. On the falling edge remains fully powered up at all times, CS must remain low until of CS, the device begins to power up and continues to power up at least 10 SCLK falling edges have elapsed after the falling edge as long as CS is held low until after the falling edge of the of CS. If CS is brought high after the 10th SCLK falling edge 10th SCLK. The device is fully powered up once 16 SCLKs have and before the 12th SCLK falling edge, then the device enters elapsed and valid data results from the next conversion, as daisy-chain mode, as shown in Figure 27. The conversion is shown in Figure 29. If CS is brought high before the 10th falling terminated and DOUT goes back into three-state. If CS is edge of SCLK, then the AD7912/AD7922 go back into power- brought high after the 13th SCLK falling edge, but before the down mode. This helps to avoid accidental power-up due to end of t , the conversion is terminated and DOUT goes glitches on the CS line or an inadvertent burst of 8 SCLK cycles CONVERT back into three-state, but the part remains in normal mode. while CS is low. Therefore, although the device might begin to power up on the falling edge of CS, it powers down again on the For the AD7922, 16 serial clock cycles are required to complete rising edge of CS, as long as this occurs before the 10th SCLK the conversion and access the complete conversion result. For falling edge. the AD7912, a minimum of 14 serial clock cycles are required to complete the conversion and access the complete conversion result. Rev. 0 | Page 18 of 32

AD7912/AD7922 AD7912/AD7922 CS 1 10 12 14 16 1 10 12 14 16 SCLK DIN CHANNEL FOR NEXT CONVERSION CHANNEL FOR NEXT CONVERSION DOUT CONVERSION RESULT CONVERSION RESULT 04351-0-023 Figure 26. Normal Mode Operation THE PART ENTERS DAISY-CHAIN MODE CS 1 2 10 12 16 SCLK THREE-STATE DIN INVALID DATA DOUT INVALID DATA THREE-STATE 04351-0-025 Figure 27. Entering Daisy-Chain Mode CS 1 2 10 16 SCLK THREE-STATE DIN INVALID DATA DOUT INVALID DATA THREE-STATE 04351-0-024 Figure 28. Entering Power- Down Mode THE PART BEGINS TO POWER UP THE PART IS FULLY THINE TPOA RTRT AGCOKES PFUOLWLEYR AECDQ UUPIR WEIDTH VIN CS NORMAL MODE A 1 5 10 13 16 1 16 SCLK DIN CHANNEL FOR NEXT CONVERSION CHANNEL FOR NEXT CONVERSION DOUT INVALID DATA CONVERSION RESULT 04351-0-026 Figure 29. Exiting Power-Down Mode Rev. 0 | Page 19 of 32

AD7912/AD7922 POWER-UP TIME the ADC. If the first valid conversion is then performed directly after the dummy conversion, care must be taken to ensure that The power-up time of the AD7912/AD7922 is 1 µs, which adequate acquisition time has been allowed. When the ADC means that with any frequency of SCLK up to 18 MHz, one powers up initially after supplies are applied, the track-and-hold dummy cycle is always sufficient to allow the device to power is in hold. It returns to track on the fifth SCLK falling edge that up. Once the dummy cycle is complete, the ADC is fully the part receives after the falling edge of CS. powered up and the input signal is fully acquired. The quiet time, tQUIET, must still be allowed from the point at which the DAISY-CHAIN MODE bus goes back into three-state after the dummy conversion to When the ADC is in this mode of operation, the part operates the next falling edge of CS. When running at a 1 MSPS as a shift register. This mode is intended for applications where throughput rate, the AD7912/AD7922 power up and acquire a more than one ADC is used, connected in a daisy-chain signal within ±1 LSB in one dummy cycle, that is, 1 µs. configuration (see Figure 33). All ADCs are addressed by the When powering up from power-down mode with a dummy same CS signal and the same serial clock. The conversion result cycle, as in Figure 29, the track-and-hold that was in hold mode stored in the internal shift register in each ADC is shifted from while the part was powered down returns to track mode on the one device to the following in the chain. See the Daisy-Chain fifth SCLK falling edge that the part receives after the falling Example in the following section for more details. edge of CS. This is shown as point A in Figure 29. At this point, To enter daisy-chain mode, the conversion process must be the part starts to acquire the signal on the channel selected in interrupted by bringing CS high after the 10th falling edge of the current dummy conversion. SCLK and before the 12th falling edge of SCLK, as shown in Although at any SCLK frequency one dummy cycle is sufficient Figure 27. To ensure that the AD7912/AD7922 are placed into to power up the device and acquire VIN, it does not necessarily daisy-chain mode, CS should not be brought high until at mean that a full dummy cycle of 16 SCLKs must always elapse least 20 ns after the 10th SCLK falling edge and before the to power up the device and acquire VIN fully. 1 µs is sufficient to 12th SCLK falling edge. Once CS has been brought high in power up the device and acquire the input signal. For example, this window of SCLKs, the part enters daisy-chain mode, the if a 5 MHz SCLK frequency was applied to the ADC, the cycle conversion that was initiated by the falling edge of CS is time would be 3.2 µs. In one dummy cycle, 3.2 µs, the part terminated, and DOUT goes back into three-state. would be powered up and V acquired fully. However, after 1 µs IN with a 5 MHz SCLK, only five SCLK cycles would have elapsed. If CS is brought high between the 10th and the 12th SCLK At this stage, the ADC would be fully powered up and the signal falling edge, the part enters daisy-chain mode and the data is acquired. Therefore, in this case, CS can be brought high after shifted from one ADC to the next one in the chain is valid data the 10th SCLK falling edge. If CS is brought high anytime after (see Figure 34 and Figure 35). If CS is brought high between the the 13th SCLK falling edge, the part enters normal mode for the 12th and the 13th SCLK falling edge, the part enters daisy-chain next conversion. CS has to be brought low again after a time, mode, but the data shifted in the chain is invalid data. t , to initiate the conversion. However, if CS is brought high QUIET To keep the part in daisy-chain mode, the CHN and STY bits in anytime after the 10th and before the 12th SCLK falling edge, the DIN word must be inverted relative to each other in each the part enters daisy-chain mode. 16 SCLKs cycle. A conversion with the CHN and STY bits set to the same value in the DIN word while the device is in daisy- When power supplies are first applied to the AD7912/AD7922, chain mode forces the part to go back into normal mode in the the ADC can power up in either power-down mode, normal next cycle, as shown in Figure 30. mode, or daisy-chain mode. Because of this, it is best to allow a dummy cycle to elapse to ensure that the part is fully powered To exit this mode of operation, the user can perform a dummy up before attempting a valid conversion. Likewise, if the user cycle or can set the STY bit to the CHN bit value on the DIN wants to keep the part in power-down mode while not in use word during a conversion cycle. When performing a dummy and to power up in power-down mode, then the dummy cycle conversion to exit this mode, CS must be brought high anytime can be used to ensure that the device is in power-down mode by after the 10th SCLK falling edge and before the 13th SCLK executing a cycle such as that shown in Figure 28. falling edge, as shown in Figure 31. The device enters normal Once supplies are applied to the AD7912/AD7922, the power- mode, and valid data from the channel selected in the dummy up time is the same as when powering up from the power-down cycle results in the next conversion. mode. It takes the part approximately 1 µs to power up fully in Figure 32 summarizes the modes of operation, how to change normal mode. It is not necessary to wait 1 µs before executing a between modes, the values for the bits in the DIN and DOUT dummy cycle to ensure the desired mode of operation. Instead, words in different modes, and in the transitions between modes. the dummy cycle can occur directly after power is supplied to Rev. 0 | Page 20 of 32

AD7912/AD7922 CS DAISY-CHAIN CYCLE NORMAL MODE 1 10 12 14 16 1 10 12 14 16 SCLK DIN CH = STY CHANNEL FOR NEXT CONVERSION DOUT VALID DATA CONVERSION RESULT 04351-0-028 Figure 30. Exiting Daisy-Chain Mode with CH = STY in the DIN Pin THE PART ENTERS NORMAL MODE CS NORMAL MODE A 1 10 13 16 1 16 SCLK DIN CHANNEL FOR NEXT CONVERSION CHANNEL FOR NEXT CONVERSION DOUT INVALID DATA CONVERSION RESULT 04351-0-027 Figure 31. Exiting Daisy-Chain Mode CS HIGH BETWEEN THE 10TH–13TH SCLK CONVERSION CYCLE DIN: CHN≠ STY CONVERSION CYCLE DIN: CHN = STY CONVERSION NORMAL MODE DAISY-CHAIN MODE CYCLE DOUT: CHN = MOD DOUT:CHN≠ MOD *CS HIGH BETWEEN THE 10TH–12TH SCLK POWER-UP TIME AND CS HIGH AFTER THE 13TH SCLK CS HIGH BETWEEN CS HIGH BETWEEN POWER-UP TIME AND THE 2ND–10TH SCLK THE 2ND–10TH SCLK CS HIGH BETWEEN POWER-DOWN THE 10TH–12TH SCLK MODE *IF CS IS BROUGHT HIGH BETWEEN THE 10TH AND THE 12TH SCLK FALLING EDGE, THE DATA SHIFTED FROM ONE ADC TO THE NEXT ONE IN THE CHAIN, WHILE THE PARTS ARE IN DAISY-CHAIN MODE, IS VALID DATA. IAFD CCS T IOS BTHREO UNGEXHTT OHINGEH I NB ETTHWE ECEHNA TINH,E W 1H2ITLHE ATHNED PTHAER T1S3 TAHR SEC INL KD AFAISLYL-ICNHGA EIND GMEO,D TEH,E IS D IANTVAA LSIHDI FDTAETDA F.ROM ONE 04351-0-029 Figure 32. Transitions between Modes of Operation Rev. 0 | Page 21 of 32

AD7912/AD7922 DAISY-CHAIN EXAMPLE tion data for the second last device in the chain, and so on. In applications where fast throughput is not critical, connecting Then the selected channel for the first device in the chain is several ADCs in a daisy chain lets the user perform simultane- clocked in the cycle executed after all the data has been ous sampling on all the ADCs contained in the chain using the read, that is, in the short cycle used to change modes of minimum number of I/O lines from the µC/DSP ports. operation. See Figure 34. The user needs to alternate modes of operation in the ADCs. 4. Enter normal mode. While the parts are in normal mode, the conversion is per- After reading the conversion results from the AD7912/ formed and the result from each ADC is stored in its internal AD7922, the devices need to be placed into normal mode register. Following the conversion, the parts are placed into to perform a new conversion. Therefore, in this cycle CS is daisy-chain mode and the user can proceed to read the result from each ADC by shifting the data from one ADC to the next. brought high between the 10th and the 13th SCLK falling edge. The DOUT line contains invalid data and DIN For clarity in the following example, only two devices are contains the selected channel for the first device in the connected in a daisy chain. Both AD7912/AD7922 are chain. The remaining devices in the chain have already set addressed by the same CS and SCLK signal. The devices are the channel for the next conversion as a result of the data configured as shown in Figure 33 for simultaneous conversion shifted in during daisy-chain mode. and shifting read operation later. The output of the device on 5. Normal conversion. the left, ADC1, feeds the input of the device on the right, ADC2. A new conversion can be performed on the newly selected During a normal conversion, the conversion result is stored channels. The process can be repeated by following the internally and output to the DOUT pin. In daisy-chain mode, previous steps. the value internally stored is output through the DOUT pin and Figure 34 shows the timing diagram for two AD7912/ the information provided at the DIN pin is shifted into the AD7922 connected in a daisy chain, as shown in Figure 33. internal register. The DIN signal corresponds to the DIN pin on the first When several AD7912/AD7922 are connected in a daisy chain, AD7912/AD7922 in the chain, and the DOUT signal the sequence is as follows: corresponds to the DOUT pin on the last AD7912/AD7922 in the chain. The words clocked into the DIN pin, which 1. Normal conversion. set up the channel for the next conversion for the two Every AD7912/AD7922 performs a conversion on its AD7912/AD7922, are shown as COMMAND1 and selected channel and the result is stored in the internal shift COMMAND2. The first word clocked in, COMMAND3, register. does not remain in any of the ADCs in the chain and is eventually lost. The channel configuration data for the first 2. Entering daisy-chain mode. device in the chain, COMMAND1, is clocked in while In this cycle, CS is brought high between the 10th and changing from daisy-chain mode to normal mode. 12th SCLK falling edges and all the devices enter daisy- chain mode. Figure 35 is a more detailed diagram that shows the data presented on the DIN pin and clocked out on the DOUT 3. Daisy-chain cycles. pin for each of the AD7912/AD7922 in Figure 33. If the While the AD7912/AD7922 are in daisy-chain mode, the DOUT1 (or DIN2) signal is ignored, Figure 35 brings conversion results from all the devices in the chain are about Figure 34. read, and the parts are configured for the next conversion. CS The user needs to perform as many read cycles as there are FSX SCLK devices in the chain. To keep all the AD7912/AD7922 in SCLK daisy-chain mode, the CHN and STY bits in the DIN input must always be inverted. Data is shifted through the µC/DSP SCLK CS SCLK CS devices in the chain. Data is clocked into the device in the DIN DOUT TX DIN1 DOUT1 DIN2 DOUT2 chain by the same clock used to clock data out. The first wdaoirsdy- cclhoacikne dm iondtoe itsh eev DenINtu aplilny olonsct.e T thhee dseecvoicneds waroer idn DR ADC1 ADC2 04351-0-030 clocked into the DIN pin contains the channel configura- Figure 33. AD7912/AD7922 Connected in Daisy Chain tion data for the last device in the chain, the third word clocked into the DIN pin contains the channel configura- Rev. 0 | Page 22 of 32

AD7912/AD7922 CHANGE MODE CS HIGH CHANGE MODE NORMAL MODE BETWEEN THE DDAAISTYA-C ISH ASIHNI FMTOEDDE DDAAISTYA-C ISH ASIHNI FMTOEDDE CS HIGH BETWEEN THE NORMAL MODE CONVERSION ON THE 10TH–12TH SCLK FROM ONE ADC TO FROM ONE ADC TO 10TH–13TH SCLK CONVERSION ON THE TWO DEVICES FALLING EDGE THE NEXT ONE THE NEXT ONE FALLING EDGE TWO DEVICES CS SCLK THE DATA WILL BE SET CHANNEL SET CHANNEL EVENTUALLY LOST, FOR ADC2, FOR ADC1, COMMAND3 COMMAND2 COMMAND1 DIN DON'T CARE DON'T CARE CH≠ STY CH≠ STY DON'T CARE DON'T CARE KEEP THE DEVICES IN DAISY-CHAIN MODE DOUT DON'T CARE DON'T CARE VALID DATA ADC2 VALID DATA ADC1 DON'T CARE DON'T CARE 04351-0-031 Figure 34. Daisy-Chain Diagrams—1 THE PARTS ENTER DAISY-CHAIN MODE NORMAL CONVERSION DAISY-CHAIN CYCLE CS 1 16 1 10 12 1 10 12 14 16 SCLK DIN DON'T CARE DON'T CARE COMMAND3 WITH CHN≠ STY SHIFTED INTO THE ADC1 INTERNAL REGISTER, THIS DATA WILL BE EVENTUALLY LOST D(DOINU2T)1* (00,, 00,, CCHHNN == MSOTYD,, VVAALLIIDD DDAATTAA AADDCC11) DON'T CARE (00,, 00,, CCHHNN≠≠MSOTYD,, VVAALLIIDD DDAATTAA AADDCC11) SHIFTED INTO THE ADC2 INTERNAL REGISTER DOUT 0, 0, CHN = MOD, VALID DATA ADC2 DON'T CARE 0, 0, CHN≠MOD, VALID DATA ADC2 THE PARTS ENTER NORMAL MODE CS DAISY-CHAIN CYCLE NORMAL CONVERSION 1 10 12 14 16 1 10 13 1 16 SCLK DIN COMMAND2 WITH CHN≠STY COMMAND1 DON'T CARE SHIFTED INTO THE ADC1 SHIFTED INTO THE ADC1 INTERNAL REGISTER, IT INTERNAL REGISTER CONTAINS CHANNEL FOR NEXT CONVERSION ON ADC1 D(DOINU2T)1* COMMAND3 COMMAND2 (00,, 00,, CCHHNN == MSOTYD,, VVAALLIIDD DDAATTAA AADDCC11) SHIFTED INTO THE ADC2 SHIFTED INTO THE ADC2 INTERNAL REGISTER, IT INTERNAL REGISTER CONTAINS CHANNEL FOR NEXT CONVERSION ON ADC2 DOUT 0, 0, CHN≠MOD, VALID DATA ADC1 COMMAND3 0, 0, CHN = MOD, VALID DATA ADC2 N*INOFTOERMATION IN BRACKETS CORRESPONDS TO DATA CLOCKED INTO DIN2 PIN 04351-0-032 Figure 35. Daisy-Chain Diagrams—II Rev. 0 | Page 23 of 32

AD7912/AD7922 POWER VS. THROUGHPUT RATE By using the power-down mode on the AD7912/AD7922 when In the previous calculations, the power dissipation when the not converting, the average power consumption of the ADC part is in power-down mode has not been taken into account. decreases at lower throughput rates. Figure 36 shows how, as the By placing the parts into power-down mode between conver- throughput rate is reduced, the device remains in its power- sions, the average power consumed by the ADC decreases as down state longer and the average power consumption over the throughput rate decreases, because the ADC remains in a time drops. power-down state for a longer time. For example, if the AD7912/AD7922 are operating in a continu- Figure 36 shows the power consumption versus throughput rate ous sampling mode with a throughput rate of 100 kSPS and a when using the power-down mode between conversions with SCLK of 18 MHz (V = 5 V), and the devices are placed in the both 5 V and 3 V supplies. DD power-down mode between conversions, then the power Power-down mode is intended for use with throughput rates of consumption is calculated as follows. The power dissipation approximately 330 kSPS and under, because at higher sampling during normal operation is 20 mW (V = 5 V). If the power-up DD rates the short time spent in power-down does not affect the time is one dummy cycle (1 µs), and the remaining conversion average power consumed by the ADC. time is another cycle (1 µs), then the AD7912/AD7922 dissipate 20 mW for 2 µs during each conversion cycle. If the throughput 100 rate is 100 kSPS and the cycle time is 10 µs, then the average power dissipated during each cycle is VDD = 5V, SCLK = 18MHz 10 (2/10) × (20 mW) = 4 mW W) Idfo VwDnD m= o3d Ve, bSeCtLwKee =n 1c8o nMveHrszi, oannsd, tthheen d tehvei cpeo iws earg adiins siinp aptoiowne r- R (m 1 VDD = 3V, SCLK = 18MHz E W during normal operation is 6 mW. The AD7912/AD7922 now O P dissipate 6 mW for 2 µs during each conversion cycle. With a throughput rate of 100 kSPS, the average power dissipated 0.1 durin(g2 /e1a0c)h × c (y6c lme iWs ) = 1.2 mW 0.01 04351-0-033 0 50 100 150 200 250 300 350 THROUGHPUT (kSPS) Figure 36. Power Consumption vs. Throughput Rate Rev. 0 | Page 24 of 32

AD7912/AD7922 SERIAL INTERFACE Figure 37 and Figure 38 show the detailed timing diagrams for If the rising edge of CS occurs before 14 SCLKs have elapsed, serial interfacing to the AD7922 and AD7912, respectively. The then the conversion is terminated and the DOUT line goes back serial clock provides the conversion clock and also controls the into three-state. If 16 SCLKs are considered in the cycle, DOUT transfer of information from the AD7912/AD7922 during returns to three-state on the 16th SCLK falling edge, as shown conversion. in Figure 38. The CS signal initiates the data transfer and conversion process. CS going low clocks out the first leading zero to be read in by The falling edge of CS puts the track-and-hold into hold mode, the microcontroller or DSP. The remaining data is then clocked takes the bus out of three-state. The analog input is sampled at out by subsequent SCLK falling edges beginning with the this point and the conversion is initiated. second leading zero. Therefore, the first falling clock edge on the serial clock has the first leading zero provided and also For the AD7922, the conversion requires 16 SCLK cycles to clocks out the second leading zero. The final bit in the data complete. Once 13 SCLK falling edges have elapsed, the track- transfer is valid on the 16th falling edge, having been clocked and-hold goes back into track on the next SCLK rising edge, as out on the previous (15th) falling edge. shown in Figure 37 at Point B. On the 16th SCLK falling edge, the DOUT line goes back into three-state. If the rising edge of In applications with a slower SCLK, it is possible to read in data CS occurs before 16 SCLKs have elapsed, then the conversion is on each SCLK rising edge. In that case, the first falling edge of terminated and the DOUT line goes back into three-state. SCLK clocks out the second leading zero and it can be read in Otherwise, DOUT returns to three-state on the 16th SCLK the first rising edge. However, the first leading zero that is falling edge, as shown in Figure 37. Sixteen serial clock cycles clocked out when CS goes low is missed, unless it is read on the are required to perform the conversion process and to access first falling SCLK edge. The 15th falling edge of SCLK clocks data from the AD7922. out the last bit and it can be read in the 15th rising SCLK edge. For the AD7912, the conversion requires 14 SCLK cycles to If CS goes low just after the SCLK falling edge has elapsed, CS complete. Once 13 SCLK falling edges have elapsed, the track- clocks out the first leading zero as before and it can be read in and-hold goes back into track on the next SCLK rising edge, as the SCLK rising edge. The next SCLK falling edge clocks out shown in Figure 38 at Point B. the second leading zero and it can be read in the following rising edge. t 1 CS t CONVERT t2 t6 B SCLK 1 2 3 4 5 13 14 15 16 t3 t4 t7 t5 t10 tQUIET DOUT Z ZERO CHN MOD DB11 DB10 DB2 DB1 DB0 DIN THREE-SXTATE X tC8HN STYt9 X X X X X THREE-STATE 04351-0-034 Figure 37. AD7922 Serial Interface Timing Diagram t 1 CS t CONVERT t2 t6 B SCLK 1 2 3 4 5 13 14 15 16 t3 t4 t7 t5 t10 tQUIET DOUT Z ZERO CHN MOD DB9 DB8 DB0 ZERO ZERO DIN THREE-SXTATE X tC8HN STYt9 X X TWXO TRAILXING ZERXOS THREE-STATE 04351-0-035 Figure 38. AD7912 Serial Interface Timing Diagram Rev. 0 | Page 25 of 32

AD7912/AD7922 AD7912/AD7922 to ADSP-218x MICROPROCESSOR INTERFACING The ADSP-218x family of DSPs are interfaced directly to the The serial interface on the AD7912/AD7922 allows the parts to AD7912/AD7922 without any glue logic required. The SPORT be directly connected to a range of microprocessors. This control register should be set up as follows: section explains how to interface the AD7912/AD7922 with some of the more common microcontroller and DSP serial TFSW = RFSW = 1, alternate framing interface protocols. INVRFS = INVTFS = 1, active low frame signal AD7912/AD7922 to TMS320C541 Interface DTYPE = 00, right-justify data ISCLK = 1, internal serial clock The serial interface on the TMS320C541 uses a continuous TFSR = RFSR = 1, frame every word serial clock and frame synchronization signals to synchronize IRFS = 0, set up RFS as an input the data transfer operations with peripheral devices like the ITFS = 1, set up TFS as an output AD7912/AD7922. The CS input allows easy interfacing between SLEN = 1111, 16 bits for the AD7922 the TMS320C541 and the AD7912/AD7922 without any glue SLEN = 1101, 14 bits for the AD7912 logic required. The serial port of the TMS320C541 is set up to operate in burst mode (FSM = 1 in the serial port control To implement the power-down mode, SLEN should be set to register, SPC) with the internal serial clock CLKX (MCM = 1 in 0111 to issue an 8-bit SCLK burst. The connection diagram is the SPC register) and the internal frame signal (TXM = 1 in the shown in Figure 40. The ADSP-218x has the TFS and RFS of the SPC register); therefore, both pins are configured as outputs. For SPORT tied together, with TFS set as an output and RFS set as the AD7922, the word length should be set to 16 bits (FO = 0 in an input. The DSP operates in alternate framing mode and the the SPC register). This DSP allows frames with a word length of SPORT control register is set up as described previously. The 16 bits or 8 bits only. In the AD7912, therefore, where 14 bits are frame synchronization signal generated on the TFS is tied to CS required, the FO bit should be set up to 16 bits, and 16 SCLKs and, as with all signal processing applications, equidistant are needed. For the AD7912, two trailing zeros are clocked out sampling is necessary. However, in this example, the timer in the last two clock cycles. interrupt is used to control the sampling rate of the ADC and, under certain conditions, equidistant sampling might not be The values in the SPC register are as follows: achieved. FO = 0 FSM = 1 AD7912/ ADSP-218x* AD7922* MCM = 1 SCLK SCLK TXM = 1 DOUT DR To implement the power-down mode on the AD7912/AD7922, DIN DT the format bit, FO, can be set to 1, which sets the word length to CS RFS 8 bits. TFS 04351-0-037 The connection diagram is shown in Figure 39. Note that, for *ADDITIONAL PINS REMOVED FOR CLARITY signal processing applications, the frame synchronization signal Figure 40. Interfacing to the ADSP-218x from the TMS320C541 must provide equidistant sampling. The timer registers are loaded with a value that provides an AD7912/ TMS320C541* interrupt at the required sample interval. When an interrupt is AD7922* received, a value is transmitted with TFS/DT (ADC control SCLK CLKX word). The TFS is used to control the RFS and, therefore, the CLKR reading of data. The frequency of the serial clock is set in the DOUT DR DIN DX SCLKDIV register. When the instruction to transmit with TFS CS FFSSXR 04351-0-036 iTasgh gaeii vnDe bnSeP, ft ohwraeat i ttirssa , unTnsXtmi0l i ts=hs ieAo SnXC 0sLt, atKhrt ehs .sa Itsfa gtteho eno fet i thmhiege rhS ,Ca lnoLdwK ,S iaCsn LcdhK he cvigkahleud e. s *ADDITIONAL PINS REMOVED FOR CLARITY are chosen such that the instruction to transmit occurs on or Figure 39. Interfacing to the TMS320C541 near the rising edge of SCLK, the data might be transmitted or it might wait until the next clock edge. Rev. 0 | Page 26 of 32

AD7912/AD7922 low and a conversion starts. Likewise, by means of the Bits For example, the ADSP-2189 has a master clock frequency of SCD2, SCKD, and SHFD in the CRB register, the Pin SC2 (the 40 MHz. If the SCLKDIV register is loaded with the value of 3, frame sync signal) and SCK in the serial port are configured as then an SCLK of 5 MHz is obtained, and eight master clock outputs, and the MSB is shifted first. periods elapse for every one SCLK period. Depending on the throughput rate selected, if the timer register is loaded with the The values are as follows: value 803 (803 + 1 = 804), then 100.5 SCLK occur between interrupts and subsequently between transmit instructions. This MOD = 0 situation results in nonequidistant sampling, because the SYN = 1 transmit instruction occurs on a SCLK edge. If the number of WL2, WL1, WL0 depend on the word length SCLKs between interrupts is a whole integer figure of N, then FSL1 = 0, FSL0 = 0 equidistant sampling is implemented by the DSP. FSP = 1, negative frame sync SCD2 = 1 AD7912/AD7922 to DSP563xx Interface SCKD = 1 The connection diagram in Figure 41 shows how the AD7912/ SHFD = 0 AD7922 can be connected to the SSI (synchronous serial interface) of the DSP563xx family of DSPs from Motorola. The Note that, for signal processing applications, the frame SSI is operated in synchronous and normal mode (SYN = 1 and synchronization signal from the DSP563xx must provide MOD = 0 in the Control Register B, CRB) with internally equidistant sampling. generated word frame sync for both Tx and Rx (Bits FSL1 = 0 and FSL0 = 0 in the CRB). Set the word length in the Control AD7912/ DSP563xx* AD7922* Register A (CRA) to 16 by setting bits WL2 = 0, WL1 = 1, and WL0 = 0 for the AD7922. This DSP does not offer the option for SCLK SCK a 14-bit word length, so the AD7912 word length is set up to DOUT SRD 16 bits like the AD7922. For the AD7912, the conversion process DIN STD uses 16 SCLK cycles, with the last two clock periods clocking out two trailing zeros to fill the 16-bit word. CS SC2 04351-0-038 To implement the power-down mode on the AD7912/AD7922, *ADDITIONAL PINS REMOVED FOR CLARITY the word length can be changed to 8 bits by setting Bits Figure 41. Interfacing to the DSP563xx WL2 = 0, WL1 = 0, and WL0 = 0 in CRA. The FSP bit in the CRB register can be set to 1, which means that the frame goes Rev. 0 | Page 27 of 32

AD7912/AD7922 APPLICATION HINTS GROUNDING AND LAYOUT ground to avoid radiating noise to other sections of the board, The printed circuit board that houses the AD7912/AD7922 and clock signals should never be run near the analog inputs. should be designed such that the analog and digital sections are Avoid crossover of digital and analog signals. Traces on opposite separated and confined to certain areas of the board. This sides of the board should run at right angles to each other to facilitates the use of ground planes that can be separated easily. reduce the effects of feedthrough through the board. A micro- A minimum etch technique is generally best for ground planes, strip technique is by far the best, but is not always possible with because it gives the best shielding. Digital and analog ground a double-sided board. In this technique, the component side of planes should be joined at only one place. If the AD7912/ the board is dedicated to ground planes, while signals are placed AD7922 are in a system where multiple devices require an on the solder side. AGND-to-DGND connection, the connection should still be made at one point only, a star ground point that should be Good decoupling is also very important. The analog supply established as close as possible to the AD7912/AD7922. should be decoupled with 10 µF tantalum in parallel with 0.1 µF capacitors to AGND. To achieve the best performance from Avoid running digital lines under the device, because these these decoupling components, the user should endeavor to keep couple noise onto the die. The analog ground plane should be the distance between the decoupling capacitor and the V and allowed to run under the AD7912/AD7922 to avoid noise DD GND pins to a minimum with short track lengths connecting coupling. The power supply lines to the AD7912/AD7922 the respective pins. should use as large a trace as possible to provide low impedance paths and reduce the effects of glitches on the power supply line. Fast-switching signals like clocks should be shielded with digital Rev. 0 | Page 28 of 32

AD7912/AD7922 EVALUATING AD7912/AD7922 PERFORMANCE The evaluation board package includes a fully assembled and The software allows the user to perform ac (Fast Fourier tested evaluation board, documentation, and software for Transform) and dc (histograms of codes) tests on the controlling the board from a PC via the EVAL-CONTROL AD7912/AD7922. BRD2. See the AD7912/AD7922 Technical Note for more information. The EVAL-CONTROL BRD2 can be used in conjunction with The technical note is included in the software, and it can also be the AD7912CB/AD7922CB evaluation board, as well as many found on the www.analog.com website under the Design Tools other Analog Devices evaluation boards ending in the CB link on the AD7912/AD7922 product page. designator to demonstrate and evaluate the ac and dc performance of the AD7912/AD7922. Rev. 0 | Page 29 of 32

AD7912/AD7922 OUTLINE DIMENSIONS 2.90BSC 3.00 BSC 8 7 6 5 8 5 1.60BSC 2.80BSC 3.00 4.90 BSC BSC 1 2 3 4 4 PIN 1 INDICATOR 0.65BSC PIN 1 1.95 0.65 BSC 0.90 BSC 0.87 0.84 0.15 1.10 MAX 0.00 1.00MAX 0.20 COPL0A.1N000..A32R82ITY SPELAANTIENG 00..2038 80°° 000...864000 0.10MAX 00..3282 SPELAANTIENG 0.08 840°°° 000...643050 COMPLIANT TO JEDEC STANDARDS MO-187AA COMPLIANT TO JEDEC STANDARDS MO-193BA Figure 42. 8-Lead Mini Small Outline Package [MSOP] Figure 43. 8-Lead Thin Small Outline Transistor Package [TSOT] (RM-8) (UJ-8) Dimensions shown in millimeters Dimensions shown in millimeters ORDERING GUIDE Temperature Linearity Package Package Model Range Error (LSB)1 Description Option Branding Quantity AD7912ARM −40°C to +85°C ±0.5 max 8-lead MSOP RM-8 C1A 1 AD7912ARM-REEL −40°C to +85°C ±0.5 max 8-lead MSOP RM-8 C1A 3000 AD7912ARM-REEL7 −40°C to +85°C ±0.5 max 8-lead MSOP RM-8 C1A 1000 AD7912AUJ-R2 −40°C to +85°C ±0.5 max 8-lead TSOT UJ-8 C1A 250 AD7912AUJ-REEL7 −40°C to +85°C ±0.5 max 8-lead TSOT UJ-8 C1A 3000 AD7922ARM −40°C to +85°C ±1.5 max 8-lead MSOP RM-8 C1B 1 AD7922ARM-REEL −40°C to +85°C ±1.5 max 8-lead MSOP RM-8 C1B 3000 AD7922ARM-REEL7 −40°C to +85°C ±1.5 max 8-lead MSOP RM-8 C1B 1000 AD7922AUJ-R2 −40°C to +85°C ±1.5 max 8-lead TSOT UJ-8 C1B 250 AD7922AUJ-REEL7 −40°C to +85°C ±1.5 max 8-lead TSOT UJ-8 C1B 3000 EVAL-AD7912CB2 Evaluation Board EVAL-AD7922CB2 Evaluation Board EVAL-CONTROL BRD23 Evaluation Control Board 1 Linearity error here refers to integral nonlinearity. 2 This evaluation board can be used standalone or in conjunction with the EVAL-CONTROL BRD2 for evaluation or demonstration purposes. 3 This board is a complete unit, allowing a PC to control and communicate with all Analog Devices evaluation boards ending in the CB designator. To order a complete evaluation kit, order a particular ADC evaluation board (EVAL-AD7922 CB, for example), the EVAL-CONTROL BRD2, and a 12 ac transformer. See the relevant evaluation board technical note for more information. Rev. 0 | Page 30 of 32

AD7912/AD7922 NOTES Rev. 0 | Page 31 of 32

AD7912/AD7922 NOTES © 2004 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D04351–0–4/04(0) Rev. 0 | Page 32 of 32

Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: A nalog Devices Inc.: AD7922ARMZ-REEL AD7912ARMZ-REEL7 AD7922ARMZ-REEL7 AD7912ARMZ AD7912ARMZ-REEL AD7912AUJZ-REEL7 AD7922ARMZ EVAL-AD7912CBZ AD7922AUJZ-REEL7 EVAL-AD7922CBZ