8-Channel, 1 MSPS, 8-/10-/12-Bit ADCs with Sequencer in 20-Lead TSSOP Data Sheet AD7908/AD7918/AD7928 FEATURES FUNCTIONAL BLOCK DIAGRAM Fast throughput rate: 1 MSPS AVDD Specified for AV of 2.7 V to 5.25 V DD Low power REFIN 6.0 mW max at 1 MSPS with 3 V supply VIN0 13.5 mW max at 1 MSPS with 5 V supply •• T/H 8-/10-/12-BIT Eight (single-ended) inputs with sequencer •• APSPURCOCXEISMSAITVIEON Wide input bandwidth • ADC • I/P AD7928, 70 dB min SINAD at 50 kHz input frequency • MUX • Flexible power/serial clock speed management • • No pipeline delays • • High speed serial interface SPI®/QSPI™/ • VIN7 MICROWIRE™/DSP compatible SCLK Shutdown mode: 0.5 μA max DOUT SEQUENCER CONTROL LOGIC 20-lead TSSOP package DIN Qualified for automotive applications CS AD7908/AD7918/AD7928 GENERAL DESCRIPTION GND VDRIVE 03089-001 The AD7908/AD7918/AD7928 are, respectively, 8-bit, 10-bit, and Figure 1. 12-bit, high speed, low power, 8-channel, successive approximation PRODUCT HIGHLIGHTS ADCs. The parts operate from a single 2.7 V to 5.25 V power supply and feature throughput rates up to 1 MSPS. The parts 1. High Throughput with Low Power Consumption. The AD7908/ contain a low noise, wide bandwidth track-and-hold amplifier that AD7918/AD7928 offer up to 1 MSPS throughput rates. At the can handle input frequencies in excess of 8 MHz. maximum throughput rate with 3 V supplies, the AD7908/ AD7918/AD7928 dissipate just 6 mW of power maximum. The conversion process and data acquisition are controlled using CS and the serial clock signal, allowing the device to easily interface 2. Eight Single-Ended Inputs with a Channel Sequencer. with microprocessors or DSPs. The input signal is sampled on the A sequence of channels can be selected, through which falling edge of CS and conversion is also initiated at this point. the ADC cycles and converts on. There are no pipeline delays associated with the part. 3. Single-Supply Operation with V Function. The AD7908/ DRIVE The AD7908/AD7918/AD7928 use advanced design techniques to AD7918/AD7928 operate from a single 2.7 V to 5.25 V supply. achieve very low power dissipation at maximum throughput rates. The V function allows the serial interface to connect directly DRIVE At maximum throughput rates, the AD7908/AD7918/AD7928 to either 3 V or 5 V processor systems independent of AV . DD consume 2 mA maximum with 3 V supplies; with 5 V supplies, the 4. Flexible Power/Serial Clock Speed Management. The conversion current consumption is 2.7 mA maximum. rate is determined by the serial clock, allowing the conversion Through the configuration of the control register, the analog input time to be reduced through the serial clock speed increase. The range for the part can be selected as 0 V to REFIN or 0 V to 2 × parts also feature various shutdown modes to maximize power REFIN, with either straight binary or twos complement output efficiency at lower throughput rates. Current consumption is coding. The AD7908/AD7918/AD7928 each feature eight single- 0.5 μA max when in full shutdown. ended analog inputs with a channel sequencer to allow a 5. No Pipeline Delay. The parts feature a standard successive preprogrammed selection of channels to be converted sequentially. approximation ADC with accurate control of the sampling The conversion time for the AD7908/AD7918/AD7928 is instant via a CS input and once off conversion control. determined by the SCLK frequency, which is also used as the master clock to control the conversion. Rev. E Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Tel: 781.329.4700 ©2006–2014 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com

AD7908/AD7918/AD7928 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Control Register .............................................................................. 15 General Description ......................................................................... 1 Sequencer Operation ................................................................. 16 Functional Block Diagram .............................................................. 1 SHADOW Register .................................................................... 17 Product Highlights ........................................................................... 1 Circuit Information .................................................................... 18 Revision History ............................................................................... 2 Converter Operation .................................................................. 18 Specifications ..................................................................................... 3 ADC Transfer Function ............................................................. 19 AD7908 Specifications ................................................................. 3 Handling Bipolar Input Signals ................................................ 19 AD7918 Specifications ................................................................. 5 Typical Connection Diagram ................................................... 19 AD7928 Specifications ................................................................. 7 Modes of Operation ................................................................... 21 Timing Specifications .................................................................. 9 Power vs. Throughput Rate ....................................................... 23 Absolute Maximum Ratings .......................................................... 10 Serial Interface ............................................................................ 23 ESD Caution ................................................................................ 10 Microprocessor Interfacing ....................................................... 24 Pin Configuration and Function Descriptions ........................... 11 Application Hints ....................................................................... 27 Terminology .................................................................................... 12 Outline Dimensions ....................................................................... 28 Typical Performance Characteristics ........................................... 13 Ordering Guide .......................................................................... 28 Performance Curves ................................................................... 13 Automotive Products ................................................................. 28 REVISION HISTORY 1/14—Rev. D to Rev. E 11/08—Rev. B to Rev. C Changes to Ordering Guide .......................................................... 28 Changes to ESD Parameter, Table 5 ............................................. 10 12/10—Rev. C to Rev. D 6/06—Rev. A to Rev. B Changes to Features Section............................................................ 1 Updated Format .................................................................. Universal Added Automotive SINAD and SNR Parameters (Table 1)........ 3 Changes to Reference Section ....................................................... 21 Added Automotive SINAD and SNR Parameters (Table 2)........ 5 9/03—Rev. 0 to Rev. A Added Automotive SINAD and SNR Parameters (Table 3)........ 7 Changes to Figure 3 ........................................................................ 15 Added Automotive Temperature Range (Table 5) ....................... 7 Changes to Reference section ....................................................... 18 Added Automotive Products Section........................................... 28 Changes to Ordering Guide .......................................................... 28 Rev. E | Page 2 of 28

Data Sheet AD7908/AD7918/AD7928 SPECIFICATIONS AD7908 SPECIFICATIONS AV = V = 2.7 V to 5.25 V, REF = 2.5 V, f = 20 MHz, T = T to T , unless otherwise noted. DD DRIVE IN SCLK A MIN MAX Table 1. Parameter B Version1 Unit Test Conditions/Comments DYNAMIC PERFORMANCE f = 50 kHz sine wave, f = 20 MHz IN SCLK Signal-to-(Noise + Distortion) (SINAD)2 49 dB min B models 48.5 dB min W models Signal-to-Noise Ratio (SNR)2 49 dB min B models 48.5 dB min W models Total Harmonic Distortion (THD)2 −66 dB max Peak Harmonic or Spurious Noise (SFDR)2 −64 dB max Intermodulation Distortion (IMD)2 fa = 40.1 kHz, fb = 41.5 kHz Second-Order Terms −90 dB typ Third-Order Terms −90 dB typ Aperture Delay 10 ns typ Aperture Jitter 50 ps typ Channel-to-Channel Isolation2 −85 dB typ f = 400 kHz IN Full Power Bandwidth 8.2 MHz typ @ 3 dB 1.6 MHz typ @ 0.1 dB DC ACCURACY2 Resolution 8 Bits Integral Nonlinearity ±0.2 LSB max Differential Nonlinearity ±0.2 LSB max Guaranteed no missed codes to 8 bits 0 V to REF Input Range Straight binary output coding IN Offset Error ±0.5 LSB max Offset Error Match ±0.05 LSB max Gain Error ±0.2 LSB max Gain Error Match ±0.05 LSB max 0 V to 2 × REF Input Range −REF to +REF biased about REF with IN IN IN IN twos complement output coding Positive Gain Error ±0.2 LSB max Positive Gain Error Match ±0.05 LSB max Zero Code Error ±0.5 LSB max Zero Code Error Match ±0.1 LSB max Negative Gain Error ±0.2 LSB max Negative Gain Error Match ±0.05 LSB max ANALOG INPUT Input Voltage Ranges 0 to REF V RANGE bit set to 1 IN 0 to 2 × REF V RANGE bit set to 0, AV /V = 4.75 V to IN DD DRIVE 5.25 V DC Leakage Current ±1 μA max Input Capacitance 20 pF typ REFERENCE INPUT REF Input Voltage 2.5 V ±1% specified performance IN DC Leakage Current ±1 μA max REF Input Impedance 36 kΩ typ f = 1 MSPS IN SAMPLE LOGIC INPUTS Input High Voltage, V 0.7 × V V min INH DRIVE Input Low Voltage, V 0.3 × V V max INL DRIVE Input Current, I ±1 μA max Typically 10 nA, V = 0 V or V IN IN DRIVE Input Capacitance, C 3 10 pF max IN Rev. E | Page 3 of 28

AD7908/AD7918/AD7928 Data Sheet Parameter B Version1 Unit Test Conditions/Comments LOGIC OUTPUTS Output High Voltage, V V − 0.2 V min I = 200 μA, AV = 2.7 V to 5.25 V OH DRIVE SOURCE DD Output Low Voltage, V 0.4 V max I = 200 μA OL SINK Floating-State Leakage Current ±1 μA max Floating-State Output Capacitance3 10 pF max Output Coding Straight (natural) binary Coding bit set to 1 Twos complement Coding bit set to 0 CONVERSION RATE Conversion Time 800 ns max 16 SCLK cycles with SCLK at 20 MHz Track-and-Hold Acquisition Time 300 ns max Sine wave input 300 ns max Full-scale step input Throughput Rate 1 MSPS max See Serial Interface section POWER REQUIREMENTS AV 2.7/5.25 V min/max DD V 2.7/5.25 V min/max DRIVE I 4 Digital inputs = 0 V or V DD DRIVE Normal Mode (Static) 600 μA typ AV = 2.7 V to 5.25 V, SCLK On or Off DD Normal Mode (Operational) 2.7 mA max AV = 4.75 V to 5.25 V, f = 20 MHz DD SCLK 2 mA max AV = 2.7 V to 3.6 V, f = 20 MHz DD SCLK Using Auto Shutdown Mode 960 μA typ f = 250 kSPS SAMPLE 0.5 μA max (Static) Full Shutdown Mode 0.5 μA max SCLK on or off (20 nA typ) Power Dissipation4 Normal Mode (Operational) 13.5 mW max AV = 5 V, f = 20 MHz DD SCLK 6 mW max AV = 3 V, f = 20 MHz DD SCLK Auto Shutdown Mode (Static) 2.5 μW max AV = 5 V DD 1.5 μW max AV = 3 V DD Full Shutdown Mode 2.5 μW max AV = 5 V DD 1.5 μW max AV = 3 V DD 1 Temperature ranges as follows: B version: −40°C to +85°C. 2 See Terminology section. 3 Sample tested @ 25°C to ensure compliance. 4 See Power vs. Throughput Rate section. Rev. E | Page 4 of 28

Data Sheet AD7908/AD7918/AD7928 AD7918 SPECIFICATIONS AV = V = 2.7 V to 5.25 V, REF = 2.5 V, f = 20 MHz, T = T to T , unless otherwise noted. DD DRIVE IN SCLK A MIN MAX Table 2. Parameter B Version1 Unit Test Conditions/Comments DYNAMIC PERFORMANCE f = 50 kHz sine wave, f = 20 MHz IN SCLK Signal-to-(Noise + Distortion) (SINAD)2 61 dB min B models 60.5 dB min W models Signal-to-Noise Ratio (SNR)2 61 dB min B models 60.5 dB min W models Total Harmonic Distortion (THD)2 −72 dB max Peak Harmonic or Spurious Noise (SFDR)2 −74 dB max Intermodulation Distortion (IMD)2 fa = 40.1 kHz, fb = 41.5 kHz Second-Order Terms −90 dB typ Third-Order Terms −90 dB typ Aperture Delay 10 ns typ Aperture Jitter 50 ps typ Channel-to-Channel Isolation2 −85 dB typ f = 400 kHz IN Full Power Bandwidth 8.2 MHz typ @ 3 dB 1.6 MHz typ @ 0.1 dB DC ACCURACY2 Resolution 10 Bits Integral Nonlinearity ±0.5 LSB max Differential Nonlinearity ±0.5 LSB max Guaranteed no missed codes to 10 bits 0 V to REF Input Range Straight binary output coding IN Offset Error ±2 LSB max Offset Error Match ±0.2 LSB max Gain Error ±0.5 LSB max Gain Error Match ±0.2 LSB max 0 V to 2 × REF Input Range −REF to +REF biased about REF with twos IN IN IN IN complement output coding Positive Gain Error ±0.5 LSB max Positive Gain Error Match ±0.2 LSB max Zero Code Error ±2 LSB max Zero Code Error Match ±0.2 LSB max Negative Gain Error ±0.5 LSB max Negative Gain Error Match ±0.2 LSB max ANALOG INPUT Input Voltage Ranges 0 to REF V RANGE bit set to 1 IN 0 to 2 × REF V RANGE bit set to 0, AV /V = 4.75 V to 5.25 V IN DD DRIVE DC Leakage Current ±1 μA max Input Capacitance 20 pF typ REFERENCE INPUT REF Input Voltage 2.5 V ±1% specified performance IN DC Leakage Current ±1 μA max REF Input Impedance 36 kΩ typ f = 1 MSPS IN SAMPLE LOGIC INPUTS Input High Voltage, V 0.7 × V V min INH DRIVE Input Low Voltage, V 0.3 × V V max INL DRIVE Input Current, I ±1 μA max Typically 10 nA, V = 0 V or V IN IN DRIVE Input Capacitance, C 3 10 pF max IN Rev. E | Page 5 of 28

AD7908/AD7918/AD7928 Data Sheet Parameter B Version1 Unit Test Conditions/Comments LOGIC OUTPUTS Output High Voltage, V V − 0.2 V min I = 200 μA, AV = 2.7 V to 5.25 V OH DRIVE SOURCE DD Output Low Voltage, V 0.4 V max I = 200 μA OL SINK Floating-State Leakage Current ±1 μA max Floating-State Output Capacitance3 10 pF max Output Coding Straight (natural) binary Coding bit set to 1 Twos complement Coding bit set to 0 CONVERSION RATE Conversion Time 800 ns max 16 SCLK cycles with SCLK at 20 MHz Track-and-Hold Acquisition Time 300 ns max Sine wave input 300 ns max Full-scale step input Throughput Rate 1 MSPS max See Serial Interface section POWER REQUIREMENTS AV 2.7/5.25 V min/max DD V 2.7/5.25 V min/max DRIVE I 4 Digital inputs = 0 V or V DD DRIVE Normal Mode (Static) 600 μA typ AV = 2.7 V to 5.25 V, SCLK on or off DD Normal Mode (Operational) 2.7 mA max AV = 4.75 V to 5.25 V, f = 20 MHz DD SCLK 2 mA max AV = 2.7 V to 3.6 V, f = 20 MHz DD SCLK Using Auto Shutdown Mode 960 μA typ f = 250 kSPS SAMPLE 0.5 μA max (Static) Full Shutdown Mode 0.5 μA max SCLK on or off (20 nA typ) Power Dissipation4 Normal Mode (Operational) 13.5 mW max AV = 5 V, f = 20 MHz DD SCLK 6 mW max AV = 3 V, f = 20 MHz DD SCLK Auto Shutdown Mode (Static) 2.5 μW max AV = 5 V DD 1.5 μW max AV = 3 V DD Full Shutdown Mode 2.5 μW max AV = 5 V DD 1.5 μW max AV = 3 V DD 1 Temperature ranges as follows: B version: –40°C to +85°C. 2 See Terminology section. 3 Sample tested @ 25°C to ensure compliance. 4 See Power vs. Throughput Rate section. Rev. E | Page 6 of 28

Data Sheet AD7908/AD7918/AD7928 AD7928 SPECIFICATIONS A = V = 2.7 V to 5.25 V, REF = 2.5 V, f = 20 MHz, T = T to T , unless otherwise noted. VDD DRIVE IN SCLK A MIN MAX Table 3. Parameter B Version1 Unit Test Conditions/Comments DYNAMIC PERFORMANCE f = 50 kHz sine wave, f = 20 MHz IN SCLK Signal-to-(Noise + Distortion) (SINAD)2 70 dB min @ 5 V, B models 69.5 dB min @ 5 V, W models 69 dB min @ 3 V typically 70 dB Signal-to-Noise Ratio (SNR)2 70 dB min B models 69.5 dB min W models Total Harmonic Distortion (THD)2 −77 dB max @ 5 V typically −84 dB −73 dB max @ 3 V typically −77 dB Peak Harmonic or Spurious Noise −78 dB max @ 5 V typically −86 dB (SFDR)2 −76 dB max @ 3 V typically −80 dB Intermodulation Distortion (IMD)2 fa = 40.1 kHz, fb = 41.5 kHz Second-Order Terms −90 dB typ Third-Order Terms −90 dB typ Aperture Delay 10 ns typ Aperture Jitter 50 ps typ Channel-to-Channel Isolation2 −85 dB typ f = 400 kHz IN Full Power Bandwidth 8.2 MHz typ @ 3 dB 1.6 MHz typ @ 0.1 dB DC ACCURACY2 Resolution 12 Bits Integral Nonlinearity ±1 LSB max Differential Nonlinearity −0.9/+1.5 LSB max Guaranteed no missed codes to 12 bits 0 V to REF Input Range Straight binary output coding IN Offset Error ±8 LSB max Typically ±0.5 LSB Offset Error Match ±0.5 LSB max Gain Error ±1.5 LSB max Gain Error Match ±0.5 LSB max 0 V to 2 × REF Input Range −REF to +REF biased about REF with twos IN IN IN IN complement output coding Positive Gain Error ±1.5 LSB max Positive Gain Error Match ±0.5 LSB max Zero Code Error ±8 LSB max Typically ±0.8 LSB Zero Code Error Match ±0.5 LSB max Negative Gain Error ±1 LSB max Negative Gain Error Match ±0.5 LSB max ANALOG INPUT Input Voltage Ranges 0 to REF V RANGE bit set to 1 IN 0 to 2 × REF V RANGE bit set to 0, AV /V = 4.75 V to 5.25 V IN DD DRIVE DC Leakage Current ±1 μA max Input Capacitance 20 pF typ REFERENCE INPUT REF Input Voltage 2.5 V ±1% specified performance IN DC Leakage Current ±1 μA max REF Input Impedance 36 kΩ typ f = 1 MSPS IN SAMPLE LOGIC INPUTS Input High Voltage, V 0.7 × V V min INH DRIVE Input Low Voltage, V 0.3 × V V max INL DRIVE Input Current, I ±1 μA max Typically 10 nA, V = 0 V or V IN IN DRIVE Input Capacitance, C 3 10 pF max IN Rev. E | Page 7 of 28

AD7908/AD7918/AD7928 Data Sheet Parameter B Version1 Unit Test Conditions/Comments LOGIC OUTPUTS Output High Voltage, V V − 0.2 V min I = 200 μA, AV = 2.7 V to 5.25 V OH DRIVE SOURCE DD Output Low Voltage, V 0.4 V max I = 200 μA OL SINK Floating-State Leakage Current ±1 μA max Floating-State Output Capacitance3 10 pF max Output Coding Straight (natural) binary Coding bit set to 1 Twos complement Coding bit set to 0 CONVERSION RATE Conversion Time 800 ns max 16 SCLK cycles with SCLK at 20 MHz Track-and-Hold Acquisition Time 300 ns max Sine wave input 300 ns max Full-scale step input Throughput Rate 1 MSPS max See Serial Interface section POWER REQUIREMENTS AV 2.7/5.25 V min/max DD V 2.7/5.25 V min/max DRIVE I 4 Digital inputs = 0 V or V DD DRIVE Normal Mode (Static) 600 μA typ AV = 2.7 V to 5.25 V, SCLK on or off DD Normal Mode (Operational) 2.7 mA max AV = 4.75 V to 5.25 V, f = 20 MHz DD SCLK 2 mA max AV = 2.7 V to 3.6 V, f = 20 MHz DD SCLK Using Auto Shutdown Mode 960 μA typ f = 250 kSPS SAMPLE 0.5 μA max (Static) Full Shutdown Mode 0.5 μA max SCLK on or off (20 nA typ) Power Dissipation4 Normal Mode (Operational) 13.5 mW max AV = 5 V, f = 20 MHz DD SCLK 6 mW max AV = 3 V, f = 20 MHz DD SCLK Auto Shutdown Mode (Static) 2.5 μW max AV = 5 V DD 1.5 μW max AV = 3 V DD Full Shutdown Mode 2.5 μW max AV = 5 V DD 1.5 μW max AV = 3 V DD 1 Temperature ranges as follows: B Version: −40°C to +85°C. 2 See Terminology section. 3 Sample tested @ 25°C to ensure compliance. 4 See Power vs. Throughput Rate section. Rev. E | Page 8 of 28

Data Sheet AD7908/AD7918/AD7928 TIMING SPECIFICATIONS AV = 2.7 V to 5.25 V, V ≤ AV , REF = 2.5 V, T = T to T , unless otherwise noted.1 DD DRIVE DD IN A MIN MAX Table 4. Limit at T , T AD7908/AD7918/AD7928 MIN MAX Parameter AV = 3 V AV = 5 V Unit Description DD DD f 2 10 10 kHz min SCLK 20 20 MHz max t 16 × t 16 × t CONVERT SCLK SCLK tQUIET 50 50 ns min Minimum quiet time required between CS rising edge and start of next conversion t 10 10 ns min CS to SCLK setup time 2 t33 35 30 ns max Delay from CS until DOUT three-state disabled t3 40 40 ns max Data access time after SCLK falling edge 4 t 0.4 × t 0.4 × t ns min SCLK low pulse width 5 SCLK SCLK t 0.4 × t 0.4 × t ns min SCLK high pulse width 6 SCLK SCLK t 10 10 ns min SCLK to DOUT valid hold time 7 t 4 15/45 15/35 ns min/max SCLK falling edge to DOUT high impedance 8 t 10 10 ns min DIN setup time prior to SCLK falling edge 9 t 5 5 ns min DIN hold time after SCLK falling edge 10 t 20 20 ns min 16th SCLK falling edge to CS high 11 t 1 1 μs max Power-up time from full power-down/auto shutdown mode 12 1 Sample tested at 25°C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of AVDD) and timed from a voltage level of 1.6 V. See Figure 2. The 3 V operating range spans from 2.7 V to 3.6 V. The 5 V operating range spans from 4.75 V to 5.25 V. 2 Mark/space ratio for the SCLK input is 40/60 to 60/40. 3 Measured with the load circuit of Figure 2 and defined as the time required for the output to cross 0.4 V or 0.7 × VDRIVE. 4 t8 is derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 2. The measured number is then extrapolated back to remove the effects of charging or discharging the 50 pF capacitor. This means that the time, t8, quoted in the timing characteristics is the true bus relinquish time of the part and is independent of the bus loading. 200µA IOL TO OUTPUT 1.6V PIN CL 50pF 200µA IOH 03089-002 Figure 2. Load Circuit for Digital Output Timing Specifications Rev. E | Page 9 of 28

AD7908/AD7918/AD7928 Data Sheet ABSOLUTE MAXIMUM RATINGS T = 25°C, unless otherwise noted. A Table 5. Stresses above those listed under Absolute Maximum Ratings Parameter Rating may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any AV to AGND −0.3 V to +7 V DD other conditions above those indicated in the operational V to AGND −0.3 V to AV + 0.3 V DRIVE DD section of this specification is not implied. Exposure to absolute Analog Input Voltage to AGND −0.3 V to AV + 0.3 V DD maximum rating conditions for extended periods may affect Digital Input Voltage to AGND −0.3 V to +7 V device reliability. Digital Output Voltage to AGND −0.3 V to AV + 0.3 V DD REF to AGND −0.3 V to AV + 0.3 V IN DD Input Current to Any Pin Except ±10 mA Supplies1 Operating Temperature Range Commercial (B Version) −40°C to +85°C Storage Temperature Range −65°C to +150°C Automotive Temperature Range −40°C to +125°C Junction Temperature 150°C TSSOP Package, Power Dissipation 450 mW θ Thermal Impedance 143°C/W (TSSOP) JA θ Thermal Impedance 45°C/W (TSSOP) JC Lead Temperature, Soldering Vapor Phase (60 sec) 215°C Infrared (15 sec) 220°C ESD 1.5 kV 1 Transient currents of up to 100 mA do not cause SCR latch-up. ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. Rev. E | Page 10 of 28

Data Sheet AD7908/AD7918/AD7928 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SCLK 1 20 AGND DIN 2 19 VDRIVE CS 3 18 DOUT AD7908/ AGND 4 AD7918/ 17 AGND AVDD 5 AD7928 16 VIN0 AVDD 6 TOP VIEW 15 VIN1 REFIN 7 (Not to Scale) 14 VIN2 AGND 8 13 VIN3 VVIINN76 190 1121 VVIINN45 03089-003 Figure 3. Pin Configuration Table 6. Pin Function Descriptions Pin No. Mnemonic Description 1 SCLK Serial Clock. Logic input. SCLK provides the serial clock for accessing data from the part. This clock input is also used as the clock source for the conversion process of the AD7908/AD7918/AD7928. 2 DIN Data In. Logic input. Data to be written to the control register of the AD7908/AD7918/AD7928 is provided on this input and is clocked into the register on the falling edge of SCLK (see the Control Register section). 3 CS Chip Select. Active low logic input. This input provides the dual function of initiating conversions on the AD7908/AD7918/AD7928, and also frames the serial data transfer. 4, 8, 17, 20 AGND Analog Ground. This is the ground reference point for all analog circuitry on the AD7908/AD7918/AD7928. All analog input signals and any external reference signal should be referred to this AGND voltage. All AGND pins should be connected together. 5, 6 AV Analog Power Supply Input. The AV range for the AD7908/AD7918/AD7928 is from 2.7 V to 5.25 V. For the 0 V DD DD to 2 × REF range, AV should be from 4.75 V to 5.25 V. IN DD 7 REF Reference Input for the AD7908/AD7918/AD7928. An external reference must be applied to this input. The IN voltage range for the external reference is 2.5 V ± 1% for specified performance. 16 to 9 V 0 to V 7 Analog Input 0 through Analog Input 7. These are eight single-ended analog input channels that are IN IN multiplexed into the on-chip track-and-hold. The analog input channel to be converted is selected by using Address Bit ADD2 through Address Bit ADD0 of the control register. The address bits, in conjunction with the SEQ and SHADOW bits, allow the sequencer to be programmed. The input range for all input channels can extend from 0 V to REF or 0 V to 2 × REF as selected via the RANGE bit in the control register. Any unused IN IN input channels must be connected to AGND to avoid noise pickup. 18 DOUT Data Out. Logic output. The conversion result from the AD7908/AD7918/AD7928 is provided on this output as a serial data stream. The bits are clocked out on the falling edge of the SCLK input. The data stream from the AD7908 consists of one leading zero, three address bits indicating which channel the conversion result corresponds to, followed by the eight bits of conversion data, followed by four trailing zeros, provided MSB first; the data stream from the AD7918 consists of one leading zero, three address bits indicating which channel the conversion result corresponds to, followed by the 10 bits of conversion data, followed by two trailing zeros, also provided MSB first; the data stream from the AD7928 consists of one leading zero, three address bits indicating which channel the conversion result corresponds to, followed by the 12 bits of conversion data, provided MSB first. The output coding can be selected as straight binary or twos complement via the CODING bit in the control register. 19 V Logic Power Supply Input. The voltage supplied at this pin determines at what voltage the serial interface of DRIVE the AD7908/AD7918/AD7928 operates. Rev. E | Page 11 of 28

AD7908/AD7918/AD7928 Data Sheet TERMINOLOGY Integral Nonlinearity Negative Gain Error Match This is the maximum deviation from a straight line passing This is the difference in negative gain error between any two through the endpoints of the ADC transfer function. The channels. endpoints of the transfer function are zero scale, a position 1 LSB Channel-to-Channel Isolation below the first code transition, and full scale, a position 1 LSB Channel-to-channel isolation is a measure of the level of above the last code transition. crosstalk between channels. It is measured by applying a full- Differential Nonlinearity scale 400 kHz sine wave signal to all seven nonselected input This is the difference between the measured and the ideal 1 LSB channels and determining how much that signal is attenuated change between any two adjacent codes in the ADC. in the selected channel with a 50 kHz signal. The figure is given worst case across all eight channels for the AD7908/AD7918/ Offset Error AD7928. This is the deviation of the first code transition (00 . . . 000) to (00 . . . 001) from the ideal, that is, AGND + 1 LSB. Power Supply Rejection (PSR) Variations in power supply affect the full-scale transition, but Offset Error Match not the converter’s linearity. Power supply rejection is the This is the difference in offset error between any two channels. maximum change in full-scale transition point due to a change in power-supply voltage from the nominal value (see the Gain Error Performance Curves section). This is the deviation of the last code transition (111 . . . 110) to (111 . . . 111) from the ideal (that is, REF – 1 LSB) after the IN Track-and-Hold Acquisition Time offset error has been adjusted out. The track-and-hold amplifier returns to track mode at the end of conversion. Track-and-hold acquisition time is the time Gain Error Match required for the output of the track-and-hold amplifier to reach This is the difference in gain error between any two channels. its final value, within ±1 LSB, after the end of conversion. Zero Code Error Signal-to-(Noise + Distortion) Ratio This applies when using the twos complement output coding This is the measured ratio of signal-to-(noise + distortion) at option, in particular to the 2 × REF input range with −REF IN IN the output of the ADC. The signal is the rms amplitude of the to +REF biased about the REF point. It is the deviation of the IN IN fundamental. Noise is the sum of all nonfundamental signals up midscale transition (all 0s to all 1s) from the ideal V voltage, IN to half the sampling frequency (f/2), excluding dc. The ratio is that is, REF − 1 LSB. S IN dependent on the number of quantization levels in the Zero Code Error Match digitization process; the more levels, the smaller the This is the difference in zero code error between any two quantization noise. The theoretical signal-to-(noise + channels. distortion) ratio for an ideal N-bit converter with a sine wave input is given by Positive Gain Error Signal-to-(Noise + Distortion) = (6.02N + 1.76)dB This applies when using the twos complement output coding option, in particular to the 2 × REF input range with −REF IN IN Thus for a 12-bit converter, this is 74 dB; for a 10-bit converter, to +REF biased about the REF point. It is the deviation of the IN IN this is 62 dB; and for an 8-bit converter, this is 50 dB. last code transition (011. . .110) to (011 . . . 111) from the ideal (that is, +REFIN − 1 LSB) after the zero code error has been Total Harmonic Distortion adjusted out. Total harmonic distortion (THD) is the ratio of the rms sum of harmonics to the fundamental. For the AD7908/AD7918/ Positive Gain Error Match AD7928, it is defined as: This is the difference in positive gain error between any two channels. V 2+V 2+V 2+V 2+V 2 2 3 4 5 6 THD(dB)= 20log Negative Gain Error V 1 This applies when using the twos complement output coding option, in particular to the 2 × REFIN input range with −REFIN where V1 is the rms amplitude of the fundamental and V2, V3, to +REFIN biased about the REFIN point. It is the deviation of the V4, V5, and V6 are the rms amplitudes of the second through the first code transition (100 . . . 000) to (100 . . . 001) from the ideal sixth harmonics. (that is, −REF + 1 LSB) after the zero code error has been IN adjusted out. Rev. E | Page 12 of 28

Data Sheet AD7908/AD7918/AD7928 TYPICAL PERFORMANCE CHARACTERISTICS PERFORMANCE CURVES Figure 7 shows a graph of total harmonic distortion vs. analog input frequency for various supply voltages, and Figure 8 shows a Figure 4 shows a typical FFT plot for the AD7928 at 1 MSPS graph of total harmonic distortion vs. analog input frequency sample rate and 50 kHz input frequency. Figure 5 shows the for various source impedances. See the Analog Input section. signal-to-(noise + distortion) ratio performance vs. input frequency for various supply voltages while sampling at 1 MSPS Figure 9 and Figure 10 show typical INL and DNL plots for the with an SCLK of 20 MHz. AD7928. Figure 6 shows the power supply rejection ratio vs. supply ripple 0 frequency for the AD7928 when no decoupling is used. The AVDD = 5V power supply rejection ratio is defined as the ratio of the power –10 2R0E0FmINV = p 2-p.5 SVI,N 1EµWF ACVAEP AOCNIT AOVRDD in the ADC output at full-scale frequency f, to the power of a –20 TA = 25°C 200 mV p-p sine wave applied to the ADC AV supply of DD –30 frequency fS B) d –40 PSRR(dB) = 10 log(Pf/Pfs) RR ( S –50 P Pf is equal to the power at frequency f in ADC output; PfS is –60 equal to the power at frequency f coupled onto the ADC AV S DD –70 supply. Here a 200 mV p-p sine wave is coupled onto the AV DD supply. –80 –10 4A0V9D6D P =O 5INVT FFT –900 100 200SUP3P0L0Y R4IP00PLE5 F0R0EQ6U0E0NC7Y0 (0kHz8)00 900 1000 03089-006 fSAMPLE = 1MSPS Figure 6. AD7928 PSRR vs. Supply Ripple Frequency fIN = 50kHz –30 SINAD = 71.147dB –50 THD = –87.229dB SFDR = –90.744dB fSAMPLE = 1MSPS NR (dB) –50 ––5650 TRAAN= G25E° C= 0V TO REFIN AVDD = VDRIVE = 2.70V S –70 –65 B) D (d –70 AVDD = VDRIVE = 3.60V –90 H T –75 –1100 50 100 150 F2R0E0QUE25N0CY (3k0H0z) 350 400 450 500 03089-004 –80 AVDD = VDRIVE = 4.75V –85 Figure 4. AD7928 Dynamic Performance at 1 MSPS AVDD = VDRIVE = 5.25V 75 AVDD = VDRIVE = 5.25V –9010 INPUT FR1E0Q0UENCY (kHz) 1000 03089-007 AVDD = VDRIVE = 4.75V Figure 7. AD7928 THD vs. Analog Input Frequency for Various Supply Voltages at 1 MSPS 70 dB) AVDD = VDRIVE = 3.60V D ( 65 A N SI 60 fSAMPLE = 1MSPS TA= 25°C AVDD = VDRIVE = 2.70V RANGE = 0V TO REFIN 5510 INPUT FRE1Q0U0ENCY (kHz) 1000 03089-005 Figure 5. AD7928 SINAD vs. Analog Input Frequency for Various Supply Voltages at 1 MSPS Rev. E | Page 13 of 28

AD7908/AD7918/AD7928 Data Sheet –50 1.0 –55 TRfSAAAN=M GP2L5EE° C == 01VM TSOP SREFIN RIN= 1000Ω 0.8 TAEVMDDP E=R VADTRUIVREE = =5 V25°C AVDD = 5.25V 0.6 –60 0.4 B) –65 S D (dB) –70 RIN= 100Ω ROR (L 0.20 TH RIN= 50Ω ER –75 L –0.2 N D RIN= 10Ω –0.4 –80 –0.6 –85 –0.8 –9010 INPUT FRE1Q0U0ENCY (kHz) 1000 03089-008 –1.00 512 1024 1536 C2O0D48E 2560 3072 3584 4096 03089-010 Figure 8. AD7928 THD vs. Analog Input Frequency for Figure 10. AD7928 Typical DNL Various Source Impedances 1.0 0.8 AVDD = VDRIVE = 5V TEMPERATURE= 25°C 0.6 0.4 B) LS 0.2 R ( O 0 R R L E –0.2 N I –0.4 –0.6 –0.8 –1.0 0 512 1024 1536 C2O04D8E 2560 3072 3584 4096 03089-009 Figure 9. AD7928 Typical INL Rev. E | Page 14 of 28

Data Sheet AD7908/AD7918/AD7928 CONTROL REGISTER The control register on the AD7908/AD7918/AD7928 is a 12-bit, write-only register. Data is loaded from the DIN pin of the AD7908/AD7918/AD7928 on the falling edge of SCLK. The data is transferred on the DIN line at the same time that the conversion result is read from the part. The data transferred on the DIN line corresponds to the AD7908/AD7918/AD7928 configuration for the next conversion. This requires 16 serial clocks for every data transfer. Only the information provided on the first 12 falling clock edges (after CS falling edge) is loaded to the control register. MSB denotes the first bit in the data stream. The bit functions are outlined in Table 7. MSB LSB WRITE SEQ DON’TCARE ADD2 ADD1 ADD0 PM1 PM0 SHADOW DON’TCARE RANGE CODING Table 7. Control Register Bit Functions Bit Mnemonic Comment 11 WRITE The value written to this bit of the control register determines whether or not the following 11 bits are loaded to the control register. If this bit is a 1, the following 11 bits are written to the control register; if it is a 0, the remaining 11 bits are not loaded to the control register, and it remains unchanged. 10 SEQ The SEQ bit in the control register is used in conjunction with the SHADOW bit to control the use of the sequencer function and access the SHADOW register (see the SHADOW register bit map). 9 DON’TCARE 8 to 6 ADD2 to These three address bits are loaded at the end of the present conversion sequence and select which analog input ADD0 channel is to be converted in the next serial transfer, or they can select the final channel in a consecutive sequence as described in Table 10. The selected input channel is decoded as shown in Table 8. The address bits corresponding to the conversion result are also output on DOUT prior to the 12 bits of data, see the Serial Interface section. The next channel to be converted on is selected by the mux on the 14th SCLK falling edge. 5, 4 PM1, PM0 Power Management Bits. These two bits decode the mode of operation of the AD7908/AD7918/AD7928 as shown in Table 9. 3 SHADOW The SHADOW bit in the control register is used in conjunction with the SEQ bit to control the use of the sequencer function and access the SHADOW register (see Table 10). 2 DON’TCARE 1 RANGE This bit selects the analog input range to be used on the AD7908/AD7918/AD7928. If it is set to 0, the analog input range extends from 0 V to 2 × REF . If it is set to 1, the analog input range extends from 0 V to REF (for the next IN IN conversion). For 0 V to 2 × REF , AV = 4.75 V to 5.25 V. IN DD 0 CODING This bit selects the type of output coding the AD7908/AD7918/AD7928 uses for the conversion result. If this bit is set to 0, the output coding for the part is twos complement. If this bit is set to 1, the output coding from the part is straight binary (for the next conversion). Table 8. Channel Selection ADD2 ADD1 ADD0 Analog Input Channel 0 0 0 V 0 IN 0 0 1 V 1 IN 0 1 0 V 2 IN 0 1 1 V 3 IN 1 0 0 V 4 IN 1 0 1 V 5 IN 1 1 0 V 6 IN 1 1 1 V 7 IN Rev. E | Page 15 of 28

AD7908/AD7918/AD7928 Data Sheet Table 9. Power Mode Selection PM1 PM0 Mode 1 1 Normal Operation. In this mode, the AD7908/AD7918/AD7928 remain in full power mode regardless of the status of any of the logic inputs. This mode allows the fastest possible throughput rate from the AD7908/AD7918/AD7928. 1 0 Full Shutdown. In this mode, the AD7908/ AD7918/AD7928 is in full shutdown mode with all circuitry powering down. The AD7908/AD7918/AD7928 retains the information in the control register while in full shutdown. The part remains in full shutdown until these bits are changed. 0 1 Auto Shutdown. In this mode, the AD7908/AD7918/AD7928 automatically enters full shutdown mode at the end of each conversion when the control register is updated. Wake-up time from full shutdown is 1 μs and the user should ensure that 1 μs has elapsed before attempting to perform a valid conversion on the part in this mode. 0 0 Invalid Selection. This configuration is not allowed. SEQUENCER OPERATION The configuration of the SEQ and SHADOW bits in the control register allows the user to select a particular mode of operation of the sequencer function. Table 10 outlines the four modes of operation of the sequencer. Table 10. Sequence Selection SEQ SHADOW Sequence Type 0 0 This configuration means that the sequence function is not used. The analog input channel selected for each individual conversion is determined by the contents of the ADD0 through ADD2 channel address bits in each prior write operation. This mode of operation reflects the traditional operation of a multichannel ADC, without the sequencer function being used, where each write to the AD7908/AD7918/AD7928 selects the next channel for conversion (see Figure 11). 0 1 This configuration selects the SHADOW register for programming. The following write operation loads the contents of the SHADOW register. This programs the sequence of channels to be converted on continuously with each successive valid CS falling edge (see the SHADOW Register section, SHADOW register bit map, and Figure 12). The channels selected need not be consecutive. 1 0 If the SEQ and SHADOW bits are set in this way, then the sequence functions are not interrupted upon completion of the write operation. This allows other bits in the control register to be altered between conversions while in a sequence, without terminating the cycle. 1 1 This configuration is used in conjunction with the ADD2 to ADD0 channel address bits to program continuous conversions on a consecutive sequence of channels from Channel 0 to a selected final channel as determined by the channel address bits in the control register (see Figure 13). Rev. E | Page 16 of 28

Data Sheet AD7908/AD7918/AD7928 SHADOW REGISTER MSB LSB VIN0 VIN1 VIN2 VIN3 VIN4 VIN5 VIN6 VIN7 VIN0 VIN1 VIN2 VIN3 VIN4 VIN5 VIN6 VIN7 Sequence One Sequence Two The SHADOW register on the AD7908/AD7918/AD7928 is a POWER-ON 16-bit, write-only register. Data is loaded from the DIN pin of the AD7908/AD7918/AD7928 on the falling edge of SCLK. The DUMMY CONVERSION DIN = ALL 1s data is transferred on the DIN line at the same time that a conversion result is read from the part. This requires 16 serial DIN: WRITE TO CONTROL REGISTER, clock falling edges for the data transfer. The information is CS WRITE BIT = 1, SELECT CODING, RANGE, AND POWER MODE. clocked into the SHADOW register, provided that the SEQ and SELECT A2 TO A0 FOR CONVERSION. SEQ = SHADOW = 0 SHADOW bits were set to 0,1, respectively, in the previous write to the control register. MSB denotes the first bit in the data stream. Each bit represents an analog input from Channel 0 DOUT: CONVERSION RESULT FROM PREVIOUSLY SELECTED to Channel 7. Through programming the SHADOW register, CS CHANNEL A2 TO A0. WRITE BIT = 1, two sequences of channels can be selected, through which the DIN: WRITE TO CONTROL REGISTER, SEQ = SHADOW = 0 WRITE BIT = 1, SELECT CODING, RANGE, cAoDn7v9e0rs8i/oAnD a7ft9e1r8 t/hAeD w7r9i2te8 tcoy tchlee wSHithA eDaOchW co rnegseisctuetri.v e ASSEENLQDE P=C OSTW HAAE2DR TO OMW OA D=0 E0F.OR CONVERSION. 03089-011 Figure 11. SEQ Bit = 0, SHADOW Bit = 0 Flowchart Sequence One is performed first and then Sequence Two. If the user does not wish to perform a second sequence option, then all 0s must be written to the last 8 LSBs of the SHADOW register. To select a sequence of channels, the associated channel POWER-ON bit must be set for each analog input. The AD7908/AD7918/ DUMMY CONVERSION AD7928 continuously cycle through the selected channels in DIN = ALL 1s ascending order beginning with the lowest channel, until a DIN: WRITE TO CONTROL REGISTER, write operation occurs (that is, the WRITE bit is set to 1) with CS WRITE BIT = 1, SELECT CODING, RANGE, AND POWER MODE. the SEQ and SHADOW bits configured in any way except 1, 0, SELECT CHANNEL A2 TO A0 FOR CONVERSION. (see Table 10). The bit functions are outlined in the SHADOW SEQ = 0 SHADOW = 1 register bit map. Figure 11 reflects the traditional operation of a multichannel DOUT: CONVERSION RESULT FROM PREVIOUSLY SELECTED CHANNEL A2 ADC, where each serial transfer selects the next channel for CS TO A0. DIN: WRITE TO SHADOW REGISTER, conversion. In this mode of operation the sequencer function is SELECTING WHICH CHANNELS TO CONVERT ON; CHANNELS SELECTED not used. NEED NOT BE CONSECUTIVE CHANNELS Figure 12 shows how to program the AD7908/AD7918/AD7928 WRITE BIT = 0 WRITE BIT = 1 SEQ = 1, SHADOW = 0 to continuously convert on a particular sequence of channels. To exit this mode of operation and revert back to the traditional CONTINUOUSLY CONTINUOUSLY CS CONVERTS ON CONVERTS ON THE mode of operation of a multichannel ADC (as outlined in THE SELECTED SELECTED SEQUENCE SEQUENCE OF OF CHANNELS BUT WILL Figure 11), ensure that the WRITE bit = 1 and the SEQ = CHANNELS ALLOW RANGE, CODING, AND SO ON, TO CHANGE SHADOW = 0 on the next serial transfer. Figure 13 shows how IN THE CONTROL REGISTER WITHOUT a sequence of consecutive channels can be converted on without INTERRUPTING THE SEQUENCE, PROVIDED having to program the SHADOW register or write to the part WRITE BIT = 0 SEQ = 1 SHADOW = 0 on each serial transfer. Again, to exit this mode of operation and WRITE BIT = 0 WRITE BIT = 1 SEQ = 1, SHADOW = 0 rAeDveCrt (baasc oku totl itnheed t riand Fitiigounrael m11o)d, ee nosf uorpee trhatei oWn RofI Ta Em builtti =ch 1a nannedl 03089-012 Figure 12. SEQ Bit = 0, SHADOW Bit = 1 Flowchart the SEQ = SHADOW = 0 on the next serial transfer. Rev. E | Page 17 of 28

AD7908/AD7918/AD7928 Data Sheet POWER-ON CONVERTER OPERATION The AD7908/AD7918/AD7928 are 8-, 10-, and 12-bit successive DUMMY CONVERSION DIN = ALL 1s approximation analog-to-digital converters based around a capacitive DAC, respectively. The AD7908/AD7918/AD7928 can DIN: WRITE TO CONTROL REGISTER, CS WANRDIT PEO BWITE =R 1M, OSDELEE.CT CODING, RANGE, convert analog input signals in the range 0 V to REFIN or 0 V to SELECT CHANNEL A2 TO A0 2 × REF . Figure 14 and Figure 15 show simplified schematics FOR CONVERSION. IN SEQ = 1 SHADOW = 1 of the ADC. The ADC is comprised of control logic, SAR, and a capacitive DAC, which are used to add and subtract fixed amounts of charge from the sampling capacitor to bring the DOUT: CONVERSION RESULT FROM CHANNEL 0. comparator back into a balanced condition. Figure 14 shows the CS CONTINUOUSLY CONVERTS ON A ADC during its acquisition phase. SW2 is closed and SW1 is in CONSECUTIVE SEQUENCE OF WRITE BIT = 0 CHANNELS FROM CHANNEL 0 UP TO, Position A. The comparator is held in a balanced condition and AND INCLUDING, THE PREVIOUSLY SELECTED A2 TO A0 IN THE CONTROL the sampling capacitor acquires the signal on the selected V REGISTER. IN channel. CAPACITIVE DAC CONTINUOUSLY CONVERTS ON THE SELECTED SEQUENCE OF CHANNELS BUT WILL ALLOW RANGE, CODING, AND CS SRTSFHOHEigEGA Ou DISSNrOEeT, W QET1RUO3 = E. W CS0NHEICTQAEHN ,OB GPiUtRE T= O IIN VN1 ITT,D SEHEHREDAR CSUDOEPONQTTW I=NR GO1BiLt = 1 FWSlEoRQwIT c=Eh 1Ba, IrSTtH =A 1DOW = 0 03089-013 VVIINN70AGND SAW1 B 4SkWΩ2 COMPARATOR COLNOTGRICOL 03089-014 CIRCUIT INFORMATION Figure 14. ADC Acquisition Phase The AD7908/AD7918/AD7928 are high speed, 8-channel, 8-bit, When the ADC starts a conversion (see Figure 15), SW2 opens 10-bit, and 12-bit, single-supply ADCs, respectively. The parts and SW1 moves to Position B, causing the comparator to can be operated from a 2.7 V to 5.25 V supply. When operated become unbalanced. The control logic and the capacitive DAC from either a 5 V or 3 V supply, the AD7908/AD7918/AD7928 are used to add and subtract fixed amounts of charge from the are capable of throughput rates of 1 MSPS when provided with sampling capacitor to bring the comparator back into a a 20 MHz clock. balanced condition. When the comparator is rebalanced, the conversion is complete. The control logic generates the ADC The AD7908/AD7918/AD7928 provide the user with an on- output code. Figure 17 and Figure 18 show the ADC transfer chip, track-and-hold ADC, and a serial interface housed in a functions. 20-lead TSSOP package. The AD7908/AD7918/AD7928 each have eight single-ended input channels with a channel CCAAPPAACCIITTIIVVEE DDAACC sequencer, allowing the user to select a channel sequence that the ADC can cycle through with each consecutive CS falling A 4kΩ edge. The serial clock input accesses data from the part, controls VIN0 SW1 CONTROL the transfer of data written to the ADC, and provides the clock B SW2 LOGIC sraonugrcee f ofor rt hthee A sDuc7c9e0s8s/ivAeD a7p9p1r8o/xAimD7at9i2o8n iAs 0D VC .t To hReE aFnINa loorg 0 i nVp utot VINA7GND COMPARATOR 03089-015 2 × REF , depending on the status of Bit 1 in the control Figure 15. ADC Conversion Phase IN register. For the 0 to 2 × REF range, the part must be operated IN Analog Input from a 4.75 V to 5.25 V supply. Figure 16 shows an equivalent circuit of the analog input The AD7908/AD7918/AD7928 provide flexible power structure of the AD7908/AD7918/AD7928. The two diodes (D1 management options to allow the user to achieve the best power and D2) provide ESD protection for the analog inputs. Care performance for a given throughput rate. These options are must be taken to ensure that the analog input signal never selected by programming the PM1 and PM0 power exceeds the supply rails by more than 300 mV. This causes these management bits in the control register. diodes to become forward biased and start conducting current into the substrate. 10 mA is the maximum current these diodes can conduct without causing irreversible damage to the part. The Capacitor C1 in Figure 16 is typically about 4 pF and can primarily be attributed to pin capacitance. The Resistor R1 is a lumped component made up of the on resistance of the track- and-hold switch and also includes the on resistance of the input Rev. E | Page 18 of 28

Data Sheet AD7908/AD7918/AD7928 multiplexer. The total resistance is typically about 400 Ω. The 011…111 Capacitor C2 is the ADC sampling capacitor and has a 011…110 capacitance of 30 pF typically. For ac applications, removing • E • high frequency components from the analog input signal is D000…001 O C000…000 recommended by use of an RC lowpass filter on the relevant C 111…111 analog input pin. In applications where harmonic distortion AD • • 1LSB = 2 × VREF/256 AD7908 and signal-to-noise ratio are critical, the analog input should be 100…010 1LSB = 2 × VREF/1024 AD7918 driven from a low impedance source. Large source impedances 110000……000001 1LSB = 2 × VREF/4096 AD7928 significantly affect the ac performance of the ADC. This can –VREF+ 1 LSB +VREF– 1 LSB necessitate the use of an input buffer amplifier. The choice of VREF– 1 LSB the op amp is a function of the particular application. ANALOG INPUT 03089-018 When no amplifier is used to drive the analog input, the source Figure 18. Twos Complement Transfer Characteristic impedance should be limited to low values. The maximum with REFIN ± REFIN Input Range source impedance depends on the amount of total harmonic HANDLING BIPOLAR INPUT SIGNALS distortion (THD) that can be tolerated. The THD increases as Figure 19 shows how useful the combination of the 2 × REF the source impedance increases, and performance degrades (see IN input range and the twos complement output coding scheme is Figure 8). for handling bipolar input signals. If the bipolar input signal is AVDD biased about REFIN and twos complement output coding is selected, then REF becomes the zero code point, −REF is IN IN negative full scale and +REF becomes positive full scale, with D1 C2 IN R1 30pF a dynamic range of 2 × REF . VIN IN C1 4pF D2 CONVERSION PHASE: SWITCH OPEN TYPICAL CONNECTION DIAGRAM TRACK PHASE: SWITCH CLOSED 03089-016 FAiDgu7r9e0 82/0A sDho7w91s8 a/ AtyDp7ic9a2l8 c. oInn nthecist isoentu dpi,a gthrae mA GfoNr Dth ep in is Figure 16. Equivalent Analog Input Circuit connected to the analog ground plane of the system. In Figure 20, REF is connected to a decoupled 2.5 V supply from a reference ADC TRANSFER FUNCTION IN source, the AD780, to provide an analog input range of 0 V to The output coding of the AD7908/AD7918/AD7928 is either 2.5 V (if RANGE bit is 1) or 0 V to 5 V (if RANGE bit is 0). straight binary or twos complement, depending on the status of Although the AD7908/AD7918/AD7928 is connected to a V of DD the LSB in the control register. The designed code transitions 5 V, the serial interface is connected to a 3 V microprocessor. occur at successive LSB values (that is, 1 LSB, 2 LSBs, and so The V pin of the AD7908/AD7918/AD7928 is connected to DRIVE on). The LSB size is REF /256 for the AD7908, REF /1024 for IN IN the same 3 V supply of the microprocessor to allow a 3 V logic the AD7918, and REF /4096 for the AD7928. The ideal transfer IN interface (see the Digital Inputs section). The conversion result characteristic for the AD7908/AD7918/AD7928 when straight is output in a 16-bit word. This 16-bit data stream consists of a binary coding is selected is shown in Figure 17, and the ideal leading zero, three address bits indicating which channel the transfer characteristic for the AD7908/AD7918/AD7928 when conversion result corresponds to, followed by the 12 bits of twos complement coding is selected is shown in Figure 18. conversion data for the AD7928 (10 bits of data for the AD7918 and 8 bits of data for the AD7908, each followed by two and four trailing zeros, respectively). For applications where power 111…111 111…110 consumption is of concern, the power-down modes should be • E • used between conversions or bursts of several conversions to D O111…000 improve power performance (see the Modes of Operation DC C011…•111 section). A • 1LSB = VREF/256 AD7908 000000……•000110 11LLSSBB == VVRREEFF//41009264 AADD77992188 000…000 0V1 LSB +VREF– 1 LSB N1.O VTREEF IS EITAHNEARL OREGF IINN POURT 2 × REFIN. 03089-017 Figure 17. Straight Binary Transfer Characteristic Rev. E | Page 19 of 28

AD7908/AD7918/AD7928 Data Sheet VREF VDD 0.1µF REFINAVDD VDRIVE VDD AD7908/ V R4 AD7918/ DSP/µP AD7928 R3 TWOS COMPLEMENT R2 VIN0 DOUT 0V V • R1 • +REFIN (= 2 × REFIN) 011…111 VIN7 R1 = R2 = R3 = R4 REFIN 000…000 –REFIN (= 0V) 100…000 03089-019 Figure 19. Handling Bipolar Signals during the sequence, then it must be ensured that the SEQ and 5V SERIAL SHADOW bits are set to 1, 0 to avoid interrupting the 0.1µF 10µF SUPPLY INTERFACE automatic conversion sequence. This pattern continues until such time as the AD7908/AD7918/AD7928 is written to and the AVDD SCLK VIN0 AD7908/ SEQ and SHADOW bits are configured with any bit combination 0V TO REFIN •• AADD77991288/ DOCUST µC/µP except 1, 0. On completion of the sequence, the AD7908/ VIN7 AD7918/AD7928 sequencer returns to the first selected channel DIN AGND REFIN VDRIVE in the SHADOW register and commence the sequence again. Rather than selecting a particular sequence of channels, a 0.1µF A2D.57V80 0.1µF 10µF 3V number of consecutive channels beginning with Channel 0 can N1.O ATLEL UNUSED INPUT CHANNELS SHOULD BE CONNECTED TO ASGUNPDP.LY 03089-020 anleseod bineg p troo gwrraimtem toe dth vei aS HthAe DcoOnWtro rle rgeigsitsetre. rT ahloisn ies, pwoistshiobulet if the Figure 20. Typical Connection Diagram SEQ and SHADOW bits are set to 1,1. The channel address bits Analog Input Selection ADD2 through ADD0 then determine the final channel in the Any one of eight analog input channels can be selected for consecutive sequence. The next conversion is on Channel 0, conversion by programming the multiplexer with the Address then Channel 1, and so on until the channel selected via the Bit ADD2 to Address Bit ADD0 in the control register. The address bits ADD2 through ADD0 is reached. The cycle begins channel configurations are shown in Table 8. The AD7908/ again on the next serial transfer, provided the WRITE bit is set AD7918/AD7928 can also be configured to automatically cycle to low, or if high, that the SEQ and SHADOW bits are set to through a number of channels as selected. The sequencer 1, 0; then the ADC continues its preprogrammed automatic feature is accessed via the SEQ and SHADOW bits in the sequence uninterrupted. control register (see Table 10). Regardless of which channel selection method is used, the 16-bit The AD7908/AD7918/AD7928 can be programmed to word output from the AD7928 during each conversion always continuously convert on a selection of channels in ascending contains a leading zero, three channel address bits that the order. The analog input channels to be converted on are conversion result corresponds to, followed by the 12-bit selected through programming the relevant bits in the conversion result. The AD7918 outputs a leading zero, three SHADOW register (see the SHADOW Register section). The channel address bits that the conversion result corresponds to, next serial transfer then acts on the sequence programmed by followed by the 10-bit conversion result and two trailing zeros; executing a conversion on the lowest channel in the selection. the AD7908 outputs a leading zero, three channel address bits The next serial transfer results in a conversion on the next that the conversion result corresponds to, followed by the 8-bit highest channel in the sequence, and so on. conversion result and four trailing zeros. (See the Serial Interface section.) It is not necessary to write to the control register once a Digital Inputs sequencer operation has been initiated. The WRITE bit must be set to zero or the DIN line tied low to ensure the control register The digital inputs applied to the AD7908/AD7918/AD7928 are is not accidentally overwritten, or the sequence operation not limited by the maximum ratings that limit the analog interrupted. If the control register is written to at any time Rev. E | Page 20 of 28

Data Sheet AD7908/AD7918/AD7928 inputs. Instead, the digital inputs applied can go to 7 V and are The conversion is initiated on the falling edge of CS and the not restricted by the AVDD + 0.3 V limit as on the analog inputs. track-and-hold enters hold mode as described in the Serial Interface section. The data presented to the AD7908/AD7918/ Another advantage of SCLK, DIN, and CS not being restricted AD7928 on the DIN line during the first 12 clock cycles of the by the AV + 0.3 V limit is the fact that power supply DD data transfer are loaded into the control register (provided sequencing issues are avoided. If CS, DIN, or SCLK are applied WRITE bit is set to 1). If data is to be written to the SHADOW before AV , there is no risk of latch-up as there would be on DD register (SEQ = 0, SHADOW = 1 on previous write), data the analog inputs if a signal greater than 0.3 V was applied prior presented on the DIN line during the first 16 SCLK cycles is to AV . DD loaded into the SHADOW register. The part remains fully powered up in normal mode at the end of the conversion as V DRIVE long as PM1 and PM0 are both loaded with 1 on every data The AD7908/AD7918/AD7928 also have the V feature. DRIVE transfer. V controls the voltage at which the serial interface operates. DRIVE VDRIVE allows the ADC to easily interface to both 3 V and 5 V Sixteen serial clock cycles are required to complete the processors. For example, if the AD7908/AD7918/AD7928 were conversion and access the conversion result. The track-and- operated with an AVDD of 5 V, the VDRIVE pin could be powered hold goes back into track on the 14th SCLK falling edge. CS can from a 3 V supply. The AD7908/AD7918/AD7928 have better then idle high until the next conversion or can idle low until dynamic performance with an AVDD of 5 V while still being able sometime prior to the next conversion, effectively idling CS low. to interface to 3 V processors. Care should be taken to ensure V does not exceed AV by more than 0.3 V. See the Once a data transfer is complete (DOUT has returned to three- DRIVE DD Absolute Maximum Ratings section. state), another conversion can be initiated after the quiet time, t , has elapsed by bringing CS low again. QUIET Reference CS An external reference source should be used to supply the 2.5 V reference to the AD7908/AD7918/AD7928. Errors in the 1 12 16 SCLK reference source results in gain errors in the AD7908/ AD7918/AD7928 transfer function and adds to the specified DOUT 1 LEADING ZERO + 3 CHANNEL full-scale errors of the part. A capacitor of at least 0.1 μF should IDENTIFIER BITS + CONVERSION RESULT be placed on the REF pin. Suitable reference sources for the IN DIN DATA IN TO CONTROL/SHADOW REGISTER AD7908/AD7918/AD7928 include the AD780, REF192, AD1582, ADR03, ADR381, ADR391, and ADR421. N12..O CSTHOEANSDTOROWL R REEGGISISTTEERR D DAATTAA I SIS L LOOAADDEEDD O ONN F FIRIRSSTT 1 162 S SCCLLKK C CYYCCLLEESS.. 03089-021 If 2.5 V is applied to the REF pin, the analog input range can IN Figure 21. Normal Mode Operation either be 0 V to 2.5 V or 0 V to 5 V, depending on the setting of Full Shutdown Mode (PM1 = 1, PM0 = 0) the RANGE bit in the control register. In this mode, all internal circuitry on the AD7908/AD7918/ MODES OF OPERATION AD7928 is powered down. The part retains information in the The AD7908/AD7918/AD7928 have a number of different control register during full shutdown. The AD7908/AD7918/ modes of operation. These modes are designed to provide AD7928 remains in full shutdown until the power management flexible power management options. These options can be bits in the control register, PM1 and PM0, are changed. chosen to optimize the power dissipation/throughput rate ratio for differing application requirements. The mode of operation If a write to the control register occurs while the part is in full of the AD7908/AD7918/AD7928 is controlled by the power shutdown, with the power management bits changed to PM0 = management bits, PM1 and PM0, in the control register, as PM1 = 1, normal mode, the part begins to power up on the CS detailed in Table 9. When power supplies are first applied to the rising edge. The track-and-hold that was in hold while the part was AD7908/AD7918/AD7928, care should be taken to ensure that in full shutdown returns to track on the 14th SCLK falling edge. the part is placed in the required mode of operation (see To ensure that the part is fully powered up, t , should Powering Up the AD7908/AD7918/AD7928 section). POWERUP have elapsed before the next CS falling edge. Figure 22 shows Normal Mode (PM1 = PM0 = 1) the general diagram for this sequence. This mode is intended for the fastest throughput rate Auto Shutdown Mode (PM1 = 0, PM0 = 1) performance, as the user does not have to worry about any In this mode, the AD7908/AD7918/AD7928 automatically power-up times with the AD7908/AD7918/AD7928 remaining enters shutdown at the end of each conversion when the control fully powered at all times. Figure 21 shows the general diagram register is updated. When the part is in shutdown, the track and of the operation of the AD7908/AD7918/AD7928 in this mode. hold is in hold mode. Figure 23 shows the general diagram of Rev. E | Page 21 of 28

AD7908/AD7918/AD7928 Data Sheet the operation of the AD7908/AD7918/AD7928 in this mode. In effectively halves the throughput rate of the part, with every shutdown mode, all internal circuitry on the AD7908/AD7918/ other conversion result being valid. In this mode, the power AD7928 is powered down. The part retains information in the consumption of the part is greatly reduced with the part entering control register during shutdown. The AD7908/AD7918/ shutdown at the end of each conversion. When the control AD7928 remains in shutdown until the next CS falling edge it register is programmed to move into auto shutdown, it does so receives. On this CS falling edge, the track-and-hold that was in at the end of the conversion. The user can move the ADC in hold while the part was in shutdown returns to track. Wakeup and out of the low power state by controlling the CS signal. time from auto shutdown is 1 μs, and the user should ensure Powering Up the AD7908/AD7918/AD7928 that 1 μs has elapsed before attempting a valid conversion. When running the AD7908/AD7918/AD7928 with a 20 MHz When supplies are first applied to the AD7908/AD7918/ clock, one dummy cycle should be sufficient to ensure the part AD7928, the ADC can power up in any of the operating modes is fully powered up. During this dummy cycle the contents of of the part. To ensure the part is placed into the required the control register should remain unchanged; therefore the operating mode, the user should perform a dummy cycle WRITE bit should be 0 on the DIN line. This dummy cycle operation as outlined in Figure 24. PART IS IN PART BEGINSTO POWER UP ON THEPART IS FULLY POWERED UP FULL SHUTDOWN CS RISING EDGE AS PM1 = PM0 = 1 ONCEtPOWER UP HAS ELAPSED t12 CS 1 14 16 1 14 16 SCLK DOUT CHANNEL IDENTIFIER BITS + CONVERSION RESULT DIN DATA IN TO CONTROL REGISTER DATA IN TO CONTROL/SHADOW REGISTER CPMON1 T=R 1O, LP MR0E G= I1STER IS LOADED ON THE FIRST 12 CLOCKS. TLOOA KDE EPPMT1 H=E PPMA0R =T 1IN IN N COORNMTARLO MLO RDEEG,ISTER 03089-022 Figure 22. Full Shutdown Mode Operation PART ENTERS SHUTDOWN PART ENTERS SHUTDOWN ON CS PART BEGINS TO POWER PART IS FULLY ON CS RISING EDGE RISING EDGE AS PM1 = 0, PM0 = 1 UP ON CS FALLING EDGE POWERED UP AS PM1 = 0, PM0 = 1 CS DUMMY CONVERSION 1 12 16 1 12 16 1 12 16 SCLK DOUT BITSC H+A CNONNEVLE IRDSEINOTNIF RIEERSULT INVALID DATA BITSC H+A CNONNEVLE IRDSEINOTNIF RIEERSULT DIN DATA IN TO CONTROL/SHADOW REGISTER DATA IN TO CONTROL/SHADOW REGISTER CFIORNSTTR 1O2 LC RLOEGCIKSST,E PRM I1S =L O0,A PDME0D = O 1N THE CNOONT TCRHOALN GREEG. WISRTIETRE CBOITN =T E0NTS SHOULD TPOM 0K =E E1P IN P CAORTN TINR OTHL IRSE MGOISDTEE, RL OOARD S PEMT 1W =R 0IT,E BIT = 0 03089-023 Figure 23. Auto Shutdown Mode Operation CORRECT VALUE IN CONTROL REGISTER, VALID DATA FROM NEXT CONVERSION, USER CAN WRITE TO SHADOW REGISTER IN NEXT CONVERSION CS DUMMY CONVERSION DUMMY CONVERSION 1 12 16 1 12 16 1 12 16 SCLK DOUT INVALID DATA INVALID DATA INVALID DATA DIN DATA IN TO CONTROL REGISTER KEEP DIN LINE TIED HIGH FOR FIRST TWO DUMMY CONVERSIONS C12O CNLTORCOKL ERDEGGEISSTER IS LOADED ON THE FIRST 03089-024 Figure 24. Placing AD7928 into the Required Operating Mode After Supplies are Applied Rev. E | Page 22 of 28

Data Sheet AD7908/AD7918/AD7928 POWER VS. THROUGHPUT RATE SERIAL INTERFACE By operating in auto shutdown mode on the AD7908/AD7918/ Figure 27, Figure 28, and Figure 29 show the detailed timing AD7928, the average power consumption of the ADC decreases diagrams for serial interfacing to the AD7908, AD7918, and at lower throughput rates. Figure 25 shows how as the AD7928, respectively. The serial clock provides the conversion throughput rate is reduced, the part remains in its shutdown clock and also controls the transfer of information to and from state longer and the average power consumption over time the AD7908/AD7918/AD7928 during each conversion. drops accordingly. The CS signal initiates the data transfer and conversion process. For example, if the AD7928 is operated in a continuous The falling edge of CS puts the track-and-hold into hold mode, sampling mode with a throughput rate of 100 kSPS and an takes the bus out of three-state; the analog input is sampled at SCLK of 20 MHz (AV = 5 V), and the device is placed in auto this point. The conversion is also initiated at this point and DD shutdown mode, that is, if PM1 = 0 and PM0 = 1, then the requires 16 SCLK cycles to complete. The track-and-hold goes power consumption is calculated as follows: back into track on the 14th SCLK falling edge as shown in Figure 27, Figure 28, and Figure 29 at Point B, except when the The maximum power dissipation during normal operation is write is to the SHADOW register, in which case the track-and- 13.5 mW (AV = 5 V). If the power-up time from auto DD hold does not return to track until the rising edge of CS, that is, shutdown is one dummy cycle, that is, 1 μs, and the remaining Point C in Figure 30. On the 16th SCLK falling edge, the DOUT conversion time is another cycle, that is, 1 μs, then the AD7928 line goes back into three-state. If the rising edge of CS occurs can be said to dissipate 13.5 mW for 2 μs during each before 16 SCLKs have elapsed, the conversion is terminated, the conversion cycle. For the remainder of the conversion cycle, DOUT line goes back into three-state, and the control register is 8 μs, the part remains in auto shutdown mode. The AD7928 can not updated; otherwise DOUT returns to three-state on the be said to dissipate 2.5 μW for the remaining 8 μs of the 16th SCLK falling edge as shown in Figure 27, Figure 28, and conversion cycle. If the throughput rate is 100 kSPS, the cycle Figure 29. Sixteen serial clock cycles are required to perform the time is 10 μs and the average power dissipated during each cycle is conversion process and to access data from the AD7908/ (2/10) × (13.5 mW) + (8 / 10) × (2.5 μW) = 2.702 mW AD7918/AD7928. For the AD7908/AD7918/AD7928, the 8/10/12 bits of data are preceded by a leading zero and the Figure 25 shows the maximum power vs. throughput rate when 3-channel address bits (ADD2 to ADD0) identify which using the auto shutdown mode with 3 V and 5 V supplies. channel the result corresponds to. CS going low provides the leading zero to be read in by the microcontroller or DSP. The 10 three remaining address bits and data bits are then clocked out by subsequent SCLK falling edges beginning with the first address bit (ADD2). Thus the first falling clock edge on the AVDD = 5V AVDD = 3V serial clock has a leading zero provided and also clocks out 1 W) Address Bit ADD2. The final bit in the data transfer is valid on m R ( the 16th falling edge, having been clocked out on the previous E W (15th) falling edge. O P 0.1 Writing of information to the control register takes place on the first 12 falling edges of SCLK in a data transfer, assuming the MSB, that is, the WRITE bit, has been set to 1. If the control register is programmed to use the SHADOW register, then 0.010 50 100THRO15U0GHPU2T0 (0kSPS)250 300 350 03089-025 walrl i1ti6n SgC oLf Kin ffaolrlminagt ieodng etos itnh eth SeH nAeDxtO seWri arle tgriasntesrf etra,k aess s phloawcen o fno r Figure 25. AD7928 Power vs. Throughput Rate example on the AD7928 in Figure 30. Two sequence options can be programmed in the SHADOW register. If the user does not want to program a second sequence, then the eight LSBs should be filled with zeros. The SHADOW register is updated upon the rising edge of CS and the track-and-hold begins to track the first channel selected in the sequence. Rev. E | Page 23 of 28

AD7908/AD7918/AD7928 Data Sheet The AD7908 outputs a leading zero and three channel address AD7908/AD7918/AD7928 to TMS320C541 bits that the conversion result corresponds to, followed by the The serial interface on the TMS320C541 uses a continuous 8-bit conversion result and four trailing zeros. The AD7918 serial clock and frame synchronization signals to synchronize outputs a leading zero and three channel address bits that the the data transfer operations with peripheral devices like the conversion result corresponds to, followed by the 10-bit AD7908/AD7918/AD7928. The CS input allows easy interfacing conversion result and two trailing zeros. The 16-bit word read between the TMS320C541 and the AD7908/AD7918/AD7928 from the AD7928 always contains a leading zero and three without any glue logic required. The serial port of the channel address bits that the conversion result corresponds to, TMS320C541 is set up to operate in burst mode with internal followed by the 12-bit conversion result. CLKX0 (Tx serial clock on Serial Port 0) and FSX0 (Tx frame sync from Serial Port 0). The serial port control register (SPC) MICROPROCESSOR INTERFACING must have the following setup: FO = 0, FSM = 1, MCM = 1, and The serial interface on the AD7908/AD7918/AD7928 allows the TXM = 1. The connection diagram is shown in Figure 26. It part to be directly connected to a range of many different should be noted that for signal processing applications, it is microprocessors. This section explains how to interface the imperative that the frame synchronization signal from the AD7908/AD7918/AD7928 with some of the more common TMS320C541 provides equidistant sampling. The V pin of DRIVE microcontroller and DSP serial interface protocols. the AD7908/AD7918/AD7928 takes the same supply voltage as that of the TMS320C541. This allows the ADC to operate at a higher voltage than the serial interface, that is, TMS320C541, if necessary. AD7908/ TMS320C5411 AD7918/ AD79281 SCLK CLKX CLKR DOUT DR DIN DT CS FSX FSR VDRIVE 1ADDITIONAL PINS REMOVED FOR CLARITY. VDD 03089-030 Figure 26. Interfacing to the TMS320C541 Rev. E | Page 24 of 28

Data Sheet AD7908/AD7918/AD7928 CS t2 t6 tCONVERT B SCLK 1 2 3 4 5 6 11 12 13 14 15 16 t3 t4 t7 t5 t8 t11 tQUIET DOUT ADD2 ADD1 ADD0 DB7 DB6 DB0 ZERO ZERO ZERO ZERO THREE-STATE THREE IDENTIFICATION BITS FOUR TRAILING ZEROS THREE-STATE DIN ZWERRIOTE St9EQ1 DONTC ADD2 ADD1 AtD1D00 CODING DONTC DONTC DONTC DONTC 03089-026 Figure 27. AD7908 Serial Interface Timing Diagram CS t2 t6 tCONVERT B SCLK 1 2 3 4 5 6 11 12 13 14 15 16 t3 t4 t7 t5 t8 t11 tQUIET DOUT ADD2 ADD1 ADD0 DB7 DB6 DB2 DB1 DB0 ZERO ZERO THREE-STATE THREE IDENTIFICATION BITS TWO TRAILING ZEROS THREE-STATE DIN ZWERRIOTE tS9EQ DONTC ADD2 ADD1 AtD1D00 CODING DONTC DONTC DONTC DONTC 03089-027 Figure 28. AD7918 Serial Interface Timing Diagram CS tCONVERT t2 t6 B tQUIET SCLK 1 2 3 4 5 6 13 14 15 16 t3 t4 t7 t5 t8 t11 DOUT ADD2 ADD1 ADD0 DB11 DB10 DB2 DB1 DB0 THREE-STATE THREE IDENTIFICATION BITS THREE-STATE DIN ZWERRIOTE tS9EQ DONTC ADD2 ADDt110 ADD0 DONTC DONTC DONTC 03089-028 Figure 29. AD7928 Serial Interface Timing Diagram C CS tCONVERT t2 t6 SCLK 1 2 3 4 5 6 13 14 15 16 t3 t4 t7 t5 t8 t11 DOUT ADD2 ADD1 ADD0 DB11 DB10 DB2 DB1 DB0 THREE-STATE THREE-STATE THREE IDENTIFICATION BITS ZERO t9 t10 DIN VIN0 VIN1 SEQVUINE2NCE 1VIN3 VIN4 VIN5 SEQUEVNINC6E 2 VIN7 03089-029 Figure 30. AD7928 Writing to SHADOW Register Timing Diagram Rev. E | Page 25 of 28

AD7908/AD7918/AD7928 Data Sheet AD7908/AD7918/AD7928 to ADSP-21xx For example, if the ADSP-2189 had a 20 MHz crystal such that it had a master clock frequency of 40 MHz, then the master The ADSP-21xx family of DSPs are interfaced directly to the cycle time would be 25 ns. If the SCLKDIV register was loaded AD7908/AD7918/AD7928 without any glue logic required. The with the value 3, then an SCLK of 5 MHz is obtained, and eight V pin of the AD7908/AD7918/AD7928 takes the same DRIVE master clock periods elapse for every one SCLK period. supply voltage as that of the ADSP-21xx. This allows the ADC Depending on the throughput rate selected, if the timer register to operate at a higher voltage than the serial interface, that is, is loaded with the value, say 803 (803 + 1 = 804), 100.5 SCLKs ADSP-21xx, if necessary. occur between interrupts and subsequently between transmit The SPORT0 control register should be set up as follows: instructions. This situation results in nonequidistant sampling TFSW = RFSW = 1, alternate framing as the transmit instruction is occurring on a SCLK edge. If the INVRFS = INVTFS = 1, active low frame signal number of SCLKs between interrupts is a whole integer figure DTYPE = 00, right justify data of N, then equidistant sampling is implemented by the DSP. SLEN = 1111, 16-bit data-words AD7908/AD7918/AD7928 to DSP563xx ISCLK = 1, internal serial clock The connection diagram in Figure 32 shows how the TFSR = RFSR = 1, frame every word AD7908/AD7918/AD7928 can be connected to the synchronous IRFS = 0 serial interface (ESSI) of the DSP563xx family of DSPs from ITFS = 1 Motorola. Each ESSI (two on board) is operated in synchronous The connection diagram is shown in Figure 31. The ADSP-21xx mode (SYN bit in CRB = 1) with internally generated word has the TFS and RFS of the SPORT tied together, with TFS set length frame sync for both Tx and Rx (Bit FSL1 = 0 and as an output and RFS set as an input. The DSP operates in Bit FSL0 = 0 in CRB). Normal operation of the ESSI is selected alternate framing mode and the SPORT control register is set by making MOD = 0 in the CRB. Set the word length to 16 by up as described. The frame synchronization signal generated on setting Bit WL1 = 1 and Bit WL0 = 0 in CRA. The FSP bit in the the TFS is tied to CS, as with all signal processing applications CRB should be set to 1 so the frame sync is negative. It should where equidistant sampling is necessary. However, in this be noted that for signal processing applications, it is imperative example the timer interrupt is used to control the sampling rate that the frame synchronization signal from the DSP563xx of the ADC, and under certain conditions equidistant sampling provides equidistant sampling. cannot be achieved. In the example shown in Figure 32, the serial clock is taken AD7908/ ADSP-21xx1 from the ESSI so the SCK0 pin must be set as an output, SCKD AD7918/ AD79281 = 1. The VDRIVE pin of the AD7908/AD7918/AD7928 takes the SCLK SCLK same supply voltage as that of the DSP563xx. This allows the DOUT DR ADC to operate at a higher voltage than the serial interface, that CS RFS is, DSP563xx, if necessary. TFS AD7908/ DSP563xx1 DIN DT VDRIVE AD7918/ AD79281 1ADDITIONAL PINS REMOVED FOR CLARITY. VDD 03089-031 DSOCLUKT SSRCDK Figure 31. Interfacing to the ADSP-21xx DIN STD CS SC2 The timer register, for example, is loaded with a value that provides an interrupt at the required sample interval. When an VDRIVE icnotnetrrroulp wt oisr dre)c. eTihveed T, Fa Sv aisl uues eisd t troa ncsomntirttoeld t hwei tRhF TSF aSn/dD tTh u(As tDhCe 1ADDITIONAL PINS REMOVED FOR CLARITY. VDD 03089-032 reading of data. The frequency of the serial clock is set in the Figure 32. Interfacing to the DSP563xx SCLKDIV register. When the instruction to transmit with TFS is given (that is, AX0 = TX0), the state of the SCLK is checked. The DSP waits until the SCLK has gone high, low, and high before transmission can start. If the timer and SCLK values are chosen, such that the instruction to transmit occurs on or near the rising edge of SCLK, then the data can be transmitted or it can wait until the next clock edge. Rev. E | Page 26 of 28

Data Sheet AD7908/AD7918/AD7928 APPLICATION HINTS feedthrough through the board. A microstrip technique is by far Grounding and Layout the best, but is not always possible with a double sided board. In this technique, the component side of the board is dedicated to The AD7908/AD7918/AD7928 have very good immunity to ground planes while signals are placed on the solder side. noise on the power supplies, as can be seen by the PSRR vs. Supply Ripple Frequency plot, Figure 6. However, care should Good decoupling is also important. All analog supplies should still be taken with regard to grounding and layout. be decoupled with 10 μF tantalum in parallel with 0.1 μF capacitors to AGND. To achieve the best performance from The printed circuit board that houses the AD7908/AD7918/ these decoupling components, they must be placed as close as AD7928 should be designed so that the analog and digital possible to the device, ideally right up against the device. The sections are separated and confined to certain areas of the 0.1 μF capacitors should have low effective series resistance board. This facilitates the use of ground planes that can be (ESR) and effective series inductance (ESI), such as the separated easily. A minimum etch technique is generally best common ceramic types or surface mount types, which provide a for ground planes as it gives the best shielding. low impedance path to ground at high frequencies to handle All four AGND pins of the AD7908/AD7918/AD7928 should be transient currents due to internal logic switching. sunk in the AGND plane. If the AD7908/AD7918/AD7928 is in Evaluating the AD7908/AD7918/AD7928 Performance a system where multiple devices require an AGND to DGND The recommended layout for the AD7908/AD7918/AD7928 is connection, the connection should be made at only one point in outlined in the AD7908/AD7918/AD7928 evaluation board. The the plane. Using a star ground point, the connection should be evaluation board package includes a fully assembled and tested established as close as possible to the AD7908/AD7918/ evaluation board, documentation, and software for controlling AD7928. the board from the PC via the eval-board controller. Avoid running digital lines under the device, as these couple The eval-board controller can be used in conjunction with the noise onto the die. The analog ground plane should be allowed AD7908/AD7918/AD7928 evaluation board, as well as many to run under the AD7908/AD7918/AD7928 to avoid noise other Analog Devices evaluation boards ending in the CB coupling. The power supply lines to the AD7908/AD7918/ designator, to demonstrate/evaluate the ac and dc performance AD7928 should use as large a trace as possible to provide low of the AD7908/AD7918/AD7928. impedance paths and reduce the effects of glitches on the power supply line. Fast switching signals, like clocks, should be The software allows the user to perform ac (fast Fourier shielded with digital ground to avoid radiating noise to other transform) and dc (histogram of codes) tests on the AD7908/ sections of the board, and clock signals should never be run AD7918/AD7928. The software and documentation are on a CD near the analog inputs. Avoid crossover of digital and analog shipped with the evaluation board. signals. Traces on opposite sides of the board should run at right angles to each other. This reduces the effects of Rev. E | Page 27 of 28

AD7908/AD7918/AD7928 Data Sheet OUTLINE DIMENSIONS 6.60 6.50 6.40 20 11 4.50 4.40 4.30 6.40 BSC 1 10 PIN 1 0.65 BSC 0.15 1.20 MAX 0.20 0.05 0.09 0.75 0.30 8° 0.60 COPLANARITY 0.19 SEATING 0° 0.45 0.10 PLANE COMPLIANT TO JEDEC STANDARDS MO-153-AC Figure 33. 20-Lead Thin Shrink Small Outline Package [TSSOP] (RU-20) Dimensions shown in millimeters ORDERING GUIDE Model1, 2 Temperature Range Linearity Error (LSB)3 Package Description Package Option AD7908BRU-REEL −40°C to +85°C ±0.2 20-Lead TSSOP RU-20 AD7908BRU-REEL7 −40°C to +85°C ±0.2 20-Lead TSSOP RU-20 AD7908BRUZ −40°C to +85°C ±0.2 20-Lead TSSOP RU-20 AD7908BRUZ-REEL −40°C to +85°C ±0.2 20-Lead TSSOP RU-20 AD7908BRUZ-REEL7 −40°C to +85°C ±0.2 20-Lead TSSOP RU-20 AD7908WYRUZ-REEL7 −40°C to +125°C ±0.2 20-Lead TSSOP RU-20 AD7918BRU-REEL7 −40°C to +85°C ±0.5 20-Lead TSSOP RU-20 AD7918BRUZ −40°C to +85°C ±0.5 20-Lead TSSOP RU-20 AD7918BRUZ-REEL −40°C to +85°C ±0.5 20-Lead TSSOP RU-20 AD7918BRUZ-REEL7 −40°C to +85°C ±0.5 20-Lead TSSOP RU-20 AD7918WYRUZ-REEL7 −40°C to +125°C ±0.5 20-Lead TSSOP RU-20 AD7928BRUZ −40°C to +85°C ±1 20-Lead TSSOP RU-20 AD7928BRUZ-REEL −40°C to +85°C ±1 20-Lead TSSOP RU-20 AD7928BRUZ-REEL7 −40°C to +85°C ±1 20-Lead TSSOP RU-20 AD7928WBRUZ-REEL −40°C to +125°C ±1 20-Lead TSSOP RU-20 1 Z = RoHS Compliant Part. 2 W = Qualified for Automotive Applications. 3 Linearity error here refers to integral linearity error. AUTOMOTIVE PRODUCTS The AD79x8W models are available with controlled manufacturing to support the quality and reliability requirements of automotive applications. Note that these automotive models may have specifications that differ from the commercial models; therefore, designers should review the Specifications section of this data sheet carefully. Only the automotive grade products shown are available for use in automotive applications. Contact your local Analog Devices account representative for specific product ordering information and to obtain the specific Automotive Reliability reports for these models. ©2006–2014 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D03089-0-1/14(E) Rev. E | Page 28 of 28

Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: A nalog Devices Inc.: AD7928BRUZ-REEL AD7908BRUZ-REEL7 AD7918WYRUZ-REEL7 AD7918BRUZ AD7908WYRUZ-REEL7 AD7908BRUZ-REEL AD7928WBRUZ-REEL AD7918BRUZ-REEL7 AD7928BRUZ-REEL7 AD7908BRUZ AD7928BRUZ EVAL-AD7928SDZ