(cid:1) 2.7 V to 5.5 V, 12-Bit, 8 s ADC in 8-Lead SOIC/PDIP AD7896 FEATURES FUNCTIONAL BLOCK DIAGRAM 100 kHz Throughput Rate Fast 12-Bit Sampling ADC with 8 (cid:1)s Conversion Time VDD 8-Lead PDIP and SOIC Single 2.7 V to 5.5 V Supply Operation AD7896 High Speed, Easy-to-Use Serial Interface TRACK-AND-HOLD On-Chip Track-and-Hold Amplifier Analog Input Range Is 0 V to Supply VIN 12-BIT High Input Impedance ADC Low Power: 9 mW Typ CONVST OUTPUT REGISTER CLOCK AGND DGND BUSY SCLK SDATA GENERAL DESCRIPTION PRODUCT HIGHLIGHTS The AD7896 is a fast, 12-bit ADC that operates from a single 1. Complete, 12-bit ADC in an 8-Lead Package. 2.7V to 5.5 V supply and is housed in small 8-lead PDIP and The AD7896 contains an 8 µs ADC, a track-and-hold ampli- 8-lead SOIC packages. The part contains an 8 µs successive fier, control logic, and a high speed serial interface, all in an approximation ADC, an on-chip track-and-hold amplifier, an 8-lead PDIP. The V input is used as the reference for the DD on-chip clock, and a high speed serial interface. part, so no external reference is needed. This offers consider- able space saving over alternative solutions. Output data from the AD7896 is provided via a high speed, serial interface port. This 2-wire serial interface has a serial 2. Low Power, Single-Supply Operation. clock input and a serial data output with the external serial The AD7896 operates from a single 2.7 V to 5.5V supply clock accessing the serial data from the part. and consumes only 9 mW typical. The automatic power- down mode, where the part goes into power down once In addition to the traditional dc accuracy specifications, such as conversion is complete and “wakes up” before the next con- linearity, full-scale, and offset errors, the AD7896 is also speci- version cycle, makes the AD7896 ideal for battery-powered fied for dynamic performance parameters, including harmonic or portable applications. distortion and signal-to-noise ratio. 3. High Speed Serial Interface. The part accepts an analog input range of 0 V to V and operates DD The part provides high speed serial data and serial clock lines from a single 2.7 V to 5.5 V supply, consuming only 9 mW allowing for an easy, 2-wire serial interface arrangement. typical. The V input is also used as the reference for the part DD so that no external reference is required. The AD7896 features a high sampling rate mode and, for low power applications, a proprietary automatic power-down mode where the part automatically goes into power-down once conver- sion is complete and “wakes up” before the next conversion cycle. The part is available in a small, 8-lead, 0.3'' wide, plastic or hermetic dual-in-line package (PDIP) and in an 8-lead, small outline IC (SOIC). Rev. D Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. under any patent or patent rights of Analog Devices. Trademarks and Tel: 781/329-4700 www.analog.com registered trademarks are the property of their respective companies. Fax: 781/461-3113 ©1994–2011 Analog Device, Inc. All rights reserved.

AD7896–SPECIFICATIONS (V =2.7 V to 5.5 V, AGND = DGND = 0 V. All specifications T to T , DD MIN MAX unless otherwise noted.) Test Conditions/ Parameter A Version1 B Version J Version S Version Unit Comments DYNAMIC PERFORMANCE 2 Signal-to-(Noise + Distortion) Ratio3 @ 25°C 70 70 70 typ 70 dB min f = 10 kHz Sine Wave, IN f = 100kHz SAMPLE T to T 70 dB min MIN MAX Total Harmonic Distortion (THD)3 –77 –77 –80 typ –77 dB max f = 10 kHz Sine Wave, IN f = 100kHz SAMPLE Peak Harmonic or Spurious Noise3 –80 –80 –80 typ dB max f = 10 kHz Sine Wave, IN f = 100kHz SAMPLE Intermodulation Distortion (IMD)3 fa = 9 kHz, fb = 9.5 kHz, f = 100kHz SAMPLE Second Order Terms –77 –77 –80 typ –77 dB max Third Order Terms –80 –80 –80 typ –80 dB max DC ACCURACY Resolution 12 12 12 12 Bits Minimum Resolution for Which No Missing Codes Are Guaranteed 12 12 12 12 Bits Relative Accuracy3 ±1 ±1/2 ±1 ±1 LSB max Differential Nonlinearity3 ±1 ±1 ±1 ±1 LSB max Positive Full-Scale Error3 ±3 ±1.5 ±3 ±3 LSB max Unipolar Offset Error ±4 ±4 ±5 ±4 LSB max V = 5 V ± 10% DD ±4 ±3 ±5 ±4 LSB max V = 2.7 V to 3.6 V DD ANALOG INPUT Input Voltage Range 0to+V 0to+V 0to+V 0 to +V V DD DD DD DD Input Current ±2 ±2 ±2 ±5 µA max LOGIC INPUTS Input High Voltage, V 2.0 2.0 2.0 2.0 V min V = 2.7 V to 3.6 V INH DD 2.4 2.4 2.4 2.4 V = 5V ± 10% DD Input Low Voltage, V 0.8 0.8 0.8 0.8 V max INL Input Current, I ±10 ±10 ±10 ±10 µA max V = 0 V to V IN IN DD Input Capacitance, C 4 10 10 10 10 pF max IN LOGIC OUTPUTS Output High Voltage, V 2.4 2.4 2.4 2.4 V min I = 400 (cid:1)A OH SOURCE Output Low Voltage, V 0.4 0.4 0.4 0.4 V max I = 1.6 mA OL SINK Output Coding Straight (Natural) Binary CONVERSION RATE Conversion Time Mode 1 Operation 8 8 8 8.5 µs max Mode 2 Operation5 14 14 14 14.5 µs max Track-and-Hold Acquisition Time3 1.5 1.5 1.5 1.5 µs max –2– Rev. D

AD7896 Test Conditions/ Parameter A Version1 B Version J Version S Version Unit Comments POWER REQUIREMENTS V 2.7/5.5 2.7/5.5 2.7/5.5 2.7/5.5 V min/max DD I 4 4 4 4 mA max Digital Input @ DGND, DD V = 2.7 V to 3.6 V DD 5 5 5 5 mA max Digital Inputs @ DGND, V = 5 V ± 10% DD Power Dissipation 10.8 10.8 10.8 10.8 mW max V = 2.7 V, Typically 9 mW DD Power-Down Mode Digital Inputs @ DGND I @ 25°C 5 5 5 typ 5 µA max V = 2.7 V to 3.6 V DD DD T to T 15 15 75 75 µA max V = 2.7 V to 3.6 V MIN MAX DD I @ 25°C 50 50 50 50 µA max V = 5 V ± 10% DD DD T to T 150 150 500 500 µA max V = 5 V ± 10% MIN MAX DD Power Dissipation @ 25°C 13.5 13.5 13.5 13.5 µW max V = 2.7 V DD NOTES 1Temperature ranges are as follows: A, B Versions: –40°C to +85°C; J Version: 0°C to +70°C; S Version: –55°C to +125°C. 2Applies to Mode 1 operation. See the section on Operating Modes. 3See Terminology. 4Sample tested @ 25°C to ensure compliance. 5This 14 µs includes the wake-up time from standby. This wake-up time is timed from the rising edge of CONVST, whereas conversion is timed from the falling edge of CONVST, for narrow CONVST pulsewidth the conversion time is effectively the wake-up time plus conversion time, hence 14 µs. This can be seen from Figure 3. Note that if the CONVST pulsewidth is greater than 6 µs, the effective conversion time will increase beyond 14 µs. Specifications subject to change without notice. TIMING CHARACTERISTICS1 (V = 2.7 V to 5.5 V, AGND = DGND = 0V) DD Parameter A, B Versions J Version S Version Unit Test Conditions/Comments t 40 40 40 ns min CONVST Pulsewidth 1 t 402 402 452 ns min SCLK High Pulsewidth 2 t 402 402 452 ns min SCLK Low Pulsewidth 3 t Data Access Time after Falling Edge of SCLK 4 603 603 703 ns max V = 5 V ± 10% DD 1003 1003 1103 ns max V = 2.7 V to 3.6 V DD t 10 10 10 ns min Data Hold Time after Falling Edge of SCLK 5 t 504 504 504 ns max Bus Relinquish Time after Falling Edge of SCLK 6 NOTES 1Sample tested at 25°C to ensure compliance. All input signals are measured with tr = tf = 1 ns (10% to 90% of V ) and timed from a voltage level of 1.4V. DD 2The SCLK maximum frequency is 10 MHz. Care must be taken when interfacing to account for the data access time, t , and the setup time required for the user’s 4 processor. These two times will determine the maximum SCLK frequency that the user’s system can operate with. See Serial Interface section for more information. 3Measured with the load circuit of Figure 1 and defined as the time required for an output to cross 0.8V or 2V. 4Derived from the measured time taken by the data outputs to change 0.5V when loaded with the circuit of Figure 1. The measured number is then extrapolated back to remove the effects of charging or discharging the 50 pF capacitor. This means that the time, t , quoted in the timing characteristics is the true bus relinquish time 6 of the part and as such is independent of external bus loading capacitances. 1.6mA TO OUTPUT 1.6V PIN 50pF 400(cid:1)A Figure 1.Load Circuit for Access Time and Bus Relinquish Time Rev. D –3–

AD7896 ABSOLUTE MAXIMUM RATINGS* PDIP Package, Power Dissipation . . . . . . . . . . . . . . . .450 mW (T = 25°C, unless otherwise noted.) (cid:2) Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 125°C/W A JA V to AGND . . . . . . . . . . . . . . . . . . . . . . . . . .–0.3 V to +7 V (cid:2) Thermal Impedance . . . . . . . . . . . . . . . . . . . . . . 50°C/W DD JC V to DGND . . . . . . . . . . . . . . . . . . . . . . . . . .–0.3V to +7V Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . . 260°C DD Analog Input Voltage to AGND . . . . . . –0.3 V to V + 0.3V SOIC Package, Power Dissipation . . . . . . . . . . . . . . . .450 mW DD Digital Input Voltage to DGND . . . . . . –0.3 V to V + 0.3 V (cid:2) Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 160°C/W DD JA Digital Output Voltage to DGND . . . . . –0.3 V to V + 0.3 V (cid:2) Thermal Impedance . . . . . . . . . . . . . . . . . . . . . . 75°C/W DD JC Operating Temperature Range Lead Temperature, Soldering Commercial (J Version) . . . . . . . . . . . . . . . . . 0°C to +70°C Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . 215°C Industrial (A, B Versions) . . . . . . . . . . . . . .–40°C to +85°C Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . 220°C Extended (S Version) . . . . . . . . . . . . . . . . .–55°C to +125°C ESD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .>4000 V Storage Temperature Range . . . . . . . . . . . . .–65°C to +150°C *Stresses above those listed under Absolute Maximum Ratings may cause perma- Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . 150°C nent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD7896 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. –4– Rev. D

AD7896 PIN CONFIGURATION VIN 1 8 BUSY VDD 2 TAODP7 V8IE96W 7 CONVST AGND 3 (Not to Scale) 6 DGND SCLK 4 5 SDATA PIN FUNCTION DESCRIPTIONS Pin No. Mnemonic Description 1 V Analog Input. The analog input range is 0 V to V . IN DD 2 V Positive supply voltage, 2.7 V to 5.5 V. DD 3 AGND Analog Ground. Ground reference for track-and-hold, comparator, and DAC. 4 SCLK Serial Clock Input. An external serial clock is applied to this input to obtain serial data from the AD7896. A new serial data bit is clocked out on the falling edge of this serial clock. Data is guaranteed valid for 10 ns after this falling edge so data can be accepted on the falling edge when a fast serial clock is used. The serial clock input should be taken low at the end of the serial data transmission. 5 SDATA Serial Data Output. Serial data from the AD7896 is provided at this output. The serial data is clocked out by the falling edge of SCLK, but the data can also be read on the falling edge of the SCLK. This is possible because data bit N is valid for a specified time after the falling edge of the SCLK (data hold time) and can be read before data bit N+1 becomes valid a specified time after the falling edge of SCLK (data access time) (see Figure 4). Sixteen bits of serial data are provided with four leading zeros followed by the 12 bits of conversion data. On the 16th falling edge of SCLK, the SDATA line is held for the data hold time and then disabled (three-stated). Output data coding is straight binary. 6 DGND Digital Ground. Ground reference for digital circuitry. 7 CONVST Convert Start. Edge-triggered logic input. On the falling edge of this input, the track-and-hold goes into its hold mode and conversion is initiated. If CONVST is low at the end of conversion, the part goes into power-down mode. In this case, the rising edge of CONVST “wakes up” the part. 8 BUSY The BUSY pin is used to indicate when the part is doing a conversion. The BUSY pin goes high on the falling edge of CONVST and returns low when the conversion is complete. Rev. D –5–

AD7896 TERMINOLOGY Total Harmonic Distortion Relative Accuracy Total harmonic distortion (THD) is the ratio of the rms sum of This is the maximum deviation from a straight line passing harmonics to the fundamental. For the AD7896, it is defined as: through the endpoints of the ADC transfer function. The end- points of the transfer function are zero scale (which is VIN = V2 +V2 +V2 +V2 +V2 AGND + 1/2 LSB), a point 1/2 LSB below the first code transi- THD(dB)=20log 2 3 4 5 6 V tion (00...000 to 00...001), and full scale (which is VIN = 1 AGND + V – 1/2 LSB), a point 1/2 LSB above the last code DD where V is the rms amplitude of the fundamental and V , V , transition (11...110 to 11 ...111). 1 2 3 V , V ,and V are the rms amplitudes of the second through the 4 5 6 Differential Nonlinearity sixth harmonics. Thisis the difference between the measured and the ideal 1 LSB Peak Harmonic or Spurious Noise change between any two adjacent codes in the ADC. Peak harmonic or spurious noise is defined as the ratio of the Unipolar Offset Error rms value of the next largest component in the ADC output This is the deviation of the first code transition (00 . . . 000 to spectrum (up to f /2 and excluding dc) to the rms value of the S 00...001) from the ideal V voltage (AGND + 1 LSB). IN fundamental. Normally, the value of this specification is deter- Positive Full-Scale Error mined by the largest harmonic in the spectrum, but for parts This is the deviation of the last code transition (11...110 to where the harmonics are buried in the noise floor, it will be a 11...111) from the ideal (V = AGND + V – 1 LSB) noise peak. IN DD after the offset error has been adjusted out. Intermodulation Distortion Track-and-Hold Acquisition Time With inputs consisting of sine waves at two frequencies, fa and Track-and-hold acquisition time is the time required for the fb, any active device with nonlinearities will create distortion output of the track-and-hold amplifier to reach its final value, products at sum and difference frequencies of mfa ± nfb where within ±1/2 LSB, after the end of conversion (the point at which m, n = 0, 1, 2, 3, etc. Intermodulation distortion terms are the track-and-hold returns into track mode). It also applies to a those for which neither m nor n are equal to zero. For example, situation where there is a step input change on the input voltage the second order terms include (fa + fb) and (fa – fb), while the applied to the selected V input of the AD7896. It means that third order terms include (2fa + fb), (2fa – fb), (fa + 2fb), and IN the user must wait for the duration of the track-and-hold acquisi- (fa – 2fb). tion time after the end of conversion or after a step input change The AD7896 is tested using the CCIF standard where two to V before starting another conversion, to ensure the part IN input frequencies near the top end of the input bandwidth are operates to specification. used. In this case, the second order terms are usually distanced Signal-to-(Noise + Distortion) Ratio in frequency from the original sine waves while the third order This is the measured ratio of signal-to-(noise + distortion) at the terms are usually at a frequency close to the input frequencies. output of the ADC. The signal is the rms amplitude of the fun- As a result, the second and third order terms are specified sepa- damental. Noise is the sum of all nonfundamental signals up to rately. The calculation of the intermodulation distortion is as half the sampling frequency (f /2), excluding dc. The ratio is per the THD specification where it is the ratio of the rms sum of S dependent on the number of quantization levels in the digitiza- the individual distortion products to the rms amplitude of the tion process; the more levels, the smaller the quantization noise. fundamental expressed in dB. The theoretical signal-to-(noise + distortion) ratio for an ideal N-bit converter with a sine wave input is given by: Signal-to-(Noise + Distortion) = (6.02N + 1.76) dB Thus, for a 12-bit converter, this is 74 dB. –6– Rev. D

AD7896 CONVERTER DETAILS track-and-hold is greater than the Nyquistrate of the ADC even The AD7896 is a fast, 12-bit ADC that operates from a single when the ADC is operated at its maximum throughput rate of 2.7 V to 5.5 V supply. It provides the user with a track-and- 100kHz (i.e., the track-and-hold can handle input frequencies hold, ADC, andserialinterfacelogicfunctionson a single in excess of 50kHz). chip.The ADCsectionofthe AD7896 consists ofa conven- The track-and-hold amplifier acquires an input signal to 12-bit tional successive approximation converter based on an R-2R accuracy in less than 1.5µs. The operation of the track-and- ladder structure. The internal reference for the AD7896 is hold is essentially transparent to the user. With the high sampling derived from V ,which allowsthepart to accept an analog DD operating mode, the track-and-hold amplifier goes from its inputrange of 0 V to V . The AD7896 has two operating DD tracking mode to its hold mode at the start of conversion (i.e., modes: the high sampling mode andtheautosleep mode the rising edge of CONVST). The aperture time for the track- where thepartautomatically goes into sleep after the end of and-hold (i.e., the delay time between the external CONVST conversion. These modes are discussed in more detail in the signal and the track-and-hold actually going into hold) is typi- Timing and Control section. cally 15ns. At the end of conversion (on the falling edge of A major advantage of the AD7896 is that it provides all of the BUSY), the part returns to its trackingmode. The acquisition preceding functions in an 8-lead package, PDIP or SOIC. This time of the track-and-hold amplifier begins at thispoint. For the offers the user considerable space saving advantages over alterna- auto shutdown mode,therising edge of CONVST wakes up the tive solutions. The AD7896 consumes only 9 mW typical, making part and the track-and-hold amplifier goes from its tracking it ideal for battery-powered applications. mode to its hold mode 6 µs after the rising edge ofCONVST (provided that the CONVST high time is less than 6 µs). Once Conversion is initiated on the AD7896 by pulsing the CONVST again the part returns to its tracking mode at the end of conver- input. On the falling edge of CONVST, the on-chip track-and- sion when the BUSY signal goes low. hold goes from track to hold mode and the conversion sequence is started. The conversion clock for the part is generated inter- Timing and Control nally using a laser-trimmed clock oscillator circuit. Conversion Figure 2 shows the timing and control sequence required to time for the AD7896 is 8 µs in the high sampling mode (14 µs obtain optimum performance from the AD7896. In the for the auto sleep mode), and the track-and-hold acquisition sequence shown, conversion is initiated on the falling edge of time is 1.5µs. To obtain optimum performance from the part, CONVST and new data from this conversion is available in the the read operation should not occur during the conversion or output register of the AD7896 8µs later. Once the read opera- during 400ns prior to the next conversion. This allows the part tion has taken place, another 400ns should be allowed before to operate at throughput rates up to 100kHz and achieves data the next fallingedgeofCONVST tooptimizethesettlingof the sheet specifications (see the Timing and Control section). track-and-hold amplifier before the next conversion is initiated. With the serial clock frequency at its maximum of 10MHz (5 V CIRCUIT DESCRIPTION operation), the achievable throughput time for the part is 8µs Analog Input Section (conversion time) plus 1.6µs (read time) plus 0.4µs (acquisi- The analog input range for the AD7896 is 0 V to V The tion time). This results in a minimum throughput time of 10µs DD. V pin drives the input to the track-and-hold amplifier directly. (equivalent to a throughput rate of 100kHz). A serial clock of IN This allows for a maximum output impedance of the circuit less than 10 MHz can be used, but this will in turn mean that driving the analog input of 1 kΩ. This ensures that the part will the throughput time will increase. be settled to 12-bit accuracy in the 1.5 µs acquisition time. This The read operation consists of 16 serial clock pulses to the output input is benign with dynamic charging currents. The designed shift register of the AD7896. After 16 serial clock pulses, the shift code transitions occur on successive integer LSB values (i.e., register is reset and the SDATA line is three-stated. If there are 1LSB, 2LSB, 3LSB, . . . , FS – 1LSB). Output coding is straight more serial clock pulses after the 16th clock, the shift register will (natural) binary with 1LSB = FS/4096 = 3.3V/4096 = 0.81mV. be moved on past its reset state. However, the shift register will be The ideal input/output transfer function is shown in Table I. reset again on the falling edge of the CONVST signal to ensure that the part returns to a known state every conversion cycle. As a Table I. Ideal Input/Output Code Table for the AD7896 result, a read operation from the output register should not Analog Input1 Code Transition straddle across the falling edge of CONVST as the output shift register will be reset in the middle of the read operation and the +FSR – 1 LSB2 (3.299194) 111 . . . 110 to 111 . . . 111 data read back into the microprocessor will appear invalid. +FSR – 2 LSB (3.298389) 111 . . . 101 to 111 . . . 110 The throughput rate of the part can be increased by reading +FSR/2 – 3 LSB (3.297583) 111 . . . 100 to 111 . . . 101 data during conversion. If the data is read during conversion, a AGND + 3 LSB (0.002417) 000 . . . 010 to 000 . . . 011 throughput time of 8µs (conversion time) plus 1.5µs (acquisi- AGND + 2 LSB (0.001611) 000 . . . 001 to 000 . . . 010 tion time) is achieved when a 10 MHz, (5 V operation) serial AGND + 1 LSB (0.000806) 000 . . . 000 to 000 . . . 001 clock is being used. This minimum throughput time of 9.5µs is NOTES achieved with a slight reduction in performance from the AD7896. 1FSR is full-scale range and is 3.3V with VDD = +3.3 V. The advantage of this arrangement is that when the serial clock 21LSB = FSR/4096 = 0.81mV with V = +3.3V. DD is significantly lower than 10 MHz, the throughput time for this Track-and-Hold Section arrangement will be significantly less than the throughput time The track-and-hold amplifier on the analog input of the AD7896 where the data is read after conversion. The signal-to-(noise + allows the ADC to accurately convert an input sine wave of full- distortion) number is likely to degrade by less than 1 dB while scale amplitude to 12-bit accuracy. The input bandwidth of the the code flicker from the part will also increase (see the AD7896 Performance section). Rev. D –7–

AD7896 OPERATING MODES before the next conversion takes place. This is achieved by Mode 1 Operation (High Sampling Performance) keeping CONVST low at the end of conversion, whereas it was The timing diagram in Figure 2 is for optimum performance in high at the end of conversion for Mode 1 operation. The rising Operating Mode 1 where the falling edge of CONVST starts the edge of CONVST “wakes up” the part. This wake-up time is 6 conversion and puts the track-and-hold amplifier into its hold µs, at which point the track-and-hold amplifier goes into its hold mode. This falling edge of CONVST also causes the BUSY mode. The conversion takes 8 µs after this, provided the signal to go high to indicate that a conversion is taking place. CONVST has gone low, giving a total of 14 µs from the rising The BUSY signal goes low when the conversion is complete, edge of CONVST to the conversion being complete, which is which is 8 µs max after the falling edge of CONVST, and new indicated by the BUSY going low. Note that since the wake- data from this conversion is available in the output register of up time from the rising edge of CONVST is 6 µs, when the the AD7896. A read operation accesses this data. This read CONVST pulsewidth is greater than 6 µs, the conversion will operation consists of 16 clock cycles, and the length of this read take more than the 14 µs shown in the diagram from the rising operation depends on the serial clock frequency. For the fastest edge of CONVST. This is because the track-and-hold amplifier throughput rate (with a serial clock of 10 MHz at 5 V opera- goes into its hold mode on the falling edge of CONVST and tion), the read operation will take 1.6 µs. The read operation then the conversion will not be complete for a further 8 µs. In must be complete at least 400 ns before the falling edge of this case, the BUSY will be the best indicator for when the the next CONVST, which gives a total time of 10 µs for the full conversion is complete. Even though the part is in sleep mode, throughput time (equivalent to 100 kHz). This mode of opera- data can still be read from the part. The read operation consists tion should be used for high sampling applications. of 16 clock cycles as in Mode 1 operation. For the fastest serial clock of 10 MHz at 5 V operation, the read operation will take Mode 2 Operation (Auto Sleep after Conversion) 1.6 µs, which must be complete at least 400 ns before the falling The timing diagram in Figure 3 is for optimum performance in edge of the next CONVST to allow the track-and-hold amplifier Operating Mode 2 where the part automatically goes into sleep to have enough time to settle. This mode is very useful when the mode once BUSY goes low after conversion and “wakes up” part is converting at a slow rate as the power consumption will be significantly reduced from that of Mode 1 operation. tCONVERT = 8(cid:1)s t1 t1 = 40ns MIN CONVST BUSY 400ns MIN SCLK tCONVERT = 8(cid:1)s CONVERSION IS CONVERSION ENDS SERIAL READ READ OPERATION OUTPUT INITIATED AND 8(cid:1)s LATER OPERATION SHOULD END 400ns SERIAL TRACK-AND-HOLD GOES PRIOR TO NEXT SHIFT INTO HOLD FALLING EDGE OF REGISTER CONVST IS RESET Figure 2.Mode 1 Timing Operation Diagram for High Sampling Performance t1 = 6(cid:1)s WAKE-UP t 1 TIME CONVST BUSY 400ns MIN SCLK tCONVERT = 14(cid:1)s PART CONVERSION CONVERSION SERIAL READ READ OPERATION OUTPUT WAKES IS INITIATED ENDS OPERATION SHOULD END 400ns SERIAL UP TRACK-AND- 14µs LATER PRIOR TO NEXT SHIFT HOLD GOES FALLING EDGE OF REGISTER INTO HOLD IS RESET CONVST Figure 3.Mode 2 Timing Diagram Where Automatic Sleep Function Is Initiated –8– Rev. D

AD7896 Serial Interface must be low when CONVST goes low in order to reset the The serial interface to the AD7896 consists of three wires: a output shift register correctly. serial clock input (SCLK), the serial data output (SDATA), and The serial clock input does not need to be continuous during a conversion status output (BUSY). This allows for an easy-to- the serial read operation. The 16 bits of data (four leading zeros use interface to most microcontrollers, DSP processors, and and 12-bit conversion result) can be read from the AD7896 in a shift registers. number of bytes. However, the SCLK input must remain low Figure 4 shows the timing diagram for the read operation to the between the two bytes. AD7896. The serial clock input (SCLK) provides the clock The maximum SCLK frequency is 10 MHz for 5 V operation source for the serial interface. Serial data is clocked out from the (giving a throughput of 100 kHz) and at 2.7 V the maximum SDATA line on the falling edge of this clock and is valid on both SCLK frequency is less than 10 MHz to allow for the longer the rising and falling edges of SCLK. The advantage of having data access time, t (60 ns @ 5 V, 100 ns @ 2.7 V (A, B, J the data valid on both the rising and falling edges of the SCLK 4 versions), 70 ns @ 5 V, 110 ns @ 2.7 V (S version)). Note that is to give the user greater flexibility in interfacing to the part and at 3.0 V operation (A, B, J versions), an SCLK of 10 MHz so that a wider range of microprocessor and microcontroller inter- (throughput rate of 100 kHz) may be acceptable if the required faces can be accommodated. This also explains the two timing processor setup time is 0 ns (this may be possible with an ASIC figures t and t that are quoted on the diagram. The time t speci- 4 5 4 or FPGA). The data must be read in the next 10 ns, which is fies how long after the falling edge of the SCLK that the next data specified as the data hold time, t , after the SCLK edge. bit becomes valid, whereas the time t specifies how long after the 5 5 falling edge of the SCLK that the current data bit is valid for. The The AD7896 counts the serial clock edges to know which bit first leading zero is clocked out on the first rising edge of from the output register should be placed on the SDATA out- SCLK; note that the first zero may be valid on the first falling put. To ensure that the part does not lose synchronization, the edge of SCLK even though the data access time is specified serial clock counter is reset on the falling edge of the CONVST at 60 ns (5 V [A, B, J versions only]) for the other bits (and the input provided the SCLK line is low. The user should ensure SCLK high time will be 50 ns with a 10 MHz SCLK). The reason that a falling edge on the CONVST input does not occur while that the first bit will be clocked out faster than the other bits is a serial data read operation is in progress. due to the internal architecture of the part. Sixteen clock pulses must be provided to the part to access the full conversion result. MICROPROCESSOR/MICROCONTROLLER INTERFACE The AD7896 provides a 3-wire serial interface that can be The AD7896 provides four leading zeros followed by the 12-bit used for connection to the serial ports of DSP processors and conversion result starting with the MSB (DB11). The last data microcontrollers. Figures 5 through 8 show the AD7896 bit to be clocked out on the penultimate falling clock edge is the interfaced to a number of different microcontrollers and DSP LSB (DB0). On the 16th falling edge of SCLK, the LSB (DB0) processors. The AD7896 accepts an external serial clock and as will be valid for a specified time to allow the bit to be read on a result, in all interfaces shown here, the processor/controller is the falling edge of SCLK, and then the SDATA line is disabled configured as the master, providing the serial clock, with the (three-stated). After this last bit has been clocked out, the SCLK AD7896 configured as the slave in the system. input should remain low until the next serial data read opera- tion. If there are extra clock pulses after the 16th clock, the AD7896–8051 Interface AD7896 will start over again with outputting data from its out- Figure 5 shows an interface between the AD7896 and the put register, and the data bus will no longer be three-stated even 8X51/L51 microcontroller. The 8X51/L51 is configured for its when the clock stops. Provided the serial clock has stopped Mode 0 serial interface mode. The diagram shows the simplest before the next falling edge of CONVST, the AD7896 will form of the interface where the AD7896 is the only part connected continue to operate correctly with the output shift register being to the serial port of the 8X51/L51 and, therefore, no decoding reset on the falling edge of CONVST. However, the SCLK line of the serial read operations is required. t2 = t3 = 40ns MIN, t4 = 60ns MAX, t5 = 10ns MIN, t6 = 50ns MAX @ 5V, A, B, VERSIONS t 2 SCLK (I/P) 1 2 3 4 5 6 15 16 THREE-STATE t3 t4 t5 t6 4 LEADING ZEROS THREE-STATE DOUT (O/P) DB11 DB10 DB0 Figure 4.Data Read Operation Rev. D –9–

AD7896 To chip select the AD7896 in systems where more than one The BUSY line can be connected to the IRQ line of the device is connected to the 8X51/L51 serial port, a port bit, 68HC11/L11 if an interrupt driven system is preferred. These configured as an output, from one of the 8X51/L51 parallel two options are shown in the diagram. ports can be used to gate on or off the serial clock to the AD7896. The serial clock rate from the 68HC11/L11 is limited to signifi- A simple AND function on this port bit and the serial clock from cantly less than the allowable input serial clock frequency with the 8X51/L51 will provide this function. The port bit should be which the AD7896 can operate. As a result, the time to read high to select the AD7896 and low when it is not selected. data from the part will actually be longer than the conversion The end of conversion is monitored by using the BUSY signal, time of the part. This means that the AD7896 cannot run at its which is shown in the interface diagram of Figure 5, with the maximum throughput rate when used with the 68HC11/L11. BUSY line from the AD7896 connected to the Port P1.2 of the 8X51/L51 so the BUSY line can be polled by the 8X51/L51. The BUSY line can be connected to the INT1 line of the PC2 OR IRQ BUSY 8X51/L51 if an interrupt driven system is preferred. These two 68HC11/L11 AD7896 options are shown on the diagram. SCK SCLK Note also that the AD7896 outputs the MSB first during a read operation while the 8X51/L51 expects the LSB first. Therefore, the data that is read into the serial buffer needs to be rearranged MISO SDATA before the correct data format from the AD7896 appears in the accumulator. Figure 6.AD7896 to 68HC11/L11 Interface The serial clock rate from the 8X51/L51 is limited to signifi- AD7896–ADSP-2105 Interface cantly less than the allowable input serial clock frequency with which the AD7896 can operate. As a result, the time to read data from the part will actually be longer than the conversion time of the part. This means that the AD7896 cannot run at its maximum throughput rate when used with the 8X51/L51. P1.2 OR BUSY INT1 8X51/L51 AD7896 P3.0 SDATA P3.1 SCLK Figure 5.AD7896 to 8X51/L51 Interface AD7896–68HC11/L11 Interface An interface circuit between the AD7896 and the 68HC11/L11 microcontroller is shown in Figure 6. For the interface shown, the 68HC11/L11 SPI port is used and the 68HC11/L11 is con- figured in its single-chip mode. The 68HC11/L11 is configured in the master mode with its CPOL bit set to a Logic 0 and its CPHA bit set to a Logic 1. As with the previous interface, the diagram shows the simplest form of the interface, where the AD7896 is the only part connected to the serial port of the 68HC11/L11 and, therefore, no decoding of the serial read operations is required. Once again, to chip select the AD7896 in systems where more than one device is connected to the 68HC11/L11 serial port, a port bit, configured as an output, from one of the 68HC11/L11 parallel ports can be used to gate on or off the serial clock to the AD7896. A simple AND function on this port bit and the serial clock from the 68HC11/L11 will provide this function. The port bit should be high to select the AD7896 and low when it is not selected. The end of conversion is monitored by using the BUSY signal which is shown in the interface diagram of Figure 6. With the BUSY line from the AD7896 connected to the Port PC2 of the 68HC11/L11, the BUSY line can be polled by the 68HC11/L11. –10– Rev. D

AD7896 Figure 9 shows a histogram plot for 8192 conversions of a dc input using the AD7896 with a 3.3 V supply. The analog input was set at the center of a code transition. It can be seen that almost all the codes appear in the one output bin, indicating very good noise performance from the ADC. The rms noise performance for the AD7896 for the plot below was 111µV. 9000 IRQ2 BUSY 8000 fSAMPLE = 95kHz, RFS1 fSCLK = 8.33MHz, AD7896 AIN CENTERED ON CODE 1005 ADSP-2105 7000 RMS NOISE = 0.138 LSB SCLK 6000 SCLK1 E C EN 5000 DR1 SDATA RR U 4000 C C O Figure 7.AD7896 to ADSP-2105 Interface 3000 AD7896–DSP56002/L002 Interface 2000 Figure 8 shows an interface circuit between the AD7896 and the 1000 DSP56002/L002 DSP processor. The DSP56002/L002 is con- figured for normal mode asynchronous operation with gated 0 1005 1006 clock. It is also set up for a 16-bit word with SCK as gated clock CODE output. In this mode, the DSP56002/L002 provides 16 serial Figure 9.Histogram of 8192 Conversions of a DC Input clock pulses to the AD7896 in a serial read operation. The The same data is presented in Figure 10 as in Figure 9, except DSP56002/L002 assumes valid data on the first falling edge of that in this case, the output data read for the device occurs SCK so the interface is simply 2-wire as shown in Figure 8. during conversion. This has the effect of injecting noise onto the The BUSY line from the AD7896 is connected to the MODA/ die while bit decisions are being made and this increases the IRQA input of the DSP56002/L002 so that an interrupt will be noise generated by the AD7896. The histogram plot for 8192 generated at the end of conversion. This ensures that the read conversions of the same dc input now shows a larger spread of operation will take place after conversion is finished. codes with the rms noise for the AD7896 increasing to 279µV. This effect will vary depending on where the serial clock edges appear with respect to the bit trials of the conversion process. It is possible to achieve the same level of performance MODA/IRQA BUSY when reading during conversion as when reading after conver- DSP56002/L002 AD7896 sion, depending on the relationship of the serial clock edges to SCK SCLK the bit trial points. SDR SDATA 8000 7000 fSAMPLE = 95kHz, Figure 8.AD7896 to DSP56002/L002 Interface fSCLK = 8.33MHz, 6000 AIN CENTERED ON CODE 1005, RMS NOISE = 0.346 LSB AD7896 PERFORMANCE E 5000 C Linearity N E The linearity of the AD7896 is determined by the on-chip 12-bit RR 4000 U DAC. This is a segmented DAC that is laser trimmed for 12-bit C integral linearity and differential linearity. Typical relative accu- OC 3000 racy numbers for the part are ±1/4LSB, while the typical DNL 2000 errors are ±1/2LSB. 1000 Noise In an ADC, noise exhibits itself as code uncertainty in dc appli- 0 1004 1005 1006 cations and as the noise floor (in an FFT, for example) in ac CODE applications. In a sampling ADC like the AD7896, all informa- Figure 10.Histogram of 8192 Conversions with tion about the analog input appears in the baseband from dc Read during Conversion to 1/2 the sampling frequency. The input bandwidth of the track-and-hold exceeds the Nyquist bandwidth and, therefore, an antialiasing filter should be used to remove unwanted signals above f /2 in the input signal in applications where S such signals exist. Rev. D –11–

AD7896 Dynamic Performance (Mode 1 Only) 12.00 With a combined conversion and acquisition time of 9.5 µs, the AD7896 is ideal for wide bandwidth signal processing applications. These applications require information on the ADC’s effect on the TS 11.75 spectral content of the input signal. Signal-to-(noise + distortion), BI F total harmonic distortion, peak harmonic or spurious noise, and O R intermodulation distortion are all specified. Figure 11 shows a BE M 11.50 typical FFT plot of a 10 kHz, 0 V to 3.3V input after being digi- U N tized by the AD7896 operating at a 102.4kHz sampling rate. E V The signal-to-(noise + distortion) ratio is 71.5 dB and the total CTI E harmonic distortion is –82.4 dB. F 11.25 F E –0 fSAMPLE = 102.4kHz 11.00 fIN = 10kHz 0 25.6 51.2 –20 SNR = 71.54dB THD = –82.43dB INPUT FREQUENCY (kHz) Figure 12.Effective Number of Bits vs. Frequency –40 Power Considerations In the automatic power-down mode, the part can be operated B –60 d at a sample rate that is considerably less than 100 kHz. In this case, the power consumption will be reduced and will depend –80 on the sample rate. Figure 13 shows a graph of the power con- sumption versus sampling rates from 10 Hz to 1 kHz in the –100 automatic power-down mode. The conditions are 2.7 V supply, 25°C, serial clock frequency of 8.33 MHz, and the data was –120 read after conversion. 0 10240 20480 30720 40960 51200 FREQUENCY (Hz) 200 Figure 11.AD7896 FFT Plot fSCLK = 8.33MHz Effective Number of Bits The formula for signal-to-(noise + distortion) ratio (see the 160 Terminology section) is related to the resolution or number of bits in the converter. Rewriting the formula below gives a mea- W) 120 sure of performance expressed in effective number of bits (N) (cid:1) ( R N = (SNR 1.76)/6.02 WE O 80 where SNR is the signal-to-(noise + distortion) ratio. P The effective number of bits for a device can be calculated from 40 its measured signal-to-(noise + distortion) ratio. Figure 12 shows a typical plot of effective number of bits versus frequency for the AD7896 from dc to fSAMPLING/2. The sampling frequency 0 is 102.4 kHz. The plot shows that the AD7896 converts an input 10 100 1000 sine wave of 51.2kHz to an effective numbers of bits of 11.25, SAMPLING RATE IN Hz which equates to a signal-to-(noise + distortion) level of 69dB. Figure 13.Power vs. Sample Rate in Auto Power- Down Mode –12– Rev. D

AD7896 OUTLINE DIMENSIONS 0.400 (10.16) 0.365 (9.27) 0.355 (9.02) 8 5 0.280 (7.11) 0.250 (6.35) 1 4 0.240 (6.10) 0.325 (8.26) 0.310 (7.87) 0.100 (2.54) 0.300 (7.62) BSC 0.060 (1.52) 0.195 (4.95) 0.210 (5.33) MAX 0.130 (3.30) MAX 0.115 (2.92) 0.015 0.150 (3.81) (0.38) 0.015 (0.38) 0.130 (3.30) MIN GAUGE 0.115 (2.92) SEATING PLANE 0.014 (0.36) 0.010 (0.25) PLANE 0.022 (0.56) 0.008 (0.20) 0.005 (0.13) 0.430 (10.92) 0.018 (0.46) MIN MAX 0.014 (0.36) 0.070 (1.78) 0.060 (1.52) 0.045 (1.14) COMPLIANTTO JEDEC STANDARDS MS-001 CONTROLLING DIMENSIONSARE IN INCHES; MILLIMETER DIMENSIONS (RCINOEFRPEANRREERENN LCTEEHA EODSNSEL MSY)AAAYNR BDEE AR CROOEU NNNFODIGETUDAR-POEPFDRFOA INSPC RWHIAH ETOEQL UFEIO VORAR LU EHSNAETL ISFN FLDOEEARSDIGSN. . 070606-A Figure 14. 8-Lead Plastic Dual In-Line Package [PDIP] Narrow Body (N-8) Dimensions shown in inches and (millimeters) 5.00(0.1968) 4.80(0.1890) 8 5 4.00(0.1574) 6.20(0.2441) 3.80(0.1497) 1 4 5.80(0.2284) 1.27(0.0500) 0.50(0.0196) 45° BSC 1.75(0.0688) 0.25(0.0099) 0.25(0.0098) 1.35(0.0532) 8° 0.10(0.0040) 0° COPLANARITY 0.51(0.0201) 1.27(0.0500) 0.10 SEATING 0.31(0.0122) 0.25(0.0098) 0.40(0.0157) PLANE 0.17(0.0067) COMPLIANTTOJEDECSTANDARDSMS-012-AA CONTROLLINGDIMENSIONSAREINMILLIMETERS;INCHDIMENSIONS A (RINEFPEARREENNCTEHEOSNELSY)AANRDEARROEUNNODTEDA-POPFRFOMPIRLLIAIMTEETFEORREUQSUEIVINALDEENSTIGSNF.OR 012407- Figure 15. 8-Lead Standard Small Outline Package [SOIC_N] Narrow Body (R-8) Dimensions shown in millimeters and (inches) Rev. D | Page 13

AD7896 ORDERING GUIDE Model1 Linearity Error (LSB) SNR (dB) Temperature Range Package Description Package Option AD7896AN ±1 70 −40°C to +85°C 8-Lead PDIP N-8 AD7896ANZ ±1 70 −40°C to +85°C 8-Lead PDIP N-8 AD7896AR ±1 70 −40°C to +85°C 8-Lead SOIC_N R-8 AD7896AR-REEL ±1 70 −40°C to +85°C 8-Lead SOIC_N R-8 AD7896ARZ ±1 70 −40°C to +85°C 8-Lead SOIC_N R-8 AD7896ARZ-REEL ±1 70 −40°C to +85°C 8-Lead SOIC_N R-8 AD7896ARZ-REEL7 ±1 70 −40°C to +85°C 8-Lead SOIC_N R-8 AD7896BR ±1/2 70 −40°C to +85°C 8-Lead SOIC_N R-8 AD7896BR-REEL ±1/2 70 −40°C to +85°C 8-Lead SOIC_N R-8 AD7896BRZ ±1/2 70 −40°C to +85°C 8-Lead SOIC_N R-8 AD7896BRZ-REEL ±1/2 70 −40°C to +85°C 8-Lead SOIC_N R-8 AD7896BRZ-REEL7 ±1/2 70 −40°C to +85°C 8-Lead SOIC_N R-8 AD7896JR ±1 70 0°C to +70°C 8-Lead SOIC_N R-8 AD7896JRZ ±1 70 0°C to +70°C 8-Lead SOIC_N R-8 AD7896JRZ-REEL ±1 70 0°C to +70°C 8-Lead SOIC_N R-8 1 Z = RoHS Compliant Part. Rev. D | Page 14

AD7896 REVISION HISTORY 11/11—Rev. C to Rev. D Changes to Total Harmonic Distortion (THD) Parameter and to Intermodulation Distortion (IMD) Parameter ..................... 2 Changes to AD7896–ADSP-2105 Interface Section ................... 10 Updated Outline Dimensions ........................................................ 13 Changes to Ordering Guide ........................................................... 14 7/03—Rev. B to Rev. C Changes to Specifications ................................................................. 2 Changes to Figure 1 ........................................................................... 3 Changes to Ordering Guide ............................................................. 4 Added ESD Caution Section ............................................................ 4 Updated Outline Dimensions ........................................................ 13 ©1994–2011 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D09374-0-11/11(D) Rev. D | Page 15