LC2MOS 8-Channel, 12-Bit Serial Data Acquisition System AD7890 FEATURES FUNCTIONAL BLOCK DIAGRAM Fast 12-bit ADC with 5.9 μs conversion time VDD MUXSHA REF OUT/ OUT IN REF IN Eight single-ended analog input channels Selection of input ranges: VIN1 SSCIAGLNINAGL1 2kΩ 2.5V ±10 V for AD7890-10 REFERENCE 0 V to 4.096 V for AD7890-4 VIN2 SSCIAGLNINAGL1 0 V to 2.5 V for AD7890-2 VIN3 SIGNAL Allows separate access to multiplexer and ADC SCALING1 CEXT On-chip track/hold amplifier VIN4 SSCIAGLNINAGL1 MUX On-chip reference VIN5 SSCIAGLNINAGL1 High-speed, flexible, serial interface CONVST Single supply, low-power operation (50 mW maximum) VIN6 SSCIAGLNINAGL1 1A2-DBCIT Power-down mode (75 μW typ) VIN7 SIGNAL SCALING1 TRACK/HOLD GENERAL DESCRIPTION VIN8 SIGNAL SCALING1 OUTPUT/CONTROL REGISTER AD7890 The AD7890 is an 8-channel 12-bit data acquisition system. The part contains an input multiplexer, an on-chip track/hold CLOCK 01357-001 amplifier, a high speed 12-bit ADC, a 2.5 V reference, and a AGND AGND DGND CLK SCLK TFS RFS DATA DATA SMODE high speed, serial interface. The part operates from a single 5 V IN OUT IN supply and accepts an analog input range of ±10 V (AD7890-10), 1NO SCALING ON AD7890-2 0 V to 4.096 V (AD7890-4), and 0 V to 2.5 V (AD7890-2). Figure 1. The multiplexer on the part is independently accessible. This Power dissipation in normal mode is low at 30 mW typical and the allows the user to insert an antialiasing filter or signal part can be placed in a standby (power-down) mode if it is not conditioning, if required, between the multiplexer and the required to perform conversions. The AD7890 is fabricated in ADC. This means that one antialiasing filter can be used for all Analog Devices, Inc.’s Linear Compatible CMOS (LC2MOS) eight channels. Connection of an external capacitor allows the process, a mixed technology process that combines precision user to adjust the time given to the multiplexer settling to bipolar circuits with low power CMOS logic. The part is available include any external delays in the filter or signal conditioning in a 24-lead, 0.3" wide, plastic or ceramic dual-in-line package or in circuitry. a 24-lead small outline package (SOIC_W). PRODUCT HIGHLIGHTS Output data from the AD7890 is provided via a high speed bidirectional serial interface port. The part contains an on-chip 1. Complete 12-Bit Data Acquisition System-on-a-Chip. control register, allowing control of channel selection, The AD7890 is a complete monolithic ADC combining an conversion start, and power-down via the serial port. Versatile, 8-channel multiplexer, 12-bit ADC, 2.5 V reference, and a high speed logic ensures easy interfacing to serial ports on track/hold amplifier on a single chip. microcontrollers and digital signal processors. 2. Separate Access to Multiplexer and ADC. In addition to the traditional dc accuracy specifications such as The AD7890 provides access to the output of the linearity, full-scale, and offset errors, the AD7890 is also multiplexer allowing one antialiasing filter for 8 channels— specified for dynamic performance parameters including a considerable savings over the 8 antialiasing filters required if harmonic distortion and signal-to-noise ratio. the multiplexer is internally connected to the ADC. 3. High Speed Serial Interface. The part provides a high speed serial interface for easy connection to serial ports of microcontrollers and DSP processors. Rev. C Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Tel: 781.329.4700 www.analog.com Trademarks and registered trademarks are the property of their respective owners. Fax: 781.461.3113 ©2006 Analog Devices, Inc. All rights reserved.

AD7890 TABLE OF CONTENTS Features..............................................................................................1 Serial Interface................................................................................17 General Description.........................................................................1 Self-Clocking Mode...................................................................17 Functional Block Diagram..............................................................1 External Clocking Mode...........................................................18 Product Highlights...........................................................................1 Simplifying the Interface...........................................................19 Revision History...............................................................................2 Microprocessor/Microcontroller Interface.................................20 Specifications.....................................................................................3 AD7890 to 8051 Interface.........................................................20 Timing Specifications..................................................................5 AD7890 to 68HC11 Interface...................................................20 Absolute Maximum Ratings............................................................6 AD7890 to ADSP-2101 Interface.............................................21 ESD Caution..................................................................................6 AD7890 to DSP56000 Interface...............................................21 Pin Configuration and Function Descriptions.............................7 AD7890 to TMS320C25/30 Interface......................................21 Terminology......................................................................................9 Antialiasing Filter.......................................................................22 Control Register..............................................................................10 Performance....................................................................................23 Theory of Operation......................................................................11 Linearity.......................................................................................23 Converter Details........................................................................11 Noise............................................................................................23 Circuit Description.....................................................................11 Dynamic Performance...............................................................24 Track/Hold Amplifier................................................................12 Effective Number of Bits...........................................................24 Reference.....................................................................................13 Outline Dimensions.......................................................................25 Timing and Control...................................................................13 Ordering Guide..........................................................................27 C Functioning.........................................................................16 EXT REVISION HISTORY 9/06—Rev. B to Rev. C Updated Format..................................................................Universal Changes to Table 1............................................................................3 Updated Outline Dimensions.......................................................25 Changes to Ordering Guide..........................................................27 2/01—Rev. A to Rev. B Rev. C | Page 2 of 28

AD7890 SPECIFICATIONS V = 5 V, AGND = DGND = 0 V, REF IN = 2.5 V, f = 2.5 MHz external, MUX OUT connect to SHA IN. All specifications T to DD CLK IN MIN T , unless otherwise noted. MAX Table 1. Parameter A Versions1 B Versions S Version Unit Test Conditions/Comments DYNAMIC PERFORMANCE Using external CONVST, any channel Signal to (Noise + Distortion) Ratio2 70 70 70 dB min f = 10 kHz sine wave, f = 100 kHz3 IN SAMPLE Total Harmonic Distortion (THD)2 −77 −77 −77 dB max f = 10 kHz sine wave, f = 100 kHz3 IN SAMPLE Peak Harmonic or Spurious Noise2 −78 −78 −78 dB max f = 10 kHz sine wave, f = 100 kHz3 IN SAMPLE Intermodulation Distortion fa = 9 kHz, fb = 9.5 kHz, f = 100 kHz3 SAMPLE 2nd Order Terms −80 −80 −80 dB typ 3rd Order Terms −80 −80 −80 dB typ Channel-to-Channel Isolation2 −80 −80 −80 dB max fIN = 1 kHz sine wave DC ACCURACY Resolution 12 12 12 Bits Min. Resolution for Which No 12 12 12 Bits Missing Codes Are Guaranteed Relative Accuracy2 ±1 ±0.5 ±1 LSB max Differential Nonlinearity2 ±1 ±1 ±1 LSB max Positive Full-Scale Error2 ±2.5 ±2.5 ±2.5 LSB max Full-Scale Error Match4 2 2 2 LSB max AD7890-2, AD7890-4 Unipolar Offset Error2 ±2 ±2 ±2 LSB max Unipolar Offset Error Match 2 2 2 LSB max AD7890-10 Only Negative Full-Scale Error2 ±2 ±2 ±2 LSB max Bipolar Zero Error2 ±5 ±5 ±5 LSB max Bipolar Zero Error Match 2 2 2 LSB max ANALOG INPUTS AD7890-10 Input Voltage Range ±10 ±10 ±10 Volts Input Resistance 20 20 20 kΩ min AD7890-4 Input Voltage Range 0 to 4.096 0 to 4.096 0 to 4.096 Volts Input Resistance 11 11 11 kΩ min AD7890-2 Input Voltage Range 0 to 2.5 0 to 2.5 0 to 2.5 Volts Input Current 50 50 200 nA max MUX OUT OUTPUT Output Voltage Range 0 to 2.5 0 to 2.5 0 to 2.5 Volts Output Resistance AD7890-10, AD7890-4 3/5 3/5 3/5 kΩ min/kΩ max AD7890-2 2 2 2 kΩ max Assuming V is driven from low impedance IN SHA IN INPUT Input Voltage Range 0 to 2.5 0 to 2.5 0 to 2.5 Volts Input Current ±50 ±50 ±50 nA max REFERENCE OUTPUT/INPUT REF IN Input Voltage Range 2.375/2.625 2.375/2.625 2.375/2.625 V min/V max 2.5 V ± 5% Input Impedance 1.6 1.6 1.6 kΩ min Resistor connected to internal reference node Input Capacitance5 10 10 10 pF max REF OUT Output Voltage 2.5 2.5 2.5 V nom REF OUT Error @ 25°C ±10 ±10 ±10 mV max T to T ±20 ±20 ±25 mV max MIN MAX REF OUT Temperature Coefficient 25 25 25 ppm/°C typ REF OUT Output Impedance 2 2 2 kΩ nom Rev. C | Page 3 of 28

AD7890 Parameter A Versions1 B Versions S Version Unit Test Conditions/Comments LOGIC INPUTS Input High Voltage, V 2.4 2.4 2.4 V min V = 5 V ± 5% INH DD Input Low Voltage, V 0.8 0.8 0.8 V max V = 5 V ± 5% INL DD Input Current, I ±10 ±10 ±10 μA max V = 0 V to V IN IN DD Input Capacitance, C 5 10 10 10 pF max IN LOGIC OUTPUTS Output High Voltage, V 4.0 4.0 4.0 V min I = 200 μA OH SOURCE Output Low Voltage, V 0.4 0.4 0.4 V max I = 1.6 mA OL SINK Serial Data Output Coding AD7890-10 Twos Complement AD7890-4 Straight (Natural) Binary AD7890-2 Straight (Natural) Binary CONVERSION RATE Conversion Time 5.9 5.9 5.9 μs max f = 2.5 MHz, MUX OUT, connected to CLK IN SHA IN Track/Hold Acquisition Time2, 5 2 2 2 μs max POWER REQUIREMENTS V 5 5 5 V nom ± 5% for specified performance DD I (Normal Mode) 10 10 10 mA max Logic inputs = 0 V or V DD DD I (Standby Mode)6 @ 25°C 15 15 15 μA typ Logic inputs = 0 V or V DD DD Power Dissipation Normal Mode 50 50 50 mW max Typically 30 mW Standby Mode @ 25°C 75 75 75 μW typ 1 Temperature ranges are as follows: A, B Versions: −40°C to +85°C; S Version: −55°C to +125°C. 2 See the Terminology section. 3 This sample rate is only achievable when using the part in external clocking mode. 4 Full-scale error match applies to positive full scale for the AD7890-2 and AD7890-4. It applies to both positive and negative full scale for the AD7890-10. 5 Sample tested @ 25°C to ensure compliance. 6 Analog inputs on AD7890-10 must be at 0 V to achieve correct power-down current. Rev. C | Page 4 of 28

AD7890 TIMING SPECIFICATIONS V = 5 V ± 5%, AGND = DGND = 0 V, REF IN = 2.5 V, f = 2.5 MHz external, MUX OUT connected to SHA IN. DD CLK IN Parameter1, 2 Limit at T , T (A, B, S Versions) Unit Conditions/Comments MIN MAX f 3 100 kHz min Master Clock Frequency. For specified performance. CLKIN 2.5 MHz max t 0.3 × t ns min Master Clock Input Low Time. CLKIN IN LO CLK IN t 0 3 × t ns min Master Clock Input High Time. CLK IN HI CLK IN tr4 25 ns max Digital Output Rise Time. Typically 10 ns. tf4 25 ns max Digital Output Fall Time. Typically 10 ns. t 5.9 μs max Conversion Time. CONVERT t 100 ns min CONVST Pulse Width. CST Self-Clocking Mode t t + 50 ns max RFS Low to SCLK Falling Edge. 1 CLK IN HI t 5 25 ns max RFS Low to Data Valid Delay. 2 t t ns nom SCLK High Pulse Width. 3 CLK IN HI t t ns nom SCLK Low Pulse Width. 4 CLK IN LO t5 20 ns max SCLK Rising Edge to Data Valid Delay. 5 t 40 ns max SCLK Rising Edge to RFS Delay. 6 t 6 50 ns max Bus Relinquish Time after Rising Edge of SCLK. 7 t 0 ns min TFS Low to SCLK Falling Edge. 8 t + 50 ns max CLK IN t 0 ns min Data Valid to TFS Falling Edge Setup Time (A2 Address Bit). 9 t 20 ns min Data Valid to SCLK Falling Edge Setup Time. 10 t 10 ns min Data Valid to SCLK Falling Edge Hold Time. 11 t 20 ns min TFS to SCLK Falling Edge Hold Time. 12 External Clocking Mode t 20 ns min RFS Low to SCLK Falling Edge Setup Time. 13 t 5 40 ns max RFS Low to Data Valid Delay. 14 t 50 ns min SCLK High Pulse Width. 15 t 50 ns min SCLK Low Pulse Width. 16 t 5 35 ns max SCLK Rising Edge to Data Valid Delay. 17 t 20 ns min RFS to SCLK Falling Edge Hold Time. 18 t 6 50 ns max Bus Relinquish Time after Rising Edge of RFS. 19 t 6 90 ns max Bus Relinquish Time after Rising Edge of SCLK. 19A t 20 ns min TFS Low to SCLK Falling Edge Setup Time. 20 t 10 ns min Data Valid to SCLK Falling Edge Setup Time. 21 t 15 ns min Data Valid to SCLK Falling Edge Hold Time. 22 t 40 ns min TFS to SCLK Falling Edge Hold Time. 23 1 Sample tested at −25°C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V. 2 See Figure 10 to Figure 13. 3 The AD7890 is production tested with fCLK IN at 2.5 MHz. It is guaranteed by characterization to operate at 100 kHz. 4 Specified using 10% and 90% points on waveform of interest. 5 These numbers are measured with the load circuit of Figure 2 and defined as the time required for the output to cross 0.8 V or 2.4 V. 6 These numbers are derived from the measured time taken by the data output to change 0.5 V when loaded with the circuit of Figure 2. The measured number is then extrapolated back to remove effects of charging or discharging the 50 pF capacitor. This means that the times quoted in the timing characteristics are the true bus relinquish times of the part and as such are independent of external bus loading capacitances. 1.6mA TO OUTPUT 2.1V PIN 50pF 200µA 01357-002 Figure 2. Load Circuit for Access Time and Bus Relinquish Time Rev. C | Page 5 of 28

AD7890 ABSOLUTE MAXIMUM RATINGS T = 25°C, unless otherwise noted. A Parameter Rating Stresses above those listed under Absolute Maximum Ratings VDD to AGND −0.3 V to +7 V may cause permanent damage to the device. This is a stress VDD to DGND −0.3 V to +7 V rating only; functional operation of the device at these or any Analog Input Voltage to AGND other conditions above those indicated in the operational AD7890-10, AD7890-4 ±17 V section of this specification is not implied. Exposure to absolute AD7890-2 −5 V, +10 V maximum rating conditions for extended periods may affect Reference Input Voltage to AGND −0.3 V to VDD + 0.3 V device reliability. Digital Input Voltage to DGND −0.3 V to V + 0.3 V DD ESD CAUTION Digital Output Voltage to DGND −0.3 V to V + 0.3 V DD Operating Temperature Range Commercial (A, B Versions) −40°C to +85°C Extended (S Version) −55°C to +125°C Storage Temperature Range −65°C to +150°C Junction Temperature 150°C PDIP Package, Power Dissipation 450 mW θJA Thermal Impedance 105°C/W Lead Temperature (Soldering, 10 sec) 260°C CERDIP Package, Power Dissipation 450 mW θJA Thermal Impedance 70°C/W Lead Temperature (Soldering, 10 sec) 300°C SOIC_W Package, Power Dissipation 450 mW θJA Thermal Impedance 75°C/W Lead Temperature, Soldering Vapor Phase (60 sec) 215°C Infrared (15 sec) 220°C Rev. C | Page 6 of 28

AD7890 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS AGND 1 24 REF OUT/REF IN SMODE 2 23 VIN8 DGND 3 22 VIN7 CEXT 4 21 VIN6 AD7890 CONVST 5 TOP VIEW 20 VIN5 CLK IN 6 (Not to Scale) 19 VIN4 SCLK 7 18 VIN3 TFS 8 17 VIN2 RFS 9 16 VIN1 DATA OUT 10 15 AGND DATAV DIND 1112 1143 SMHUAX IONUT 01357-003 Figure 3. Pin Configuration Table 2. Pin Function Descriptions Pin No. Mnemonic Description 1 AGND Analog Ground. Ground reference for track/hold, comparator, and DAC. 2 SMODE Control Input. Determines whether the part operates in its external clocking (slave) or self-clocking (master) serial mode. With SMODE at a logic low, the part is in its self-clocking serial mode with RFS and SCLK as outputs. This self-clocking mode is useful for connection to shift registers or to serial ports of DSP processors. With SMODE at a logic high, the part is in its external clocking serial mode with SCLK and RFS as inputs. This external clocking mode is useful for connection to the serial port of microcontrollers, such as the 8xC51 and the 68HCxx, and for connection to the serial ports of DSP processors. 3 DGND Digital Ground. Ground reference for digital circuitry. 4 C External Capacitor. An external capacitor is connected to this pin to determine the length of the internal pulse EXT (see the Control Register section). Larger capacitances on this pin extend the pulse to allow for settling time delays through an external antialiasing filter or signal conditioning circuitry. 5 CONVST Convert Start. Edge-triggered logic input. A low-to-high transition on this input puts the track/hold into hold and initiates conversion if the internal pulse has timed out (see the Control Register section). If the internal pulse is active when the CONVST goes high, the track/hold does not proceed to hold until the pulse times out. If the internal pulse times out when CONVST goes high, the rising edge of CONVST drives the track/hold into hold and initiates conversion. 6 CLK IN Clock Input. An external TTL-compatible clock is applied to this input pin to provide the clock source for the conversion sequence. In the self-clocking serial mode, the SCLK output is derived from this CLK IN pin. 7 SCLK Serial Clock Input. In the external clocking (slave) mode (see the Serial Interface section), this is an externally applied serial clock used to load serial data to the control register and to access data from the output register. In the self-clocking (master) mode, the internal serial clock, which is derived from the clock input (CLK IN), appears on this pin. Once again, it is used to load serial data to the control register and to access data from the output register. 8 TFS Transmit Frame Synchronization Pulse. Active low logic input with serial data expected after the falling edge of this signal. 9 RFS Receive Frame Synchronization Pulse. In the external clocking mode, this pin is an active low logic input with RFS provided externally as a strobe or framing pulse to access serial data from the output register. In the self- clocking mode, it is an active low output, which is internally generated and provides a strobe or framing pulse for serial data from the output register. For applications which require that data be transmitted and received at the same time, RFS and TFS should be connected together. 10 DATA OUT Serial Data Output. Sixteen bits of serial data are provided with one leading zero, preceding the three address bits of the control register and the 12 bits of conversion data. Serial data is valid on the falling edge of SCLK for sixteen edges after RFS goes low. Output coding from the ADC is twos complement for the AD7890-10 and straight binary for the AD7890-4 and AD7890-2. 11 DATA IN Serial Data Input. Serial data to be loaded to the control register is provided at this input. The first five bits of serial data are loaded to the control register on the first five falling edges of SCLK after TFS goes low. Serial data on subsequent SCLK edges is ignored while TFS remains low. 12 V Positive Supply Voltage, 5 V ± 5%. DD 13 MUX OUT Multiplexer Output. The output of the multiplexer appears at this pin. The output voltage range from this output is 0 V to 2.5 V for the nominal analog input range to the selected channel. The output impedance of this output is nominally 3.5 kΩ. If no external antialiasing filter is required, MUX OUT should be connected to SHA IN. Rev. C | Page 7 of 28

AD7890 Pin No. Mnemonic Description 14 SHA IN Track/Hold Input. The input to the on-chip track/hold is applied to this pin. It is a high impedance input and the input voltage range is 0 V to 2.5 V. 15 AGND Analog Ground. Ground reference for track/hold, comparator, and DAC. 16 V Analog Input Channel 1. Single-ended analog input. The analog input range on is ±10 V (AD7890-10), 0 V to IN1 4.096 V (AD7890-4), and 0 V to 2.5 V (AD7890-2). The channel to be converted is selected using the A0, A1, and A2 bits in the control register. The multiplexer has guaranteed break-before-make operation. 17 V Analog Input Channel 2. Single-ended analog input. The analog input range on is ±10 V (AD7890-10), 0 V to IN2 4.096 V (AD7890-4), and 0 V to 2.5 V (AD7890-2). The channel to be converted is selected using the A0, A1, and A2 bits in the control register. The multiplexer has guaranteed break-before-make operation. 18 V Analog Input Channel 3. Single-ended analog input. The analog input range on is ±10 V (AD7890-10), 0 V to IN3 4.096 V (AD7890-4), and 0 V to 2.5 V (AD7890-2). The channel to be converted is selected using the A0, A1, and A2 bits in the control register. The multiplexer has guaranteed break-before-make operation. 19 V Analog Input Channel 4. Single-ended analog input. The analog input range on is ±10 V (AD7890-10), 0 V to IN4 4.096 V (AD7890-4), and 0 V to 2.5 V (AD7890-2). The channel to be converted is selected using the A0, A1, and A2 bits in the control register. The multiplexer has guaranteed break-before-make operation. 20 V Analog Input Channel 5. Single-ended analog input. The analog input range on is ±10 V (AD7890-10), 0 V to IN5 4.096 V (AD7890-4), and 0 V to 2.5 V (AD7890-2). The channel to be converted is selected using the A0, A1, and A2 bits in the control register. The multiplexer has guaranteed break-before-make operation. 21 V Analog Input Channel 6. Single-ended analog input. The analog input range on is ±10 V (AD7890-10), 0 V to IN6 4.096 V (AD7890-4), and 0 V to 2.5 V (AD7890-2). The channel to be converted is selected using the A0, A1, and A2 bits in the control register. The multiplexer has guaranteed break-before-make operation. 22 V Analog Input Channel 7. Single-ended analog input. The analog input range on is ±10 V (AD7890-10), 0 V to IN7 4.096 V (AD7890-4), and 0 V to 2.5 V (AD7890-2). The channel to be converted is selected using the A0, A1, and A2 bits in the control register. The multiplexer has guaranteed break-before-make operation. 23 V Analog Input Channel 8. Single-ended analog input. The analog input range on is ±10 V (AD7890-10), 0 V to IN8 4.096 V (AD7890-4) and 0 V to 2.5 V (AD7890-2). The channel to be converted is selected using the A0, A1, and A2 bits in the control register. The multiplexer has guaranteed break-before-make operation. 24 REF OUT/REF IN Voltage Reference Output/Input. The part can be used with either its own internal reference or with an external reference source. The on-chip 2.5 V reference voltage is provided at this pin. When using this internal reference as the reference source for the part, REF OUT should decoupled to AGND with a 0.1 μF disc ceramic capacitor. The output impedance of this reference source is typically 2 kΩ. When using an external reference source as the reference voltage for the part, the reference source should be connected to this pin. This overdrives the internal reference and provides the reference source for the part. The REF IN input is buffered on-chip. The nominal reference voltage for correct operation of the AD7890 is 2.5 V. Rev. C | Page 8 of 28

AD7890 TERMINOLOGY Signal to (Noise + Distortion) Ratio Channel-to-Channel Isolation This is the measured ratio of signal to (noise + distortion) at the Channel-to-channel isolation is a measure of the level of crosstalk output of the A/D converter. The signal is the rms amplitude of between channels. It is measured by applying a full-scale 1 kHz the fundamental. Noise is the rms sum of all nonfundamental signal to any one of the other seven inputs and determining how signals up to half the sampling frequency (f/2), excluding dc. much that signal is attenuated in the channel of interest. The figure S The ratio is dependent upon the number of quantization levels given is the worst case across all eight channels. in the digitization process; the more levels, the smaller the Relative Accuracy quantization noise. The theoretical signal to (noise + distortion) Relative accuracy or endpoint nonlinearity is the maximum ratio for an ideal N-bit converter with a sine wave input is given by: deviation from a straight line passing through the endpoints of Signal to (Noise + Distortion) = (6.02N + 1.76) dB the ADC transfer function. Thus, for a 12-bit converter, this is 74 dB. Differential Nonlinearity Total Harmonic Distortion This is the difference between the measured and the ideal 1 LSB Total harmonic distortion (THD) is the ratio of the rms sum of change between any two adjacent codes in the ADC. harmonics to the fundamental. For the AD7890, it is defined as Positive Full-Scale Error (AD7890-10) V 2 +V 2 +V 2 +V 2 +V 2 This is the deviation of the last code transition (01 . . . 110 to THD(dB)=20log 2 3 4 5 6 V 01 . . . 111) from the ideal (4 × REF IN − 1 LSB) after the 1 bipolar zero error has been adjusted out. where: Positive Full-Scale Error (AD7890-4) V is the rms amplitude of the fundamental and 1 This is the deviation of the last code transition (11 . . . 110 to V, V, V, V and V are the rms amplitudes of the second 2 3 4 5, 6 11 . . . 111) from the ideal (1.638 × REF IN − 1 LSB) after the through the sixth harmonics. unipolar offset error has been adjusted out. Peak Harmonic or Spurious Noise Positive Full-Scale Error (AD7890-2) Peak harmonic or spurious noise is defined as the ratio of the This is the deviation of the last code transition (11 . . . 110 to rms value of the next largest component in the ADC output 11 . . . 111) from the ideal (REF IN − 1 LSB) after the unipolar spectrum (up to f/2 and excluding dc) to the rms value of the S offset error has been adjusted out. fundamental. Normally, the value of this specification is determined by the largest harmonic in the spectrum, but for Bipolar Zero Error (AD7890-10) parts where the harmonics are buried in the noise floor, it is This is the deviation of the midscale transition (all 0s to all 1s) determined by a noise peak. from the ideal 0 V (AGND). Intermodulation Distortion Unipolar Offset Error (AD7890-2, AD7890-4) With inputs consisting of sine waves at two frequencies, fa and This is the deviation of the first code transition (00 . . . 000 to fb, any active device with nonlinearities creates distortion 00 . . . 001) from the ideal 0 V (AGND). products at sum and difference frequencies of mfa ± nfb where m, n = 0, 1, 2, 3, and so on. Intermodulation terms are those for Negative Full-Scale Error (AD7890-10) which neither m nor n are equal to zero. For example, the This is the deviation of the first code transition (10 . . . 000 to second-order terms include (fa + fb) and (fa − fb), while the 10 . . . 001) from the ideal (−4 × REF IN + 1 LSB) after bipolar third-order terms include (2fa + fb), (2fa − fb), (fa + 2fb), and zero error has been adjusted out. (fa − 2fb). Track/Hold Acquisition Time The AD7890 is tested using the CCIF standard where two input Track/hold acquisition time is the time required for the output frequencies near the top end of the input bandwidth are used. of the track/hold amplifier to reach its final value, within In this case, the second and third order terms are of different ±1/2 LSB, after the end of conversion (the point at which the significance. The second-order terms are usually distanced in track/hold returns to track mode). It also applies to situations frequency from the original sine waves while the third-order where a change in the selected input channel takes place or terms are usually at a frequency close to the input frequencies. where there is a step input change on the input voltage applied As a result, the second- and third-order terms are specified to the selected V input of the AD7890. It means that the user IN separately. The calculation of the intermodulation distortion is must wait for the duration of the track/hold acquisition time as per the THD specification where it is the ratio of the rms after the end of conversion or after a channel change/step input sum of the individual distortion products to the rms amplitude change to V before starting another conversion, to ensure that IN of the fundamental expressed in dBs. the part operates to specification. Rev. C | Page 9 of 28

AD7890 CONTROL REGISTER The control register for the AD7890 contains 5 bits of information. If, however, the CONV bit of the register is set to a Logic 1, then Six serial clock pulses must be provided to the part in order to a conversion is initiated whenever a control register write takes write data to the control register (seven if the write is required place regardless of how many serial clock cycles the TFS to put the part in standby mode). If TFS returns high before six remains low for. The default (power-on) condition of all bits in serial clock cycles, then no data transfer takes place to the the control register is 0. control register and the write cycle has to be restarted to write the data to the control register. MSB LSB A2 A1 A0 CONV STBY Table 3. Bit Name Description A2 Address Input. This input is the most significant address input for multiplexer channel selection. A1 Address Input. This is the 2nd most significant address input for multiplexer channel selection. A0 Address Input. Least significant address input for multiplexer channel selection. When the address is written to the control register, an internal pulse is initiated, the pulse width of which is determined by the value of capacitance on the C pin. When EXT this pulse is active, it ensures the conversion process cannot be activated. This allows for the multiplexer settling time, track/hold acquisition time before the track/hold goes into hold, and the conversion is initiated. In applications where there is an antialiasing filter between the MUX OUT pin and the SHA IN pin , the filter settling time can be taken into account before the input on the SHA IN pin is sampled. When the internal pulse times out, the track/hold goes into hold and conversion is initiated. CONV Conversion Start. Writing a 1 to this bit initiates a conversion in a similar manner to the CONVST input. Continuous conversion starts do not take place when there is a 1 in this location. The internal pulse and the conversion process are initiated after the sixth serial clock cycle of the write operation if a 1 is written to this bit. With a 1 in this bit, the hardware conversion start (the CONVST input) is disabled. Writing a 0 to this bit enables the hardware CONVST input. STBY Standby Mode Input. Writing a 1 to this bit places the device in its standby, or power-down, mode. Writing a 0 to this bit places the device in its normal operating mode. The part does not enter its standby mode until the seventh falling edge of SCLK in a write operation. Therefore, the part requires seven serial clock pulses in its serial write operation if it is required to put the part into standby. Rev. C | Page 10 of 28

AD7890 THEORY OF OPERATION CONVERTER DETAILS This allows the part to operate at throughput rates up to 117 kHz in the external clocking mode and achieve data sheet The AD7890 is an 8-channel, 12-bit, single supply, serial data specifications. The part can operate at slightly higher acquisition system. It provides the user with signal scaling, throughput rates (up to 127 kHz), again in external clocking multiplexer, track/hold, reference, ADC, and versatile serial mode with degraded performance (see the Timing and Control logic functions on a single chip. The signal scaling allows the section). The throughput rate for self-clocking mode is limited part to handle ±10 V input signals (AD7890-10) and 0 V to by the serial clock rate to 78 kHz. 4.096 V input signals (AD7890-4) while operating from a single 5 V supply. The AD7890-2 contains no signal scaling and All unused inputs should be connected to a voltage within the accepts an analog input range of 0 V to 2.5 V. The part operates nominal analog input range to avoid noise pickup. On the from a 2.5 V reference, which can be provided from the part’s AD7890-10, if any one of the input channels which are not own internal reference or from an external reference source. being converted goes more negative than −12 V, it can interfere with the conversion on the selected channel. Unlike other single chip data acquisition solutions, the AD7890 provides the user with separate access to the multiplexer and CIRCUIT DESCRIPTION the ADC. This means that the flexibility of separate multiplexer The AD7890 is offered as three part types: the AD7890-10 and ADC solutions is not sacrificed with the one-chip solution. handles a ±10 V input voltage range, the AD7890-4 handles a With access to the multiplexer output, the user can implement 0 V to 4.096 V input range, while the AD7890-2 handles a 0 V external signal conditioning between the multiplexer and the to 2.5 V input voltage range. track/hold. It means that one antialiasing filter can be used on the output of the multiplexer to provide the antialiasing AD7890-10 Analog Input function for all eight channels. Figure 4 shows the analog input section for the AD7890-10. The analog input range for each of the analog inputs is ±10 V into Conversion is initiated on the AD7890 either by pulsing the an input resistance of typically 33 kΩ. This input is benign with CONVST input or by writing a Logic 1 to the CONV bit of the no dynamic charging currents with the resistor attenuator stage control register. When using the hardware CONVST input, on followed by the multiplexer and, in cases where MUX OUT is the rising edge of the CONVST signal, the on-chip track/hold connected to SHA IN, this is followed by the high input goes from track to hold mode and the conversion sequence is impedance stage of the track/hold amplifier. The designed code started, provided the internal pulse has timed out. This internal transitions occur on successive integer LSB values (such as: pulse (which appears at the CEXT pin) is initiated whenever the 1 LSB, 2 LSBs, 3 LSBs...). Output coding is twos complement multiplexer address is loaded to the AD7890 control register. binary with 1 LSB − FSR/4096 = 20 V/4096 = 4.88 mV. The This pulse goes from high to low when a serial write to the part ideal input/output transfer function is shown in Table 4. is initiated. It starts to discharge on the sixth falling clock edge of SCLK in a serial write operation to the part. The track/hold MUX OUT cannot go into hold and conversion cannot be initiated until the C pin has crossed its trigger point of 2.5 V. The discharge 2.5V EXT REFERENCE time of the voltage on CEXT depends upon the value of capacitor 2kΩ connected to the C pin (see the C Functioning section). REF OUT/ EXT EXT REF IN The fact that the pulse is initiated every time a write to the TO ADC REFERENCE control register takes place means that the software conversion CIRCUITRY start and track/hold signal is always delayed by the internal pulse. 7.5kΩ 30kΩ 200Ω1 VINX The conversion clock for the part is generated from the clock 10kΩ sfoigrn tahle a AppDli7e8d9 t0o i sth 5e.9 C μLsK f rIoNm p tihne o rfi stihneg p eadrgt.e C oof nthvee rhsiaornd wtiamree AGND AD7890-10 01357-004 1EQUIVALENT ON-RESISTANCE OF MULTIPLEXER CONVST signal and the track/hold acquisition time is 2 μs. To Figure 4. AD7890-10 Analog Input Structure obtain optimum performance from the part, the data read operation or control register write operation should not occur during the conversion or during 500 ns prior to the next conversion. Rev. C | Page 11 of 28

AD7890 Table 4. Ideal Input/Output Code Table for the AD7890-10 this is followed by the high input impedance stage of the track/ Analog Input1 Digital Output Code Transition hold amplifier. The analog input range is, therefore, 0 V to 2.5 V +FSR/2 − 1 LSB2 (9.995117 V) 011 . . . 110 to 011 . . . 111 into a high impedance stage with an input current of less than +FSR/2 − 2 LSBs (9.990234 V) 011 . . . 101 to 011 . . . 110 50 nA. The designed code transitions occur on successive +FSR/2 − 3 LSBs (9.985352 V) 011 . . . 100 to 011 . . . 101 integer LSB values (such as: l LSB, 2 LSBs, 3 LSBs . . . FS-1 AGND + 1 LSB (0.004883 V) 000 . . . 000 to 000 . . . 001 LSBs). Output coding is straight (natural) binary with 1 LSB = AGND (0.000000 V) 111 . . . 111 to 000 . . . 000 FSR/4096 = 2.5 V/4096 = 0.61 mV. The ideal input/output AGND − 1 LSB (−0.004883 V) 111 . . . 110 to 111 . . . 111 transfer function is shown in Table 6. −FSR/2 + 3 LSBs (−9.985352 V) 100 . . . 010 to 100 . . . 011 Table 6. Ideal Input/Output Code Table for the AD7890-2 −FSR/2 + 2 LSBs (−9.990234 V) 100 . . . 001 to 100 . . . 010 Analog Input1 Digital Output Code Transition −FSR/2 + 1 LSB (−9.995117 V) 100 . . . 000 to 100 . . . 001 +FSR − 1 LSB2 (2.499390 V) 111 . . . 110 to 111 . . . 111 +FSR − 2 LSBs (2.498779 V) 111 . . . 101 to 111 . . . 110 1FSR is full-scale range and is 20 V with REF IN = 2.5 V. 21 LSB = FSR/4096 = 4.883 mV with REF IN = 2.5 V. +FSR − 3 LSBs (2.498169 V) 111 . . . 100 to 111 . . . 101 AD7890-4 Analog Input AGND + 3 LSBs (0.001831 V) 000 . . . 010 to 010 . . . 011 AGND + 2 LSBs (0.001221 V) 000 . . . 001 to 001 . . . 010 Figure 5 shows the analog input section for the AD7890-4. The AGND + 1 LSB (0.000610 V) 000 . . . 000 to 000 . . . 001 analog input range for each of the analog inputs is 0 to 4.096 V into an input resistance of typically 15 kΩ. This input is benign 1FSR is full-scale range and is 2.5 V with REF IN = 2.5 V. with no dynamic charging currents with the resistor attenuator 21 LSB = FSR/4096 = 0.61 mV with REF IN = 2.5 V. stage followed by the multiplexer and in cases where MUX OUT is TRACK/HOLD AMPLIFIER connected to SHA IN this is followed by the high input impedance stage of the track/hold amplifier. The designed code The SHA IN input on the AD7890 connects directly to the input transitions occur on successive integer LSB values (such as: stage of the track/hold amplifier. This is a high impedance input 1 LSB, 2 LSBs, 3 LSBs . . . ). Output coding is straight (natural) with input leakage currents of less than 50 nA. Connecting the binary with 1 LSB = FSR/4096 = 4.096 V/4096 = 1 mV. The MUX OUT pin directly to the SHA IN pin connects the ideal input/output transfer function is shown in Table 5. multiplexer output directly to the track/hold amplifier. The input MUX OUT voltage range for this input is 0 V to 2.5 V. If external circuitry is connected between MUX OUT and SHA IN, then the user must 2.5V ensure that the input voltage range to the SHA IN input is 0 V to REFERENCE 2.5 V to ensure that the full dynamic range of the converter is 2kΩ REF OUT/ utilized. REF IN TO ADC REFERENCE The track/hold amplifier on the AD7890 allows the ADC to CIRCUITRY accurately convert an input sine wave of full-scale amplitude to 6kΩ 200Ω1 12-bit accuracy. The input bandwidth of the track/hold is VINX 9.38kΩ greater than the Nyquist rate of the ADC even when the ADC is AGND AD7890-4 01357-005 othpee rtraatecdk /ahto iltds mcaanx himanudmle t ihnrpouutg fhrepquut ernatcei eosf i1n1 e7x kcHeszs o(ffo 5r8 e xkaHmzp).l e, 1EQUIVALENT ON-RESISTANCE OF MULTIPLEXER The track/hold amplifier acquires an input signal to 12-bit Figure 5. AD7890-4 Analog Input Structure accuracy in less than 2 μs. The operation of the track/hold is Table 5. Ideal Input/Output Code Table for the AD7890-4 essentially transparent to the user. The track/hold amplifier Analog Input1 Digital Output Code Transition goes from its tracking mode to its hold mode at the start of +FSR − 1 LSB2 (4.095 V) 111 . . . 110 to 111 . . . 111 conversion. The start of conversion is the rising edge of +FSR − 2 LSBs (4.094 V) 111 . . . 101 to 111 . . . 110 CONVST (assuming the internal pulse has timed out) for +FSR − 3 LSBs (4.093 V) 111 . . . 100 to 111 . . . 101 hardware conversion starts and for software conversion starts is AGND + 3 LSBs (0.003 V) 000 . . . 010 to 000 . . . 011 the point where the internal pulse is timed out. The aperture AGND + 2 LSBs (0.002 V) 000 . . . 001 to 000 . . . 010 time for the track/hold (for example, the delay time between the AGND + 1 LSB (0.001 V) 000 . . . 000 to 000 . . . 001 external CONVST signal and the track/hold actually going into 1FSR is full-scale range and is 4.096 V with REF IN = 2.5 V. hold) is typically 15 ns. For software conversion starts, the time 21 LSB = FSR/4096 = 1 mV with REF IN = 2.5 V. depends on the internal pulse widths. Therefore, for software conversion starts, the sampling instant is not very well defined. AD7890-2 Analog Input For sampling systems which require well defined, equidistant The analog input section for the AD7890-2 contains no biasing sampling, it may not be possible to achieve optimum performance resistors and the selected analog input connects to the multi- from the part using the software conversion start. At the end of plexer and, in cases where MUX OUT is connected to SHA IN, Rev. C | Page 12 of 28

AD7890 conversion, the part returns to its tracking mode. The acquisition the user provides the frame sync and serial clock signals to obtain time of the track/ hold amplifier begins at this point. the serial data from the part. In this second mode, the user has control of the serial clock rate up to a maximum of 10 MHz. The REFERENCE two modes are discussed in the Serial Interface section. The AD7890 contains a single reference pin, labeled REF OUT/ The part also provides hardware and software conversion start REF IN, which either provides access to the part’s own 2.5 V features. The former provides a well-defined sampling instant reference or to which an external 2.5 V reference can be connected with the track/hold going into hold on the rising edge of the to provide the reference source for the part. The part is specified CONVST signal. For the software conversion start, a write to with a 2.5 V reference voltage. Errors in the reference source results the CONV bit to the control register initiates the conversion in gain errors in the AD7890’s transfer function and adds to the sequence. However, for the software conversion start an internal specified full-scale errors on the part. On the AD7893-10, it also pulse has to time out before the input signal is sampled. This results in an offset error injected in the attenuator stage. pulse, plus the difficulty in maintaining exactly equal delays The AD7890 contains an on-chip 2.5 V reference. To use this between each software conversion start command, means that reference as the reference source for the AD7890, simply connect a the dynamic performance of the AD7890 may have difficulty 0.1 μF disc ceramic capacitor from the REF OUT/REF IN pin to meeting specifications when used in software conversion start AGND. The voltage which appears at this pin is internally buffered mode. The AD7890 provides separate channel select and before being applied to the ADC. If this reference is required for conversion start control. This allows the user to optimize the use external to the AD7890, it should be buffered as the source throughput rate of the system. Once the track/hold has gone into impedance of this output is 2 kΩ nominal. The tolerance on the hold mode, the input channel can be updated and the input voltage internal reference is ±10 mV at 25°C with a typical temperature can settle to the new value while the present conversion is in coefficient of 25 ppm/°C and a maximum error over temperature progress. of ±25 mV. Assuming the internal pulse has timed out before the CONVST If the application requires a reference with a tighter tolerance or pulse is exercised, the conversion consists of 14.5 master clock the AD7890 needs to be used with a system reference, then the cycles. In the self-clocking mode, the conversion time is defined user has the option of connecting an external reference to this as the time from the rising edge of CONVST to the falling edge REF OUT/REF IN pin. The external reference effectively of RFS (for example, when the device starts to transmit its overdrives the internal reference and thus provides the reference conversion result). This time includes the 14.5 master clock source for the ADC. The reference input is buffered, but has a cycles plus the updating of the output register and delay time in nominal 2 kΩ resistor connected to the AD7890’s internal outputting the RFS signal, resulting in a total conversion time of reference. Suitable reference sources for the AD7890 include the 5.9 μs maximum. Figure 6 shows the conversion timing for the AD680, AD780, and REF-43 precision 2.5 V references. AD7890 when used in the self-clocking (master) mode with TIMING AND CONTROL hardware CONVST. The timing diagram assumes that the The AD7890 is capable of two interface modes, selected by the internal pulse is not active when the CONVST signal goes high. SMODE input. The first of these is a self-clocking mode where To ensure this, the channel address to be converted should be the part provides the frame sync, serial clock, and serial data at selected by writing to the control register prior to the CONVST the end of conversion. In this mode the serial clock rate is pulse. Sufficient setup time should be allowed between the determined by the master clock rate of the part (at the CLK IN control register write and the CONVST to ensure that the internal input). The second mode is an external clocking mode where pulse has timed out. The duration of the internal pulse (and hence the duration of setup time) depends on the value of C . EXT CONVST (I) TRACK/HOLD GOES INTO THE HOLD tCONVERT RFS (O) SCLK (O) THREE-STATE DATA OUT (O)1 N12..O ((OIT) E)S SSIG:IGNNIFIFIEIESS A ANN I NOPUUTTP.UT. PULL-UP RESISTOR ON SCLK. 01357-006 Figure 6. Self-Clocking (Master) Mode Conversion Sequence Rev. C | Page 13 of 28

AD7890 When using the device in the external-clocking mode, the before the next rising edge of CONVST to optimize the settling output register can be read at any time and the most up-to-date of the track/hold before the next conversion is initiated. conversion result is obtained. However, reading data from the output register or writing data to the control register during The diagram shows the read operation and the write operation conversion or during the 500 ns prior to the next CONVST taking place in parallel. On the sixth falling edge of SCLK in the results in reduced performance from the part. A read operation write sequence the internal pulse is initiated. Assuming MUX OUT to the output register has the most effect on performance with is connected to SHA IN, 2 μs are required between this sixth the signal-to-noise ratio likely to degrade, especially when falling edge of SCLK and the rising edge of CONVST to allow higher serial clock rates are used while the code flicker from the for the full acquisition time of the track/hold amplifier. With part also increases (see the Performance section). the serial clock rate at its maximum of 10 MHz, the achievable throughput rate for the part is 5.9 μs (conversion time) plus 0.6 Figure 7 shows the timing and control sequence required to μs (six serial clock pulses before internal pulse is initiated) plus obtain optimum performance from the part in the external 2 μs (acquisition time). This results in a minimum throughput clocking mode. In the sequence shown, conversion is initiated time of 8.5 μs (equivalent to a throughput rate of 117 kHz). If on the rising edge of CONVST and new data is available in the the part is operated with a slower serial clock, it affects the output register of the AD7890 5.9 μs later. Once the read achievable throughput rate for optimum performance. operation has taken place, a further 500 ns should be allowed CONVST SCLK RFS TFS tCONVERT 500ns MIN 01357-007 CONVERSION IS CONVERSION SERIAL READ READ AND WRITE NEXT CONVERSION INITIATED AND ENDS 5.9µs AND WRITE OPERATIONS SHOULD END START COMMAND TRACK/HOLD GOES LATER OPERATIONS 500ns PRIOR TO NEXT INTO HOLD RISING EDGE OF CONVST Figure 7. External Clocking (Slave) Mode Timing Sequence for Optimum Performance Rev. C | Page 14 of 28

AD7890 CONVST occurs 5.9 μs later and can be used as either an active In the self-clocking mode, the AD7890 indicates when low or falling edge-triggered interrupt signal to tell the conversion is complete by bringing the RFS line low and processor to read the data from the AD7890. Provided the read initiating a serial data transfer. In the external clocking mode, operation is completed 500 ns before the rising edge of there is no indication of when conversion is complete. In many CONVST, the AD7890 operates to specification. applications, this is not a problem as the data can be read from the part during conversion or after conversion. However, This scheme limits the throughput rate to 11.8 μs minimum. applications that seek to achieve optimum performance from However, depending upon the response time of the the AD7890 has to ensure that the data read does not occur microprocessor to the interrupt signal and the time taken by the during conversion or during 500 ns prior to the rising edge processor to read the data, this may be the fastest which the of CONVST. system could have operated. In any case, the CONVST signal This can be achieved in either of two ways. The first is to ensure does not have to have a 50:50 duty cycle. This can be tailored to optimize the throughput rate of the part for a given system. in software that the read operation is not initiated until 5.9 μs after the rising edge of CONVST. This is only possible if the Alternatively, the CONVST signal can be used as a normal software knows when the CONVST command is issued. The narrow pulse width. The rising edge of CONVST can be used as second scheme would be to use the CONVST signal as both the an active high or rising edge-triggered interrupt. A software conversion start signal and an interrupt signal. The simplest delay of 5.9 μs can then be implemented before data is read way to do this is to generate a square wave signal for CONVST from the part. with high and low times of 5.9 μs (see Figure 8). Conversion is initiated on the rising edge of CONVST. The falling edge of CONVST SCLK RFS TFS tCONVERT 500ns MIN 01357-008 CONVERSION IS CONVERSION MICROPROCESSOR SERIAL READ READ AND WRITE NEXT CONVST INITIATED AND ENDS 5.9µs INT SERVICE AND WRITE OPERATIONS SHOULD RISING EDGE TRACK/HOLD GOES LATER OR POLLING OPERATIONS END 500ns PRIOR INTO HOLD ROUTINE TO NEXT RISING EDGE OF CONVST Figure 8. CONVST Used as Status Signal in External Clocking Mode Rev. C | Page 15 of 28

AD7890 C FUNCTIONING The duration of the internal pulse can be seen on the C pin. EXT EXT The C pin goes from a low to a high when a serial write to The C input on the AD7890 provides a means of determining EXT EXT how long after a new channel address is written to the part that the part is initiated (on the falling edge of TFS). It starts to a conversion can take place. The reason behind this is two-fold. discharge on the sixth falling edge of SCLK in the serial write First, when the input channel to the AD7890 is changed, the operation. Once the CEXT pin has discharged to crossing its input voltage on this new channel is likely to be very different nominal trigger point of 2.5 V, the internal pulse is timed out. from the previous channel voltage. Therefore, the part’s track/ The internal pulse is initiated each time a write operation to the hold has to acquire the new voltage before an accurate control register takes place. As a result, the pulse is initiated and conversion can take place. An internal pulse delays any the conversion process delayed for all software conversion start conversion start command (as well as the signal to send the commands. For hardware conversion start, it is possible to track/hold into hold) until after this pulse has timed out. separate the conversion start command from the internal pulse. The second reason is to allow the user to connect external If the multiplexer output (MUX OUT) is connected directly to antialiasing or signal conditioning circuitry between the the track/hold input (SHA IN), then no external settling has to MUX OUT pin and the SHA IN pin. This external circuitry be taken into account by the internal pulse width. In applications introduces extra settling time into the system. The C pin EXT where the multiplexer is switched and conversion is not provides a means for the user to extend the internal pulse to initiated until more than 2 μs after the channel is changed (as is take this extra settling time into account. Effectively varying the possible with a hardware conversion start), the user does not value of the capacitor on the C pin varies the duration of the EXT have to worry about connecting any capacitance to the internal pulse. Figure 9 shows the relationship between the C pin. The 2 μs equates to the track/hold acquisition time of EXT value of the C capacitor and the internal delay. EXT the AD7890. In applications where the multiplexer is switched 64 and conversion is initiated at the same time (such as with a software conversion start), a 120 pF capacitor should be 56 connected to C to allow for the acquisition time of the EXT µs) 48 TA = +25°C track/hold before conversion is initiated. TH ( TA = +85°C WID 40 If external circuitry is connected between the MUX OUT pin E LS 32 and SHA IN pin, then the extra settling time introduced by this U P circuitry must be taken into account. In the case where the NAL 24 TA = –40°C multiplexer change command and the conversion start R TE 16 command are separated, they need to be separated by greater N I than the acquisition time of the AD7890 plus the settling time 80 01357-009 othf et hCeE XeTx tcearpnaacli tcairnccuei.t Irny aifp tphleic uatsieorn dso wesh enroet thhaev me tuol twipolerxrye ra ibso ut 0 250 500 750 1000 1250 1500 1750 2000 switched and conversion is initiated at the same time (such as CEXT CAPACITANCE (pF) with a software conversion start), the capacitor on C needs to EXT Figure 9. Internal Pulse Width vs. CEXT allow for the acquisition time of the track/hold and the settling time of the external circuitry before conversion is initiated. Rev. C | Page 16 of 28

AD7890 SERIAL INTERFACE framing signal used for the transfer of data from the AD7890. The AD7890’s serial communications port provides a flexible This self-clocking mode can be used with processors that allow arrangement to allow easy interfacing to industry-standard an external device to clock their serial port, including most microprocessors, microcontrollers, and digital signal processors. digital signal processors. A serial read to the AD7890 accesses data from the output register via the DATA OUT line. A serial write to the AD7890 Read Operation writes data to the control register via the DATA IN line. Figure 10 shows a timing diagram for reading from the AD7890 Two different modes of operation are available, optimized for in the self-clocking mode. At the end of conversion, RFS goes different types of interface where the AD7890 can act either as low and the serial clock (SCLK) and serial data (DATA OUT) master in the system (it provides the serial clock and data outputs become active. Sixteen bits of data are transmitted with framing signal) or acts as slave (an external serial clock and one leading zero, followed by the three address bits of the framing signal can be provided to the AD7890). The former is control register, followed by the 12-bit conversion result starting self-clocking mode while the latter is external clocking mode. with the MSB. Serial data is clocked out of the device on the SELF-CLOCKING MODE rising edge of SCLK and is valid on the falling edge of SCLK. The RFS output remains low for the duration of the 16 clock The AD7890 is configured for its self-clocking mode by tying the SMODE pin of the device to a logic low. In this mode, the cycles. On the 16th rising edge of SCLK, the RFS output is driven AD7890 provides the serial clock signal and the serial data high and DATA OUT is disabled. RFS (O) t 6 t 1 t 3 SCLK (O) t 4 t2 t5 t7 DATA OUT (O)THREE-STATE LEZAEDRIONG A2 A1 A0 DB11 DB10 DB0 THREE-STATE 01357-010 NOTES: 1. (I) SIGNIFIES AN INPUT. 2. (O) SIGNIFIES AN OUTPUT. PULL-UP RESISTOR ON SCLK. Figure 10. Self-Clocking (Master) Mode Output Register Read TFS (I) t8 t t12 3 SCLK (O) t 9 t11 t4 t 10 DATA IN (I) A2 A1 A0 CONV STBY DCOANR’ET DCOANR’ET DCOANR’ET NOTES: 01357-011 1. (I) SIGNIFIES AN INPUT. 2. (O) SIGNIFIES AN OUTPUT. PULL-UP RESISTOR ON SCLK. Figure 11. Self-Clocking (Master) Mode Control Register Write Rev. C | Page 17 of 28

AD7890 Write Operation However, RFS must remain low for the duration of the data transfer operation. Once again, 16th bits of data are transmitted Figure 11 shows a write operation to the control register of the with one leading zero, followed by the three address bits in the AD7890. The TFS input is taken low to indicate to the part that control register, followed by the 12-bit conversion result starting a serial write is about to occur. TFS going low initiates the SCLK with the MSB. If RFS goes low during the high time of SCLK, output and this is used to clock data out of the processors serial the leading zero is clocked out from the falling edge of RFS (as port and into the control register of the AD7890. The AD7890 control register requires only five bits of data. These are loaded per Figure 12). If RFS goes low during the low time of SCLK, on the first five clock cycles of the serial clock with data on all the leading zero is clocked out on the next rising edge of SCLK. subsequent clock cycles being ignored. However, the part This ensures that, regardless of whether RFS goes low during a requires six serial clock cycles to load data to the control high time or low time of SCLK, the leading zero is valid on the register. Serial data to be written to the AD7890 must be valid first falling edge of SCLK after RFS goes low, provided t14 and t17 on the falling edge of SCLK. are adhered to. Serial data is clocked out of the device on the rising edge of SCLK and is valid on the falling edge of SCLK. At EXTERNAL CLOCKING MODE the end of the read operation, the DATA OUT line is three-stated The AD7890 is configured for its external clocking mode by by a rising edge on either the SCLK or RFS inputs, whichever tying the SMODE pin of the device to a logic high. In this occurs first. If a serial read from the output register is in progress mode, SCLK and RFS of the AD7890 are configured as inputs. when conversion is complete, the updating of the output register is This external-clocking mode is designed for direct interface to deferred until the serial data read is complete and RFS returns high. systems, which provide a serial clock output which is Write Operation synchronized to the serial data output including microcontrollers such as the 80C51, 87C51, 68HC11, and Figure 13 shows a write operation to the control register of the 68HC05, and most digital signal processors. AD7890. As with self-clocking mode, the TFS input goes low to indicate to the part that a serial write is about to occur. As before, Read Operation the AD7890 control register requires only five bits of data. These Figure 12 shows the timing diagram for reading from the are loaded on the first five clock cycles of the serial clock; data on all AD7890 in the external clocking mode. RFS goes low to access subsequent clock cycles are ignored. However, the part requires six data from the AD7890. The serial clock input does not have to be serial clocks to load data to the control register. Serial data to be continuous. The serial data can be accessed in a number of bytes. written to the AD7890 must be valid on the falling edge of SCLK. RFS (I) t 18 t13 t15 SCLK (I) t16 t t19 t 17 14 t 19A LEADING THREE-STATE DATA OUT (O) ZERO A2 A1 A0 DB11 DB10 DB0 NOTES: 01357-012 1. (I) SIGNIFIES AN INPUT. 2. (O) SIGNIFIES AN OUTPUT. Figure 12. External Clocking (Slave) Mode Output Register Read TFS (I) t t 20 23 SCLK (I) t 22 t 21 DATA IN (I) A2 A1 A0 CONV STBY DCOANR’ET DCOANR’ET DCOANR’ET NOTES: 01357-013 1. (I) SIGNIFIES AN INPUT. 2. (O) SIGNIFIES AN OUTPUT. PULL-UP RESISTOR ON SCLK. Figure 13. External Clocking (Slave) Mode Control Register Write Rev. C | Page 18 of 28

AD7890 SIMPLIFYING THE INTERFACE To minimize the number of interconnect lines to the AD7890, Care must be taken with this scheme that the read operation is the user can connect the RFS and TFS lines of the AD7890 completed before the next conversion starts, if the user wants to together and read and write from the part simultaneously. In obtain optimum performance from the part. In the case of the this case, new control register data should be provided on the software conversion start, the conversion command is written DATA IN line selecting the input channel and possibly to the control register on the sixth serial clock edge. However, providing a conversion start command while the part provides the read operation continues for another 10 serial clock cycles. the result from the conversion just completed on the To avoid reading during the sampling instant or during DATA OUT line. conversion, the user should ensure that the internal pulse width is sufficiently long (by choosing C ) so that the read operation EXT In the self-clocking mode, this means that the part provides all is completed before the next conversion sequence begins. the signals for the serial interface. It does require that the Failure to do this results in significantly degraded performance microprocessor has the data to be written to the control register from the part, both in terms of signal-to-noise ratio and dc available in its output register when the part brings the TFS line parameters. In the case of a hardware conversion start, the user low. In the external clocking mode, it means that the user only should ensure that the delay between the sixth falling edge of has to supply a single frame synchronization signal to control the serial clock in the write operation and the next rising edge both the read and write operations. of CONVST is greater than the internal pulse width. Rev. C | Page 19 of 28

AD7890 MICROPROCESSOR/MICROCONTROLLER INTERFACE The AD7890’s flexible serial interface allows for easy VDD connection to the serial ports of DSP processors and SMODE microcontrollers. Figure 14 through Figure 17 show the AD7890 interfaced to a number of different microcontrollers P1.0 RFS and DSP processors. In some of the interfaces shown, the P1.1 TFS 8xC51 AD7890 AD7890 is configured as the master in the system, providing DATA OUT the serial clock and frame sync for the read operation while in P3.0 DATA IN others it acts as a slave with these signals provided by the mADicr7o8p9ro0c eTssOor 8. 051 INTERFACE P3.1 SCLK 01357-014 Figure 14. AD7890 to 8xC51 Interface Figure 14 shows an interface between the AD7890 and the AD7890 TO 68HC11 INTERFACE 8xC51 microcontroller. The AD7890 is configured for its external clocking mode while the 8xC51 is configured for its An interface circuit between the AD7890 and the 68HC11 Mode 0 serial interface mode. The diagram shown in Figure 14 microcontroller is shown in Figure 15. For the interface shown, makes no provisions for monitoring when conversion is the AD7890 is configured for its external clocking mode while complete on the AD7890 (assuming hardware conversion start the 68HC11’s SPI port is used and the 68HC11 is configured in is used). To monitor the conversion time on the AD7890, a its single-chip mode. The 68HC11 is configured in the master scheme, such as the scheme outlined with CONVST in the mode with its CPOL bit set to a Logic 0 and its CPHA bit set to Simplifying the Interface section, can be used. This can be a Logic 1. implemented in two ways. One is to connect the CONVST line As with the previous interface, there are no provisions for to another parallel port bit, which is configured as an input. monitoring when conversion is complete on the AD7890. To This port bit can then be polled to determine when conversion is monitor the conversion time on the AD7890, a scheme, such as complete. An alternative is to use an interrupt driven system where the scheme outlined with CONVST in the Simplifying the the CONVST line is connected to the INT1 input of the 8xC51. Interface section, can be used. This can be implemented in two Since the 8xC51 contains only one serial data line, the DATA ways. One is to connect the CONVST line to another parallel OUT and DATA IN lines of the AD7890 must be connected port bit, which is configured as an input. This port bit can then together. This means that the 8xC51 cannot communicate with be polled to determine when conversion is complete. An alternative the output register and control register of the AD7890 at the is to use an interrupt driven system in which case the CONVST same time. The 8xC51 outputs the LSB first in a write operation line should be connected to the IRQ input of the 68HC11. so care should be taken in arranging the data, which is to be DVDD DVDD transmitted to the AD7890. Similarly, the AD7890 outputs the MSB first during a read operation while the 8xC51 expects the SS SMODE LSB first. Therefore, the data that is to be read into the serial port needs to be rearranged before the correct data word from PC0 RFS the AD7890 is available in the microcontroller. PC1 TFS 68HC11 AD7890 The serial clock rate from the 8xC51 is limited to significantly SCK SCLK less than the allowable input serial clock frequency with which MISO DATA OUT the AD7890 can operate. As a result, the time to read data from tThhei sp maret aisn as ctthuaatl tlyh elo AnDge7r8 t9h0a nca tnhneo cto rnuvne rasti oitns mtimaxei mofu tmhe part. MOSI DATA IN 01357-015 Figure 15. AD7890 to 68HC11 Interface throughput rate when used with the 8xC51. Rev. C | Page 20 of 28

AD7890 The serial clock rate from the 68HC11 is limited to significantly AD7890 TO DSP56000 INTERFACE less than the allowable input serial clock frequency with which Figure 17 shows an interface circuit between the AD7890 and the AD7890 can operate. As a result, the time to read data from the DSP56000 DSP processor. The AD7890 is configured for its the part is actually longer than the conversion time of the part. external clocking mode. The DSP56000 is configured for This means that the AD7890 cannot run at its maximum normal mode, synchronous operation with continuous clock. It throughput rate when used with the 68HC11. is also set up for a 16-bit word with SCK and SC2 as outputs. The FSL bit of the DSP56000 should be set to 0. AD7890 TO ADSP-2101 INTERFACE An interface circuit between the AD7890 and the ADSP-2101 The RFS and TFS inputs of the AD7890 are connected together DSP processor is shown in Figure 16. The AD7890 is so data is transmitted to and from the AD7890 at the same time. configured for its external clocking mode with the ADSP-2101 With the DSP56000 in synchronous mode, it provides a providing the serial clock and frame synchronization signals. common frame synchronization pulse for read and write The RFS1 and TFS1 inputs and outputs are configured for operations on its SC2 output. This is inverted before being active low operation. applied to the RFS and TFS inputs of the AD7890. DVDD To monitor the conversion time on the AD7890, a scheme, such as the scheme outlined with CONVST in the Simplifying the SMODE Interface section, can be used. This can be implemented by RFS1 RFS connecting the CONVST line directly to the IRQA input of the TFS1 TFS DSP56000. ADSP-2101 AD7890 SCLK1 SCLK DVDD DR1 DATA OUT SMODE DT1 DATA IN 01357-016 SC2 RFS Figure 16. AD7890 to ADSP-2101 Interface TFS DSP56000 AD7890 In the scheme shown, the maximum serial clock frequency the SCK SCLK ADSP-2101 can provide is 6.25 MHz. This allows the AD7890 SRD DATA OUT to be operated at a sample rate of 111 kHz. If it is desirable to o11p7e rkaHtez t,h aen A eDxt7e8rn9a0l aste irtisa lm caloxcimk oufm 1 0th MroHugz hcpaunt b rea tper oofv ided STD DATA IN 01357-017 Figure 17. AD7890 to DSP56000 Interface to drive the serial clock input of both the AD7890 and the ADSP-2101. AD7890 TO TMS320C25/30 INTERFACE Figure 18 shows an interface circuit between the AD7890 and To monitor the conversion time on the AD7890, a scheme, such the TMS320C25/30 DSP processor. The AD7890 is configured as the scheme outlined with CONVST in the Simplifying the for its self-clocking mode where it provides the serial clock and Interface section, can be used. This can be implemented by frame synchronization signals. However, the TMS320C25/30 connecting the CONVST line directly to the IRQ2 input of the requires a continuous serial clock. In the scheme outlined here, ADSP-2101. An alternative to this, where the user does not have the AD7890’s master clock signal, CLK IN, is used to provide to worry about monitoring the conversion status, is to operate the serial clock for the processor. The AD7890 output SCLK, to the AD7890 in its self-clocking mode. In this scheme, the actual which the serial data is referenced, is a delayed version of the interface connections would remain the same as in Figure 16, CLK IN signal. The typical delay between the CLK IN and but now the AD7890 provides the serial clock and receive frame SCLK is 20 ns and is no more than 50 ns over supplies and synchronization signals. Using the AD7890 in its self-clocking temperature. Therefore, there is still sufficient setup time for mode limits the throughput rate of the system as the serial clock DATA OUT to be clocked into the DSP on the edges of the rate is limited to 2.5 MHz. CLK IN signal. When writing data to the AD7890, the processor’s data hold time is sufficiently long to cater for the delay between the two clocks. The AD7890’s RFS signal connects to both the FSX and FSR inputs of the processor. The processor can generate its own FSX signal, so if required, the interface can be modified so that the RFS and TFS signals are separated and the processor generates the FSX signal which is connected to the TFS input of the AD7890. Rev. C | Page 21 of 28

AD7890 In the scheme outlined here, the user does not have to worry ANTIALIASING FILTER about monitoring the end of conversion. Once conversion is The AD7890 provides separate access to the multiplexer and complete, the AD7890 takes care of transmitting back its ADC via the MUX OUT pin and the SHA IN pin. One of the conversion result to the processor. Once the 16 bits of data have reasons for this is to allow the user to implement an antialiasing been received by the processor into its serial shift register, it filter between the multiplexer and the ADC. Inserting the generates an internal interrupt. Since the RFS pin and the TFS antialiasing filter at this point has the advantage that one pin are connected together, data is transmitted to the control antialiasing filter can suffice for all eight channels rather than a register of the AD7890 whenever the AD7890 transmits its separate antialiasing filter for each channel if they were to be conversion result. The user just has to ensure that the word to placed prior to the multiplexer. be written to the AD7890 control register is set up prior to the end of conversion. As part of the interrupt routine, which The antialiasing filter inserted between the MUX OUT pin and recognizes that data has been read in, the processor can set up the SHA IN pin is generally a low-pass filter to remove high the data it is going to write to the control register next time around. frequency signals which could possibly be aliased back in-band during the sampling process. It is recommended that this filter CLK INPUT is an active filter, ideally with the MUX OUT pin of the AD7890 driving a high impedance stage and the SHA IN pin of the part CLK IN being driven from a low impedance stage. This removes any TMS320C25/C30 SMODE effects from the variation of the part’s multiplexer on-resistance FSR RFS with input signal voltage, and removes any effects of a high FSX TFS source impedance at the sampling input of the track/hold. With CLKX AD7890 an external antialiasing filter in place, the additional settling SCLK time associated with the filter should be accounted for by using CLKR a larger capacitance on C . DR DATA OUT EXT DX DATA IN 01357-018 Figure 18. AD7890 to TMS320C25/30 Interface Rev. C | Page 22 of 28

AD7890 PERFORMANCE LINEARITY are achieved with a serial clock rate of 2.5 MHz. If a higher serial clock rate is used, the code transition noise degrades from The linearity of the AD7890 is primarily determined by the on- that shown in the plot in Figure 20. This has the effect of chip 12-bit D/A converter. This is a segmented DAC that is laser injecting noise onto the die while bit decisions are being made, trimmed for 12-bit integral linearity and differential linearity. increasing the noise generated by the AD7890. The histogram Typical relative numbers for the part are ±1/4 LSB while the plot for 8192 conversions of the same dc input now shows a typical DNL errors are ±1/2 LSB. larger spread of codes with the rms noise for the AD7890-2 NOISE increasing to 170 μV. This effect varies depending on where the serial clock edges appear with respect to the bit trials of the In an ADC, noise exhibits itself as code uncertainty in dc conversion process. applications and as the noise floor (in an FFT, for example) in ac applications. In a sampling ADC like the AD7890, all information It is possible to achieve the same level of performance when about the analog input appears in the baseband from dc to 1/2 the reading during conversion as when reading after conversion, sampling frequency. The input bandwidth of the track/hold exceeds depending on the relationship of the serial clock edges to the bit the Nyquist bandwidth and, therefore, an antialiasing filter should trial points (for example, the relationship of the serial clock be used to remove unwanted signals above fS/2 in the input signal edges to the CLK IN edges). The bit decision points on the in applications where such signals exist. AD7890 are on the falling edges of the master clock (CLK IN) during the conversion process. Clocking out new data bits at Figure 19 shows a histogram plot for 8192 conversions of a dc these points (for example, the rising edge of SCLK) is the most input using the AD7890. The analog input was set at the center critical from a noise standpoint. The most critical bit decisions of a code transition. The timing and control sequence used was are the MSBs, so to achieve the level of performance outlined in as per Figure 7 where the optimum performance of the ADC is Figure 20, reading within 1 μs after the rising edge of CONVST achieved. The same performance can be achieved in self- should be avoided. clocking mode where the part transmits its data after conversion is complete. Almost all of the codes appear in the 8000 one output bin indicating very good noise performance from SAMPLING 7000 FREQUENCY = 102.4kHz the ADC. The rms noise performance for the AD7890-2 for the TA = 25°C plot in Figure 19 was 81 μV. Since the analog input range, and E 6000 D O hence LSB size, on the AD7893-4 is 1.638 times what it is for C F 5000 the AD7893-2, the same output code distribution results in an S O output rms noise of 143 μV for the AD7893-4. For the AD7890-10, CE 4000 N E with an LSB size eight times that of the AD7890-2, the code R R 3000 U distribution represents an output rms noise of 648 μV. C C O 2000 9000 87000000 STAA M= P2L5°INCG FREQUENCY = 102.4kHz 10000 01357-020 E (X–4) (X–3) (X–2) (X–1) X (X+1) (X+2) (X+3) (X+4) COD 6000 CODE F Figure 20. Histogram of 8192 Conversions with Read During Conversion O S 5000 E C Writing data to the control register also has the effect of N 4000 E R introducing digital activity onto the part while conversion is in R U 3000 C progress. However, since there are no output drivers active C O 2000 during a write operation, the amount of current flowing on the die is less than for a read operation. Therefore, the amount of 10000 01357-019 noise injected into the die is less than for a read operation. (X–4) (X–3) (X–2) (X–1) X (X+1) (X+2) (X+3) (X+4) Figure 21 shows the effect of a write operation during CODE conversion. The histogram plot for 8192 conversions of the Figure 19. Histogram of 8192 Conversions of a DC Input same dc input now shows a larger spread of codes than for ideal conditions but smaller than for a read operation. The resulting In the external clocking mode, it is possible to write data to the rms noise for the AD7890-2 is 110 μV. In this case, the serial control register or read data from the output register while a clock frequency is 10 MHz. conversion is in progress. The same data is presented in Figure 20 as in Figure 19, except that in Figure 20, the output data read for the device occurs during conversion. These results Rev. C | Page 23 of 28

AD7890 8000 0 SAMPLE RATE = 102.4kHz SAMPLING INPUT FREQUENCY = 10kHz 7000 FREQUENCY = 102.4kHz SNR = 71.5dB TA = 25°C TA = 25°C F CODE 65000000 DE (dB) 30 O U NCES 4000 MPLIT 60 E A RR 3000 AL U N C G 90 OC 2000 SI 10000 01357-021 120 01357-022 (X–4) (X–3) (X–2) (X–1) X (X+1) (X+2) (X+3) (X+4) 0 25.6 51.2 CODE FREQUENCY (kHz) Figure 21. Histogram of 8192 Conversions with Write During Conversion Figure 22. AD7890 FFT Plot DYNAMIC PERFORMANCE EFFECTIVE NUMBER OF BITS The AD7890 contains an on-chip track/hold, allowing the part The formula for signal to (noise + distortion) ratio (see the to sample input signals up to 50 kHz on any of its input Terminology section) is related to the resolution or number of channels. Many AD7890 applications simply require it to bits in the converter. Rewriting the formula provides a measure sequence through low frequency input signals across its eight of performance expressed in effective number of bits (N): channels. There may be some applications, however, for which N = (SNR — 1.76)/6.02 the dynamic performance of the converter out to 40 kHz input frequency is of interest. For these wider band sampling where SNR is signal to (noise + distortion) ratio. applications, it is recommended that the hardware conversion The effective number of bits for a device can be calculated from start method is used. its measured signal to (noise + distortion) ratio. Figure 23 These applications require information on the ADC’s effect on shows a typical plot of effective number of bits versus frequency the spectral content of the input signal. Signal to (noise + for the AD7890-2 from dc to 40 kHz. The sampling frequency is distortion), total harmonic distortion, peak harmonic or 102.4 kHz. The plot shows that the AD7890 converts an input spurious and intermodulation distortion are all specified. sine wave of 40 kHz to an effective numbers of bits of 11 which Figure 22 shows a typical FFT plot of a 10 kHz, 0 V to 2.5 V equates to a signal to (noise + distortion) level of 68 dB. input after being digitized by the AD7890-2 operating at a 12.0 102.4 kHz sampling rate. The signal to (noise + distortion) is 71.5 dB and the total harmonic distortion is −85 dB. Note that reading data from the part during conversion at 10 MHz serial TS 11.5 BI clock does have a significant impact on dynamic performance. F O For sampling applications, it is therefore recommended not to R E B read data during conversion. UM 11.0 N E V TI C E F 10.5 F E 10.0 01357-023 0 20 40 INPUT FREQUENCY (kHz) Figure 23. Effective Number of Bits vs. Frequency Rev. C | Page 24 of 28

AD7890 OUTLINE DIMENSIONS 1.280 (32.51) 1.250 (31.75) 1.230 (31.24) 24 13 0.280 (7.11) 0.250 (6.35) 1 12 0.240 (6.10) 0.325 (8.26) 0.310 (7.87) 0.100 (2.54) 0.300 (7.62) BSC 0.060 (1.52) 0.195 (4.95) 0.210 (5.33) MAX 0.130 (3.30) MAX 0.115 (2.92) 0.015 0.150 (3.81) (0.38) 0.015 (0.38) 0.130 (3.30) MIN GAUGE 0.115 (2.92) SEATING PLANE 00..001140 ((00..3265)) PLANE 0.022 (0.56) 0.008 (0.20) 0.005 (0.13) 0.430 (10.92) 0.018 (0.46) MIN MAX 0.014 (0.36) 0.070 (1.78) 0.060 (1.52) 0.045 (1.14) COMPLIANTTO JEDEC STANDARDS MS-001 CONTROLLING DIMENSIONSARE IN INCHES; MILLIMETER DIMENSIONS (RCINOEFRPEANRREEREN NLCTEEHA EODSNSEL MSY)AAAYNR BDEE AR CROOEU NNNFODIGETUDAR-POEPFDRFOA INSPC RWHIAH ETOEQL UFEIO VORAR LU EHSNAETL ISFN FLDOEEARSDIGSN.. 071006-A Figure 24. 24-Lead Plastic Dual In-Line Package [PDIP] Narrow Body (N-24-1) Dimensions shown in inches and (millimeters) 0.005 (0.13) 0.098 (2.49) MIN MAX 0.310 (7.87) 24 13 0.220 (5.59) 1 12 PIN 1 0.060 (1.52) 0.200 (5.08) 1.280 (32.51) MAX 0.015 (0.38) 0.320 (8.13) MAX 0.290 (7.37) 0.150 (3.81) MIN 0.015 (0.38) 0.200 (5.08) 15° 0.008 (0.20) 0.125 (3.18) 0.100 0.070 (1.78) SEATING 0° 0.023 (0.58) (B2.S5C4) 0.030 (0.76) PLANE 0.014 (0.36) CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. Figure 25. 24-Lead Ceramic Dual In-Line Package [CERDIP] (Q-24) Dimensions shown in inches and (millimeters) Rev. C | Page 25 of 28

AD7890 15.60 (0.6142) 15.20 (0.5984) 24 13 7.60 (0.2992) 7.40 (0.2913) 1 10.65 (0.4193) 12 10.00 (0.3937) 0.75 (0.0295) 45° 2.65 (0.1043) 0.25 (0.0098) 0.30 (0.0118) 2.35 (0.0925) 8° 0.10 (0.0039) 0° COPLANARITY 0.10 1.27 B(0S.C0500) 00..5311 ((00..00210212)) SPELAATNIENG 00..3230 ((00..00103709)) 10..2470 ((00..00510507)) COMPLIANTTO JEDEC STANDARDS MS-013-AD C(RINOEFNPEATRRREOENNLCLTEIHN EOGSN EDLSIYM)AEANNRDSEI AORRNOESU NANORDEET DAIN-PO MPFRIFLO LMPIIMRLELIATIMTEEER TFSEO; RIRN ECUQHSU EDI VIINMA LEDENENSSTIIOGSN NFS.OR 060706-A Figure 26. 24-Lead Standard Small Outline Package [SOIC_W] Wide Body (RW-24) Dimensions shown in millimeters and( inches) Rev. C | Page 26 of 28

AD7890 ORDERING GUIDE Model Temperature Range Package Description Linearity Error Package Option AD7890AN-2 −40°C to +85°C 24-Lead PDIP ±1 LSB N-24-1 AD7890ANZ-21 −40°C to +85°C 24-Lead PDIP ±1 LSB N-24-1 AD7890BN-2 −40°C to +85°C 24-Lead PDIP ±1/2 LSB N-24-1 AD7890BNZ-21 −40°C to +85°C 24-Lead PDIP ±1/2 LSB N-24-1 AD7890AR-2 −40°C to +85°C 24-Lead SOIC_W ±1 LSB RW-24 AD7890AR-2REEL −40°C to +85°C 24-Lead SOIC_W ±1 LSB RW-24 AD7890ARZ-21 −40°C to +85°C 24-Lead SOIC_W ±1 LSB RW-24 AD7890ARZ-2REEL1 −40°C to +85°C 24-Lead SOIC_W ±1 LSB RW-24 AD7890BR-2 −40°C to +85°C 24-Lead SOIC_W ±1/2 LSB RW-24 AD7890BR-2REEL −40°C to +85°C 24-Lead SOIC_W ±1/2 LSB RW-24 AD7890BRZ-21 −40°C to +85°C 24-Lead SOIC_W ±1/2 LSB RW-24 AD7890BRZ-2REEL1 −40°C to +85°C 24-Lead SOIC_W ±1/2 LSB RW-24 AD7890SQ-2 −55°C to +125°C 24-Lead CERDIP ±1 LSB Q-24 AD7890AN-4 −40°C to +85°C 24-Lead PDIP ±1 LSB N-24 AD7890ANZ-41 −40°C to +85°C 24-Lead PDIP ±1 LSB N-24 AD7890BN-4 −40°C to +85°C 24-Lead PDIP ±1/2 LSB N-24 AD7890BNZ-41 −40°C to +85°C 24-Lead PDIP ±1/2 LSB N-24 AD7890AR-4 −40°C to +85°C 24-Lead SOIC_W ±1 LSB RW-24 AD7890AR-4REEL −40°C to +85°C 24-Lead SOIC_W ±1 LSB RW-24 AD7890ARZ-41 −40°C to +85°C 24-Lead SOIC_W ±1 LSB RW-24 AD7890ARZ-4REEL1 −40°C to +85°C 24-Lead SOIC_W ±1 LSB RW-24 AD7890BR-4 −40°C to +85°C 24-Lead SOIC_W ±1/2 LSB RW-24 AD7890BR-4REEL −40°C to +85°C 24-Lead SOIC_W ±1/2 LSB RW-24 AD7890BRZ-41 −40°C to +85°C 24-Lead SOIC_W ±1/2 LSB RW-24 AD7890BRZ-4REEL1 −40°C to +85°C 24-Lead SOIC_W ±1/2 LSB RW-24 AD7890SQ-4 −55°C to +125°C 24-Lead CERDIP ±1 LSB Q-24 AD7890AN-10 −40°C to +85°C 24-Lead PDIP ±1 LSB N-24-1 AD7890ANZ-101 −40°C to +85°C 24-Lead PDIP ±1 LSB N-24-1 AD7890BN-10 −40°C to +85°C 24-Lead PDIP ±1/2 LSB N-24-1 AD7890BNZ-101 −40°C to +85°C 24-Lead PDIP ±1/2 LSB N-24-1 AD7890AR-10 −40°C to +85°C 24-Lead SOIC_W ±1 LSB RW-24 AD7890AR-10REEL −40°C to +85°C 24-Lead SOIC_W ±1 LSB RW-24 AD7890ARZ-101 −40°C to +85°C 24-Lead SOIC_W ±1 LSB RW-24 AD7890ARZ-10REEL1 −40°C to +85°C 24-Lead SOIC_W ±1 LSB RW-24 AD7890BR-10 −40°C to +85°C 24-Lead SOIC_W ±1/2 LSB RW-24 AD7890BR-10REEL −40°C to +85°C 24-Lead SOIC_W ±1/2 LSB RW-24 AD7890BRZ-101 −40°C to +85°C 24-Lead SOIC_W ±1/2 LSB RW-24 AD7890BRZ-10REEL1 −40°C to +85°C 24-Lead SOIC_W ±1/2 LSB RW-24 AD7890SQ-10 −55°C to +125°C 24-Lead CERDIP ±1 LSB Q-24 1 Z = Pb-free part. Rev. C | Page 27 of 28

AD7890 NOTES ©2006 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. C01357-0-9/06(C) Rev. C | Page 28 of 28