a LC2MOS 4-Channel, 12-Bit Simultaneous Sampling Data Acquisition System AD7874 FEATURES FUNCTIONAL BLOCK DIAGRAM Four On-Chip Track/Hold Amplifiers Simultaneous Sampling of 4 Channels Fast 12-Bit ADC with 8 (cid:109)s Conversion Time/Channel INT CS RD CONVST VDDVDD 29 kHz Sample Rate for All Four Channels On-Chip Reference CONTROL LOGIC INTERNAL CLK CLOCK (cid:54)10 V Input Range V TRACK/ IN1 HOLD 1 (cid:54)5 V Supplies APPLICATIONS VIN2 THROALCDK 2/ COMP Sonar MUX SAR Motor Controllers VIN3 THROALCDK 3/ Adaptive Filters DATA DB0 REGISTERS Digital Signal Processing VIN4 THROALCDK 4/ DB11 REFERENCE BUFFER 12-BIT DAC REF IN AD7874 GENERAL DESCRIPTION The AD7874 is a four-channel simultaneous sampling, 12-bit 3V REF OUT data acquisition system. The part contains a high speed 12-bit REFERENCE ADC, on-chip reference, on-chip clock and four track/hold am- AGND DGND V SS plifiers. This latter feature allows the four input channels to be sampled simultaneously, thus preserving the relative phase PRODUCT HIGHLIGHTS information of the four input channels, which is not possible if 1. Simultaneous Sampling of Four Input Channels. all four channels share a single track/hold amplifier. This makes Four input channels, each with its own track/hold amplifier, the AD7874 ideal for applications such as phased-array sonar allow simultaneous sampling of input signals. Track/hold ac- and ac motor controllers where the relative phase information is quisition time is 2 m s, and the conversion time per channel is important. 8 m s, allowing 29 kHz sample rate for all four channels. The aperture delay of the four track/hold amplifiers is small and 2. Tight Aperture Delay Matching. specified with minimum and maximum limits. This allows sev- The aperture delay for each channel is small and the aperture eral AD7874s to sample multiple input channels simultaneously delay matching between the four channels is less than 4 ns. without incurring phase errors between signals connected to Additionally, the aperture delay specification has upper and several devices. A reference output/reference input facility also lower limits allowing multiple AD7874s to sample more than allows several AD7874s to be driven from the same reference four channels. source. 3. Fast Microprocessor Interface. In addition to the traditional dc accuracy specifications such as The high speed digital interface of the AD7874 allows direct linearity, full-scale and offset errors, the AD7874 is also fully connection to all modern 16-bit microprocessors and digital specified for dynamic performance parameters including distor- signal processors. tion and signal-to-noise ratio. The AD7874 is fabricated in Analog Devices’ Linear Compat- ible CMOS (LC2MOS) process, a mixed technology process that combines precision bipolar circuits with low-power CMOS logic. The part is available in a 28-pin, 0.6" wide, plastic or her- metic dual-in-line package (DIP), in a 28-terminal leadless ce- ramic chip carrier (LCCC) and in a 28-pin SOIC. REV.C Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. otherwise under any patent or patent rights of Analog Devices. Tel: 617/329-4700 Fax: 617/326-8703

AD7874–SPECIFICATIONS (V = +5 V, V = –5 V, AGND = DGND = 0 V, REF IN = +3 V, f = 2.5 MHz DD SS CLK external. All specifications T to T unless otherwise noted.) MIN MAX Parameter A Version B Version S Version Units Test Conditions/Comments SAMPLE-AND-HOLD Acquisition Time2 to 0.01% 2 2 2 m s max Droop Rate2, 3 1 1 2 mV/ms max –3 dB Small Signal Bandwidth3 500 500 500 kHz typ V = 500 mV p-p IN Aperture Delay2 0 0 0 ns min 40 40 40 ns max Aperture Jitter2, 3 200 200 200 ps typ Aperture Delay Matching2 4 4 4 ns max SAMPLE-AND-HOLD AND ADC DYNAMIC PERFORMANCE Signal-to-Noise Ratio 70 71 70 dB min f = 10 kHz Sine Wave, f = 29 kHz IN SAMPLE Total Harmonic Distortion –78 –80 –78 dB max f = 10 kHz Sine Wave, f = 29 kHz IN SAMPLE Peak Harmonic or Spurious Noise –78 –80 –78 dB max f = 10 kHz Sine Wave, f = 29 kHz IN SAMPLE Intermodulation Distortion fa = 9 kHz, fb = 9.5 kHz, f = 29 kHz SAMPLE 2nd Order Terms –80 –80 –80 dB max 3rd Order Terms –80 –80 –80 dB max Channel-to-Channel Isolation2 –80 –80 –80 dB max DC ACCURACY Resolution 12 12 12 Bits Relative Accuracy – 1 – 1/2 – 1 LSB max Differential Nonlinearity – 1 – 1 – 1 LSB max No Missing Codes Guaranteed Positive Full-Scale Error4 – 5 – 5 – 5 LSB max Any Channel Negative Full-Scale Error4 – 5 – 5 – 5 LSB max Any Channel Full-Scale Error Match 5 5 5 LSB max Between Channels Bipolar Zero Error – 5 – 5 – 5 LSB max Any Channel Bipolar Zero Error Match 4 4 4 LSB max Between Channels ANALOG INPUTS Input Voltage Range – 10 – 10 – 10 Volts Input Current – 600 – 600 – 600 m A max REFERENCE OUTPUTS REF OUT 3 3 3 V nom REF OUT Error @ +25(cid:176) C – 0.33 – 0.33 – 0.33 % max T to T – 1 – 1 – 1 % max MIN MAX REF OUT Temperature Coefficient – 35 – 35 – 35 ppm/(cid:176) C typ Reference Load Change – 1 – 1 – 2 mV max Reference Load Current Change (0–500 m A) Reference Load Should Not Be Changed During Conversion REFERENCE INPUT Input Voltage Range 2.85/3.15 2.85/3.15 2.85/3.15 V min/V max 3 V – 5% Input Current – 1 – 1 – 1 m A max Input Capacitance3 10 10 10 pF max LOGIC INPUTS Input High Voltage, V 2.4 2.4 2.4 V min V = 5 V – 5% INH DD Input Low Voltage, V 0.8 0.8 0.8 V max V = 5 V – 5% INL DD Input Current, I – 10 – 10 – 10 m A max V = 0 V to V IN IN DD Input Capacitance, C 3 10 10 10 pF max IN LOGIC OUTPUTS Output High Voltage, V 4.0 4.0 4.0 V min V = 5 V – 5%; I = 40 m A OH DD SOURCE Output Low Voltage, V 0.4 0.4 0.4 V max V = 5 V – 5%; I = 1–6 mA OL DD SINK DB0–DB11 Floating-State Leakage Current – 10 – 10 – 10 m A max V = 0 V to V IN DD Floating-State Output Capacitance 10 10 10 pF max Output Coding 2s COMPLEMENT POWER REQUIREMENTS V +5 +5 +5 V nom – 5% for Specified Performance DD V –5 –5 –5 V nom – 5% for Specified Performance SS I 18 18 18 mA max CS = RD = CONVST = +5 V; Typically 12 mA DD I 12 12 12 mA max CS = RD = CONVST = +5 V; Typically 8 mA SS Power Dissipation 150 150 150 mW max CS = RD = CONVST = +5 V; Typically 100 mW NOTES 1Temperature ranges are as follows: A, B Versions: –40(cid:176)C to +85(cid:176)C; S Version: –55(cid:176)C to +125(cid:176)C. 2See Terminology. 3Sample tested @ +25(cid:176)C to ensure compliance. 4Measured with respect to the REF IN voltage and includes bipolar offset error. 5For capacitive loads greater than 50 pF a series resistor is required. Specifications subject to change without notice. –2– REV. C

AD7874 (V = +5 V (cid:54) 5%, V = –5 V (cid:54) 5%, AGND = DGND = O V, t = 2.5 MHz external unless TIMING CHARACTERISTICS1 DD SS CLK otherwise noted.) Parameter A, B Versions S Version Units Conditions/Comments t 50 50 ns min CONVST Pulse Width 1 t 0 0 ns min CS to RD Setup Time 2 t 60 70 ns min RD Pulse Width 3 t 0 0 ns min CS to RD Hold Time 4 t 60 60 ns max RD to INT Delay 5 t 2 57 70 ns max Data Access Time after RD 6 t 3 5 5 ns min Bus Relinquish Time after RD 7 45 50 ns max t 130 150 ns min Delay Time between Reads 8 t 31 31 m s min CONVST to INT, External Clock CONV 32.5 32.5 m s max CONVST to INT, External Clock 31 31 m s min CONVST to INT, Internal Clock 35 35 m s max CONVST to INT, Internal Clock t 10 10 m s max Minimum Input Clock Period CLK NOTES 1Timing Specifications in bold print are 100% production tested. All other times are sample tested at +25(cid:176)C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of +5 V) and timed from a voltage level of 1.6 V. 2t is measured with the load circuit of Figure 1 and defined as the time required for an output to cross 0.8 V or 2.4 V. 6 3t is derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 2. The measured number is then extrapolated 7 back to remove the effects of charging or discharging the 50 pF capacitor. This means that the time, t , quoted in the timing characteristics is the true bus relinquish 7 time of the part and as such is independent of external bus loading capacitances. Specifications subject to change without notice. 1.6mA ABSOLUTE MAXIMUM RATINGS* (T = +25(cid:176)C unless otherwise noted) A V to AGND . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V DD VDD to DGND . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V TO OUTPPUINT +2.1V V to AGND . . . . . . . . . . . . . . . . . . . . . . . . . +0.3 V to –7 V 50pF SS AGND to DGND . . . . . . . . . . . . . . . . –0.3 V to V + 0.3 V DD V to AGND . . . . . . . . . . . . . . . . . . . . . . . . .–15 V to +15 V IN REF OUT to AGND . . . . . . . . . . . . . . . . . . . . . . . 0 V to VDD 200m A Digital Inputs to DGND . . . . . . . . . . . –0.3 V to V + 0.3 V DD Digital Outputs to DGND . . . . . . . . . . –0.3 V to V + 0.3 V Figure 1.Load Circuit for Access Time DD Operating Temperature Range Commercial (A, B Versions) . . . . . . . . . . . –40(cid:176) C to +85(cid:176) C 1.6mA Extended (S Version) . . . . . . . . . . . . . . . . –55(cid:176) C to +125(cid:176) C Storage Temperature Range . . . . . . . . . . . . –65(cid:176) C to +150(cid:176) C Lead Temperature (Soldering, 10 secs) . . . . . . . . . . . +300(cid:176) C TO OUTPUT +2.1V PIN Power Dissipation (Any Package) to +75(cid:176) C . . . . . . 1,000 mW 50pF Derates above +75(cid:176) C by . . . . . . . . . . . . . . . . . . . . 10 mW/(cid:176) C 200m A *Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those listed in the Figure 2.Load Circuit for Bus Relinquish Time operational sections of this specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily WARNING! accumulate on the human body and test equipment and can discharge without detection. Although the AD7874 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. ESD SENSITIVE DEVICE REV. C –3–

AD7874 TERMINOLOGY PIN CONFIGURATIONS ACQUISITION TIME Acquisition Time is the time required for the output of the DIP and SOIC track/hold amplifiers to reach their final values, within – 1/2 LSB, after the falling edge of INT (the point at which the track/ holds return to track mode). This includes switch delay time, VIN1 1 28 VIN4 slewing time and settling time for a full-scale voltage change. VIN2 2 27 VIN3 VDD 3 26 VSS APERTURE DELAY INT 4 25 REF OUT Aperture Delay is defined as the time required by the internal CONVST 5 24 REF IN switches to disconnect the hold capacitors from the inputs. This RD 6 23 AGND produces an effective delay in sample timing. It is measured by AD7874 CS 7 22 DB0 (LSB) applying a step input and adjusting the CONVST input position TOP VIEW until the output code follows the step input change. CLK 8 (Not to Scale) 21 DB1 VDD 9 20 DB2 APERTURE DELAY MATCHING DB11 (MSB) 10 19 DB3 Aperture Delay Matching is the maximum deviation in aperture DB10 1111 18 DB4 delays across the four on-chip track/hold amplifiers. DB9 12 17 DB5 DB8 13 16 DB6 APERTURE JITTER DGND 14 15 DB7 Aperture Jitter is the uncertainty in aperture delay caused by internal noise and variation of switching thresholds with signal LCCC level. DROOP RATE INT VDDVIN2 VIN1 VIN4 VIN3VSS Droop Rate is the change in the held analog voltage resulting 4 3 2 1 28 27 26 from leakage currents. CONVST 5 25 REF OUT CHANNEL-TO-CHANNEL ISOLATION RD 6 24 REF IN Channel-to-Channel Isolation is a measure of the level of CS 7 AD7874 23 AGND crosstalk between channels. It is measured by applying a full- CLK 8 TOP VIEW 22 DB0 (LSB) (Not to Scale) scale 1 kHz signal to the other three inputs. The figure given is VDD 9 21 DB1 the worst case across all four channels. DB11 (MSB) 10 20 DB2 DB10 11 19 DB3 SNR, THD, IMD 12 13 14 15 16 17 18 See DYNAMIC SPECIFICATIONS section. 9 8 D 7 6 5 4 B B N B B B B D D G D D D D D –4– REV. C

AD7874 PIN FUNCTION DESCRIPTION Pin Mnemonic Description 1 V Analog Input Channel 1. This is the first of the four input channels to be converted in a con- IN1 version cycle. Analog input voltage range is – 10 V. 2 V Analog Input Channel 2. Analog input voltage range is – 10 V. IN2 3 V Positive supply voltage, +5 V – 5%. This pin should be decoupled to AGND. DD 4 INT Interrupt. Active low logic output indicating converter status. See Figure 7. 5 CONVST Convert Start. Logic Input. A low to high transition on this input puts the track/hold into its hold mode and starts conversion. The four channels are converted sequentially, Channel 1 to Channel 4. The CONVST input is asynchronous to CLK and independent of CS and RD. 6 RD Read. Active low logic input. This input is used in conjunction with CS low to enable the data outputs. Four successive reads after a conversion will read the data from the four chan- nels in the sequence, Channel 1, 2, 3, 4. 7 CS Chip Select. Active low logic input. The device is selected when this input is active. 8 CLK Clock Input. An external TTL-compatible clock may be applied to this input pin. Alterna- tively, tying this pin to V enables the internal laser trimmed clock oscillator. SS 9 V Positive Supply Voltage, +5 V – 5%. Same as Pin 3; both pins must be tied together at the DD package. This pin should be decoupled to DGND. 10 DB11 Data Bit 11 (MSB). Three-state TTL output. Output coding is 2s complement. 11–13 DB10–DB8 Data Bit 10 to Data Bit 8. Three-state TTL outputs. 14 DGND Digital Ground. Ground reference for digital circuitry. 15–21 DB7–DB1 Data Bit 7 to Data Bit 1. Three-state TTL outputs. 22 DB0 Data Bit 0 (LSB). Three-state TTL output. 23 AGND Analog Ground. Ground reference for track/hold, reference and DAC. 24 REF IN Voltage Reference Input. The reference voltage for the part is applied to this pin. It is inter- nally buffered, requiring an input current of only – 1 m A. The nominal reference voltage for correct operation of the AD7874 is 3 V. 25 REF OUT Voltage Reference Output. The internal 3 V analog reference is provided at this pin. To oper- ate the AD7874 with internal reference, REF OUT is connected to REF IN. The external load capability of the reference is 500 m A. 26 V Negative Supply Voltage, –5 V – 5%. SS 27 V Analog Input Channel 3. Analog input voltage range is – 10 V. IN3 28 V Analog Input Channel 4. Analog input voltage range is – 10 V. IN4 ORDERING GUIDE Relative Temperature SNR Accuracy Package Model1 Range (dBs) (LSB) Option2 AD7874AN –40(cid:176) C to +85(cid:176) C 70 min – 1 max N-28 AD7874BN –40(cid:176) C to +85(cid:176) C 72 min – 1/2 max N-28 AD7874AR –40(cid:176) C to +85(cid:176) C 70 min – 1 max R-28 AD7874BR –40(cid:176) C to +85(cid:176) C 72 min – 1/2 max R-28 AD7874AQ –40(cid:176) C to +85(cid:176) C 70 min – 1 max Q-28 AD7874BQ –40(cid:176) C to +85(cid:176) C 72 min – 1/2 max Q-28 AD7874SQ3 –55(cid:176) C to +125(cid:176) C 70 min – 1 max Q-28 AD7874SE3 –55(cid:176) C to +125(cid:176) C 70 min – 1 max E-28A NOTES 1To order MIL-STD-883, Class B processed parts, add /883B to part number. Contact 1our local sales office for military data sheet and availability. 2E = Leaded Ceramic Chip Carrier; N = Plastic DIP; Q = Cerdip; R = SOIC. 3Available to /883B processing only. REV. C –5–

AD7874 CONVERTER DETAILS EXTERNAL REFERENCE The AD7874 is a complete 12-bit, 4-channel data acquisition In some applications, the user may require a system reference or system. It is comprised of a 12-bit successive approximation some other external reference to drive the AD7874 reference in- ADC, four high speed track/hold circuits, a four-channel analog put. Figure 4 shows how the AD586 5 V reference can be used multiplexer and a 3 V Zener reference. The ADC uses a succes- to provide the 3 V reference required by the AD7874 REF IN. sive approximation technique and is based on a fast-settling, voltage switching DAC, a high speed comparator, a fast CMOS +15V SAR and high speed logic. +VIN VIN1 7R* TO INTERNAL Conversion is initiated on the rising edge of CONVST. All four GND COMPARATOR input track/holds go from track to hold on this edge. Conversion VOUT TRACK/HOLD 1 AD586 is first performed on the Channel 1 input voltage, then Channel 10kW 2 is converted and so on. The four results are stored in on-chip 2.1R* 3R* REF registers. When all four conversions have been completed, INT IN goes low indicating that data can be read from these locations. 1kW The conversion sequence takes either 78 or 79 rising clock edges TO ADC depending on the synchronization of CONVST with CLK. In- REFERENCE ternal delays and reset times bring the total conversion time 15kW CIRCUITRY from CONVST going high to INT going low to 32.5 m s maxi- AGND mum for a 2.5 MHz external clock. The AD7874 uses an im- AD7874** plicit addressing scheme whereby four successive reads to the same memory location access the four data words sequentially. *R = 3.6kW TYP The first read accesses Channel 1 data, the second read accesses **ADDITIONAL PINS OMITTED FOR CLARITY Channel 2 data and so on. Individual data registers cannot be Figure 4.AD586 Driving AD7874 REF IN accessed independently. TRACK-AND-HOLD AMPLIFIER INTERNAL REFERENCE The track-and-hold amplifier on each analog input of the The AD7874 has an on-chip temperature compensated buried AD7874 allows the ADC to accurately convert an input sine Zener reference which is factory trimmed to 3 V – 10 mV (see wave of 20 V p-p amplitude to 12-bit accuracy. The input band- Figure 3). The reference voltage is provided at the REF OUT width of the track/hold amplifier is greater than the Nyquist rate pin. This reference can be used to provide both the reference of the ADC even when the ADC is operated at its maximum voltage for the ADC and the bipolar bias circuitry. This is throughput rate. The small signal 3 dB cutoff frequency occurs achieved by connecting REF OUT to REF IN. typically at 500 kHz. The four track/hold amplifiers sample their respective input V DD channels simultaneously. The aperture delay of the track/hold circuits is small and, more importantly, is well matched across the four track/holds on one device and also well matched from TEMPERATURE device to device. This allows the relative phase information be- COMPENSATION tween different input channels to be accurately preserved. It also allows multiple AD7874s to sample more than four channels simultaneously. AD7874 The operation of the track/hold amplifiers is essentially transpar- VSS ent to the user. Once conversion is initiated, the four channels are automatically converted and there is no need to select which REF OUT channel is to be digitized. Figure 3.AD7874 Internal Reference The reference can also be used as a reference for other compo- ANALOG INPUT nents and is capable of providing up to 500 m A to an external The analog input of Channel 1 of the AD7874 is as shown in load. In systems using several AD7874s, using the REF OUT of Figure 4. The analog input range is – 10 V into an input resis- one device to provide the REF IN for the other devices ensures tance of typically 30 kW . The designed code transitions occur good full-scale tracking between all the AD7874s. Because the midway between successive integer LSB values (i.e., 1/2 LSB, AD7874 REF IN is buffered, each AD7874 presents a high im- 3/2 LSBs, 5/2 LSBs, . . . FS – 3/2 LSBs). The output code is pedance to the reference so one AD7874 REF OUT can drive 2s complement binary with 1 LSB = FS/4096 = 20 V/4096 = several AD7874 REF INs. 4.88 mV. The ideal input/output transfer function is shown in Figure 5. The maximum recommended capacitance on REF OUT for normal operation is 50 pF. If the reference is required for other system uses, it should be decoupled to AGND with a 200 W re- sistor in series with a parallel combination of a 10 m F tantalum capacitor and a 0.1 m F ceramic capacitor. –6– REV. C

AD7874 Gain error can be adjusted at either the first code transition OUTPUT CODE (ADC negative full scale) or the last code transition (ADC posi- tive full scale). The trim procedures for both cases are as 011...111 follows: 011...110 Positive Full-Scale Adjust Apply a voltage of +9.9927 V (FS/2 – 3/2 LSBs) at V. Adjust 1 R2 until the ADC output code flickers between 0111 1111 1110 000...010 000...001 –FS and 0111 1111 1111. 2 000...000 Negative Full-Scale Adjust 111...111 +F2S –1LSB Apply a voltage of –9.9976 V ( –FS + 1/2 LSB) at V1 and adjust 111...110 R2 until the ADC output code flickers between 1000 0000 0000 FS=20V and 1000 0000 0001. 1LSB = FS 100...001 4096 An alternative scheme for adjusting full-scale error in systems 100...000 which use an external reference is to adjust the voltage at the REF IN pin until the full-scale error for any of the channels is adjusted out. The good full-scale matching of the channels will 0V INPUT VOLTAGE ensure small full-scale errors on the other channels. Figure 5.Input/Output Transfer Function TIMING AND CONTROL Conversion is initiated on the AD7874 by asserting the OFFSET AND FULL-SCALE ADJUSTMENT CONVST input. This CONVST input is an asynchronous input In most Digital Signal Processing (DSP) applications, offset and which is independent of the ADC clock. This is essential for full-scale errors have little or no effect on system performance. applications where precise sampling in time is important. In Offset error can always be eliminated in the analog domain by these applications, the signal sampling must occur at exactly ac coupling. Full-scale error effect is linear and does not cause equal intervals to minimize errors due to sampling uncertainty problems as long as the input signal is within the full dynamic or jitter. In these cases, the CONVST input is driven from a range of the ADC. Invariably, some applications will require timer or precise clock source. Once conversion is started, that the input signal span the full analog input dynamic range. CONVST should not be asserted again until conversion is com- In such applications, offset and full-scale error will have to be plete on all four channels. adjusted to zero. In applications where precise time interval sampling is not criti- Figure 6 shows a circuit which can be used to adjust the offset cal, the CONVST pulse can be generated from a microproces- and full-scale errors on the AD7874 (Channel 1 is shown for ex- sor WRITE or READ line gated with a decoded address ample purposes only). Where adjustment is required, offset er- (different to the AD7874 CS address). CONVST should not be ror must be adjusted before full-scale error. This is achieved by derived from a decoded address alone because very short trimming the offset of the op amp driving the analog input of CONVST pulses (which may occur in some microprocessor sys- the AD7874 while the input voltage is a 1/2 LSB below analog tems as the address bus is changing at the start of an instruction ground. The trim procedure is as follows: apply a voltage of cycle) could initiate a conversion. –2.44 mV (–1/2 LSB) at V in Figure 6 and adjust the op amp 1 offset voltage until the ADC output code flickers between 1111 All four track/hold amplifiers go from track to hold on the rising 1111 1111 and 0000 0000 0000. edge of the CONVST pulse. The four track/hold amplifiers re- main in their hold mode while all four channels are converted. INPUT The rising edge of CONVST also initiates a conversion on the RANGE = – 10V Channel 1 input voltage (V ). When conversion is complete V1 on Channel 1, its result is sItNo1red in Data Register 1, one of four R1 on-chip registers used to store the conversion results. When the 10kW result from the first conversion is stored, conversion is initiated R2 on the voltage held by track/hold 2. When conversion has been 500W V IN1 completed on the voltage held by track/hold 4 and its result is R4 stored in Data Register 4, INT goes low to indicate that the 10kW AD7874* conversion process is complete. R3 R5 10kW 10kW The sequence in which the channel conversions takes place is AGND automatically taken care of by the AD7874. This means that the user does not have to provide address lines to the AD7874 or worry about selecting which channel is to be digitized. Reading data from the device consists of four read operations to *ADDITIONAL PINS OMITTED FOR CLARITY the same microprocessor address. Addressing of the four on-chip data registers is again automatically taken care of by the Figure 6.AD7874 Full-Scale Adjust Circuit AD7874. REV. C –7–

AD7874 The first read operation to the AD7874 after conversion always accesses data from Data Register 1 (i.e., the conversion result from the V input). INT is reset high on the falling edge of IN1 RD during this first read operation. The second read always ac- cesses data from Data Register 2 and so on. The address pointer is reset to point to Data Register 1 on the rising edge of CONVST. A read operation to the AD7874 should not be at- tempted during conversion. The timing diagram for the AD7874 conversion sequence is shown in Figure 7. TRACK/HOLDS GO INTO HOLD t 1 CONVST tCONV t ACQUISITION INT t 5 CS t t 8 2 t 4 RD t3 t6 t7 DATA HIGH-IMPEDANCE DCAHT1A HIGZH-DCAHT2A HIGZH-DCAHT3A HIGZH-DCAHT4A HIGH-Z TIMES t2, t3, t4, t6, t7, AND t8 ARE THE SAME FOR ALL FOUR READ OPERATIONS. Figure 7.AD7874 Timing Diagram Figure 8.AD7874 FFT Plot AD7874 DYNAMIC SPECIFICATIONS The AD7874 is specified and 100% tested for dynamic perfor- Effective Number of Bits The formula given in Equation 1 relates the SNR to the number mance specifications as well as traditional dc specifications such of bits. Rewriting the formula, as in Equation 2, it is possible to as Integral and Differential Nonlinearity. These ac specifications get a measure of performance expressed in effective number of are required for the signal processing applications such as bits (N). phased array sonar, adaptive filters and spectrum analysis. These applications require information on the ADC’s effect on SNR- 1.76 the spectral content of the input signal. Hence, the parameters N = (2) 6.02 for which the AD7874 is specified include SNR, harmonic dis- The effective number of bits for a device can be calculated di- tortion, intermodulation distortion and peak harmonics. These rectly from its measured SNR. terms are discussed in more detail in the following sections. Figure 9 shows a typical plot of effective number of bits versus Signal-to-Noise Ratio (SNR) frequency for an AD7874BN with a sampling frequency of SNR is the measured signal to noise ratio at the output of the 29 kHz. The effective number of bits typically falls between ADC. The signal is the rms magnitude of the fundamental. 11.75 and 11.87 corresponding to SNR figures of 72.5 dB and Noise is the rms sum of all the nonfundamental signals up to 73.2 dB. half the sampling frequency (fs/2) excluding dc. SNR is depen- dent upon the number of quantization levels used in the digiti- zation process; the more levels, the smaller the quantization noise. The theoretical signal to noise ratio for a sine wave input is given by SNR = (6.02N + 1.76) dB (1) where N is the number of bits. Thus for an ideal 12-bit converter, SNR = 74 dB. The output spectrum from the ADC is evaluated by applying a sine wave signal of very low distortion to the V input which is IN sampled at a 29 kHz sampling rate. A Fast Fourier Transform z (FFT) plot is generated from which the SNR data can be ob- tained. Figure 8 shows a typical 2048 point FFT plot of the Figure 9.Effective Numbers of Bits vs. Frequency AD7874BN with an input signal of 10 kHz and a sampling frequency of 29 kHz. The SNR obtained from this graph is 73.2 dB. It should be noted that the harmonics are taken into account when calculating the SNR. –8– REV. C

AD7874 Total Harmonic Distortion (THD) Peak Harmonic or Spurious Noise Total Harmonic Distortion (THD) is the ratio of the rms sum Harmonic or Spurious Noise is defined as the ratio of the rms of harmonics to the rms value of the fundamental. For the value of the next largest component in the ADC output spec- AD7874, THD is defined as trum (up to fs/2 and excluding dc) to the rms value of the fun- damental. Normally, the value of this specification will be V 2+V 2+V 2+V 2+V 2 determined by the largest harmonic in the spectrum, but for THD =20log 2 3 4 5 6 V parts where the harmonics are buried in the noise floor the peak 1 will be a noise peak. where V is the rms amplitude of the fundamental and V , V , 1 2 3 V , V and V are the rms amplitudes of the second through the AC Linearity Plot 4 5 6 sixth harmonic. The THD is also derived from the FFT plot of When a sine wave of specified frequency is applied to the VIN in- the ADC output spectrum. put of the AD7874 and several million samples are taken, a his- togram showing the frequency of occurrence of each of the 4096 Intermodulation Distortion ADC codes can be generated. From this histogram data it is With inputs consisting of sine waves at two frequencies, fa and possible to generate an ac integral linearity plot as shown in Fig- fb, any active device with nonlinearities will create distortion ure 11. This shows very good integral linearity performance products at sum and difference frequencies of mfa – nfb where from the AD7874 at an input frequency of 10 kHz. The absence m, n = 0, 1, 2, 3 . . ., etc. Intermodulation terms are those for of large spikes in the plot shows good differential linearity. Sim- which neither m or n are equal to zero. For example, the second plified versions of the formulae used are outlined below. order terms include (fa + fb) and (fa – fb) while the third order terms include (2fa + fb), (2fa – fb), (fa + 2fb) and (fa – 2fb). Ø (V(i)- V(o))(cid:215) 4096ø INL(i)=ºŒ V(fs)- V(o) ßœ - i Using the CCIF standard where two input frequencies near the top end of the input bandwidth are used, the second and third where INL(i) is the integral linearity at code i. V(fs) and V(o) are order terms are of different significance. The second order terms the estimated full-scale and offset transitions, and V(i) is the es- are usually distanced in frequency from the original sine waves timated transition for the ith code. while the third order terms are usually at a frequency close to V(i), the estimated code transition point is derived as follows: the input frequencies. As a result, the second and third order [ ] terms are specified separately. The calculation of the intermodu- p(cid:215) cum(i) lation distortion is as per the THD specification where it is the V(i)=- A(cid:215) Cos N ratio of the rms sum of the individual distortion products to the where A is the peak signal amplitude, N is the number of histo- rms amplitude of the fundamental expressed in dBs. In this case, gram samples the input consists of two, equal amplitude, low distortion sine waves. Figure 10 shows a typical IMD plot for the AD7874. i (cid:229) andcum(i)= V(n)occurrences n=o Figure 11. AD7874 AC INL Plot Figure 10.AD7874 IMD Plot REV. C –9–

AD7874 MICROPROCESSOR INTERFACING TIMER The AD7874 high speed bus timing allows direct interfacing to PA2 DSP processors as well as modern 16-bit microprocessors. ADDRESS BUS Suitable microprocessor interfaces are shown in Figures 12 PA0 through 16. ADDR AD7874–ADSP-2100 Interface DECODE CONVST Figure 12 shows an interface between the AD7874 and the MEN EN CS ADSP-2100. Conversion is initiated using a timer which allows very accurate control of the sampling instant on all four chan- TMS32010 AD7874* nels. The AD7874 INT line provides an interrupt to the ADSP- 2100 when conversion is completed on all four channels. The INT INT four conversion results can then be read from the AD7874 using four successive reads to the same memory address. The follow- DEN RD ing instruction reads one of the four results (this instruction is DB11 repeated four times to read all four results in sequence): DB0 MR0 = DM(ADC) D15 where MR0 is the ADSP-2100 MR0 register and DATA BUS D0 ADC is the AD7874 address. *ADDITIONAL PINS OMITTED FOR CLARITY Figure 13.AD7874–TMS32010 Interface DMA13 TIMER ADDRESS BUS AD7874–TMS320C25 Interface DMA0 Figure 14 shows an interface between the AD7874 and the CONVST TMS320C25. As with the two previous interfaces, conversion is ADDR DECODE CS initiated with a timer and the processor is interrupted when the conversion sequence is completed. The TMS320C25 does not DMS EN have a separate RD output to drive the AD7874 RD input di- ADSP-2100 AD7874* rectly. This has to be generated from the processor STRB and (ADSP-2101/ ADSP-2102) R/W outputs with the addition of some logic gates. The RD sig- nal is OR-gated with the MSC signal to provide the one WAIT IRQn INT state required in the read cycle for correct interface timing. Conversion results are read from the AD7874 using the follow- DMRD (RD) RD ing instruction: DB11 IN D,ADC DB0 where D is Data Memory address and DMD15 ADC is the AD7874 address. DATA BUS DMD0 * ADDITIONAL PINS OMITTED FOR CLARITY TIMER A15 Figure 12.AD7874–ADSP-2100 Interface ADDRESS BUS A0 AD7874–ADSP-2101/ADSP-2102 Interface The interface outlined in Figure 12 also forms the basis for an interface between the AD7874 and the ADSP-2101/ADSP-2102. DAECDODRDE CONVST The READ line of the ADSP-2101/ADSP-2102 is labeled RD. IS EN CS In this interface, the RD pulse width of the processor can be programmed using the Data Memory Wait State Control Regis- TMS320C25 AD7874* ter. The instruction used to read one of the four results is as INTn INT outlined for the ADSP-2100. STRB AD7874–TMS32010 Interface RD R/W An interface between the AD7874 and the TMS32010 is shown in Figure 13. Once again the conversion is initiated using an ex- READY ternal timer and the TMS32010 is interrupted when all four DB11 conversions have been completed. The following instruction is MSC DB0 used to read the conversion results from the AD7874: IN D,ADC D15 DATA BUS where D is Data Memory address and D0 *ADDITIONAL PINS OMITTED FOR CLARITY ADC is the AD7874 address. Figure 14.AD7874–TMS320C25 Interface –10– REV. C

AD7874 Some applications may require that the conversion is initiated AD7874–8086 Interface by the microprocessor rather than an external timer. One option Figure 16 shows an interface between the AD7874 and the 8086 is to decode the AD7874 CONVST from the address bus so microprocessor. Unlike the previous interface examples, the that a write operation starts a conversion. Data is read at the microprocessor initiates conversion. This is achieved by gating end of the conversion sequence as before. Figure 16 shows an the 8086 WR signal with a decoded address output (different to example of initiating conversion using this method. Note that the AD7874 CS address). The AD7874 INT line is used to in- for all interfaces, a read operation should not be attempted dur- terrupt the microprocessor when the conversion sequence is ing conversion. completed. Data is read from the AD7874 using the following instruction: AD7874–MC68000 Interface An interface between the AD7874 and the MC68000 is shown MOV AX,ADC in Figure 15. As before, conversion is initiated using an external where AX is the 8086 accumulator and timer. The AD7874 INT line can be used to interrupt the pro- ADC is the AD7874 address. cessor or, alternatively, software delays can ensure that conver- sion has been completed before a read to the AD7874 is attempted. Because of the nature of its interrupts, the 68000 ADDRESS BUS requires additional logic (not shown in Figure 15) to allow it to be interrupted correctly. For further information on 68000 in- terrupts, consult the 68000 users manual. 8086 ADDR DECODE CS The MC68000 AS and R/W outputs are used to generate a separate RD input signal for the AD7874. CS is used to drive AD7874* ALE LATCH the 68000 DTACK input to allow the processor to execute a normal read operation to the AD7874. The conversion results CONVST WR are read using the following 68000 instruction: RD RD MOVE.W ADC,D0 where D0 is the 68000 D0 register and DB11 ADC is the AD7874 address. DB0 AD15 A15 TIMER ADDRESS/DATA BUS ADDRESS BUS AD0 A0 *ADDITIONAL PINS OMITTED FOR CLARITY ADDR CONVST Figure 16.AD7874–8086 Interface MC68000 DECODE CS EN DTACK AD7874* AS RD R/W DB11 DB0 D15 DATA BUS D0 *ADDITIONAL PINS OMITTED FOR CLARITY Figure 15.AD7874–MC68000 Interface REV. C –11–

AD7874 APPLICATIONS A block diagram of a vector motor control application using the Vector Motor Control AD7874 is shown in Figure 17. The position of the field is de- The current drawn by a motor can be split into two compo- rived by determining the current in each phase of the motor. nents: one produces torque and the other produces magnetic Only two phase currents need to be measured because the third flux. For optimal performance of the motor, these two compo- can be calculated if two phases are known. Channel 1 and nents should be controlled independently. In conventional Channel 2 of the AD7874 are used to digitize this information. methods of controlling a three-phase motor, the current (or Simultaneous sampling is critical to maintain the relative phase voltage) supplied to the motor and the frequency of the drive are information between the two channels. A current sensing isola- the basic control variables. However, both the torque and flux tion amplifier, transformer or Hall effect sensor is used between are functions of current (or voltage) and frequency. This cou- the motor and the AD7874. Rotor information is obtained by pling effect can reduce the performance of the motor because, measuring the voltage from two of the inputs to the motor. for example, if the torque is increased by increasing the fre- Channel 3 and Channel 4 of the AD7874 are used to obtain this quency, the flux tends to decrease. information. Once again the relative phase of the two channels Vector control of an ac motor involves controlling phase in addi- is important. A DSP microprocessor is used to perform the tion to drive and current frequency. Controlling the phase of the mathematical transformations and control loop calculations on motor requires feedback information on the position of the rotor the information fed back by the AD7874. relative to the rotating magnetic field in the motor. Using this information, a vector controller mathematically transforms the three phase drive currents into separate torque and flux compo- nents. The AD7874, with its four-channel simultaneous sam- pling capability, is ideally suited for use in vector motor control applications. DSP MICROPROCESSOR I C DAC TORQUE & FLUX CONTROL LOOP DRIVE IB VB 3 CTAWLCOU TLOA TTIHORNESE & DAC CIRCUITRY V MPHOATOSER PHASE A INFORMATION DAC IA TORQUE SETPOINT FLUX ISOLATION SETPOINT AMPLIFIERS V IN1 TRANSFORMATION TO TORQUE & FLUX CURRENT V COMPONENTS IN2 AD7874* V IN3 VIN4 VOLTAGE ATTENUATORS *ADDITIONAL PINS OMITTED FOR CLARITY Figure 17.Vector Motor Control Using the AD7874 –12– REV. C

AD7874 MULTIPLE AD7874s the input signal connects to the buffer amplifier driving the ana- Figure 18 shows a system where a number of AD7874s can be log input of the ADC. If the shorting plug is omitted, a wire link configured to handle multiple input channels. This type of con- can be used to connect the input signal to the PCB component figuration is common in applications such as sonar, radar, etc. grid. The AD7874 is specified with maximum and minimum limits on Microprocessor connections to the board are made via a 26- aperture delay. This means that the user knows the maximum contact IDC connector, SKT8, the pinout for which is shown in difference in the sampling instant between all channels. This al- Figure 19. This connector contains all data, control and status lows the user to maintain relative phase information between the signals of the AD7874 (with the exception of the CLK input different channels. and the CONVST input which are provided via SKT5 and A common read signal from the microprocessor drives the RD SKT7, respectively). It also contains decoded R/W and STRB input of all AD7874s. Each AD7874 is designated a unique ad- inputs which are necessary for TMS32020 interfacing (and also dress selected by the address decoder. The reference output of for 68000 interfacing although pin labels on the 68000 are dif- AD7874 number 1 is used to drive the reference input of all ferent). Note that the AD7874 CS input must be decoded prior other AD7874s in the circuit shown in Figure 18. One REF to the AD7874 evaluation board. OUT pin can drive several AD7874 REF IN pins. Alternatively, SKT1, SKT2, SKT3 and SKT4 provide the inputs for V , an external or system reference can be used to drive all REF IN IN1 V , V , V respectively. Assuming LK1 to LK4 are in inputs. A common reference ensures good full-scale tracking be- IN2 IN3 IN4 place, these input signals are fed to four buffer amplifiers, IC1, tween all channels. before being applied to the AD7874. The use of an external clock source is optional; there is a shorting plug (LK5) on the V AD7874 CLK input which must be connected to either –5 V CH1 (for the ADCs own internal clock) or to SKT5. SKT6 and V RD RD CH2 SKT7 provide the reference and CONVST inputs respectively. VCH3 AD7874(1) Shorting plug LK6 provides the option of using the external ref- VCH4 CS erence or the ADCs own internal reference. REF OUT R/W 1 2 STRB RD 3 4 N/C CS 5 6 N/C V CH5 V RD N/C 7 8 INT CH6 V AD7874(2) ADDRESS N/C 9 10 N/C CH7 DECODE VCH8 CS ADDRESS DB10 11 12 DB11 REF IN DB8 13 14 DB9 DB6 15 16 DB7 DB4 17 18 DB5 REF IN V RD DB2 19 20 DB3 CHm VCHm+1 AD7874(n) DB0 21 22 DB1 VCHm+2 +5V 23 24 +5V CS V CHm+3 GND 25 26 GND Figure 18.Multiple AD7874s in Multichannel System Figure 19.SKT8, IDC Connector Pinout DATA ACQUISITION BOARD POWER SUPPLY CONNECTIONS Figure 20 shows the AD7874 in a data acquisition circuit. The The PCB requires two analog power supplies and one 5 V digi- corresponding printed circuit board (PCB) layout and silkscreen tal supply. The analog supplies are labeled V+ and V– and the are shown in Figures 21 to 23. A 26-contact IDC connector pro- range for both supplies is 12 V to 15 V (see silkscreen in Figure vides for a microprocessor connection to the board. 23). Connection to the 5 V digital supply is made via SKT8. The +5 V supply and the –5 V supply required by the AD7874 A component grid is provided near the analog inputs on the are generated from voltage regulators (IC3 and IC4) on the V+ PCB which may be used to provide antialiasing filters for the and V– supplies. analog input channels or to provide signal conditioning circuitry. To facilitate this option, four shorting plugs (labeled LK1 to LK4 on the PCB) are provided on the analog inputs, one plug per input. If the shorting plug for a particular channel is used, REV. C –13–

AD7874 V+ IC3 CONVST C3 78L05 C7 SKT6 C4 C8 IC1 LK1 VDD AD713 V DD SKT1 VIN1 CONVST SKT8 DB11 11 LK2 DATA BUS DB0 22 SKT2 VIN2 INT 8 CS 5 LK3 +5V 23, 24 SKT3 VIN3 IC2 R2 R1 AD7874 A IC5 2 LK4 IC5 1 B SKT4 V RD 3 IN4 A DGND REF IN 25, 26 V AGND B SS REF C1 C2 DGND OUT VSS CLK LK5 OUT IC4 A B V– 79L05 IN C6 REFERENCE CLK C5 SKT6 SKT5 Figure 20.Data Acquisition Circuit Using the AD7874 Figure 21.PCB Silkscreen for Figure 20 –14– REV. C

AD7874 Figure 22.PCB Component Side Layout for the Circuit of Figure 20 Figure 23.PCB Solder Side Layout for the Circuit of Figure 20 REV. C –15–

AD7874 SHORTING PLUG OPTIONS COMPONENT LIST There are seven shorting plug options which must be set before IC1 AD713 Quad Op Amp using the board. These are outlined below: IC2 AD7874 Analog-to-Digital Converter LK1–LK4 Connects the analog inputs to the buffer amplifi- IC3 MC78L05 +5 V Regulator ers. The analog inputs may also be connected to a IC4 MC79L05 –5 V Regulator component grid for signal conditioning. IC5 74HC00 Quad NAND Gate LK5 Steerlneaclt sc leoitchke sro tuhrec Ae.D7874 internal clock or an ex- CCR112,,, RCC234,, CC56,, CC78,, CC910 1010.01 m kmFWF C PCuaaplpla-aUccitipto orRrssesistors 5–5/91 – LK6 Selects either the AD7874 internal reference or an LK1, LK2, LK3 Shorting Plugs 8a 8 external reference source. LK4, LK5, LK6 13 C LK7 Connects the AD7874 RD input directly to the LK7 RD input of SKT8 or to a decoded STRB and SKT1, SKT2, SKT3, BNC Sockets R/W input. This shorting plug setting depends on SKT4, SKT5, SKT6, the microprocessor, e.g., the TMS32020 and SKT7 68000 require a decoded RD signal. SKT8 26-Contact (2-Row) IDC Connector OUTLINE DIMENSIONS Dimensions shown in inches and (mm). Plastic (N-28) SOIC (R-28) Cerdip (Q-28) LCCC (E-28A) 0.100 (2.54)1 0.064 (1.63) 0.055 (1.40) 0.075 0.045 (1.14) (1.91) REF 0.028 (0.71) 0.022 (0.56) 28 0(.10.5207 –– 00..1030)5 NO. 1 PIN INDEX S.A. U. BOTTOM VIEW N D I R(01E..0F042 30 x Px 4 L45C5(cid:176)(cid:176)S) 0(0.0.5210 xx 4455(cid:176)(cid:176)) REF NTE 0.458 (11.63)2 RI 0.442 (11.23) P NOTES 1. THIS DIMENSION CONTROLS THE OVERALL PACKAGE THICKNESS. 2. APPLIES TO ALL FOUR SIDES. 3. ALL TERMINALS ARE GOLD PLATED. –16– REV. C

Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: A nalog Devices Inc.: AD7874ARZ AD7874AQ 5962-9152101M3A AD7874BRZ AD7874BN AD7874ANZ AD7874AR AD7874AN AD7874BNZ AD7874SE 5962-9152101MXA AD7874SQ AD7874BQ AD7874ARZ-REEL AD7874ARZ-REEL7 AD7874AR-REEL7