4-Channel, Simultaneous Sampling, High Speed, 12-Bit ADC AD7864 FEATURES FUNCTIONAL BLOCK DIAGRAM High speed (1.65 μs) 12-bit ADC AVDD VREF VREFGND DVDD VDRIVE 4 simultaneously sampled inputs 4 track-and-hold amplifiers STBY TRACK-A×N4D-HOLD 6kΩ REFE2.R5EVNCE DGND VIN1A SIGNAL 0.35 μs track-and-hold acquisition time VIN1B SCALING AD7864 AGND 1.65 μs conversion time per channel VIN2A SIGNAL RD HW/SW select of channel sequence for conversion VIN2B SCALING MUX Single-supply operation VIN3A SIGNAL OUTPUT DB11 VIN3B SCALING 12-BIT DATA Selection of input ranges VIN4A SIGNAL ADC REGISTERS DB0 ±10 V, ±5 V for AD7864-1 VIN4B SCALING ±2.5 V for AD7864-3 0 V to 2.5 V, 0 V to 5 V for AD7864-2 SOLFATTWCAHRE DB0 TO DB3 CS FRSTDATA High speed parallel interface that allows BUSY CONVERSION WR Interfacing to 3 V processors EOC CONTROL LOGIC INT/EXT CLOCK INT SELECT CLOCK Low power, 90 mW typical POovwerevro slatavgineg p mrootdeect, i2o0n μ oWn atynpailcoagl inputs CONVSTSL1SL2SL3SL4 SHE/SL CLKIN INCTL/EKXT AGND AGND 01341-001 Figure 1. APPLICATIONS Data is read from the part by a 12-bit parallel data bus using the AC motor control standard CS and RD signals. Maximum throughput for a single Uninterrupted power supplies channel is 500 kSPS. For all four channels, the maximum throughput Data acquisition systems is 130 kSPS for the read-during-conversion sequence operation. Communications The throughput rate for the read-after-conversion sequence GENERAL DESCRIPTION operation depends on the read cycle time of the processor. See the Timing and Control section. The AD7864 is available in a The AD7864 is a high speed, low power, 4-channel, simulta- small (0.3 square inch area) 44-lead MQFP. neous sampling 12-bit analog-to-digital converter (ADC) that operates from a single 5 V supply. The part contains a 1.65 μs PRODUCT HIGHLIGHTS successive approximation ADC, four track-and-hold amplifiers, 1. Four track-and-hold amplifiers and a fast (1.65 μs) ADC for a 2.5 V reference, an on-chip clock oscillator, signal conditioning simultaneous sampling and conversion of any subset of the circuitry, and a high speed parallel interface. The input signals four channels. on four channels sample simultaneously preserving the relative 2. A single 5 V supply consuming only 90 mW typical, makes phase information of the signals on the four analog inputs. The it ideal for low power and portable applications. See the part accepts analog input ranges of ±10 V, ±5 V (AD7864-1), 0 V Standby Mode Operation section. to +2.5 V, 0 V to +5 V (AD7864-2), and ±2.5 V (AD7864-3). 3. High speed parallel interface for easy connection to micro- Any subset of the four channels can be converted to maximize processors, microcontrollers, and digital signal processors. the throughput rate on the selected sequence. Select the channels to 4. Available in three versions with different analog input convert via hardware (channel select input pins) or software (pro- ranges. The AD7864-1 offers the standard industrial input gramming the channel select register). ranges of ±10 V and ±5 V; the AD7864-3 offers the common signal processing input range of ±2.5 V; the AD7864-2 can A single conversion start signal (CONVST) simultaneously places be used in unipolar, 0 V to 2.5 V and 0 V to 5 V, all the track-and-holds into hold and initiates a conversion se- applications. quence for the selected channels. The EOC signal indicates the end 5. Features very tight aperture delay matching between the of each individual conversion in the selected conversion sequence. four input sample-and-hold amplifiers. The BUSY signal indicates the end of the conversion sequence. Rev. D Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Tel: 781.329.4700 www.analog.com Trademarks and registered trademarks are the property of their respective owners. Fax: 781.461.3113 ©1998–2009 Analog Devices, Inc. All rights reserved.

AD7864 TABLE OF CONTENTS Features .............................................................................................. 1 Standby Mode Operation .......................................................... 18 Applications ....................................................................................... 1 Accessing the Output Data Registers ....................................... 18 General Description ......................................................................... 1 Offset and Full-Scale Adjustment ................................................ 20 Functional Block Diagram .............................................................. 1 Positive Full-Scale Adjust .......................................................... 20 Product Highlights ........................................................................... 1 Negative Full-Scale Adjust ......................................................... 20 Revision History ............................................................................... 2 Dynamic Specifications ................................................................. 21 Specifications ..................................................................................... 3 Signal-to-Noise Ratio (SNR)..................................................... 21 Timing Characteristics ................................................................ 5 Effective Number of Bits ........................................................... 21 Absolute Maximum Ratings ............................................................ 6 Intermodulation Distortion ...................................................... 21 ESD Caution .................................................................................. 6 AC Linearity Plots ...................................................................... 22 Pin Configuration and Function Descriptions ............................. 7 Measuring Aperture Jitter .......................................................... 22 Terminology ...................................................................................... 9 Microprocessor Interfacing ........................................................... 24 Theory of Operation ...................................................................... 11 AD7864 to ADSP-2100/ADSP-2101/ADSP-2102 Interface . 24 Converter Details ........................................................................ 11 AD7864 to TMS320C5x Interface ............................................ 24 Circuit Description ......................................................................... 13 AD7864 to MC68HC000 Interface .......................................... 24 Analog Input ............................................................................... 13 Vector Motor Control ................................................................ 25 Selecting a Conversion Sequence ................................................. 15 Multiple AD7864s in A System ................................................. 26 Timing and Control ................................................................... 15 Outline Dimensions ....................................................................... 27 Using an External Clock ............................................................ 17 Ordering Guide .......................................................................... 27 REVISION HISTORY 2/09—Rev. C to Rev. D 3/04—Rev. A to Rev. B. Change to t Parameter, Table 2 ...................................................... 5 Changes to Specifications and to Footnote 4 ................................. 2 2 Changes to Timing Characteristics Footnote 1 ............................. 4 2/09—Rev. B to Rev. C Addition to Absolute Maximum Ratings ....................................... 5 Updated Format .................................................................. Universal Changes to Ordering Guide ............................................................. 5 Changes to t Timing Parameter, Table 2....................................... 5 5 Changes to Figure 7 ......................................................................... 11 Changes to Figure 15 ...................................................................... 20 Changes to Figure 11 ...................................................................... 13 Changes to AD7864 to MC68HC000 Interface Section ............ 24 Updated Outline Dimensions ....................................................... 19 Changes to Figure 25 ...................................................................... 24 Added Revision History ................................................................ 20 Updated Outline Dimensions ....................................................... 29 Updated Publication Code ............................................................ 20 Changes to Ordering Guide .......................................................... 29 Rev. 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AD7864 SPECIFICATIONS V = 5 V ± 5%, AGND = DGND = 0 V, V = internal, clock = internal; all specifications T to T , unless otherwise noted. DD REF MIN MAX Table 1. Parameter A Version1 B Version Unit Test Conditions/Comments SAMPLE AND HOLD −3 dB Full Power Bandwidth 3 3 MHz typ Aperture Delay 20 20 ns max Aperture Jitter 50 50 ps max Aperture Delay Matching 4 4 ns max DYNAMIC PERFORMANCE2 fIN = 100.0 kHz, fS = 500 kSPS Signal-to-(Noise + Distortion) Ratio3 @ 25°C 70 72 dB min T to T 70 70 dB min MIN MAX Total Harmonic Distortion3 −80 −80 dB max Peak Harmonic or Spurious Noise3 −80 −80 dB max Intermodulation Distortion3 fa = 49 kHz, fb = 50 kHz Second-Order Terms −80 −80 dB typ Third-Order Terms −80 −80 dB typ Channel-to-Channel Isolation3 −80 −80 dB max f = 50 kHz sine wave IN DC ACCURACY Any channel Resolution 12 12 Bits Relative Accuracy3 ±1 ±1/2 LSB max Differential Nonlinearity3 ±0.9 ±0.9 LSB max No missing codes AD7864-1 Positive Gain Error3 ±3 ±3 LSB max Positive Gain Error Match3 +3 ±3 LSB max Negative Gain Error3 ±3 ±3 LSB max Negative Gain Error Match3 +3 ±3 LSB max Bipolar Zero Error ±4 ±3 LSB max Bipolar Zero Error Match +2 ±2 LSB max AD7864-3 Positive Gain Error3 ±3 LSB max Positive Gain Error Match3 2 LSB max Negative Gain Error3 ±3 LSB max Negative Gain Error Match3 2 LSB max Bipolar Zero Error ±3 LSB max Bipolar Zero Error Match 2 LSB max AD7864-2 Positive Gain Error3 ±3 LSB max Positive Gain Error Match3 3 LSB max Unipolar Offset Error ±3 LSB max Unipolar Offset Error Match 2 LSB max ANALOG INPUTS AD7864-1 Input Voltage Range ±5, ±10 ±5, ±10 V Input Resistance 9, 18 9, 18 kΩ min AD7864-3 Input Voltage Range ±2.5 ±2.5 V Input Resistance 4.5 4.5 kΩ min Rev. D | Page 3 of 28

AD7864 Parameter A Version1 B Version Unit Test Conditions/Comments AD7864-2 Input Voltage Range 0 to 2.5, 0 to 5 0 to 2.5, 0 to 5 V Input Current (0 V to 2.5 V Option) ±100 ±100 nA max Input Resistance (0 V to 5 V Option) 9 9 kΩ min REFERENCE INPUT/OUTPUT V In Input Voltage Range 2.375/2.625 2.375/2.625 V /V 2.5 V ± 5% REF MIN MAX V In Input Capacitance4 10 10 pF max REF V Out Output Voltage 2.5 2.5 V nom REF V Out Error @ 25°C ±10 ±10 mV max REF V Out Error T to T ±20 ±20 mV max REF MIN MAX V Out Temperature Coefficient 25 25 ppm/°C typ REF V Out Output Impedance 6 6 kΩ typ See the Reference section REF LOGIC INPUTS Input High Voltage, V 2.4 2.4 V min V = 5 V ± 5% INH DD Input Low Voltage, V 0.8 0.8 V max V = 5 V ± 5% INL DD Input Current, I ±10 ±10 μA max IN Input Capacitance, C 4 10 10 pF max IN LOGIC OUTPUTS Output High Voltage, V 4.0 4.0 V min I = 400 μA OH SOURCE Output Low Voltage, V 0.4 0.4 V max I = 1.6 mA OL SINK DB11 to DB0 High Impedance Leakage Current ±10 ±10 μA max Capacitance4 10 10 pF max Output Coding AD7864-1, AD7864-3 Twos complement AD7864-2 Straight (natural) binary CONVERSION RATE Conversion Time 1.65 1.65 μs max For one channel Track-And-Hold Acquisition Time2, 3 0.35 0.35 μs max Throughput Time 130 130 kSPS max For all four channels POWER REQUIREMENTS V 5 5 V nom ±5% for specified performance DD I 5 μA typical, logic inputs = 0 V or V DD DD Normal Mode 24 24 mA max Standby Mode 20 20 μA max Typically 4 μA Power Dissipation Normal Mode 120 120 mW max Typically 90 mW Standby Mode 100 100 μW max Typically 20 μW 1 Temperature ranges are as follows: A, B versions: –40°C to +85°C. The A version is fully specified up to 105°C with a maximum sample rate of 450 kSPS and IDD maximum (normal mode) of 26 mA. 2 Performance is measured through the full channel (SHA and ADC). 3 See the Terminology section. 4 Sample tested at initial release to ensure compliance. Rev. D | Page 4 of 28

AD7864 TIMING CHARACTERISTICS V = 5 V± 5%, AGND = DGND = 0 V, V = internal, clock = internal; all specifications T to T , unless otherwise noted.1, 2 DRIVE REF MIN MAX Table 2. Parameter A, B Versions Unit Test Conditions/Comments t 1.65 μs max Conversion time, internal clock CONV 13 Clock cycles Conversion time, external clock 2.6 μs max CLKIN = 5 MHz t 0.34 μs max Acquisition time ACQ tBUSY No. of channels × μs max Selected number of channels multiplied by (tCONV + EOC pulse (tCONV + t9) − t9 width)—EOC pulse width tWAKE-UP —External VREF 2 μs max STBY rising edge to CONVST rising edge tWAKE-UP —Internal VREF3 6 ms max STBY rising edge to CONVST rising edge t1 35 ns min CONVST pulse width t2 70 ns max CONVST rising edge to BUSY rising edge READ OPERATION t3 0 ns min CS to RD setup time t4 0 ns min CS to RD hold time t 35 ns min Read pulse width, V = 5 V 5 DRIVE 40 ns min Read pulse width, V = 3 V DRIVE t64 35 ns max Data access time after falling edge of RD, VDRIVE = 5 V 40 ns max Data access time after falling edge of RD, VDRIVE = 3 V t75 5 ns min Bus relinquish time after rising edge of RD 30 ns max t 10 ns min Time between consecutive reads 8 t9 75 ns min EOC pulse width 180 ns max t10 70 ns max RD rising edge to FRSTDATA edge (rising or falling) t11 15 ns max EOC falling edge to FRSTDATA falling delay t12 0 ns min EOC to RD delay WRITE OPERATION t13 20 ns min WR pulse width t14 0 ns min CS to WR setup time t15 0 ns min WR to CS hold time t16 5 ns min Input data setup time of rising edge of WR t 5 ns min Input data hold time 17 1 Sample tested at initial release to ensure compliance. All input signals are measured with tr = tf = 1 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V. 2 See Figure 9, Figure 10,and Figure 11. 3 Refer to the Standby Mode Operation section. The maximum specification of 6 ms is valid when using a 0.1 μF decoupling capacitor on the VREF pin. 4 Measured with the load circuit of Figure 2 and defined as the time required for an output to cross 0.8 V or 2.4 V. 5 These times are derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit shown in Figure 2. The measured number is then extrapolated back to remove the effects of charging or discharging the 50 pF capacitor. This means that the times quoted in the timing characteristics are the true bus relinquish times of the part, and as such, are independent of external bus loading capacitances. 1.6mA TO OUTPUT 1.6V 50pF 400µA 01341-002 Figure 2. Load Circuit for Access Time and Bus Relinquish Time Rev. D | Page 5 of 28

AD7864 ABSOLUTE MAXIMUM RATINGS T = 25°C, unless otherwise noted. A Stresses above those listed under Absolute Maximum Ratings Table 3. may cause permanent damage to the device. This is a stress Parameter Rating rating only; functional operation of the device at these or any AV to AGND −0.3 V to +7 V DD other conditions above those indicated in the operational DV to DGND −0.3 V to +7 V DD section of this specification is not implied. Exposure to absolute AGND to DGND −0.3 V to +0.3 V maximum rating conditions for extended periods may affect AV to DV −0.3 V to +0.3 V DD DD device reliability. Analog Input Voltage to AGND AD7864-1 (±10 V Input Range) ±20 V ESD CAUTION AD7864-1 (±5 V Input Range) −7 V to +20 V AD7864-3 −7 V to +20 V AD7864-2 −1 V to +20 V Reference Input Voltage to AGND −0.3 V to V + 0.3 V DD Digital Input Voltage to DGND −0.3 V to V + 0.3 V DD Digital Output Voltage to DGND −0.3 V to V + 0.3 V DD V to AGND −0.3 V to AV + 0.3 V DRIVE DD V to DGND −0.3 V to DV + 0.3 V DRIVE DD Operating Temperature Range Commercial (A and B Versions) −40°C to +85°C Storage Temperature Range −65°C to +150°C Junction Temperature 150°C MQFP Package, Power Dissipation 450 mW θ Thermal Impedance 95°C/W JA Lead Temperature, Soldering Vapor Phase (60 sec) 215°C Infrared (15 sec) 220°C Rev. D | Page 6 of 28

AD7864 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS OC B0 B1 B2 B3 B4 B5 GND DRIVEVDD B6 E D D D D D D D V D D 44 43 42 41 40 39 38 37 36 35 34 BUSY 1 33 DB7 FRSTDATA 2 PIN 1 32 DB8 CONVST 3 31 DB9 CS 4 30 DB10 RD 5 AD7864 29 DB11 WR 6 TOP VIEW 28 CLKIN SL1 7 (Not to Scale) 27 INT/EXT CLK SL2 8 26 AGND SL3 9 25 AVDD SL4 10 24 VREF H/S SEL 11 23 VREFGND 12 13 14 15 16 17 18 19 20 21 22 AGND VIN4BVIN4AVIN3BVIN3A AGND VIN2BVIN2AVIN1BVIN1A STBY 01341-003 Figure 3. Pin Configuration Table 4. Pin Function Descriptions Pin No. Mnemonic Description 1 BUSY Busy Output. The busy output is triggered high by the rising edge of CONVST and remains high until conversion is completed on all selected channels. 2 FRSTDATA First Data Output. FRSTDATA is a logic output which, when high, indicates that the output data register pointer is addressing Register 1—see the Accessing the Output Data Registers section. 3 CONVST Convert Start Input. Logic input. A low-to-high transition on this input puts all track-and-holds into their hold mode and starts conversion on the selected channels. In addition, the state of the channel sequence selection is also latched on the rising edge of CONVST. 4 CS Chip Select Input. Active low logic input. The device is selected when this input is active. 5 RD Read Input. Active low logic input that is used in conjunction with CS low to enable the data outputs. Ensure the WR pin is at logic high while performing a read operation. 6 WR Write Input. A rising edge on the WR input, with CS low and RD high, latches the logic state on DB0 to DB3 into the channel select register. 7 to 10 SL1 to SL4 Hardware Channel Select. Conversion sequence selection can also be made via the SL1 to SL4 pins if H/S SEL is Logic 0. The selection is latched on the rising edge of CONVST. See the Selecting a Conversion Sequence section. 11 H/S SEL Hardware/Software Select Input. When this pin is at Logic 0, the AD7864 conversion sequence selection is controlled via the SL1 to SL4 input pins. When this pin is at Logic 1, the sequence is controlled via the channel select register. See the Selecting a Conversion Sequence section. 12 AGND Analog Ground. General analog ground. Connect this AGND pin to the AGND plane of the system. 13 to 16 V , V Analog Inputs. See the Analog Input section. IN4x IN3x 17 AGND Analog Ground. Analog ground reference for the attenuator circuitry. Connect this AGND pin to the AGND plane of the system. 18 to 21 V , V Analog Inputs. See the Analog Input section. IN2x IN1x 22 STBY Standby Mode Input. TTL-compatible input that is used to put the device into the power save or standby mode. The STBY input is high for normal operation and low for standby operation. 23 V GND Reference Ground. This is the ground reference for the on-chip reference buffer of the part. Connect the REF V GND pin to the AGND plane of the system. REF 24 V Reference Input/Output. This pin provides access to the internal reference (2.5 V ± 5%) and also allows the REF internal reference to be overdriven by an external reference source (2.5 V). Connect a 0.1 μF decoupling capacitor between this pin and AGND. 25 AV Analog Positive Supply Voltage, 5.0 V ± 5%. DD 26 AGND Analog Ground. Analog ground reference for the DAC circuitry. Rev. D | Page 7 of 28

AD7864 Pin No. Mnemonic Description 27 INT/EXT CLK Internal/External Clock Select Input. When this pin is at Logic 0, the AD7864 uses its internally generated master clock. When this pin is at Logic 1, the master clock is generated externally to the device. 28 CLKIN Conversion Clock Input. This is an externally applied clock that allows the user to control the conversion rate of the AD7864. Each conversion needs 14 clock cycles for the conversion to be completed and an EOC pulse to be generated. The clock should have a duty cycle that is no worse than 60/40. See the Using An External Clock section. 29 to 34 DB11 to DB6 Data Bit 11 is the MSB, followed by Data Bit 10 to Data Bit 6. Three-state TTL outputs. Output coding is twos complement for the AD7864-1 and AD7864-3. Output coding is straight (natural) binary for the AD7864-2. 35 DV Positive Supply Voltage for Digital Section, 5.0 V ± 5%. Connect a 0.1 μF decoupling capacitor between this pin DD and AGND. Both DV and AV should be externally tied together. DD DD 36 VDRIVE This pin provides the positive supply voltage for the output drivers (DB0 to DB11), BUSY, EOC, and FRSTDATA. It is normally tied to DV . Decouple V with a 0.1 μF capacitor to improve performance when reading during DD DRIVE the conversion sequence. To facilitate interfacing to 3 V processors and DSPs, the output data drivers can also be powered by a 3 V ± 10% supply. 37 DGND Digital Ground. This is the ground reference for digital circuitry. Connect this DGND pin to the AGND plane of the system at the AGND pin. 38, 39 DB5, DB4 Data Bit 5 to Data Bit 4. Three-state TTL outputs. 40 to 43 DB3 to DB0 Data Bit 3 to Data Bit 0. Bidirectional data pins. When a read operation takes place, these pins are three-state TTL outputs. The channel select register is programmed with the data on the DB0 to DB3 pins with standard CS and WR signals. DB0 represents Channel 1, and DB3 represents Channel 4. 44 EOC End-of-Conversion. Active low logic output indicating conversion status. The end of each conversion in a conversion sequence is indicated by a low-going pulse on this line. Rev. D | Page 8 of 28

AD7864 TERMINOLOGY Channel-to-Channel Isolation Signal-to-(Noise + Distortion) Ratio Channel-to-channel isolation is a measure of the level of This is the measured ratio of signal-to-(noise + distortion) at crosstalk between channels. It is measured by applying a full- the output of the ADC. The signal is the rms amplitude of the scale 50 kHz sine wave signal to all nonselected input channels fundamental. Noise is the rms sum of all nonfundamental signals and determining how much that signal is attenuated in the up to half the sampling frequency (f/2), excluding dc. The ratio S selected channel. The figure given is the worst case across all depends on the number of quantization levels in the digitization four channels. process; the more levels, the smaller the quantization noise. The theoretical signal-to-(noise + distortion) ratio for an ideal N-bit Relative Accuracy converter with a sine wave input is given by Relative accuracy, or endpoint nonlinearity, is the maximum deviation from a straight line passing through the endpoints of Signal-to-(Noise + Distortion) = (6.02 N + 1.76) dB the ADC transfer function. Thus, for a 12-bit converter, this is 74 dB. Differential Nonlinearity Total Harmonic Distortion (THD) This is the difference between the measured and the ideal 1 LSB THD is the ratio of the rms sum of harmonics to the change between any two adjacent codes in the ADC. fundamental. For the AD7864, it is defined as Positive Full-Scale Error THD(dB)=20log V22 +V32 +V42 +V52 +V62 This is the deviation of the last code transition (01...110 to 01...111) V from the ideal, 4 × V − 3/2 LSB (AD7864-1, ±10 V), or 2 × 1 REF V − 3/2 LSB (AD7864-1, ±5 V range), or V − 3/2 LSB where V is the rms amplitude of the fundamental, and V, V, REF REF 1 2 3 (AD7864-3, ±2.5 V range), after the bipolar offset error has V, V, and V are the rms amplitudes of the second through the 4 5 6 been adjusted out. fifth harmonics. Positive Full-Scale Error (AD7864-2, 0 V to 2.5 V and 0 V to 5 V) Peak Harmonic or Spurious Noise This is the deviation of the last code transition (11...110 to 11...111) Peak harmonic or spurious noise is defined as the ratio of the from the ideal 2 × V − 3/2 LSB (AD7864-2, 0 V to 5 V range) rms value of the next largest component in the ADC output REF or V − 3/2 LSB (AD7864-2, 0 V to 2.5 V range), after the spectrum (up to f/2 and excluding dc) to the rms value of the REF S unipolar offset error has been adjusted out. fundamental. Normally, the value of this specification is deter- mined by the largest harmonic in the spectrum, but for parts Bipolar Zero Error (AD7864-1, ±10 V/±5 V, AD7864-3, ±2.5 V) where the harmonics are buried in the noise floor, it is a noise peak. This is the deviation of the midscale transition (all 0s to all 1s) from the ideal, AGND − 1/2 LSB. Intermodulation Distortion With inputs consisting of sine waves at two frequencies, fa and Unipolar Offset Error (AD7864-2, 0 V to 2.5 V and 0 V to 5 V) fb, any active device with nonlinearities creates distortion products This is the deviation of the first code transition (00...000 to at sum and difference frequencies of mfa ± nfb, where m, n = 0, 00...001) from the ideal, AGND + 1/2 LSB. 1, 2, 3, and so on. Intermodulation terms are those for which Negative Full-Scale Error (AD7864-1, ±10 V/±5 V, and neither m nor n are equal to zero. For example, second-order AD7864-3, ±2.5 V) terms include (fa + fb) and (fa − fb), whereas third-order terms This is the deviation of the first code transition (10...000 to include (2 fa + fb), (2 fa − fb), (fa + 2 fb), and (fa − 2 fb). 10...001) from the ideal, −4 × V + 1/2 LSB (AD7864-1, ±10 V), REF The AD7864 is tested using the CCIF standard, where two input −2 × V + 1/2 LSB (AD7864-1, ±5 V range) or −V + 1/2 LSB REF REF frequencies near the top end of the input bandwidth are used. (AD7864-3, ±2.5 V range), after bipolar zero error has been In this case, the second- and third-order terms are of different adjusted out. significance. The second-order terms are usually distanced in Track-and-Hold Acquisition Time frequency from the original sine waves, whereas the third-order Track-and-hold acquisition time is the time required for the terms are usually at a frequency close to the input frequencies. As output of the track-and-hold amplifier to reach its final value, a result, the second- and third-order terms are specified separately. within ±1/2 LSB, after the end of a conversion (the point at The calculation of the intermodulation distortion is as per the which the track-and-hold returns to track mode). It also applies THD specification where it is the ratio of the rms sum of the to situations where there is a step input change on the input individual distortion products to the rms amplitude of the funda- voltage applied to the selected V /V input of the AD7864. INxA INxB mental expressed in decibels. Rev. D | Page 9 of 28

AD7864 It means that the user must wait for the duration of the track- and-hold acquisition time after the end of conversion or after a step input change to V /V before starting another INxA INxB conversion to ensure that the part operates to specification. Rev. D | Page 10 of 28

AD7864 THEORY OF OPERATION CONVERTER DETAILS Conversion time for each channel of the AD7864 is 1.65 μs, and the track-and-hold acquisition time is 0.35 μs. To obtain optimum The AD7864 is a high speed, low power, 4-channel simultaneous performance from the part, the read operation should not occur sampling 12-bit ADC that operates from a single 5 V supply. during a channel conversion or during the 100 ns prior to the The part contains a 1.65 μs successive approximation ADC, four next CONVST rising edge. This allows the part to operate at track-and-hold amplifiers, an internal 2.5 V reference, and a throughput rates up to 130 kHz for all four channels and high speed parallel interface. There are four analog inputs that achieve data sheet specifications. can be simultaneously sampled, thus preserving the relative phase information of the signals on all four analog inputs. Track-and-Hold Amplifiers Thereafter, conversions are completed on the selected subset of The track-and-hold amplifiers on the AD7864 allow the ADCs the four channels. The part accepts an analog input range of to accurately convert an input sine wave of full-scale amplitude ±10 V or ±5 V (AD7864-1), ±2.5 V (AD7864-3), and 0 V to to 12-bit accuracy. The input bandwidth of the track-and-hold +2.5 V or 0 V to +5 V (AD7864-2). Overvoltage protection on is greater than the Nyquist rate of the ADC even when the ADC the analog inputs of the part allows the input voltage to go to is operated at its maximum throughput rate of 500 kSPS (that is, ±20 V, (AD7864-1 ±10 V range), −7 V or +20 V (AD7864-1 the track-and-hold can handle input frequencies in excess of ±5 V range), −1 V to +20 V (AD7864-2), and −7 V to +20 V 250 kHz). (AD7864-3), without causing damage. The AD7864 has two The track-and-hold amplifiers acquire input signals to 12-bit operating modes: reading-between-conversions and reading- accuracy in less than 350 ns. The operation of the track-and- after-the-conversion sequence. These modes are discussed in holds are essentially transparent to the user. The four track-and- more detail in the Timing and Control section. hold amplifiers sample their respective input channels simulta- A conversion is initiated on the AD7864 by pulsing the CONVST neously, on the rising edge of CONVST. The aperture time for input. On the rising edge of CONVST, all four on-chip track- the track-and-holds (that is, the delay time between the external and-holds are placed into hold simultaneously and the conversion CONVST signal and the track-and-hold actually going into hold) sequence is started on all the selected channels. Channel selection is typically 15 ns and, more importantly, is well matched across is made via the SL1 to SL4 pins if H/S SEL is Logic 0 or via the the four track-and-holds on one device as well as being well channel select register if H/S SEL is Logic 1—see the Selecting a matched from device to device. This allows the relative phase Conversion Sequence section. The channel select register is information between different input channels to be accurately programmed via the bidirectional data lines (DB0 to DB3) and preserved. It also allows multiple AD7864s to sample more than a standard write operation. The selected conversion sequence is four channels simultaneously. At the end of a conversion sequence, latched on the rising edge of CONVST, therefore, changing a the part returns to its tracking mode. The acquisition time of selection only takes effect once a new conversion sequence is the track-and-hold amplifiers begin at this point. initiated. The BUSY output signal is triggered high on the rising Reference edge of CONVST and remains high for the duration of the conver- The AD7864 contains a single reference pin, labeled V . The sion sequence. The conversion clock for the part is generated REF V pin provides access to the 2.5 V reference within the part, internally using a laser trimmed, clock oscillator circuit. REF or it serves as the reference source for the part by connecting There is also the option of using an external clock, by tying the V to an external 2.5 V reference. The part is specified with a REF INT/EXT CLK pin logic high, and applying an external clock to 2.5 V reference voltage. Errors in the reference source result in the CLKIN pin. However, the optimum throughput is obtained gain errors in the transfer function of the AD7864 and adds to by using the internally generated clock—see the Using an the specified full-scale errors on the part. On the AD7864-1 and External Clock section. The EOC signal indicates the end of AD7864-3, it also results in an offset error injected in the attenuator each conversion in the conversion sequence. The BUSY signal stage; see Figure 4 and Figure 6. indicates the end of the full conversion sequence, and at this The AD7864 contains an on-chip 2.5 V reference. To use this time, all four track and holds return to tracking mode. The reference as the reference source for the AD7864, simply con- conversion results can be read either at the end of the full nect a 0.1 μF disk ceramic capacitor from the V pin to AGND. REF conversion sequence (indicated by BUSY going low), or as each The voltage that appears at this pin is internally buffered before result becomes available (indicated by EOC going low). Data is being applied to the ADC. If this reference is used externally to read from the part via a 12-bit parallel data bus with standard the AD7864, it should be buffered because the part has a FET CS and RD signals—see the Timing and Control section. switch in series with the reference output resulting in a 6 kΩ Rev. D | Page 11 of 28

AD7864 nominal source impedance for this output. The tolerance on the has the option of connecting an external reference to this V REF internal reference is ±10 mV at 25°C with a typical temperature pin. The external reference effectively overdrives the internal coefficient of 25 ppm/°C and a maximum error overtemperature reference and thus provides the reference source for the ADC. of ±20 mV. The reference input is buffered before being applied to the ADC with the maximum input current of ±100 μA. Suitable reference If the application requires a reference with a tighter tolerance or sources for the AD7864 include the AD680, AD780, REF192, the AD7864 needs to be used with a system reference, the user and REF43 precision 2.5 V references. Rev. D | Page 12 of 28

AD7864 CIRCUIT DESCRIPTION ANALOG INPUT Table 5. Ideal Input/Output Code Table for the AD7864-1 Analog Input1 Digital Output Code Transition The AD7864 is offered in three models: the AD7864-1, where +FSR/2 − 3/2 LSB2 011...110 to 011...111 each input can be configured for ±10 V or a ±5 V input voltage +FSR/2 − 5/2 LSB 011...101 to 011...110 range; the AD7864-3, which handles the input voltage range of +FSR/2 − 7/2 LSB 011...100 to 011...101 ±2.5 V; and the AD7864-2, where each input can be configured to have a 0 V to +2.5 V or 0 V to +5 V input voltage range. AGND + 3/2 LSB 000...001 to 000...010 AGND + 1/2 LSB 000...000 to 000...001 AD7864-1 AGND − 1/2 LSB 111...111 to 000...000 Figure 4 shows the analog input section of the AD7864-1. Each AGND − 3/2 LSB 111...110 to 111...111 input can be configured for ±5 V or ±10 V operation on the −FSR/2 + 5/2 LSB 100...010 to 100...011 AD7864-1. For ±5 V (AD7864-1) operation, the V and V INxA INxB −FSR/2 + 3/2 LSB 100...001 to 100...010 inputs are tied together and the input voltage is applied to both. −FSR/2 + 1/2 LSB 100...000 to 100...001 For ±10 V (AD7864-1) operation, the V input is tied to AGND INxB 1 FSR is full-scale range and is 20 V for the ±10 V range and +10 V for the ±5 V and the input voltage is applied to the V input. The V and INxA INxA range, with VREF = 2.5 V. VINxB inputs are symmetrical and fully interchangeable. Thus for 2 1 LSB = FSR/4096 = 4.883 mV (±10 V for the AD7864-1) and 2.441 mV (±5 V ease of printed circuit board (PCB) layout on the ±10 V range, for the AD7864-1) with VREF = 2.5 V. the input voltage may be applied to the V input while the INxB AD7864-2 V input is tied to AGND. INxA Figure 5 shows the analog input section of the AD7864-2. Each AD7864-1 input can be configured for 0 V to 5 V operation or 0 V to 2.5 V operation. For 0 V to 5 V operation, the V input is tied to INxB 6kΩ 2.5V AGND and the input voltage is applied to the V input. For REFERENCE INxA VREF 0 V to 2.5 V operation, the VINxA and VINxB inputs are tied together and the input voltage is applied to both. The V and V INxA INxB TO ADC inputs are symmetrical and fully interchangeable. Thus for ease REFERENCE CIRCUITRY R1 of PCB layout on the 0 V to 5 V range, the input voltage may be R2 VIN1A applied to the VINxB input while the VINxA input is tied to AGND. For the AD7864-2, R1 = 6 kΩ and R2 = 6 kΩ. The designed R3 VIN1B T/H TCOO MINPTAERRANTAOLR code transitions occur on successive integer least significant bit R4 values. Output coding is straight (natural) binary with 1 LSB = AGND 01341-004 FthSeR 0/4 V0 9t6o =2. 52 .V5 Van/4d0 09 6V = t o0 .56 1V m opVt,i oannds, 5re Vsp/4e0ct9i6v e=ly 1. . 22 mV, for Figure 4. AD7864-1 Analog Input Structure Table 6 shows the ideal input and output transfer function for For the AD7864-1, R1 = 6 kΩ, R2 = 24 kΩ, R3 = 24 kΩ, and the AD7864-2. R4 = 12 kΩ. The resistor input stage is followed by the high input impedance stage of the track-and-hold amplifier. AD7864-2 The designed code transitions take place midway between 6kΩ successive integer least significant bit values (that is, 1/2 LSB, 2.5V REFERENCE 3/2 LSB, 5/2 LSB, and so forth). Least significant bit size is given VREF by the formula 1 LSB = FSR/4096. For the ±5 V range, 1 LSB = 10 V/4096 = 2.44 mV. For the ±10 V range, 1 LSB = 20 V/4096 = TO ADC REFERENCE CIRCUITRY 4.88 mV. Output coding is twos complement binary with 1 LSB = FSR/4096. The ideal input/output transfer function for the VIN1A R1 AD7864-1 is shown in Table 5. R2 VIN1B T/H TCOO MINPTAERRANTAOLR 01341-005 Figure 5. AD7864-2 Analog Input Structure Rev. D | Page 13 of 28

AD7864 Table 6. Ideal Input/Output Code Table for the AD7864-2 The designed code transitions take place midway between Analog Input1 Digital Output Code Transition successive integer least significant bit values (that is, 1/2 LSB, +FSR − 3/2 LSB2 111...110 to 111...111 3/2 LSB, 5/2 LSB, and so on). Least significant bit size is given by +FSR − 5/2 LSB 111...101 to 111...110 the formula 1 LSB = FSR/4096. Output coding is twos comple- +FSR − 7/2 LSB 111...100 to 111...101 ment binary with 1 LSB = FSR/4096 = 5 V/4096 = 1.22 mV. The AGND + 5/2 LSB 000...010 to 000...011 ideal input/ output transfer function for the AD7864-3 is shown AGND + 3/2 LSB 000...001 to 000...010 in Table 7. AGND + 1/2 LSB 000...000 to 000...001 Table 7. Ideal Input/Output Code Table for the AD7864-3 1 FSR is the full-scale range and is 0 V to 2.5 V and 0 V to 5 V for the AD7864-2 Analog Input1 Digital Output Code Transition 2 1w LitShB V =RE FF S=R 2/.450 V9.6 and is 0.61 mV (0 V to 2.5 V) and 1.22 mV (0 V to 5 V) for the +FSR/2 − 3/2 LSB2 011...110 to 011...111 AD7864-2 with VREF = 2.5 V. +FSR/2 − 5/2 LSB 011...101 to 011...110 AD7864-3 +FSR/2 − 7/2 LSB 011...100 to 011...101 Figure 6 shows the analog input section of the AD7864-3. The AGND + 3/2 LSB 000...001 to 000...010 analog input range is ±2.5 V on the V input. The V input AGND + 1/2 LSB 000...000 to 000...001 IN1A IN1B can be left unconnected, but if it is connected to a potential, AGND − 1/2 LSB 111...111 to 000...000 that potential must be AGND. AGND − 3/2 LSB 111...110 to 111...111 −FSR/2 + 5/2 LSB 100...010 to 100...011 AD7864-3 −FSR/2 + 3/2 LSB 100...001 to 100...010 −FSR/2 + 1/2 LSB 100...000 to 100...001 6kΩ 2.5V REFERENCE 1 FSR is the full-scale range and is 5 V, with VREF = 2.5 V. VREF 2 1 LSB = FSR/4096 = 1.22 mV (±2.5 V − AD7864-3) with VREF = 2.5 V. TO ADC REFERENCE CIRCUITRY R1 R2 VIN1A T/H TCOO MINPTAERRANTAOLR VIN1B 01341-006 Figure 6. AD7864-3 Analog Input Structure For the AD7864-3, R1 = 6 kΩ and R2 = 6 kΩ. As a result, drive the V input from a low impedance source. The resistor input IN1A stage is followed by the high input impedance stage of the track- and-hold amplifier. Rev. D | Page 14 of 28

AD7864 SELECTING A CONVERSION SEQUENCE Any subset of the four channels, V to V , can be selected for TIMING AND CONTROL IN1 IN4 conversion. The selected channels are converted in ascending Reading Between Each Conversion in the Conversion order. For example, if the channel selection includes V , V , IN4 IN1 Sequence and V , the conversion sequence is V , V , and then V . IN3 IN1 IN3 IN4 Figure 9 shows the timing and control sequence required to The conversion sequence selection can be made either by using obtain the optimum throughput rate from the AD7864. To the hardware channel select input pins (SL1 through SL4) or by obtain the optimum throughput from the AD7864, the user programming the channel select register. A logic high on a must read the result of each conversion as it becomes available. hardware channel select pin (or Logic 1 in the channel select The timing diagram in Figure 9 shows a read operation each register) when CONVST goes logic high marks the associated time the EOC signal goes logic low. The timing in Figure 9 analog input channel for inclusion in the conversion sequence. shows a conversion on all four analog channels (SL1 to SL4 = 1, Figure 7 shows the arrangement used. The H/S SEL controls a see the Selecting a Conversion Sequence section), thus there are multiplexer that selects the source of the conversion sequence four EOC pulses and four read operations to access the result of information, that is, from the hardware channel select pins (SL1 each of the four conversions. to SL4) or from the channel selection register. When a conver- A conversion is initiated on the rising edge of CONVST. This sion begins, the output from the multiplexer is latched until the places all four track-and-holds into hold simultaneously. New end of the conversion sequence. The data bus bits, DB0 to DB3, data from this conversion sequence is available for the first (DB0 representing Channel 1 through DB3 representing Channel 4) channel selected (V ) 1.65 μs later. The conversion on each are bidirectional and become inputs to the channel select register IN1 subsequent channel is completed at 1.65 μs intervals. The end of when RD is logic high and CS and WR are logic low. The logic each conversion is indicated by the falling edge of the EOC state on DB0 to DB3 is latched into the channel select register signal. The BUSY output signal indicates the end-of-conversion when WR goes logic high. for all selected channels (four in this case). H/S SEL Data is read from the part via a 12-bit parallel data bus with HARDWARE CHANNEL SELECT INDIVIDUAL SELECT PINS TRACK-AND-HOLDS standard CS and RD signals. The CS and RD inputs are SL1 FOR CONVERSION SL2 internally gated to enable the conversion result onto the data D3 DD2ATDA1 BDU0S SSLL34 ER bus. The data lines (DB0 to DB11) leave their high impedance X CHARNENGEILS TSEERLECT LTIPLE LATCH SEQUENCER psteartme wanheennt lbyo ttihed C lSo ganicd l oRwD a anrde ltohgei cR Dlo wsi.g Tnhael ruesfeodre t,o C aSc cceasns bthe e U M conversion result. Because each conversion result is latched into its output data register prior to EOC going logic low, another WR TRANSPARENT WHILE WAITING FOR CONVST. LATCHED ON THE RISING option is to tie the EOC and RD pins together and use the rising EDGE OF CONVST AND DURING A WCSR CONVERSION SEQUENCE. 01341-007 AedDge7 8o6f 4E hOaCs stoom laet cshp ethciea cl ofenavteurrseiso nth raets pueltr.m Ailtt hreoaudgihn gth deu ring a Figure 7. Channel Select Inputs and Registers conversion (such as a separate supply for the output data RD drivers, VDRIVE) for optimum performance it is recommended that the read operation be completed when EOC is logic low, that t 13 is, before the start of the next conversion. Although Figure 10 WR shows the read operation occurring during the EOC pulse, a t t15 read operation can occur at any time. Figure 10 shows a timing 14 specification referred to as the quiet time. Quiet time is the CS amount of time that should be left after a read operation and t16 t17 before the next conversion is initiated. The quiet time depends DATA DATA IN 01341-008 Thehaev siliyg noanl dlaabteal bedu sF cRaSpTaDcitAaTnAce (, fbirustt 5d0a tnas- wtoo r1d0)0 i nnsd iics attyepsi tcoa lt.h e Figure 8. Channel Selection via Software Control user that the pointer associated with the output data registers is pointing to the first conversion result by going logic high. The pointer is reset to point to the first data location (that is, the first conversion result,) at the end of the first conversion (FRSTDATA Rev. D | Page 15 of 28

AD7864 logic high). The pointer is incremented to point to the next is already high when the next conversion sequence initiates. See register (next conversion result) when that conversion result is the Accessing the Output Data Registers section. available. Thus, FRSTDATA in Figure 9 is shown as going low Reading After the Conversion Sequence just prior to the second EOC pulse. Repeated read operations Figure 10 shows the same conversion sequence as Figure 9. In during a conversion continue to access the data at the current this case, however, the results of the four conversions (on V to pointer location until the pointer is incremented at the end of IN1 V ) are read after all conversions have finished, that is, when that conversion. Note that FRSTDATA has an indeterminate IN4 BUSY goes logic low. The FRSTDATA signal goes logic high at logic state after initial power-up. This means that for the first the end of the first conversion just prior to EOC going logic low. conversion sequence after power-up, the FRSTDATA logic As mentioned previously, FRSTDATA has an indeterminate output may already be logic high before the end of the first state after initial power-up, therefore FRSTDATA may already conversion (this condition is indicated by the dashed line in be logic high. Unlike the case when reading between each Figure 9). Also, the FRSTDATA logic output may already be conversion, the output data register pointer is incremented on high as a result of the previous read sequence, as is the case after the rising edge of RD because the next conversion result is the fourth read in Figure 9. The fourth read (rising edge of RD) available. This means FRSTDATA goes logic low after the first resets the pointer to the first data location. Therefore, FRSTDATA rising edge on RD. t1 tACQ CONVST t BUSY QUIET BUSY t2 TIME tCONV tCONV tCONV tCONV t 8 EOC t t 11 10 FRSTDATA t 12 RD t3 t4 t5 CS t t 7 6 DATA VIN1 VIN2 VIN3 VIN4 100ns H/S SEL SL1 TO SL4 100ns 01341-009 Figure 9. Timing Diagram for Reading During Conversion t 1 CONVST t BUSY QUIET BUSY t2 TIME EOC t 8 RD tt33 t 4 CS t t 7 6 DATA VIN1 VIN2 VIN3 VIN4 VIN1 t t FRSTDATA 10 10 01341-010 Figure 10. Timing Diagram, Reading After the Conversion Sequence Rev. D | Page 16 of 28

AD7864 This means a conversion time of 2.6 μs compared to 1.65 μs Successive read operations access the remaining conversion when using the internal clock. In some instances, however, it results in an ascending channel order. Each read operation may be useful to use an external clock when high throughput increments the output data register pointer. The read operation rates are not required. For example, two or more AD7864s can that accesses the last conversion result causes the output data be synchronized by using the same external clock for all register pointer to be reset so that the next read operation accesses devices. In this way, there is no latency between output logic the first conversion result again. This is shown in Figure 10, signals like EOC due to differences in the frequency of the wherein the fifth read after BUSY goes low accessing the result of the conversion on V . Thus, the output data registers act as internal clock oscillators. Figure 11 shows how the various logic IN1 a circular buffer in which the conversion results are continually outputs are synchronized to the CLK signal. Each conversion accessible. The FRSTDATA signal goes high when the first requires 14 clocks. The output data register pointer is reset to conversion result is available. point to the first register location on the falling edge of the 12th clock cycle of the first conversion in the conversion sequence— Data is enabled onto the data bus (DB0 to DB11) using CS and see the Accessing the Output Data Registers section. At this RD. Both CS and RD have the same functionality as described point, the logic output FRSTDATA goes logic high. The result of in the previous section. There are no restrictions or performance the first conversion transfers to the output data registers on the implications associated with the position of the read operations falling edge of the 13th clock cycle. The FRSTDATA signal is after BUSY goes low. The only restriction is that there is minimum reset on the falling edge of the 13th clock cycle of the next time between read operations. Notice that the quiet time must conversion, that is, when the result of the second conversion is be allowed before the start of the next conversion. transferred to its output data register. As mentioned previously, USING AN EXTERNAL CLOCK the pointer is incremented by the rising edge of the RD signal if the result of the next conversion is available. The EOC signal The logic input INT/EXT CLK allows the user to operate the goes logic low on the falling edge of the 13th clock cycle and is AD7864 using the internal clock oscillator or an external clock. reset high again on the falling edge of the 14th clock cycle. To achieve optimum performance on the AD7864, use the internal clock. The highest external clock frequency allowed is 5 MHz. 1 2 3 4 5 6 7 8 9 1011121314 1 2 3 4 5 6 7 8 91011121314 1 2 1314 CLK CONVST FRSTDATA EOC RD FIRST CONVERSION LAST CONVERSION COMPLETE COMPLETE BUSY 01341-011 Figure 11. Using an External Clock Rev. D | Page 17 of 28

AD7864 STANDBY MODE OPERATION 1.0 The AD7864 has a standby mode whereby the device can be 0.9 placed in a low current consumption mode (5 μA typical). The 0.8 s) AD7864 is placed in standby by bringing the Logic Input STBY m 0.7 E ( low. The AD7864 can be powered up again for normal opera- M 0.6 TI tion by bringing STBY logic high. The output data buffers remain UP 0.5 +105°C operational while the AD7864 is in standby. This means the user ER- 0.4 +25°C W O 0.3 can continue to access the conversion results while the AD7864 P 0.2 is in standby. This feature can be used to reduce the average power 0.1 consumption in a system using low throughput rates. To reduce –40°C 0 average power consumption, the AD7864 can be placed in standby agto tehs el oewnd a nodf eias cthak ceonn voeurts oiof ns tsaenqdubeyn acge,a itnh aptr iiso, rw thoe tnh eB sUtaSrYt of 0.0001 0.001 STAN0D.0B1Y TIME (Se0c.1onds) 1 10 01341-012 Figure 12. Power-Up Time vs. Standby Time Using the On-Chip Reference the next conversion sequence. The time it takes the AD7864 to (Decoupled with 0.1 μF Capacitor) come out of standby is referred to as the wake-up time. The ACCESSING THE OUTPUT DATA REGISTERS wake-up time limits the maximum throughput rate at which the There are four output data registers, one for each of the four AD7864 can be operated when powering down between conver- possible conversion results from a conversion sequence. The sion sequences. The AD7864 wakes up in approximately 2 μs when result of the first conversion in a conversion sequence is placed using an external reference. The wake-up time is also 2 μs when in Register 1, the second result is placed in Register 2, and so the standby time is less than 1 ms while using the internal refer- forth. For example, if the conversion sequence V , V , and ence. Figure 12 shows the wake-up time of the AD7864 for IN1 IN3 V is selected (see the Selecting a Conversion Sequence section), standby times greater than 1 ms. Note that when the AD7864 IN4 the results of the conversion on V , V , and V are placed in is left in standby for periods of time greater than 1 ms, the part IN1 IN3 IN4 Register 1 to Register 3, respectively. The output data register requires more than 2 μs to wake up. For example, after initial pointer is reset to point to Register 1 at the end of the first con- power-up using the internal reference, the AD7864 requires 6 ms to power up. The maximum throughput rate that can be version in the sequence, immediately prior to EOC going low. achieved when powering down between conversions is 1/(t + At this point, the logic output, FRSTDATA, goes logic high to BUSY 2 μs) = 100 kSPS, approximately. When operating the AD7864 in a indicate that the output data register pointer is addressing Reg- standby mode between conversions, the power savings can be ister 1. When CS and RD are both logic low, the contents of the significant. For example, with a throughput rate of 10 kSPS, the addressed register are enabled onto the data bus (DB0 to DB11). AD7864 is powered down (IDD = 5 μA) for 90 μs out of every 100 μs (see Figure 13). Therefore, the average power consumption drops to 125/10 mW or 12.5 mW approximately. 100µs t CONVST B7µUsSY tBUSY BUSY t WAKE-UP STBY IDD= 20µA 2µs 01341-013 Figure 13. Power-Down Between Conversion Sequences Rev. D | Page 18 of 28

AD7864 When reading the output data registers after a conversion may be used to enable the register contents onto the data bus, sequence, that is, when BUSY goes low, the register pointer is as described in the Reading Between Each Conversion in the incremented on the rising edge of the RD signal, as shown in Conversion Sequence subsection within the Selecting a Figure 14. However, when reading the conversion results during Conversion Sequence section. The pointer is reset to point the conversion sequence, the pointer is not incremented until a to Register 1 on the rising edge of the RD signal when the last valid conversion result is in the register to be addressed. In this conversion result in the sequence is being read. In the example case, the pointer is incremented when the conversion has ended shown, this means that the pointer is set to Register 1 when the and the result has been transferred to the output data register. contents of Register 3 are read. This happens immediately before EOC goes low, therefore EOC FRSTDATA OUTPUT DATA REGISTERS VDRIVE OE NO. 1 (VIN1) 2-BIT COUNTER DE OE NO. 2 (VIN3) OUTPUT O POINTER* EC OE NO. 3 (VIN4) DRIVERS DB0 TO DB11 D OE OE NO. 4NOT VALID RESET AD7864 RD CS * TITSHH REEE CPSOOEINTNV TWEEHRRES INISO TNNH ORETE LSINAUCSLRTT E CIMSO EINNNV TTEEHRDES BIOOYUN TA RP REUISTSU IDNLAGTT IEASD RRGEEEGA ODISN.T ERRD. UTNHTEI LPOINTER 01341-014 Figure 14. Output Data Registers Rev. D | Page 19 of 28

AD7864 OFFSET AND FULL-SCALE ADJUSTMENT In most digital signal processing (DSP) applications, offset and NEGATIVE FULL-SCALE ADJUST full-scale errors have little or no effect on system performance. Apply a voltage of −9.9976 V (−FS + 1/2 LSB) at V and adjust 1 Offset error can always be eliminated in the analog domain by R2 until the ADC output code flickers between 1000 0000 0000 ac coupling. Full-scale error effect is linear and does not cause and 1000 0000 0001. problems as long as the input signal is within the full dynamic An alternative scheme for adjusting full-scale error in systems range of the ADC. Invariably, some applications require that the that use an external reference is to adjust the voltage at the V input signal spans the full analog input dynamic range. In such REF pin until the full-scale error for any of the channels is adjusted applications, offset and full-scale error have to be adjusted to zero. out. Good full-scale matching of the channels ensures small Figure 15 shows a circuit that can be used to adjust the offset full-scale errors on the other channels. and full-scale errors on the AD7864 (V on the AD7864-1 INxA INPUT version is shown for example purposes only). Where adjustment RANGE = ±10V is required, offset error must be adjusted before full-scale error. V1 This is achieved by trimming the offset of the op amp driving R1 10kΩ the analog input of the AD7864 while the input voltage is 1/2 R2 500Ω LSB below analog ground. The trim procedure is as follows: VINxA apply a voltage of −2.44 mV (−1/2 LSB) at V in Figure 15 and R4 1 adjust the op amp offset voltage until the ADC output code 10kΩ AD7864-1* R3 R5 10kΩ 10kΩ flickers between 1111 1111 1111 and 0000 0000 0000. AGND Adjust gain error at either the first code transition (ADC negative full scale) or the last code transition (ADC positive full scale). The trim procedures for both cases are as follows. *ADDITIONAL PINS OMITTED FOR CLARITY. 01341-015 POSITIVE FULL-SCALE ADJUST Figure 15. Full-Scale Adjust Circuit Apply a voltage of 9.9927 V (FS − 3/2 LSB) at V and adjust R2 1 until the ADC output code flickers between 0111 1111 1110 and 0111 1111 1111. Rev. D | Page 20 of 28

AD7864 DYNAMIC SPECIFICATIONS The AD7864 is specified and 100% tested for dynamic perfor- graph is 72.6 dB. Note that the harmonics are taken into mance specifications as well as traditional dc specifications, such account when calculating the SNR. as integral and differential nonlinearity. These ac specifications are 0 AD7864-1 @ 25°C required for signal processing applications such as phased array –10 5V SUPPLY SAMPLINGAT 499,712Hz sonar, adaptive filters, and spectrum analysis. These applications –20 INPUT FREQUENCY OF 99,857Hz 8192 SAMPLESTAKEN require information on the effect of the ADC on the spectral –30 content of the input signal. Thus, the parameters for which the –40 AD7864 is specified include SNR, harmonic distortion, inter- B) –50 modulation distortion, and peak harmonics. These terms are (d –60 discussed in more detail in the following sections. –70 SIGNAL-TO-NOISE RATIO (SNR) –80 –90 SNR is the measured signal-to-noise ratio at the output of the –100 ADC. The signal is the rms magnitude of the fundamental. –110 Nhaolifs oef i sth teh es armmpsl isnugm f roefq aulel nthcey n(foS/n2f)u enxdcalmudeinntga ld sci.g SnNalRs udpep toen ds 0 50 F1R0E0QUENCY (1k5H0z) 200 250 01341-017 on the number of quantization levels used in the digitization Figure 17. FFT Plot process; the more levels, the smaller the quantization noise. The EFFECTIVE NUMBER OF BITS theoretical signal-to-noise ratio for a sine wave input is given by The formula given in Equation 1 relates the SNR to the number SNR = (6.02N + 1.76) dB (1) of bits. Rewriting the formula, as in Equation 2, it is possible to where N is the number of bits. get a measure of performance expressed in effective number of bits (N). Thus, for an ideal 12-bit converter, SNR = 74 dB. SNR−1.76 Figure 16 shows a histogram plot for 8192 conversions of a dc N = (2) 6.02 input using the AD7864 with a 5 V supply. The analog input was The effective number of bits for a device can be calculated set at the center of a code. The figure shows that all the codes directly from its measured SNR. Figure 18 shows a typical plot appear in the one output bin, indicating very good noise of effective number of bits vs. frequency for an AD7864-2. performance from the ADC. 12 9000 8000 11 S –40°C 7000 BIT 10 F +25°C 6000 S O 9 UNTS 5000 MBER 8 O U +105°C C 4000 E N V 7 TI 3000 C E F 6 F 2000 E 5 1000 0 1054 1055 1056 1057 10A58DC1 0C5O9D1E060 1061 1062 1063 1064 01341-016 40 500 100F0REQU1E5N0C0Y (kHz2)000 2500 3000 01341-018 Figure 16. Histogram of 8192 Conversions of a DC Input Figure 18. Effective Numbers of Bits vs. Frequency The output spectrum from the ADC is evaluated by applying a INTERMODULATION DISTORTION sine wave signal of very low distortion to the analog input. A With inputs consisting of sine waves at two frequencies, fa and fast fourier transform (FFT) plot is generated from which the fb, any active device with nonlinearities creates distortion products SNR data can be obtained. Figure 17 shows a typical 4096 point at sum and difference frequencies of mfa ± nfb where m, n = 0, FFT plot of the AD7864 with an input signal of 99.9 kHz and a 1, 2, 3, and so forth. Intermodulation terms are those for which sampling frequency of 500 kHz. The SNR obtained from this neither m nor n are equal to zero. For example, the second-order Rev. D | Page 21 of 28

AD7864 terms include (fa + fb) and (fa − fb), whereas the third-order 2.5 terms include (2fa + fb), (2fa − fb), (fa + 2fb), and (fa − 2fb). 2.0 Using the CCIF standard where two input frequencies near the 1.5 top end of the input bandwidth are used, the second- and third- 1.0 order terms are of different significance. The second-order 0.5 B) S terms are usually distanced in frequency from the original sine L (L 0 waves, whereas the third-order terms are usually at a frequency N I –0.5 close to the input frequencies. As a result, the second- and –1.0 third-order terms are specified separately. The calculation of the –1.5 intermodulation distortion is as per the THD specification –2.0 where it is the ratio of the rms sum of the individual distortion –2.5 pdreocidbueclsts. Itno tthhies rcmasse a, mthpel iintupduet ocfo nthseis ftus nodf atwmoe,n etqaul aexl pamrepsslietdu dine , 0 500 1000 1500ADC20 C0O0DE2500 3000 3500 4000 01341-021 low distortion sine waves. Figure 19 shows a typical IMD plot Figure 21. Typical INL Plot for the AD7864. MEASURING APERTURE JITTER 0 AD7864-1 @ 25°C A convenient way to measure aperture jitter is to use the –10 5V SUPPLY SAMPLINGAT 131072Hz relationship it is known to have with SNR (signal-to-noise plus INPUT FREQUENCY OF –20 48,928HzAND 50,016Hz distortion) given as follows: 4096 SAMPLESTAKEN –30 ⎛ 1 ⎞ dB)––5400 SNRJITTER =20×log10⎜⎜⎝(2)×π× fIN ×σ ⎟⎟⎠ (3) ( –60 where: SNR is the signal-to-noise due to the rms time jitter. –70 JITTER σ is the rms time jitter. –80 f is the sinusoidal input frequency (1 MHz in this case). IN –90 Equation 3 demonstrates that the signal-to-noise ratio due to –100 0 10 20FREQU3E0NCY (kH4z0) 50 60 01341-019 jqiutteenr cdieegs,r athdee sm seigansuifriecdan StNlyR w pitehr fforermquaennccey o. Af tth loe wA Din7p8u6t4 f ries - Figure 19. IMD Plot indicative of noise performance due to quantization noise and AC LINEARITY PLOTS system noise only (72 dB used as a typical figure in this example). The plots shown in Figure 20 and Figure 21 show typical DNL Therefore, by measuring the overall SNR performance and INL plots for the AD7864. (including noise due to jitter, system, and quantization) of the 3 AD7864, a good estimation of the jitter performance of the AD7864 can be calculated. 2 12 1 11 B) S L (L 0 10 N D 9 –1 B O N E 8 –2 7 –3 0 500 1000 1500ADC20 C0O0DE2500 3000 3500 4000 01341-020 6 Figure 20. Typical DNL Plot 5 900k 950k FREQU1.E0N0MCY (Hz) 1.05M 1.10M 01341-022 Figure 22. ENOB of the AD7864 at 1 MHz Rev. D | Page 22 of 28

AD7864 From Figure 22, the ENOB of the AD7864 at 1 MHz is From Equation 3 approximately 11 bits. This is equivalent to 68 dB SNR. 70.2 dB = 20 × log [1/(2 × π × 1 MHz × σ)] 10 SNR = SNR + SNR = 68 dB TOTAL JITTER QUANT σ = 49 ps 68 dB = SNR + 72 dB (at 100 kHz) JITTER where σ is the rms jitter of the AD7864. SNR = 70.2 dB JITTER Rev. D | Page 23 of 28

AD7864 MICROPROCESSOR INTERFACING The high speed parallel interface of the AD7864 allows easy requirements. The following instruction is used to read the interfacing to most DSPs and microprocessors. This interface conversion results from the AD7864: consists of the data lines (DB0 to DB11), CS, RD, WR, EOC, IN D,ADC and BUSY. where D is the data memory address and ADC is the AD7864 AD7864 TO ADSP-2100/ADSP-2101/ADSP-2102 address. INTERFACE TMS320C5x Figure 23 shows an interface between the AD7864 and the ADDRESS A0 TO A13 ADSP-210x. The CONVST signal can be generated by the DECODE DS ADSP-210x or from some other external source. Figure 23 shows the CS being generated by a combination of the DMS VIN1 CS VIN2 RD RD signal and the address bus of the ADSP-210x. In this way, the VIN3 WR WE AD7864 is mapped into the data memory space of the VIN4 DB0 TO DB11 D0 TO D15 ADSP-210x. AD7864 The AD7864 BUSY line provides an interrupt to the ADSP-210x BUSY INTn wchhaennn tehlse. cTohnev ceorsnivoenr ssieoqnu reenscuel tiss ccaonm tphleente b oen r eaalld t hfreo smel ethctee d CONVST PA0 01341-024 AD7864 using successive read operations. Alternately, one can Figure 24. AD7864 to TMS320C5x Interface use the EOC pulse to interrupt the ADSP-210x when the AD7864 TO MC68HC000 INTERFACE conversion on each channel is complete when reading between An interface between the AD7864 and the MC68HC000 is each conversion in the conversion sequence (Figure 9). The shown in Figure 25. The conversion can be initiated from the AD7864 is read using the following instruction: MC68HC000 or from an external source. The AD7864 BUSY MR0 = DM(ADC) line can be used to interrupt the processor or, alternatively, where MR0 is the ADSP-210x MR0 register and ADC is the software delays can ensure that the conversion has been AD7864 address. completed before a read to the AD7864 is attempted. Because of the nature of its interrupts, the MC68HC000 requires additional ADSP-210x logic (not shown in Figure 25) to allow it to be interrupted ADDRESS A0 TO A13 correctly. For further information on MC68HC000 interrupts, DECODE DMS consult the Addendum to MC68000 Users Manual. VIN1 CS The MC68HC000 AS and R/W outputs are used to generate a VIN2 RD RD VIN3 WR WR separate RD input signal for the AD7864. RD is used to drive VIN4 the MC68HC000 DTACK input to allow the processor to DB0 TO DB11 D0 TO D24 execute a normal read operation to the AD7864. The conversion AD7864 results are read using the following MC68HC000 instruction: BUSY IRQn MOVE.W ADC,D0 CONVST DT1/F0 01341-023 where D0 is the MC68HC000 D0 register and ADC is the Figure 23. AD7864 to ADSP-210x Interface AD7864 address. AD7864 TO TMS320C5x INTERFACE Figure 24 shows an interface between the AD7864 and the TMS320C5x. As with the previous interfaces, conversion can be initiated from the TMS320C5x or from an external source, and the processor is interrupted when the conversion sequence is completed. The CS signal to the AD7864 is derived from the DS signal and a decode of the address bus. This maps the AD7864 into external data memory. The RD signal from the TMS320C5x is used to enable the ADC data onto the data bus. The AD7864 has a fast parallel bus, consequently there are no wait state Rev. D | Page 24 of 28

AD7864 Vector control of an ac motor involves controlling phase in MC68HC000 addition to drive and current frequency. Controlling the phase ADDRESS A0 TO A15 DECODE of the motor requires feedback information on the position of the rotor relative to the rotating magnetic field in the motor. VIN1 CS Using this information, a vector controller mathematically trans- VIN2 DTACK VIN3 AS forms the three-phase drive currents into separate torque and VIN4 RD R/W flux components. The AD7864, with its 4-channel simultaneous AD7864 sampling capability, is ideally suited for use in vector motor DB0 TO DB11 D0 TO D15 control applications. A block diagram of a vector motor control application using the CONVST CLOCK 01341-025 AD7864 is shown in Figure 26. The position of the field is derived by determining the current in each phase of the motor. Only Figure 25. AD7864 to MC68HC000 Interface two phase currents need to be measured because the third can VECTOR MOTOR CONTROL be calculated if two phases are known. V and V of the IN1 IN2 The current drawn by a motor can be split into two components: AD7864 are used to digitize this information. one produces torque and the other produces magnetic flux. For Simultaneous sampling is critical to maintain the relative phase optimal performance of the motor, control these two compo- information between the two channels. A current sensing isola- nents independently. In conventional methods of controlling tion amplifier, transformer, or Hall effect sensor is used between a three-phase motor, the current (or voltage) supplied to the the motor and the AD7864. Rotor information is obtained by motor and the frequency of the drive are the basic control measuring the voltage from two of the inputs to the motor. V IN3 variables. However, both the torque and flux are functions of and V of the AD7864 are used to obtain this information. IN4 current (or voltage) and frequency. This coupling effect can Once again, the relative phase of the two channels is important. reduce the performance of the motor because, for example, if A DSP microprocessor is used to perform the mathematical the torque is increased by increasing the frequency, the flux transformations and control loop calculations on the tends to decrease. information fed back by the AD7864. DSP MICROPROCESSOR IC DAC TORQUE AND FLUX CACLOCNUTLRAOTILO LNOSO APND DAC CIRDCRUIVITERY IB VB TPHHRAESEE- PHATSWEO I NTFOO TRHMRAETEION IA VA MOTOR DAC TORQUE + SETPFOLIUNXT + – AISMOPLLAIFTIIEORNS SETPOINT – VIN1 TRANSFORMATION VIN2 TO TORQUE AND FLUX CURRENT AD7864* COMPONENTS VIN3 VIN4 *ADDITIONAL PINS OMITTED FOR CLARITY. ATTVEONLUTAATGOERS 01341-027 Figure 26. Vector Motor Control Using the AD7864 Rev. D | Page 25 of 28

AD7864 MULTIPLE AD7864S IN A SYSTEM the different channels. The AD7864 has a maximum aperture delay matching of 4 ns. Figure 27 shows a system where a number of AD7864s are configured to handle multiple input channels. This type of All AD7864s use the same external SAR clock (5 MHz). configuration is common in applications such as sonar and Therefore, the conversion time for all devices is identical; radar. The AD7864 is specified with maximum limits on consequently, all devices can be read simultaneously. In the aperture delay match. This means that the user knows the example shown in Figure 27, the data outputs of two AD7864s difference in the sampling instant between all channels. This are enabled onto a 32-bit wide data bus when EOC goes low. allows the user to maintain relative phase information between VIN1 EOC ADSP-2106x VIN2 12 32 VIN3 AD7864 REF193 VIN4 VREF CS CLKIN RD RD VIN1 VIN2 12 VIN3 AD7864 VIN4 VREF CS ADDRESS DECODE CLKIN RD 5MHz 01341-026 Figure 27. Multiple AD7864s in Multichannel System Rev. D | Page 26 of 28

AD7864 OUTLINE DIMENSIONS 14.15 1.03 2.45 13.90 SQ 0.88 MAX 13.65 0.73 44 34 1.95 REF 1 33 SEATING PIN 1 PLANE TOP VIEW 10.20 (PINS DOWN) 10.00 SQ 9.80 2.20 2.00 0.23 1.80 0.11 11 23 0.25 MIN 7° 12 22 0.10 0° COPLANARITY 0.45 VIEW A 0.30 0.80 BSC LEAD WIDTH VIEW A LEAD PITCH ROTATED 90° CCW COMPLIANTTO JEDEC STANDARDS MO-112-AA-1 041807-A Figure 28. 44-Lead Metric Quad Flat Package [MQFP] (S-44-2) Dimensions shown in millimeters ORDERING GUIDE Relative Temperature Package Model Input Ranges Accuracy Range1 Package Description Option AD7864ASZ-12 ±5 V, ±10 V ±1 LSB −40°C to +85°C 44-Lead MQFP S-44-2 AD7864ASZ-1REEL2 ±5 V, ±10 V ±1 LSB −40°C to +85°C 44-Lead MQFP S-44-2 AD7864BSZ-12 ±5 V, ±10 V ±0.5 LSB −40°C to +85°C 44-Lead MQFP S-44-2 AD7864BSZ-1REEL2 ±5 V, ±10 V ±0.5 LSB −40°C to +85°C 44-Lead MQFP S-44-2 AD7864ASZ-22 0 V to 2.5 V, 0 V to 5 V ±1 LSB −40°C to +85°C 44-Lead MQFP S-44-2 AD7864ASZ-2REEL2 0 V to 2.5 V, 0 V to 5 V ±1 LSB −40°C to +85°C 44-Lead MQFP S-44-2 AD7864ASZ-32 ±2.5 V ±1 LSB −40°C to +85°C 44-Lead MQFP S-44-2 AD7864ASZ-3REEL2 ±2.5 V ±1 LSB −40°C to +85°C 44-Lead MQFP S-44-2 EVAL-AD7864-2CB3 Evaluation Board EVAL-AD7864-3CB3 Evaluation Board EVAL-CONTROL BRD24 Controller Board 1 The A version is fully specified up to 105°C with a maximum sample rate of 450 kSPS and IDD maximum (normal mode) of 26 mA. 2 Z = RoHS Compliant Part. 3 This can be used as a stand alone evaluation board or in conjunction with the Evaluation Controller Board for evaluation/demonstration purposes. 4 This board is a complete unit, allowing a PC to control and communicate with all Analog Devices, Inc., evaluation boards ending in the CB designators. To order a complete evaluation kit, the particular ADC evaluation board needs to be ordered, for example, EVAL-AD7864-1CB, the EVAL-CONTROL BRD2, and a 12 V ac transformer. See the Evaluation Board application note for more information. Rev. D | Page 27 of 28

AD7864 NOTES ©1998–2009 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D01341-0-2/09(D) Rev. D | Page 28 of 28

Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: A nalog Devices Inc.: AD7864ASZ-1 AD7864BSZ-1REEL AD7864ASZ-3 AD7864ASZ-2 AD7864ASZ-2REEL AD7864BSZ-1 AD7864ASZ-1REEL