LC2MOS 16-Bit Voltage Output DAC Data Sheet AD7846 FEATURES FUNCTIONAL BLOCK DIAGRAM 16-bit monotonicity over temperature VCC VDD 21 4 ±2 LSBs integral linearity error Microprocessor compatible with readback capability VREF+ 7 AD7846 R R Unipolar or bipolar output A2 6 RIN R Multiplying capability 16 SEGMENT Low power (100 mW typical) R SWITCH A3 5 VOUT MATRIX 12-BIT DAC R 12 VREF– 8 A1 DAC LATCH 23 CS 4 12 CONTROL 22 R/W LOGIC 25 LDAC I/O LATCH 24 CLR VS9S DB1105DB30 DG20ND 08490-001 Figure 1. GENERAL DESCRIPTION The AD7846 is a 16-bit DAC constructed with the Analog Devices, This means that the DAC output can be reset to 0 V in both the Inc., LC2MOS process. It has V and V reference inputs unipolar and bipolar configurations. REF+ REF− and an on-chip output amplifier. These can be configured to The AD7846 is available in 28-lead plastic, ceramic, and PLCC give a unipolar output range (0 V to +5 V, 0 V to +10 V) or packages. bipolar output ranges (±5 V, ±10 V). PRODUCT HIGHLIGHTS The DAC uses a segmented architecture. The four MSBs in the 1. 16-Bit Monotonicity DAC latch select one of the segments in a 16-resistor string. The guaranteed 16-bit monotonicity over temperature Both taps of the segment are buffered by amplifiers and fed to a makes the AD7846 ideal for closed-loop applications. 12-bit DAC, which provides a further 12 bits of resolution. This 2. Readback architecture ensures 16-bit monotonicity. Excellent integral The ability to read back the DAC register contents linearity results from tight matching between the input offset minimizes software routines when the AD7846 is used in voltages of the two buffer amplifiers. ATE systems. In addition to the excellent accuracy specifications, the AD7846 3. Power Dissipation also offers a comprehensive microprocessor interface. There are Power dissipation of 100 mW makes the AD7846 the 16 data I/O pins, plus control lines (CS, R/W, LDAC and CLR). lowest power, high accuracy DAC on the market. R/W and CS allow writing to and reading from the I/O latch. This is the readback function, which is useful in ATE applications. LDAC allows simultaneous updating of DACs in a multi-DAC system and the CLR line will reset the contents of the DAC latch to 00…000 or 10…000 depending on the state of R/W. Rev. H Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Tel: 781.329.4700 ©2000–2017 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com

AD7846 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Output Stage ................................................................................ 12 Functional Block Diagram .............................................................. 1 Unipolar Binary Operation ........................................................... 13 General Description ......................................................................... 1 Bipolar Operation ........................................................................... 14 Product Highlights ........................................................................... 1 Multiplying Operation ............................................................... 14 Revision History ............................................................................... 2 Position Measurement Application .............................................. 15 Specifications ..................................................................................... 3 Microprocessor Interfacing ........................................................... 16 AC Performance Characteristics ................................................ 4 AD7846-to-8086 Interface ........................................................ 16 Timing Characteristics ................................................................ 5 AD7846-to-MC68000 Interface ............................................... 16 Absolute Maximum Ratings ............................................................ 6 Digital Feedthrough ....................................................................... 17 ESD Caution .................................................................................. 6 Application Hints ........................................................................... 18 Pin Configurations and Function Descriptions ........................... 7 Noise ............................................................................................ 18 Typical Performance Characteristics ............................................. 8 Grounding ................................................................................... 18 Terminology .................................................................................... 10 Printed Circuit Board Layout ................................................... 18 Circuit Description ......................................................................... 11 Outline Dimensions ....................................................................... 20 Digital Section ............................................................................. 11 Ordering Guide .......................................................................... 22 Digital-to-Analog Conversion .................................................. 11 REVISION HISTORY 8/2017—Rev. G to Rev. H Changes to Figure 7 Caption and Figure 8 Caption..................... 7 Changes to Ordering Guide .......................................................... 22 4/2010—Rev. F to Rev. G Change to Figure 1 ........................................................................... 1 12/2009—Rev. E to Rev. F Updated Format .................................................................. Universal Changes to Table 4 ............................................................................ 6 Deleted Other Output Voltage Ranges Section ............................ 9 Deleted Figure 20 and Table 5; Renumbered Sequentially ......... 9 Deleted Test Application Section and Figure 21 ........................ 10 Deleted Figure 29 to Figure 31 ...................................................... 14 Changes to Printed Circuit Board Layout Section ..................... 18 Updated Outline Dimensions ....................................................... 20 Changes to Ordering Guide .......................................................... 22 Rev. H | Page 2 of 24

Data Sheet AD7846 SPECIFICATIONS V = +14.25 V to +15.75 V; V = −14.25 V to –15.75 V; V = +4.75 V to +5.25 V. V loaded with 2 kΩ, 1000 pF to 0 V; V = +5 V; DD SS CC OUT REF+ R connected to 0 V. All specifications T to T , unless otherwise noted. IN MIN MAX Table 1. Parameter1 J, A Versions K, B Versions Unit Test Conditions/Comments RESOLUTION 16 16 Bits UNIPOLAR OUTPUT V = 0 V, V = 0 V to +10 V REF− OUT Relative Accuracy at +25°C ±12 ±4 LSB typ 1 LSB = 153 μV T to T ±16 ±8 LSB max MIN MAX Differential Nonlinearity Error ±1 ±0.5 LSB max All grades guaranteed monotonic Gain Error at +25°C ±12 ±6 LSB typ V load = 10 MΩ OUT T to T ±16 ±16 LSB max MIN MAX Offset Error at +25°C ±12 ±6 LSB typ T to T ±16 ±16 LSB max MIN MAX Gain TC2 ±1 ±1 ppm FSR/°C typ Offset TC2 ±1 ±1 ppm FSR/°C typ BIPOLAR OUTPUT V = –5 V, V = −10 V to +10 V REF− OUT Relative Accuracy at +25°C ±6 ±2 LSB typ 1 LSB = 305 μV T to T ±8 ±4 LSB max MIN MAX Differential Nonlinearity Error ±1 ±0.5 LSB max All grades guaranteed monotonic Gain Error at +25°C ±6 ±4 LSB typ V load = 10 MΩ OUT T to T ±16 ±16 LSB max MIN MAX Offset Error at +25°C ±6 ±4 LSB typ V load = 10 MΩ OUT T to T ±16 ±12 LSB max MIN MAX Bipolar Zero Error at +25°C ±6 ±4 LSB typ T to T ±12 ±8 LSB max MIN MAX Gain TC2 ±1 ±1 ppm FSR/°Ctyp Offset TC2 ±1 ±1 ppm FSR/°Ctyp Bipolar Zero TC2 ±1 ±1 ppm FSR/°Ctyp REFERENCE INPUT Input Resistance 20 20 kΩ min Resistance from V to V REF+ REF− 40 40 kΩ max Typically 30 kΩ V Range V + 6 to V + 6 to V min to REF+ SS SS V − 6 V − 6 V max DD DD V Range V + 6 to V + 6 to V min to REF− SS SS V − 6 V − 6 V max DD DD OUTPUT CHARACTERISTICS Output Voltage Swing V + 4 to V + 4 to V max SS SS V − 3 V − 3 DD DD Resistive Load 2 2 kΩ min To 0 V Capacitive Load 1000 1000 pF max To 0 V Output Resistance 0.3 0.3 Ω typ Short Circuit Current ±25 ±25 mA typ To 0 V or any power supply DIGITAL INPUTS V (Input High Voltage) 2.4 2.4 V min IH V (Input Low Voltage) 0.8 0.8 V max IL I (Input Current) ±10 ±10 μA max IN C (Input Capacitance)2 10 10 pF max IN Rev. H | Page 3 of 24

AD7846 Data Sheet Parameter1 J, A Versions K, B Versions Unit Test Conditions/Comments DIGITAL OUTPUTS V (Output Low Voltage) 0.4 0.4 V max I = 1.6 mA OL SINK V (Output High Voltage) 4.0 4.0 V min I = 400 μA OH SOURCE Floating State Leakage Current ±10 ±10 μA max DB0 to DB15 = 0 to V CC Floating State Output Capacitance2 10 10 pF max POWER REQUIREMENTS3 V +11.4/+15.75 +11.4/+15.75 V min/V max DD V −11.4/−15.75 −11.4/−15.75 V min/V max SS V +4.75/+5.25 +4.75/+5.25 V min/V max CC I 5 5 mA max V unloaded DD OUT I 5 5 mA max V unloaded SS OUT I 1 1 mA max CC Power Supply Sensitivity4 1.5 1.5 LSB/V max Power Dissipation 100 100 mW typ V unloaded OUT 1 Temperature ranges as follows: J, K versions: 0°C to +70°C; A, B versions: −40°C to +85°C. 2 Guaranteed by design and characterization, not production tested. 3 The AD7846 is functional with power supplies of ±12 V. See the Typical Performance Characteristics section. 4 Sensitivity of gain error, offset error, and bipolar zero error to V , V variations. DD SS AC PERFORMANCE CHARACTERISTICS These characteristics are included for design guidance and are not subject to test. V = +5 V; V = +14.25 V to +15.75 V; V = −14.25 V REF+ DD SS to −15.75 V; V = +4.75 V to +5.25 V; R connected to 0 V, unless otherwise noted. CC IN Table 2. Parameter Limit at T to T (All Versions) Unit Test Conditions/Comments MIN MAX Output Settling Time1 6 μs max To 0.006% FSR, V loaded, V = 0 V, typically 3.5 μs OUT REF− 9 μs max To 0.003% FSR, V loaded, V = –5 V, typically 6.5 μs OUT REF− Slew Rate 7 V/μs typ Digital-to-Analog Glitch Impulse 70 nV-sec typ DAC alternately loaded with 10…0000 and 01…1111, V unloaded OUT AC Feedthrough 0.5 mV p-p typ V = 0 V, V = 1 V rms, 10 kHz sine wave, DAC loaded REF− REF+ with all 0s Digital Feedthrough 10 nV-sec typ DAC alternately loaded with all 1s and all 0s. CS high Output Noise Voltage 50 nV/√Hz typ Measured at V , DAC loaded with 0111011…11, OUT Density, 1 kHz to 100 kHz V = V = 0 V REF+ REF− 1 LDAC = 0. Settling time does not include deglitching time of 2.5 µs (typ). Rev. H | Page 4 of 24

Data Sheet AD7846 TIMING CHARACTERISTICS V = +14.25 V to +15.75 V, V = −14.25 V to −15.75 V, V = +4.75 V to +5.25 V, unless otherwise noted. DD SS CC Table 3. Parameter1 Limit at T to T (All Versions) Unit Test Conditions/Comments MIN MAX t 0 ns min R/W to CS setup time 1 t 60 ns min CS pulse width (write cycle) 2 t 0 ns min R/W to CS hold time 3 t 60 ns min Data setup time 4 t 0 ns min Data hold time 5 t2 120 ns max Data access time 6 t3 10 ns min Bus relinquish time 7 60 ns max t 0 ns min CLR setup time 8 t 70 ns min CLR pulse width 9 t 0 ns min CLR hold time 10 t 70 ns min LDAC pulse width 11 t 130 ns min CS pulse width (read cycle) 12 1 Timing specifications are sample tested at +25°C to ensure compliance. All input control signals are specified with tR = tF = 5 ns (10% to 90% of +5 V) and timed from a voltage level of 1.6 V. 2 t is measured with the load circuits of Figure 3 and Figure 4 and defined as the time required for an output to cross 0.8 V or 2.4 V. 6 3 t is defined as the time required for an output to change 0.5 V when loaded with the circuits of Figure 5 and Figure 6. 7 t1 t3 t1 t3 5V R/W t2 t12 05VV CS t4 t5 t6 t7 0V DB0 5V TO DATA VALID DATA VALID DB15 t8 t9 t10 t8 t9 t10 0V 5V CLR 0V t11 LDAC 50VV 08490-006 Figure 2. Timing Diagram DBn DBn 3kΩDGND 100pF 08490-002 3kΩDGND 10pF 08490-004 Figure 3. Load Circuit for Access Time (t)—High Z to V Figure 5. Load Circuit for Access Time (t)—High Z to V 6 OH 7 OH 5V 5V 3kΩ 3kΩ DBn DBn 1D0G0NpDF 08490-003 1D0GpNFD 08490-005 Figure 4. Load Circuits for Bus Relinquish Time (t)—High Z to V Figure 6. Load Circuits for Bus Relinquish Time (t)—High Z to V 6 OL 7 OL Rev. H | Page 5 of 24

AD7846 Data Sheet ABSOLUTE MAXIMUM RATINGS Table 4. Stresses at or above those listed under Absolute Maximum Parameter Rating Ratings may cause permanent damage to the product. This is a V to DGND −0.4 V to +17 V stress rating only; functional operation of the product at these DD V to DGND −0.4 V, V + 0.4 V, or +7 V or any other conditions above those indicated in the operational CC DD (whichever is lower) section of this specification is not implied. Operation beyond V to DGND +0.4 V to −17 V the maximum operating conditions for extended periods may SS V to DGND V + 0.4 V, V − 0.4 V affect product reliability. REF+ DD SS VREF− to DGND VDD + 0.4 V, VSS − 0.4 V ESD CAUTION V to DGND1 V + 0.4 V, V − 0.4 V, or ±10 V OUT DD SS (whichever is lower) R to DGND V + 0.4 V, V − 0.4 V IN DD SS Digital Input Voltage to DGND −0.4 V to V + 0.4 V CC Digital Output Voltage to DGND −0.4 V to V + 0.4 V CC Power Dissipation (Any Package) To +75°C 1000 mW Derates above +75°C 10 mW/°C Operating Temperature Range J, K Versions 0°C to +70°C A, B Versions −40°C to +85°C Storage Temperature Range −65°C to +150°C Lead Temperature (Soldering) +300°C 1 V can be shorted to DGND, V , V , or V provided that the power OUT DD SS CC dissipation of the package is not exceeded. Rev. H | Page 6 of 24

Data Sheet AD7846 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS DB2 1 28 DB3 VDD DB0 DB1 DB2 DB3 DB4 DB5 DB1 2 27 DB4 4 3 2 1 28 27 26 DB0 3 26 DB5 VOUT 5 PIN 1 25LDAC IDENTIFIER VDD 4 25 LDAC RIN 6 24CLR VOUT 5 24 CLR VREF+ 7 AD7846 23CS RIN 6 AD7846 23 CS VREF– 8 TOP VIEW 22R/W VREF+ 7 TOP VIEW 22 R/W VSS 9 (Not to Scale) 21 VCC VREF– 8 (Not to Scale) 21 VCC DB15 10 20DGND VSS 9 20 DGND DB14 11 19DB6 DB15 10 19 DB6 12 13 14 15 16 17 18 DDBB1134 1112 1187 DDBB87 DB13 DB12 DB11 DB10 DB9 DB8 DB7 08490-008 DDBB1112 1134 1165 DDBB190 08490-007 Figure 7. PDIP or CERDIP Pin Configuration Figure 8. PLCC or LCC Pin Configuration Table 5. Pin Function Descriptions Pin Mnemonic Description 1 to 3 DB2 to DB0 Data I/Os. DB0 is LSB. 4 V Positive Supply for Analog Circuitry. This is +15 V nominal. DD 5 V DAC Output Voltage. OUT 6 R Input to Summing Resistor of DAC Output Amplifier. This is used to select output voltage ranges. See Table 6. IN 7 V V Input. The DAC is specified for V = +5 V. REF+ REF+ REF+ 8 V V Input. For unipolar operation connect V to 0 V, and for bipolar operation connect it to −5 V. The device is REF− REF− REF− specified for both conditions. 9 V Negative Supply for the Analog Circuitry. This is −15 V nominal. SS 10 to 19 DB15 to DB6 Data I/Os. DB15 is MSB. 20 DGND Ground for Digital Circuitry. 21 V Positive Supply for Digital Circuitry. This is +5 V nominal. CC 22 R/WE R/WE Input. This pin can be used to load data to the DAC or to read back the DAC latch contents. 23 CSE Chip Select Input. This pin selects the device. 24 CLRE Clear Input. The DAC can be cleared to 000…000 or 100…000. See Table 7. 25 LDACE Asynchronous Load Input to DAC. 26 to 28 DB5 to DB3 Data I/Os. Table 6. Output Voltage Ranges Output Range V V R REF+ REF− IN 0 V to +5 V +5 V 0 V V OUT 0 V to +10 V +5 V 0 V 0 V +5 V to −5 V +5 V −5 V V OUT +5 V to −5 V +5 V 0 V +5 V +10 V to −10 V +5 V −5 V 0 V Rev. H | Page 7 of 24

AD7846 Data Sheet TYPICAL PERFORMANCE CHARACTERISTICS 500 A1 –0.40V 450 VREF+ = VREF– = 0V V/√Hz) 400 GDAACIN L =O +A1DED WITH ALL 1s n Y ( 350 T NSI 300 E D L 250 A R T 200 C E SP 150 E OIS 100 N 1V 2mV 20µs 08490-009 500100 1k FREQU1E0NkCY (Hz) 100k 1M 08490-012 Figure 9. AC Feedthrough, VREF+ = 1 V rms, 10 kHz Sine Wave Figure 12. Noise Spectral Density 8 VDD = +15V 7 VSS = –15V VREF+ = +1V rms 6 VREF– = 0V VOUT 50mV/DIV p) 5 p- V m 4 (UT O V 3 2 1 DATA 5V/DIV 0100 1k FREQU1E0NkCY (Hz) 100k 1M 08490-010 0.5µs/DIV 08490-013 Figure 10. AC Feedthrough to VOUT vs. Frequency Figure 13. Digital-to-Analog Glitch Impulse Without Internal Deglitcher (10…000 to 011…111 Transition) 30 VDD = +15V VSS = –15V 25 VREF+ = ±5V SINE WAVE VREF– = 0V GAIN = +2 VOUT 50mV/DIV 20 p) p- V 15 (OUT LDAC 5V/DIV V 10 5 DATA 5V/DIV 010 100 1kFREQU1E0NkCY (Hz)100k 1M 10M 08490-011 1µs/DIV 08490-014 Figure 11. Large Signal Frequency Response Figure 14. Digital-to-Analog Glitch Impulse with Internal Deglitcher (10…000 to 011…111 Transition) Rev. H | Page 8 of 24

Data Sheet AD7846 4.0 A1 0V TA = +25°C 3.5 VREF+ = +5V VREF+, ±5V VGRAEIFN– = = +01V 3.0 B) 2.5 S L L ( N 2.0 I 1.5 VOUT+, ±10V 1.0 10V 5V 2µs 08490-015 0.511 12 13VDD, VSS (V1)4 15 16 08490-018 Figure 15. Pulse Response (Large Signal) Figure 18. Typical Integral Nonlinearity vs. VDD/VSS 1.0 A1 0.025V TA = +25°C 0.9 VREF+ = +5V VREF+, ±50mV 0.8 VGRAEIFN– = = +01V 0.7 B) 0.6 S L (L 0.5 N D 0.4 0.3 0.2 VOUT+, ±100mV 100mV 50mV 1µs 08490-016 0.0111 12 13VDD, VSS (V1)4 15 16 08490-019 Figure 16. Pulse Response (Small Signal) Figure 19. Typical Differential Nonlinearity vs. VDD/VSS REF 2.24V MARKER 442.0Hz 10dB/DIV RANGE 3.98V 1.70V SRTBAWR 3TH 1z00.0Hz VBW 10Hz STOSPT 2402020 .S0EHCz 08490-017 Figure 17. Spectral Response of Digitally Constructed Sine Wave Rev. H | Page 9 of 24

AD7846 Data Sheet TERMINOLOGY Least Significant Bit Offset Error This is the analog weighting of 1 bit of the digital word in a This is the error present at the device output with all 0s loaded DAC. For the AD7846, 1 LSB = (V − V )/216. in the DAC. It is due to op amp input offset voltage and bias REF+ REF− current and the DAC leakage current. Relative Accuracy Relative accuracy or endpoint nonlinearity is a measure of the Bipolar Zero Error maximum deviation from a straight line passing through the When the AD7846 is connected for bipolar output and 10…000 endpoints of the DAC transfer function. It is measured after is loaded to the DAC, the deviation of the analog output from adjusting for both endpoints (that is, offset and gain errors are the ideal midscale of 0 V is called the bipolar zero error. adjusted out) and is normally expressed in least significant bits Digital-to-Analog Glitch Impulse or as a percentage of full-scale range. This is the amount of charge injected from the digital inputs to Differential Nonlinearity the analog output when the inputs change state. This is normally Differential nonlinearity is the difference between the measured specified as the area of the glitch in either pA-sec or nV-sec change and the ideal change between any two adjacent codes. A depending upon whether the glitch is measured as a current or specified differential nonlinearity of ±1 LSB over the operating a voltage. temperature range ensures monotonicity. Multiplying Feedthrough Error Gain Error This is an ac error due to capacitive feedthrough from either of Gain error is a measure of the output error between an ideal the V terminals to V when the DAC is loaded with all 0s. REF OUT DAC and the actual device output with all 1s loaded after offset Digital Feedthrough error has been adjusted out. Gain error is adjustable to zero When the DAC is not selected (that is, CS is held high), high with an external potentiometer. frequency logic activity on the digital inputs is capacitively coupled through the device to show up as noise on the V pin. OUT This noise is digital feedthrough. Rev. H | Page 10 of 24

Data Sheet AD7846 CIRCUIT DESCRIPTION DIGITAL SECTION Table 7. Control Logic Truth Table Figure 20 shows the digital control logic and on-chip data latches CS R/W LDAC CLR Function in the AD7846. Table 7 is the associated truth table. The digital- 1 X X X 3-state DAC I/O latch in high-Z state to-analog converter (DAC) has two latches that are controlled 0 0 X X DAC I/O latch loaded with DB15 by four signals: CS, R/W, LDAC, and CLR. The input latch is to DB0 0 1 X X Contents of DAC I/O latch available connected to the data bus (DB15 to DB0). A word is written to on DB15 to DB0 the input latch by bringing CS low and R/W low. The contents X X 0 1 Contents of DAC I/O latch transferred of the input latch can be read back by bringing CS low and R/W to DAC latch high. This feature is called readback and is used in system X 0 X 0 DAC latch loaded with 000…000 diagnostic and calibration routines. X 1 X 0 DAC latch loaded with 100…000 Data is transferred from the input latch to the DAC latch with DIGITAL-TO-ANALOG CONVERSION the LDAC strobe. The equivalent analog value of the DAC latch Figure 21 shows the digital-to-analog section of the AD7846. contents appears at the DAC output. The CLR pin resets the There are three DACs, each of which has its own buffer DAC latch contents to 000…000 or 100…000, depending on the amplifiers. DAC1 and DAC2 are 4-bit DACs. They share a state of R/W. Writing a CLR loads 000…000 and reading a CLR 16-resistor string but have their own analog multiplexers. The loads 100…000. To reset a DAC to 0 V in a unipolar system, the voltage reference is applied to the resistor string. DAC3 is a user must assert CLR while R/W is low; to reset to 0 V in a 12-bit voltage mode DAC with its own output stage. bipolar system, assert the CLR while R/W is high. The four MSBs of the 16-bit digital code drive DAC1 and DAC2, R/W and the 12 LSBs control DAC3. Using DAC1 and DAC2, the CLR MSBs select a pair of adjacent nodes on the resistor string and present that voltage to the positive and negative inputs of DAC DAC3. This DAC interpolates between these two voltages to 16 produce the analog output voltage. To prevent nonmonotonicity in the DAC due to amplifier offset DB15 RST LDAC DB15 TO DB0 voltages, DAC1 and DAC2 leap along the resistor string. For DB15 SET LATCHES DB14 TO DB0 example, when switching from Segment 1 to Segment 2, DAC1 RST switches from the bottom of Segment 1 to the top of Segment 2 16 while DAC2 stays connected to the top of Segment 1. The code 3-STATE I/O driving DAC3 is automatically complemented to compensate CS LATCH for the inversion of its inputs. This means that any linearity 16 effects due to amplifier offset voltages remain unchanged when DB15 DB0 08490-020 switching from one segment to the next and 16-bit monotonicity is ensured if DAC3 is monotonic. Thus, 12-bit resistor matching Figure 20. Input Control Logic in DAC3 guarantees overall 16-bit monotonicity. This is much more achievable than 16-bit matching, which a conventional R-2R structure needs. Rev. H | Page 11 of 24

AD7846 Data Sheet VREF+ SEGMENT 16 R DAC1 DAC2 RIN S1 S2 R S3 S4 DAC3 A1 A3 VOUT 12-BIT DAC S15 S14 S17 S16 A2 DB11 TO DB0 DB15 TO DB12 DB15 TO DB12 VREF– SEGMENT 1 08490-021 Figure 21. Digital-to-Analog Conversion OUTPUT STAGE RIN The output stage of the AD7846 is shown in Figure 22. It is capable 10kΩ 10kΩ of driving a 2 kΩ/1000 pF load. It also has a resistor feedback C1 network that allows the user to configure it for gains of 1 or 2. Table 6 shows the different output ranges that are possible. VOUT An additional feature is that the output buffer is configured as a DAC3 track-and-hold amplifier. Although normally tracking its input, this amplifier is placed in a hold mode for approximately 2.5 µs ONE SHOT aofuttepr utth aet l eitasd pinregv eiodugse voof lLtaDgAe Cw.h Tilhe itsh seh AorDt 7st8a4t6e kise ienptse rtnhea lDlyA C LDAC 08490-022 changing to its new value. Thus, any glitches that occur in the Figure 22. Output Stage transition are not seen at the output. In systems where the LDAC is tied permanently low, the deglitching is not in operation. Figure 13 and Figure 14 show the outputs of the AD7846 without and with the deglitcher. Rev. H | Page 12 of 24

Data Sheet AD7846 UNIPOLAR BINARY OPERATION Figure 23 shows the AD7846 in the unipolar binary circuit Table 8. Code Table for Figure 23 configuration. The DAC is driven by the AD586 +5 V reference. Binary Number in DAC Latch Because R is tied to 0 V, the output amplifier has a gain of 2 IN MSB LSB1 Analog Output (V ) OUT and the output range is 0 V to +10 V. If a 0 V to +5 V range is 1111 1111 1111 1111 +10 (65,535/65,536) V required, R must be tied to V , configuring the output stage IN OUT 1000 0000 0000 0000 +10 (32,768/65,536) V for a gain of 1. Table 8 gives the code table for the circuit of 0000 0000 0000 0001 +10 (1/65,536) V Figure 23. 0000 0000 0000 0000 0 V +15V +5V 1 LSB = 10 V/216 = 10 V/65,536 = 152 μV. 4 21 Offset and gain can be adjusted in Figure 23 as follows: 2 VDD VCC 6 7 VREF+ VOUT 5 V(0OVU TTO +10V)  tThoe a DdAjuCst wofiftshe at,l ld 0issc, oannnde acdt jtuhset VthReE FV− inp uvto flrtaogme u0 nVt,i ll oVad 8 AD586 REF− OUT C1 5 R101kΩ AD7846* = 0 V. 1µF 4 RIN 6  For gain adjustment, the AD7846 must be loaded with all 8 VREF– DGND 20 1s and R1 adjusted until VOUT = 10 (65,535)/(65,536) = 9.999847 V. If a simple resistor divider is used to vary the SIGNAL VSS V voltage, it is important that the temperature GROUND REF− * OADMDITITTIEODN FAOL RP ICNLSARITY –15V 08490-023 creoseisfftaicniceen t(s− o30f 0th pepsme r/°eCsi)s.t Oortsh merawtcishe ,t hexatt roaf othffes DetA eCrr oinrps uatr e Figure 23. Unipolar Binary Operation introduced over temperature. Many circuits do not require these offset and gain adjustments. In these circuits, R1 can be omitted. Pin 5 of the AD586 can be left open circuit and Pin 8 (V ) of the AD7846 tied to 0 V. REF− Rev. H | Page 13 of 24

AD7846 Data Sheet BIPOLAR OPERATION Figure 24 shows the AD7846 set up for ±10 V bipolar operation. Full-scale and bipolar zero adjustment are provided by varying The AD588 provides precision ±5 V tracking outputs that are the gain and balance on the AD588. R2 varies the gain on the fed to the V and V inputs of the AD7846. The code table REF+ REF− AD588 while R3 adjusts the +5 V and −5 V outputs together for Figure 24 is shown in Table 9. with respect to ground. +15V +15V +5V For bipolar zero adjustment on the AD7846, load the DAC with R1 39kΩ 100…000 and adjust R3 until V = 0 V. Full scale is adjusted OUT 7 4 6 2 +15V V4DD V2C1C 9b.y9 l9o9a6d9i4n gV .t he DAC with all 1s and adjusting R2 until VOUT = C1 1µF 3 7 VREF+ VOUT 5 VOUT 9 (–10V TO +10V) When bipolar zero and full-scale adjustment are not needed, R2 R2 AD588 1 AD7846* and R3 can be omitted, Pin 12 on the AD588 must be connected to 10kΩ 5 RIN 6 Pin 11, and Pin 5 must be left floating. If a user wants a 5 V 14 10 15 8 VREF– DGND 20 output range, there are two choices. By tying Pin 6 (RIN) of the 11 16 –15V SIGNAL AD7846 to VOUT (Pin 5), the output stage gain is reduced to VSS GROUND unity and the output range is ±5 V. If only a positive 5 V reference R3 12 8 13 9 is available, bipolar ±5 V operation is still possible. Tie V to 100kΩ REF− *ADDITIONAL PINS OMITTED FOR CLARITY –15V 08490-024 r0a Vng aen. Hd ocwonevneerc, tt hReI Nli ntoe aVriRtEyF,+ g. aTinh,i sa nadls oo fgfsievte es rar o±r5 s pVe coiufitcpautito ns Figure 24. Bipolar ±10 V Operation are the same as the unipolar 0 V to 5 V range. Table 9. Offset Binary Code Table for Figure 24 MULTIPLYING OPERATION Binary Number in DAC Latch The AD7846 is a full multiplying DAC. To obtain four-quadrant MSB LSB1 Analog Output (VOUT) multiplication, tie V to 0 V, apply the ac input to V , and REF− REF+ 1111 1111 1111 1111 +10 (32,767/32,768) V tie R to V . Figure 11 shows the large signal frequency IN REF+ 1000 0000 0000 0001 +10 (1/32,768) V response when the DAC is used in this fashion. 1000 0000 0000 0000 0 V 0111 1111 1111 1111 −10 (1/32,768) V 0000 0000 0000 0000 −10 (32,768/32,768) V 1 LSB = 10 V/215 = 10 V/32,768 = 305 μV. Rev. H | Page 14 of 24

Data Sheet AD7846 POSITION MEASUREMENT APPLICATION Ftiiognu rues i2n5g s ahno wlisn tehaer AvaDri7a8b4l6e idni sap plaocseitmioenn mt teraasnusrdeumceenr t( aLpVpDliTca)-, ASIN ω t LVDT x ASIN ω t 7 VREF+VOUT 5 RIN 6 an AD630 synchronous demodulator and a comparator to make AD7846* a 16-bit LVDT-to-digital converter. The LVDT is excited with a fixed frequency and fixed amplitude sine wave (usually 2.5 kHz, 8 VREF– –(1–x) ASIN ω t DGND 20 2 V p-p). The outputs of the secondary coil are in antiphase and DB15 DB0 SIGNAL their relative amplitudes depend on the position of the core in the 10 3 GROUND LVDT. The AD7846 output interpolates between these two inputs PROCESSOR DATA BUS in response to the DAC input code. The AD630 is set up so that it rectifies the DAC output signal. Thus, if the output of the DAC is 9 16 in phase with the V input, the inverting input to the compara- REF+ R1 10AD630* tor is positive, and if it is in phase with V , the output is nega- 100kΩ REF− 13 tive. By turning on each bit of the DAC in succession starting C1 1µF with the MSB and deciding to leave it on or turn it off based on itsh eo bcotaminpeadra. tor output, a 16-bit measurement of the core position *ADDITIONAL PINS OMITTED FOR CLARITY TPOROCESSOR PORT 08490-027 Figure 25. AD7846 in Position Measurement Application Rev. H | Page 15 of 24

AD7846 Data Sheet MICROPROCESSOR INTERFACING AD7846-TO-8086 INTERFACE AD7846-TO-MC68000 INTERFACE Figure 26 shows the 8086 16-bit processor interfacing to the Interfacing between the AD7846 and MC68000 is accomplished AD7846. The double buffering feature of the DAC is not used in using the circuit of Figure 28. The following routine writes data this circuit because LDAC is permanently tied to 0 V. AD0 to AD15 to the DAC latches and then outputs the data via the DAC latch. (the 16-bit data bus) are connected to the DAC data bus (DB0 to DB15). The 16-bit word is written to the DAC in one MOV 1000 MOVE.W #W, The desired DAC data, instruction and the analog output responds immediately. In this D0 W, is loaded into example, the DAC address is 0xD000. Data Register 0. W may be any value ADDRESS BUS between 0 and 65535 (decimal) or 0 and ADDRESS CS FFFF (hexadecimal). DECODE ALE L1A6-TBCITH LDAC MOVE.W D0, The data, W, is 8086 +5V CLR $E000 transferred between DEN AD7846* D0 and the DAC RD register. R/W WR MOVE.W #228, Control is returned AD0 TO AD15 DATA BUS DB0 TO DB15 TRAP D7 to the System Monitor *LINEAR CIRCUITRY OMITTED FOR CLARITY 08490-028 #14 uisnisntgr utchteisoen st.w o Figure 26. AD7846-to-8086 Interface Circuit In a multiple DAC system, the double buffering of the AD7846 A1 TO A23 ADDRESS BUS allows the user to simultaneously update all DACs. In Figure 27, a MC68000 16-bit word is loaded to the input latches of each of the DACs in DS ADDEDCROEDSES CS sequence. Then, with one instruction to the appropriate address, +5V CLR CS4 (that is, LDAC) is brought low, updating all the DACs DTACK LDAC AD7846* simultaneously. R/W R/W ADDRESS BUS D0 TO D15 DATA BUS DB0 TO DB15 DAEDCDOREDSES CS *LINEAR CIRCUITRY OMITTED FOR CLARITY 08490-030 ALE L1A6-TBCITH Figure 28. AD7846-to-MC68000 Interface 8086 LDAC DEN AD7846* RD R/W WR CLR +5V AD0 TO AD15 DATA BUS DB0 TO DB15 CS AD7846* LDAC R/W CLR +5V DB0 TO DB15 CS AD7846* LDAC R/W CLR +5V DB0 TO DB15 *LINEAR CIRCUITRY OMITTED FOR CLARITY 08490-029 Figure 27. AD7846-to-8086 Interface: Multiple DAC System Rev. H | Page 16 of 24

Data Sheet AD7846 DIGITAL FEEDTHROUGH In the preceding interface configurations, most digital inputs to To minimize this digital feedthrough, isolate the DAC from the the AD7846 are directly connected to the microprocessor bus. noise source. Figure 29 shows an interface circuit that isolates Even when the device is not selected, these inputs are constantly the DAC from the bus. changing. The high frequency logic activity on the bus can feed Note that to make use of the AD7846 readback feature using through the DAC package capacitance to show up as noise on the isolation technique of Figure 29, the latch needs to be the analog output. bidirectional. A1 TO A15 ADDRESS BUS ADDEDCROEDSES CS PRMOCICERSOS-OR +5V CLR LDAC R/W R/W DIR G AD7846* D0 TO D15 DATA BUS B BUS A BUS DB0 TO DB15 2× 74LS245 *LINEAR CIRCUITRY OMITTED FOR CLARITY 08490-031 Figure 29. AD7846 Interface Circuit Using Latches to Minimize Digital Feedthrough Rev. H | Page 17 of 24

AD7846 Data Sheet APPLICATION HINTS NOISE R1 to R5 represent lead and track resistances on the printed circuit board. R1 is the resistance between the analog power In high resolution systems, noise is often the limiting factor. supply ground and the signal ground. Because current flowing With a 10 V span, a 16-bit LSB is 152 μV (–96 dB). Thus, the in R1 is very low (bias current of AD588 sense amplifier), the noise floor must stay below −96 dB in the frequency range of effect of R1 is negligible. R2 and R3 represent track resistance interest. Figure 12 shows the noise spectral density for the between the AD588 outputs and the AD7846 reference inputs. AD7846. Because of the force and sense outputs on the AD588, these GROUNDING resistances will also have a negligible effect on accuracy. As well as noise, the other prime consideration in high resolution R4 is the resistance between the DAC output and the load. If R L DAC systems is grounding. With an LSB size of 152 μV and a is constant, then R4 introduces a gain error only that can be load current of 5 mA, 1 LSB of error can be introduced by series trimmed out in the calibration cycle. R5 is the resistance resistance of only 0.03 Ω. between the load and the analog common. If the output voltage Figure 30 shows recommended grounding for the AD7846 in a is sensed across the load, R5 introduces a further gain error, typical application. which can be trimmed out. If, on the other hand, the output voltage is sensed at the analog supply common, R5 appears as ANALOG SUPPLY DIGITAL SUPPLY part of the load and therefore introduces no errors. +15V 0V –15V +5V DGND PRINTED CIRCUIT BOARD LAYOUT Figure 31 shows the AD7846 in a typical application with the AD588 reference, producing an output analog voltage in the R1 ±10 V range. Full-scale and bipolar zero adjustment are SIGNAL GROUND provided by Potentiometer R2 and Potentiometer R3. Latches 2 9 16 4 9 21 20 (2 × 74LS245) isolate the DAC digital inputs from the active R2 microprocessor bus and minimize digital feedthrough. 1 7 6 AD588* 3 AD7846* R3 5 R4 VOUT 15 8 (+5V TO –5V) 14 RL R5 *ADDITIONAL PINS OMITTED FOR CLARITY 08490-032 Figure 30. AD7846 Grounding Rev. H | Page 18 of 24

Data Sheet AD7846 +15V J1 C5 C6 C1 10µF 0.1µF +5V 4 21 C31/A31 10µF C7 0.1µF R1 DB15 10 39kΩ 20 C2 2 18 0.1µF DB14 11 C4/A4 3 17 C5/A5 DB13 12 4 16 4 6 2 C6/A6 C12 DB12 13 5 74LS245 15 C7/A7 1µF 6 14 C8/A8 7 3 7 VREF+ DB11 14 7 13 C9/A9 8 12 1 DB10 15 C10/A10 9 11 C11/A11 AD7846 DB9 16 AD588 10 1 19 5 R2 14 DB8 17 100kΩ +5V 10 15 8 VREF– DB7 18 20 –15V DB6 19 2 18 C12/A12 11 3 17 C13/A13 DB5 26 4 16 16 9 VSS C14/A14 C4 C3 5 15 12 0.1µF 10µF DB4 27 6 74LS245 14 C15/A15 C16/A16 DB3 28 7 13 C17/A17 8 13 9 8 12 DB2 1 C18/A18 9 11 C19/A19 R3 20 DGND DB1 2 10 1 19 C20/A20 100kΩ DB0 3 C21/A21 C22/A22 6 RIN R/W 22 C23/A23 C32/A32 CS 23 (+10V TO –V1O0UVT) 5 VOUT CLR 24 LDAC 25 08490-033 Figure 31. Schematic for AD7846 Board Rev. H | Page 19 of 24

AD7846 Data Sheet OUTLINE DIMENSIONS 0.005 (0.13) 0.100 (2.54) MIN MAX 28 15 0.610 (15.49) 0.500 (12.70) 1 14 PIN 1 0.620 (15.75) 0.225(5.72) 1.490 (37.85) MAX 0.015 (0.38) 0.590 (14.99) MAX MIN 0.150 (3.81) MIN 0.018 (0.46) 0.200 (5.08) 15° 0.008 (0.20) 0.125 (3.18) 0.100 0.070 (1.78) SEATING 0° 0.026 (0.66) (B2.S5C4) 0.030 (0.76) PLANE 0.014 (0.36) C(RINEOFNPEATRRREOENNLCLTEIHN EOGSN EDLSIYM)AEANNRDSEI AORRNOESU NANORDEET DAIN-PO IPFNRFCO HINPECRSHI;A METEQIL UFLIOIVMRAE LUTEESNRET DISNI M FDOEERNSSIGIONN.S 030106-A Figure 32. 28-Lead Ceramic Dual In-Line Package [CERDIP] (Q-28-2) Dimensions shown in inches and (millimeters) 1.565 (39.75) 1.380 (35.05) 28 15 0.580 (14.73) 0.485 (12.31) 1 14 0.625 (15.88) 0.100 (2.54) 0.600 (15.24) BSC 0.195 (4.95) 0.250 (6.35) 0.015 (0.38) MAX GAUGE 0.125 (3.17) 0.015 PLANE 0.200 (5.08) (M0I.N38) 0.115 (2.92) SEATING 0.015 (0.38) PLANE 0.008 (0.20) 0.700 (17.78) 0.022 (0.56) 0.005 (0.13) MAX 0.014 (0.36) MIN 0.070 (1.78) 0.050 (1.27) COMPLIANTTO JEDEC STANDARDS MS-011 CONTROLLING DIMENSIONSARE IN INCHES; MILLIMETER DIMENSIONS (RCINEOFRPEANRREERENN LCTEEHA EODSNSEL MSY)AAAYNR BDEE AR CROOEU NNNFODIGETUDAR-POEPFDRFOA INSPC RWHIAH ETOEQL UFEIO VLRAE LAUEDSNSET. ISN FDOERSIGN. 071006-A Figure 33. 28-Lead Plastic Dual In-Line Package [PDIP] Wide Body (N-28-2) Dimensions shown in inches and (millimeters) 0.300(7.62) 0.100(2.54) 0.075 REF 0.064(1.63) (1.91) 0.020(0.51) REF MIN 19 25 0.028(0.71) 18 26 0.022(0.56) 0.05(1.27) 00..445482((1111..6233))SQ (101M..46SA53QX8) BOVITETWON128 0.15(3.81) 0.075(1.91) REF REF 12 4 11 5 0.088(2.24) 0.055(1.40) 0.095(2.41) 0.054(1.37) 0.045(1.14) 0.075(1.90) C(RINOEFNPEATRRREOENNLCLTEIHNEOGSNDELISYM)AEANNRDSEIAORRNOESUNANORDETEDAIN-POIPNFRFCOHINPECRSHI;AMTEEQILUFLOIIVMRAELUTEESNRETDISNIMFDOEERNSSIGIONNS 022106-A Figure 34. 28-Terminal Ceramic Leadless Chip Carrier [LCC] (E-28-1) Dimensions shown in inches and (millimeters) Rev. H | Page 20 of 24

Data Sheet AD7846 0.180 (4.57) 0.048 (1.22) 0.165 (4.19) 0.042 (1.07) 0.056 (1.42) 0.042 (1.07) 0M.0IN20 (0.51) 4 26 00..004482 ((11..2027)) 5 IDEPNINTI F1IER 25 00..002113 ((00..5333)) BOTTOM TOP VIEW 0.050 0.430 (10.92) VIEW (PINS DOWN) (B1S.2C7) 0.032 (0.81) 0.390 (9.91) (PINS UP) 11 19 0.026 (0.66) 12 18 00..445560 ((1111..548320))SQ 0.120 (3.04) 00..004255 ((10..1644))R 0.090 (2.29) 0.495 (12.57) SQ 0.485 (12.32) COMPLIANT TO JEDEC STANDARDS MO-047-AB C(RINEO FNPETARRREOENLNCLTEIHN EOGSN DELISYM) AEANNRSDEI OARRNOESU NNADOREETD IAN-OP IPFNRFC OHINPECRSHI;A METQIEL ULFIIOVMAREL TUEESNRET DSINI MF DOEERNSSIGIONN.S 042508-A Figure 35. 28-Lead Plastic Leaded Chip Carrier [PLCC] (P-28) Dimensions shown in inches and (millimeters) Rev. H | Page 21 of 24

AD7846 Data Sheet ORDERING GUIDE Relative Model1 Temperature Range Accuracy Package Description Package Option 5962-89697013A −55°C to +125°C ±16 LSB 28-Terminal Ceramic Leadless Chip Carrier [LCC] E-28-1 5962-8969701XA −55°C to +125°C ±16 LSB 28-Lead Wide Body Ceramic Dual In-Line Package [CERDIP] Q-28-2 AD7846JNZ 0°C to +70°C ±16 LSB 28-Lead Plastic Dual In-Line Package [PDIP] N-28-2 AD7846KNZ 0°C to +70°C ±8 LSB 28-Lead Plastic Dual In-Line Package [PDIP] N-28-2 AD7846JPZ 0°C to +70°C ±16 LSB 28-Lead Plastic Leaded Chip Carrier [PLCC] P-28 AD7846JPZ-REEL 0°C to +70°C ±16 LSB 28-Lead Plastic Leaded Chip Carrier [PLCC] P-28 AD7846KPZ 0°C to +70°C ±8 LSB 28-Lead Plastic Leaded Chip Carrier [PLCC] P-28 AD7846KPZ-REEL 0°C to +70°C ±8 LSB 28-Lead Plastic Leaded Chip Carrier [PLCC] P-28 AD7846BPZ −40°C to +85°C ±8 LSB 28-Lead Plastic Leaded Chip Carrier [PLCC] P-28 1 Z = RoHS Compliant Part. Rev. H | Page 22 of 24

Data Sheet AD7846 NOTES Rev. H | Page 23 of 24

AD7846 Data Sheet NOTES ©2000–2017 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D08490-0-8/17(H) Rev. H | Page 24 of 24

Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: A nalog Devices Inc.: 5962-8969701XA AD7846KPZ AD7846KN AD7846JNZ AD7846BP AD7846AP AD7846BPZ AD7846JN AD7846JP-REEL AD7846KP 5962-89697013A AD7846KPZ-REEL AD7846APZ AD7846JPZ-REEL AD7846JP AD7846JPZ AD7846KNZ