None

AD781–SPECIFICATIONS DC SPECIFICATIONS (T to T , V = +12 V (cid:54) 10%, V = –12 V (cid:54) 10%, C = 20 pF, unless otherwise noted) MIN MAX CC EE L AD781J AD781A AD781S Parameter Min Typ Max Min Typ Max Min Typ Max Units SAMPLING CHARACTERISTICS Acquisition Time 10 V Step to 0.01% 600 700 600 700 600 700 ns 10 V Step to 0.1% 500 600 500 600 500 600 ns Small Signal Bandwidth 4 4 4 MHz Full Power Bandwidth 1 1 1 MHz HOLD CHARACTERISTICS Effective Aperture Delay (25(cid:176) C) –35 –25 –15 –35 –25 –15 –35 –25 –15 ns Aperture Jitter (25(cid:176) C) 50 75 50 75 50 75 ps Hold Settling (to 1 mV, 25(cid:176) C) 250 500 250 500 250 500 ns Droop Rate 0.01 1 0.01 1 0.01 1 m V/m s Feedthrough (25(cid:176) C) (V = – 5 V, 100 kHz) –86 –86 –86 dB IN ACCURACY CHARACTERISTICS1 Hold Mode Offset –4 –1 +3 –4 –1 +3 –4 –1 +3 mV Hold Mode Offset Drift 10 10 10 m V/(cid:176) C Sample Mode Offset 50 200 50 200 50 200 mV Nonlinearity – 0.002 – 0.003 – 0.002 – 0.003 – 0.003 – 0.005 % FS Gain Error – 0.01 – 0.025 – 0.01 – 0.025 – 0.01 – 0.025 % FS OUTPUT CHARACTERISTICS Output Drive Current –5 +5 –5 +5 –5 +5 mA Output Resistance, DC 0.3 0.5 0.3 0.5 0.3 0.5 W Total Output Noise (DC to 5 MHz) 150 150 150 m V rms Sampled DC Uncertainty 85 85 85 m V rms Hold Mode Noise (DC to 5 MHz) 125 125 125 m V rms Short Circuit Current Source 20 20 20 mA Sink 10 10 10 mA INPUT CHARACTERISTICS Input Voltage Range –5 +5 –5 +5 –5 +5 V Bias Current 50 250 50 250 50 250 nA Input Impedance 50 50 50 MW Input Capacitance 2 2 2 pF DIGITAL CHARACTERISTICS Input Voltage Low 0.8 0.8 0.8 V Input Voltage High 2.0 2.0 2.0 V Input Current High (V = 5 V) 2 10 2 10 2 10 m A IN POWER SUPPLY CHARACTERISTICS Operating Voltage Range – 10.8 – 12 – 13.2 – 10.8 – 12 – 13.2 – 10.8 – 12 – 13.2 V Supply Current 4 6.5 4 6.5 4 7 mA +PSRR (+12 V – 10%) 70 80 70 80 70 80 dB –PSRR (–12 V – 10%) 65 75 65 75 65 75 dB Power Consumption 95 175 95 175 95 185 mW TEMPERATURE RANGE Specified Performance 0 +70 –40 +85 –55 +125 (cid:176)C NOTE 1Specified and tested over an input range of – 5 V. Specifications subject to change without notice. Specifications shown in boldface are tested on all devices at final electrical test. Results from those tests are used to calculate outgoing quality levels. All min and max specifications are guaranteed although only those shown in boldface are tested. –2– REV. A

AD781 (T to T , V = +12 V (cid:54) 10%, V = –12 V (cid:54) 10%, C = 20 pF, HOLD MODE AC SPECIFICATIONS MIN MAX CC EE L unless otherwise noted)1 AD781J AD781A AD781S Parameter Min Typ Max Min Typ Max Min Typ Max Units TOTAL HARMONIC DISTORTION F = 10 kHz –90 –80 –90 –80 –90 –80 dB IN F = 50 kHz –73 –73 –73 dB IN F = 100 kHz –68 –68 –68 dB IN SIGNAL-TO-NOISE AND DISTORTION F = 10 kHz 72 78 72 78 72 78 dB IN F = 50 kHz 73 73 73 dB IN F = 100 kHz 67 67 67 dB IN INTERMODULATION DISTORTION F = 49 kHz, F = 50 kHz IN1 IN2 2nd Order Products –77 –77 –77 dB 3rd Order Products –78 –78 –78 dB NOTE 1F amplitude = 0 dB and F = 500 kHz unless otherwise indicated. IN SAMPLE Specifications shown in boldface are tested on all devices at final electrical test. Results from those tests are used to calculate outgoing quality levels. All min and max specifications are guaranteed although only those shown in boldface are tested. Specifications subject to change without notice. ABSOLUTE MAXIMUM RATINGS* PIN CONFIGURATION With Spec Respect to Min Max Unit VCC 1 8 OUT V Common –0.3 +15 V AD781 CC IN 2 7 S/H V Common –15 +0.3 V TOP VIEW EE Control Input Common –0.5 +7 V COMMON 3 (Not to Scale) 6 NC Analog Input Common –12 +12 V Output Short Circuit to NC 4 5 VEE Ground, V , or V Indefinite CC EE Maximum Junction Temperature +175 (cid:176) C ORDERING GUIDE Storage –65 +150 (cid:176) C Temperature Package Lead Temperature (10 sec max) +300 (cid:176)C Model1 Range Description Options2 Power Dissipation 195 mW AD781JN 0(cid:176) C to +70(cid:176) C 8-Pin Plastic DIP N-8 AD781AN –40(cid:176)C to +85 (cid:176) C 8-Pin Plastic DIP N-8 *Stresses above those listed under “Absolute Maximum Ratings” may cause per- manent damage to the device. This is a stress rating only and functional opera- AD781SQ –55(cid:176)C to +125 (cid:176) C 8-Pin Cerdip Q-8 tion of the device at these or any other conditions above those indicated in the NOTES operational section of this specification is not implied. 1For details on grade and package offerings screened in accordance with MIL-STD-883, refer to the Analog Devices Military Products Databook or current AD781/883B data sheet. 2N = Plastic DIP; Q = Cerdip. CAUTION ESD (electrostatic discharge) sensitive device. The digital control inputs are diode protected; WARNING! however, permanent damage may occur on unconnected devices subject to high energy electro- static fields. Unused devices must be stored in conductive foam or shunts. ESD SENSITIVE DEVICE REV. A –3–

AD781 80 10.0 –10 70 ns V+ – Y 60 1.0 A –15 s L mV/ DE R – dB 4500 V– mATE – 0.1 RTURE –20 R R E PS 30 OOP E AP 20 DR 0.01 CTIV –25 E F 10 F E 0 0.001 –30 1 10 100 1k 10k 100k 1M 0 25 50 75 100 125 150 100 1k 10k 100k 1M FREQUENCY – Hz TEMPERATURE – (cid:176)C FREQUENCY – Hz Power Supply Rejection Ratio vs. Droop Rate vs. Temperature, Effective Aperture Delay vs. Frequency V = 0 V Frequency IN 200 5 5 150 100 mA 4 mA 4 BIAS CURRENT – nA –1–5050000 SUPPLY CURRENT – 32 SUPPLY CURRENT – 32 –150 –200 1 1 –10 –5 0 5 10 –75 –50 –25 0 25 50 75 100 125 150 – 10 – 11 – 12 – 13 – 14 – 15 INPUT VOLTAGE – V TEMPERATURE – (cid:176)C SUPPLY VOLTAGE – V Bias Current vs. Input Voltage Supply Current vs. Temperature Supply Current vs. Supply Voltage 1000 s 750 n – E M TI N 500 O TI SI UI Q AC 250 0 0 2 4 6 8 10 INPUT STEP – V Acquisition Time (to 0.01%) vs. Input Step Size –4– REV. A

AD781 DEFINITIONS OF SPECIFICATIONS Signal-To-Noise and Distortion (S/N+D) Ratio—S/N+D is Acquisition Time—The length of time that the SHA must the ratio of the rms value of the measured input signal to the remain in the sample mode in order to acquire a full-scale input rms sum of all other spectral components below the Nyquist step to a given level of accuracy. frequency, including harmonics but excluding dc. The value for S/N+D is expressed in decibels. Small Signal Bandwidth—The frequency at which the held output amplitude is 3 dB below the input amplitude, under an Total Harmonic Distortion (THD)—THD is the ratio of the input condition of a 100 mV p-p sine wave. rms sum of the first six harmonic components to the rms value of the measured input signal and is expressed as a percentage or Full Power Bandwidth—The frequency at which the held in decibels. output amplitude is 3 dB below the input amplitude, under an input condition of a 10 V p-p sine wave. Intermodulation Distortion (IMD)—With inputs consisting of sine waves at two frequencies, fa and fb, any device with Effective Aperture Delay—The difference between the switch nonlinearities will create distortion products, of order (m+n), at delay and the analog delay of the SHA channel. A negative sum and difference frequency of mfa– nfb, where m, n = 0, 1, 2, number indicates that the analog portion of the overall delay is 3.... Intermodulation terms are those for which m or n is not greater than the switch portion. This effective delay represents equal to zero. For example, the second order terms are (fa+fb) the point in time, relative to the hold command, that the input and (fa–fb), and the third order terms are (2fa+fb), (2fa–fb), signal will be sampled. (fa+2fb) and (fa–2fb). The IMD products are expressed as the Aperture Jitter—The variations in aperture delay for decibel ratio of the rms sum of the measured input signals to the successive samples. Aperture jitter puts an upper limit on the rms sum of the distortion terms. The two signals are of equal maximum frequency that can be accurately sampled. amplitude, and peak value of their sums is –0.5 dB from full Hold Settling Time—The time required for the output to scale. The IMD products are normalized to a 0 dB input signal. settle to within a specified level of accuracy of its final held value after the hold command has been given. FUNCTIONAL DESCRIPTION The AD781 is a complete sample-and hold amplifier that Droop Rate—The drift in output voltage while in the hold provides high speed sampling to 12-bit accuracy in less than mode. 700 ns. Feedthrough—The attenuated version of a changing input The AD781 is completely self-contained, including an on-chip signal that appears at the output when the SHA is in the hold hold capacitor, and requires no external components or mode. adjustments to perform the sampling function. Both input and Hold Mode Offset—The difference between the input signal output are treated as a single-ended signal, referred to common. and the held output. This offset term applies only in the hold The AD781 utilizes a proprietary circuit design which includes a mode and includes the error caused by charge injection and all self-correcting architecture. This sample-and-hold circuit other internal offsets. It is specified for an input of 0 V. corrects for internal errors after the hold command has been Tracking Mode Offset—The difference between the input and given, by compensating for amplifier gain and offset errors, and output signals when the SHA is in the track mode. charge injection errors. Due to the nature of the design, the Nonlinearity--The deviation from a straight line on a plot of SHA output in the sample mode is not intended to provide an input vs. (held) output as referenced to a straight line drawn accurate representation of the input. However, in hold mode, between endpoints, over an input range of –5 V and +5 V. the internal circuitry is reconfigured to produce an accurately held version of the input signal. Below is a block diagram of the Gain Error—Deviation from a gain of +1 on the transfer AD781. function of input vs. held output. Power Supply Rejection Ratio—A measure of change in the held output voltage for a specified change in the positive or VCC 1 8 OUT negative supply. IN 2 7 S/H Sampled DC Uncertainty—The internal rms SHA noise that X1 is sampled onto the hold capacitor. COMMON 3 6 NC Hold Mode Noise—The rms noise at the output of the SHA while in the hold mode, specified over a given bandwidth. NC 4 AD781 5 VEE Total Output Noise—The total rms noise that is seen at the Functional Block Diagram output of the SHA while in the hold mode. It is the rms summation of the sampled dc uncertainty and the hold mode noise. Output Drive Current—The maximum current the SHA can source (or sink) while maintaining a change in hold mode offset of less than 2.5 mV. REV. A –5–

AD781 DYNAMIC PERFORMANCE (VO U T HOLD – V IN ), mV The AD781 is compatible with 12-bit A-to-D converters in terms of both accuracy and speed. The fast acquisition time, fast +1 hold settling time and good output drive capability allow the AD781 to be used with high speed, high resolution A-to-D converters like the AD674 and AD7672. The AD781’s fast acquisition time provides high throughput rates for multichannel data acquisition systems. Typically, the sample and hold can V I N , VOLTS acquire a 10 V step in less than 600 ns. Figure 1 shows the –5 –4 –3 –2 –1 1 2 3 4 +5 settling accuracy as a function of acquisition time. 0.08 HOLD MODE OFFSET % – Y GAIN ERROR –1 C RA 0.06 NONLINEARITY U C C A ON 0.04 Figure 3.Hold Mode Offset, Gain Error and Nonlinearity TI UISI For applications where it is important to obtain zero offset, the CQ 0.02 hold mode offset may be nulled externally at the input to the A V OUT 0 Apl-itsoh-eDd tchornovuegrhte trh. eA Adj-utost-mDe intst eolff othr eb oy fafsne te xmtearyn bael aamccpolmifi-er 0 250 500 750 1000 with offset nulling capability (e.g., AD711). The offset will ACQUISITION TIME – ns change less than 0.5 mV over the specified temperature range. Figure 1.V Settling vs. Acquisition Time OUT The hold settling determines the required time, after the hold SUPPLY DECOUPLING AND GROUNDING command is given, for the output to settle to its final specified CONSIDERATIONS accuracy. The typical settling behavior of the AD781 is shown As with any high speed, high resolution data acquisition system, in Figure 2. The settling time of the AD781 is sufficiently fast to the power supplies should be well regulated and free from exces- allow the SHA, in most cases, to directly drive an A-to-D sive high frequency noise (ripple). The supply connection to the converter without the need for an added “start convert” delay. AD781 should also be capable of delivering transient currents to the device. To achieve the specified accuracy and dynamic per- formance, decoupling capacitors must be placed directly at both the positive and negative supply pins to common. Ceramic type 0.1 m F capacitors should be connected from V and V to CC EE common. ANALOG DIGITAL P.S. P.S. +12V C –12V C +5V 0.1µF 0.1µF 1µF 1µF 1µF + INPUTS 7 9 11 15 1 DIGITAL Figure 2.Typical AD781 Hold Mode AD781 AD674 DATA OUTPUT HOLD MODE OFFSET SIGNAL GROUND The dc accuracy of the AD781 is determined primarily by the hold mode offset. The hold mode offset refers to the difference Figure 4.Basic Grounding and Decoupling Diagram between the final held output voltage and the input signal at the The AD781 does not provide separate analog and digital ground time the hold command is given. The hold mode offset arises leads as is the case with most A-to-D converters. The common from a voltage error introduced onto the hold capacitor by pin is the single ground terminal for the device. It is the refer- charge injection of the internal switches. The nominal hold ence point for the sampled input voltage and the held output mode offset is specified for a 0 V input condition. Over the voltage and also the digital ground return path. The common input range of –5 V to +5 V, the AD781 is also characterized for pin should be connected to the reference (analog) ground of the an effective gain error and nonlinearity of the held value, as A-to-D converter with a separate ground lead. Since the analog shown in Figure 3. As indicated by the AD781 specifications, and digital grounds in the AD781 are connected internally, the the hold mode offset is very stable over temperature. –6– REV. A

AD781 common pin should also be connected to the digital ground, Measurements of Figures 7 and 8 were made using a 14-bit A/D which is usually tied to analog common at the A-to-D converter. converter with V = 10 V p-p and a sample frequency of IN Figure 4 illustrates the recommended decoupling and grounding 100 kSPS. practice. 1% NOISE CHARACTERISTICS Designers of data conversion circuits must also consider the 1/2 BIT @ 8 BITS effect of noise sources on the accuracy of the data acquisition system. A sample-and-hold amplifier that precedes the A-to-D 0.1% converter introduces some noise and represents another source 1/2 BIT @ 10 BITS of uncertainty in the conversion process. The noise from the AD781 is specified as the total output noise, which includes 1/2 BIT @ both the sampled wideband noise of the SHA in addition to the 12 BITS band limited output noise. The total output noise is the rms 0.01% sum of the sampled dc uncertainty and the hold mode noise. A 1/2 BIT @ 14 BITS plot of the total output noise vs. the equivalent input bandwidth APERTURE JITTER TYPICAL AT 50ps of the converter being used is given in Figure 5. 300 1k 10k 100k 1M FREQUENCY – Hz Figure 6.Error Magnitude vs. Frequency s m V r 200 –65 m– E –70 S OI N UT 100 –75 P T B U d O D – –80 H T 0 –85 1k 10k 100k 1M 10M FREQUENCY – Hz –90 Figure 5.RMS Noise vs. Input Bandwidth of ADC –95 DRIVING THE ANALOG INPUTS 100 1k 10k 100k 1M For best performance, it is important to drive the AD781 analog FREQUENCY – Hz input from a low impedance signal source. This enhances the Figure 7.Total Harmonic Distortion vs. Frequency sampling accuracy by minimizing the analog and digital crosstalk. Signals which come from higher impedance sources 90 (e.g., over 5 kW ) will have a relatively higher level of crosstalk. 80 For applications where signals have high source impedance, an operational amplifier buffer in front of the AD781 is required. 70 The AD711 (precision BiFET op amp) is recommended for 60 these applications. B d – 50 D) HIGH FREQUENCY SAMPLING + 40 Aperture jitter and distortion are the primary factors which limit N frequency domain performance of a sample-and-hold amplifier. S/( 30 Aperture jitter modulates the phase of the hold command and 20 produces an effective noise on the sampled analog input. The magnitude of the jitter induced noise is directly related to the 10 frequency of the input signal. 0 100 1k 10k 100k A graph showing the magnitude of the jitter induced error vs. FREQUENCY – Hz frequency of the input signal is given in Figure 6. Figure 8.Signal/(Noise and Distortion) vs. Frequency The accuracy in sampling high frequency signals is also con- strained by the distortion and noise created by the sample-and hold. The level of distortion increases with frequency and re- duces the “effective number of bits” of the conversion. REV. A –7–

AD781 AD781 TO AD674 INTERFACE 20 Figure 9 shows a typical data acquisition circuit using the AD781, a high linearity, low aperture jitter SHA and the AD674 0 a 12-bit high speed ADC. The time between the AD674 status –20 line going high and the actual start of conversion allows the B d AD781 to settle to 0.01%. As a result, the AD674 status line – –40 can be used to control the AD781; only an inverter is needed to DE U –60 1 interface the two devices. MPLIT –80 10–2/9 STATUS A 9– –100 0 5 +5V C1 0.1µF –120 +12V 7404 6 2 1 OR EQUIV. CE 12/8 VL –140 0.1µF 28 STS 0 3 7 10 13 16 20 23 26 30 33 FREQUENCY BINS – kHz 15 DGND VCC1 7S/H 4 NC 3 CS Figure 10.FFT Plot of AD781 to AD674 Interface, 6 NC 4 A0 AD674 FIN = 1 kHz IN VIN 32 ADO7U8T18 13 10 VIN 16 12-BIT GND 5 VEE NC 14 20 VIN D0–11 27 TDHARTEAE-STATE GAIN 10 REF IN 0.1µF 100W –12V 8 REF OUT 100W 12 BIP OFFSET OFFSET CONVERT 5 R/C 9 AGND 7 11 +12V –12V 4.7µF 0.1µF 0.1µF 4.7µF Figure 9.AD781 to AD674 Interface OUTLINE DIMENSIONS Dimensions shown in inches and (mm). Cerdip (Q) Package Mini-DIP (N) Package A. S. U. N D I E T N RI P –8– REV. A