Low Power, Buffered 24-Bit Sigma-Delta ADC Data Sheet AD7791 FEATURES FUNCTIONAL BLOCK DIAGRAM Power Supply: 2.5 V to 5.25 V operation GND VDD REFIN(+)REFIN(–) Normal: 75 μA max Power-down: 1 μA max VDD CLOCK RMS noise: 1.1 μV at 9.5 Hz update rate 19.5-bit p-p resolution (22 bits effective resolution) AIN(+) - DOUT/RDY Integral nonlinearity: 3.5 ppm typical AIN(–) BUF ADC SERIAL DIN INTERFACE SCLK Simultaneous 50 Hz and 60 Hz rejection CS Internal clock oscillator GND AD7791 Rail-to-rail input buffer 04227-0-001 V monitor channel Figure 1. DD Temperature range: –40°C to +105°C 10-lead MSOP GENERAL DESCRIPTION The AD7791 is a low power, complete analog front end for INTERFACE low frequency measurement applications. It contains a low 3-wire serial noise 24-bit ∑-Δ ADC with one differential input that can be SPI®, QSPI™, MICROWIRE™, and DSP compatible buffered or unbuffered. Schmitt trigger on SCLK The device operates from an internal clock. Therefore, the user APPLICATIONS does not have to supply a clock source to the device. The output Smart transmitters data rate from the part is software programmable and can be Battery applications varied from 9.5 Hz to 120 Hz, with the rms noise equal to Portable instrumentation 1.1 μV at the lower update rate. The internal clock frequency Sensor measurement can be divided by a factor of 2, 4, or 8, which leads to a reduc- Temperature measurement tion in the current consumption. The update rate, cutoff fre- Pressure measurement frequency, and settling time will scale with the clock frequency. Weigh scales The part operates with a power supply from 2.5 V to 5.25 V. 4 to 20 mA loops When operating from a 3 V supply, the power dissipation for the part is 225 μW maximum. It is housed in a 10-lead MSOP. Rev. A Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no re- sponsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Tel: 781.329.4700 ©2004–2013 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com

AD7791 Data Sheet TABLE OF CONTENTS AD7791—Specifications .................................................................. 3 Noise Performance ..................................................................... 14 Timing Characteristics, ................................................................... 5 Reduced Current Modes ........................................................... 14 Absolute Maximum Ratings ............................................................ 7 Digital Interface .......................................................................... 15 ESD Caution .................................................................................. 7 Single Conversion Mode ....................................................... 16 Pin Configuration and Function Descriptions ............................. 8 Continuous Conversion Mode ............................................. 16 Typical Performance Characteristics ............................................. 9 Continuous Read Mode ........................................................ 17 On-chip Registers ........................................................................... 10 Circuit Description......................................................................... 18 Communications Register (RS1, RS0 = 0, 0) .......................... 10 Analog Input Channel ............................................................... 18 Status Register (RS1, RS0 = 0, 0; Bipolar/Unipolar Configuration .............................................. 18 Power-on/Reset = 0x8C) ........................................................... 11 Data Output Coding .................................................................. 18 Mode Register (RS1, RS0 = 0, 1; Power-on/Reset = 0x02) ............................................................ 11 Reference Input ........................................................................... 18 V Monitor ................................................................................ 19 Filter Register (RS1, RS0 = 1, 0; DD Power-on/Reset = 0x04) ............................................................ 12 Grounding and Layout .............................................................. 19 Data Register (RS1, RS0 = 1, 1; Outline Dimensions ....................................................................... 20 Power-on/Reset = 0x000000) .................................................... 13 Ordering Guide .......................................................................... 20 ADC Circuit Information .............................................................. 14 Overview ...................................................................................... 14 REVISION HISTORY 3/13—Rev. 0 to Rev. A Moved ESD Caution Section ............................................................ 7 Changes to Figure 13 ....................................................................... 15 Changes to Reference Input Section ............................................. 18 Updated Outline Dimensions ........................................................ 20 Changes to Ordering Guide ........................................................... 20 8/03—Revision 0: Initial Version Rev. A | Page 2 of 20

Data Sheet AD7791 AD7791—SPECIFICATIONS1 Table 1. (V = 2.5 V to 5.25 V; REFIN(+) = 2.5 V; REFIN(–) = GND; GND = 0 V; CDIV1 = CDIV0 = 0; DD all specifications T to T , unless otherwise noted.) MIN MAX Parameter AD7791B Unit Test Conditions/Comments ADC CHANNEL SPECIFICATION Output Update Rate 9.5 Hz min nom 120 Hz max nom ADC CHANNEL No Missing Codes2 24 Bits min Update Rate ≤ 20 Hz Resolution 19.5 Bits p-p 9.5 Hz Update Rate Output Noise 1.1 µV rms typ Integral Nonlinearity ±15 ppm of FSR max 3.5 ppm typ Offset Error ±3 µV typ Offset Error Drift vs. Temperature ±10 nV/°C typ Full-Scale Error3 ±10 µV typ Gain Drift vs. Temperature ±0.5 ppm/°C typ Power Supply Rejection 90 dB min 100 dB typ, AIN = 1 V ANALOG INPUTS Differential Input Voltage Ranges ±REFIN V nom REFIN = REFIN(+) – REFIN(–); Absolute AIN Voltage Limits2 GND + 100 mV V min Buffered Mode of Operation V – 100 mV V max DD Analog Input Current Buffered Mode of Operation Average Input Current2 ±1 nA max Average Input Current Drift ±5 pA/°C typ Absolute AIN Voltage Limits2 GND – 30 mV V min Unbuffered Mode of Operation V + 30 mV V max DD Analog Input Current Unbuffered Mode of Operation Input current varies with input voltage. Average Input Current ±400 nA/V typ Average Input Current Drift ±50 pA/V/°C typ Normal Mode Rejection2 @ 50 Hz, 60 Hz 65 dB min 73 dB typ, 50 ± 1 Hz, 60 ± 1 Hz, FS[2:0] = 1004 @ 50 Hz 80 dB min 90 dB typ, 50 ± 1 Hz, FS[2:0] = 1014 @ 60 Hz 80 dB min 90 dB typ, 60 ± 1 Hz, FS[2:0] = 0114 Common Mode Rejection AIN = 1 V @DC 90 dB min 100 dB typ, FS[2:0] = 1004 @ 50 Hz, 60 Hz2 100 dB min 50 ± 1 Hz (FS[2:0] = 1014), 60 ± 1 Hz (FS[2:0] = 0114) REFERENCE INPUT REFIN Voltage 2.5 V nom REFIN = REFIN(+) – REFIN(–) Reference Voltage Range2 0.1 V min V V max DD Absolute REFIN Voltage Limits2 GND – 30 mV V min V + 30 mV V max DD Average Reference Input Current 0.5 µA/V typ Average Reference Input Current Drift ±0.03 nA/V/°C typ 1 Temperature Range –40°C to +105°C. 2 Specification is not production tested but is supported by characterization data at initial product release. 3 Full-scale error applies to both positive and negative full-scale and applies at the factory calibration conditions (VDD = 4 V). 4 FS[2:0] are the three bits used in the filter register to select the output word rate. Rev. A | Page 3 of 20

AD7791 Data Sheet SPECIFICATIONS (continued)1 Parameter AD7791B Unit Test Conditions/Comments REFERENCE INPUT (continued) Normal Mode Rejection2 @ 50 Hz, 60 Hz 65 dB min 73 dB typ, 50 ± 1 Hz, 60 ± 1 Hz, FS[2:0] = 1004 @ 50 Hz 80 dB min 90 dB typ, 50 ± 1 Hz, FS[2:0] = 1014 @ 60 Hz 80 dB min 90 dB typ, 60 ± 1 Hz, FS[2:0] = 0114 Common Mode Rejection AIN = 1 V @ DC 100 dB typ FS[2:0] = 1004 @ 50 Hz, 60 Hz 110 dB typ 50 ± 1 Hz (FS[2:0] = 1014), 60 ± 1 Hz (FS[2:0] = 0114) LOGIC INPUTS All Inputs Except SCLK2 V , Input Low Voltage 0.8 V max V = 5 V INL DD 0.4 V max V = 3 V DD V , Input High Voltage 2.0 V min V = 3 V or 5 V INH DD SCLK Only (Schmitt-Triggered Input)2 V(+) 1.4/2 V min/V max V = 5 V T DD V(–) 0.8/1.4 V min/V max V = 5 V T DD V(+) – V(–) 0.3/0.85 V min/V max V = 5 V T T DD V(+) 0.9/2 V min/V max V = 3 V T DD V(–) 0.4/1.1 V min/V max V = 3 V T DD V(+) - V(–) 0.3/0.85 V min/V max V = 3 V T T DD Input Currents ±1 µA max V = V or GND IN DD Input Capacitance 10 pF typ All Digital Inputs LOGIC OUTPUTS V , Output High Voltage2 V – 0.6 V min V = 3 V, I = 100 µA OH DD DD SOURCE V , Output Low Voltage2 0.4 V max V = 3 V, I = 100 µA OL DD SINK V , Output High Voltage2 4 V min V = 5 V, I = 200 µA OH DD SOURCE V , Output Low Voltage2 0.4 V max V = 5 V, I = 1.6 mA OL DD SINK Floating-State Leakage Current ±1 µA max Floating-State Output Capacitance 10 pF typ Data Output Coding Offset Binary POWER REQUIREMENTS5 Power Supply Voltage V – GND 2.5/5.25 V min/max DD Power Supply Currents I Current6 75 µA max 65 µA typ, V = 3.6 V, Unbuffered Mode DD DD 145 µA max 130 µA typ, V = 3.6 V, Buffered Mode DD 80 µA max 73 µA typ, V = 5.25 V, Unbuffered Mode DD 160 µA max 145 µA typ, V = 5.25 V, Buffered Mode DD I (Power-Down Mode) 1 µA max DD 5 Digital inputs equal to VDD or GND. 6 The current consumption can be further reduced by using the ADC in one of the low power modes (see Table 14). Rev. A | Page 4 of 20

Data Sheet AD7791 TIMING CHARACTERISTICS1, 2 Table 2. (V = 2.5 V to 5.25 V; GND = 0 V, REFIN(+) = 2.5 V, REFIN(–) = GND, CDIV1 = CDIV0 = 0, Input Logic 0 = 0 V, DD Input Logic 1 = V , unless otherwise noted.) DD Limit at T , T MIN MAX Parameter (B Version) Unit Conditions/Comments t 100 ns min SCLK High Pulsewidth 3 t 100 ns min SCLK Low Pulsewidth 4 Read Operation t1 0 ns min CS Falling Edge to DOUT/RDY Active Time 60 ns max V = 4.75 V to 5.25 V DD 80 ns max V = 2.5 V to 3.6 V DD t 3 0 ns min SCLK Active Edge to Data Valid Delay4 2 60 ns max V = 4.75 V to 5.25 V DD 80 ns max V = 2.5 V to 3.6 V DD t55, 6 10 ns min Bus Relinquish Time after CS Inactive Edge 80 ns max t6 100 ns max SCLK Inactive Edge to CS Inactive Edge t7 10 ns min SCLK Inactive Edge to DOUT/RDY High Write Operation t8 0 ns min CS Falling Edge to SCLK Active Edge Setup Time4 t 30 ns min Data Valid to SCLK Edge Setup Time 9 t 25 ns min Data Valid to SCLK Edge Hold Time 10 t11 0 ns min CS Rising Edge to SCLK Edge Hold Time 1 Sample tested during initial release to ensure compliance. All input signals are specified with tR = tF = 5 ns (10% to 90% of VDD) and timed from a voltage level of 1.6 V. 2 See Figure 3 and Figure 4. 3 These numbers are measured with the load circuit of Figure 2 and defined as the time required for the output to cross the VOL or VOH limits. 4 SCLK active edge is falling edge of SCLK. 5 These numbers are derived from the measured time taken by the data output to change 0.5 V when loaded with the circuit of Figure 2. The measured number is then extrapolated back to remove the effects of charging or discharging the 50 pF capacitor. This means that the times quoted in the timing characteristics are the true bus relinquish times of the part and, as such, are independent of external bus loading capacitances. 6 RDY returns high after a read of the ADC. In single conversion mode and continuous conversion mode, the same data can be read again, if required, while RDY is high, although care should be taken to ensure that subsequent reads do not occur close to the next output update. In continuous read mode, the digital word can be read only once. Rev. A | Page 5 of 20

AD7791 Data Sheet ISINK (1.6mA WITH VDD = 5V, 100A WITH VDD = 3V) TO OUTPUT 1.6V PIN 50pF ISOURCE (200A WITH VDD = 5V, 100A WITH VDD = 3V) 04227-0-002 Figure 2. Load Circuit for Timing Characterization CS (I) t1 t6 t5 DOUT/RDY (O) MSB LSB t2 t7 t3 SCLK (I) t4 04227-0-003 I = INPUT, O = OUTPUT Figure 3. Read Cycle Timing Diagram CS (I) t8 t11 SCLK (I) t9 t10 DIN (I) MSB LSB 04227-0-004 I = INPUT, O = OUTPUT Figure 4. Write Cycle Timing Diagram Rev. A | Page 6 of 20

Data Sheet AD7791 ABSOLUTE MAXIMUM RATINGS Table 3. (T = 25°C, unless otherwise noted.) A Parameter Rating Stresses above those listed under Absolute Maximum Ratings VDD to GND –0.3 V to +7 V may cause permanent damage to the device. This is a stress Analog Input Voltage to GND –0.3 V to VDD + 0.3 V rating only; functional operation of the device at these or any Reference Input Voltage to GND –0.3 V to VDD + 0.3 V other conditions above those listed in the operational sections Total AIN/REFIN Current (Indefinite) 30 mA of this specification is not implied. Exposure to absolute Digital Input Voltage to GND –0.3 V to VDD + 0.3 V maximum rating conditions for extended periods may affect Digital Output Voltage to GND –0.3 V to VDD + 0.3 V device reliability. Operating Temperature Range –40°C to +105°C ESD CAUTION Storage Temperature Range –65°C to +150°C Maximum Junction Temperature 150°C MSOP θ Thermal Impedance 206°C/W JA θ Thermal Impedance 44°C/W JC Lead Temperature, Soldering (10 sec) 300°C IR Reflow, Peak Temperature 220°C Rev. A | Page 7 of 20

AD7791 Data Sheet PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SCLK 1 10 DIN Pin CS 2 AD7791 9 DOUT/RDY No. Mnemonic Function AIN(+) 3 TOP VIEW 8 VDD AIN(–) 4 (Not to Scale) 7 GND 6 REFIN(–) Negative Reference Input. This reference input can lie anywhere between GND and REF(+) 5 6 REF(–) V – 0.1 V. DD 04227-0-005 Figure 5. Pin Configuration 7 GND Ground Reference Point. 8 V Supply Voltage, 2.5 V to 5.25 V. DD 9 DOUT/RDY Serial Data Output/Data Ready Output. Table 4. Pin Function Descriptions DOUT/RDY serves a dual purpose . It functions Pin as a serial data output pin to access the output No. Mnemonic Function shift register of the ADC. The output shift reg- ister can contain data from any of the 1 SCLK Serial Clock Input for Data Transfers to and on-chip data or control registers. In addition, from the ADC. The SCLK has a Schmitt- DOUT/RDY operates as a data ready pin, triggered input, making the interface suita- ble for opto-isolated applications. The serial going low to indicate the completion of a clock can be continuous with all data conversion. If the data is not read after the transmitted in a continuous train of pulses. conversion, the pin will go high before the Alternatively, it can be a noncontinuous next update occurs. clock with the information being trans- The DOUT/RDY falling edge can be used as an mitted to or from the ADC in smaller interrupt to a processor, indicating that valid batches of data. data is available. With an external serial clock, 2 CS Chip Select Input. This is an active low logic the data can be read using the DOUT/RDY pin. input used to select the ADC. CS can be With CS low, the data/control word informa- used to select the ADC in systems with tion is placed on the DOUT/RDY pin on the more than one device on the serial bus or as SCLK falling edge and is valid on the SCLK a frame synchronization signal in communi- rising edge. cating with the device. CS can be hardwired The end of a conversion is also indicated by low, allowing the ADC to operate in 3-wire the RDY bit in the status register. When CS is mode with SCLK, DIN, and DOUT used to high, the DOUT/RDY pin is three-stated but interface with the device. the RDY bit remains active. 3 AIN(+) Analog Input. AIN(+) is the positive terminal 10 DIN Serial Data Input to the Input Shift Register of the fully differential analog input. on the ADC. Data in this shift register is trans- 4 AIN(–) Analog Input. AIN(–) is the negative termi- ferred to the control registers within nal of the fully differential analog input. the ADC, the register selection bits of the 5 REFIN(+) Positive Reference Input. REFIN(+) can lie communications register identifying the anywhere between V and GND + 0.1 V. appropriate register. DD The nominal reference voltage (REFIN(+) – REFIN(–)) is 2.5 V, but the part functions with a reference from 0.1 V to V . DD Rev. A | Page 8 of 20

Data Sheet AD7791 TYPICAL PERFORMANCE CHARACTERISTICS 0 9 VDD = 3V –10 8 V1.R1E8F7 5=H 2z. 0U4P8DVATE RATE –20 TA = 25°C 7 RMS NOISE = 1.25µF –30 –40 6 E dB––6500 URENC 5 C 4 –70 C O –80 3 –90 2 –100 1 –110 –120 0 0 20 40 60 80 100 120 140 160 8388592 8388616 FREQUENCY (Hz) CODE 04227-0-012 04227-0-014 Figure 6. Frequency Response with 16.6 Hz Update Rate Figure 9. Noise Histogram for Clock Divide by 8 Mode (CDIV0 = CDIV1 = 1) VDD = 3V 8388616 100 VREF = 2.048V 9.5Hz UPDATE RATE TA = 25°C RMS NOISE = 1µV 80 E C EN60 E R D U O C C C O40 20 VDD = 3V, VREF = 2.048V 1.1875Hz UPDATE RATE TA = 25°C, RMS NOISE = 1.25µF 0 8388592 8388591 CODE 8388619 0 20 40 60 80 100 04227-0-010 READ NO. 04227-0-013 Figure 7. Noise Distribution Histogram Figure 10. Noise Plot in Clock Divide by 8 Mode (CDIV1 = CDIV0 = 0) (CDIV0 = CDIV1 = 1) 8388619 3.0 VDD = 5V UPDATE RATE = 16.6Hz TA = 25°C 2.5 V) 2.0 µ ODE OISE ( 1.5 C N S M R 1.0 0.5 VDD = 3V, VREF = 2.048V, 9.5Hz UPDATE RATE 8388591 TA = 25°C, RMS NOISE = 1µV 0 0 200 400 600 800 1000 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 READ NO. 04227-0-011 VREF (V) 04227-0-015 Figure 8. Typical Noise Plot with 16.6 Hz Update Rate Figure 11. RMS Noise vs. Reference Voltage (CDIV1 = CDIV0 = 0) Rev. A | Page 9 of 20

AD7791 Data Sheet ON-CHIP REGISTERS The ADC is controlled and configured via a number of on-chip registers, which are described on the following pages. In the following descriptions, set implies a Logic 1 state and cleared implies a Logic 0 state, unless otherwise stated. COMMUNICATIONS REGISTER (RS1, RS0 = 0, 0) The communications register is an 8-bit write-only register. All communications to the part must start with a write operation to the communications register. The data written to the communications register determines whether the next operation is a read or write oper- ation, and to which register this operation takes place. For read or write operations, once the subsequent read or write operation to the selected register is complete, the interface returns to where it expects a write operation to the communications register. This is the default state of the interface and, on power-up or after a reset, the ADC is in this default state waiting for a write operation to the communica- tions register. In situations where the interface sequence is lost, a write operation of at least 32 serial clock cycles with DIN high returns the ADC to this default state by resetting the entire part. Table 5 outlines the bit designations for the communications register. CR0 through CR7 indicate the bit location, CR denoting the bits are in the communications register. CR7 denotes the first bit of the data stream. The number in brackets indicates the power-on/reset default status of that bit. CR7 CR6 CR5 CR4 CR3 CR2 CR1 CR0 WEN(0) 0(0) RS1(0) RS0(0) R/W(0) CREAD(0) CH1(0) CH0(0) Table 5. Communications Register Bit Designations Bit Location Bit Name Description CR7 WEN Write Enable Bit. A 0 must be written to this bit so that the write to the communications register actually occurs. If a 1 is the first bit written, the part will not clock on to subsequent bits in the register. It will stay at this bit location until a 0 is written to this bit. Once a 0 is written to the WEN bit, the next seven bits will be loaded to the communications register. CR6 0 This bit must be programmed to Logic 0 for correct operation. CR5–CR4 RS1–RS0 Register Address Bits. These address bits are used to select which of the ADC’s registers are being select- ed during this serial interface communication. See Table 6. CR3 R/W A 0 in this bit location indicates that the next operation will be a write to a specified register. A 1 in this position indicates that the next operation will be a read from the designated register. CR2 CREAD Continuous Read of the Data Register. When this bit is set to 1 (and the data register is selected), the serial interface is configured so that the data register can be continuously read, i.e., the contents of the data register are placed on the DOUT pin automatically when the SCLK pulses are applied. The commu- nications register does not have to be written to for data reads. To enable continuous read mode, the instruction 001111XX must be written to the communications register. To exit the continuous read mode, the instruction 001110XX must be written to the communications register while the RDY pin is low. While in continuous read mode, the ADC monitors activity on the DIN line so that it can receive the instruction to exit continuous read mode. Additionally, a reset will occur if 32 consecutive 1s are seen on DIN. Therefore, DIN should be held low in continuous read mode until an instruction is to be written to the device. CR1–CR0 CH1–CH0 These bits are used to select the analog input channel. The differential channel can be selected (AIN(+)/AIN(–)) or an internal short (AIN(–)/AIN(–)) can be selected. Alternatively, the power supply can be selected, i.e., the ADC can measure the voltage on the power supply, which is useful for monitoring power supply variation. The power supply voltage is divided by 5 and then applied to the modulator for conversion. The ADC uses a 1.17 V ± 5% on-chip reference as the reference source for the analog to digi- tal conversion. Any change in channel resets the filter and a new conversion is started. Table 6. Register Selection Table 7. Channel Selection RS1 RS0 Register Register Size CH1 CH0 Channel 0 0 Communications Register 8-Bit 0 0 AIN(+) – AIN(–) during a Write Operation 0 1 Reserved 0 0 Status Register during a 8-Bit 1 0 AIN(–) – AIN(–) Read Operation 1 1 V Monitor DD 0 1 Mode Register 8-Bit 1 0 Filter Register 8-Bit 1 1 Data Register 24-Bit Rev. A | Page 10 of 20

Data Sheet AD7791 STATUS REGISTER (RS1, RS0 = 0, 0; POWER-ON/RESET = 0x8C) The status register is an 8-bit read-only register. To access the ADC status register, the user must write to the communications register, select the next operation to be a read, and load bits RS1 and RS0 with 0. Table 8 outlines the bit designations for the status register. SR0 through SR7 indicate the bit locations, SR denoting the bits are in the status register. SR7 denotes the first bit of the data stream. The number in brackets indicates the power-on/reset default status of that bit. SR7 SR6 SR5 SR4 SR3 SR2 SR1 SR0 RDY(1) ERR(0) 0(0) 0(0) 1(1) WL(1) CH1(0) CH0(0) Table 8. Status Register Bit Designations Bit Location Bit Name Description SR7 RDY Ready bit for ADC. Cleared when data is written to the ADC data register. The RDY bit is set automatically after the ADC data register has been read or a period of time before the data register is updated with a new conversion result to indicate to the user not to read the conversion data. It is also set when the part is placed in power-down mode. The end of a conversion is indicated by the DOUT/RDY pin also. This pin can be used as an alternative to the status register for monitoring the ADC for conversion data. SR6 ERR ADC Error Bit. This bit is written to at the same time as the RDY bit. Set to indicate that the result written to the ADC data register has been clamped to all 0s or all 1s. Error sources include overrange, under- range. Cleared by a write operation to start a conversion. SR5 0 This bit is automatically cleared. SR4 0 This bit is automatically cleared. SR3 1 This bit is automatically set. SR2 1 This bit is automatically set if the device is an AD7791. It can be used to distinguish between the AD7791 and AD7790, in which the bit is cleared. SR1–SR0 CH1–CH0 These bits indicate which channel is being converted by the ADC. MODE REGISTER (RS1, RS0 = 0, 1; POWER-ON/RESET = 0x02) The mode register is an 8-bit register from which data can be read or to which data can be written. This register is used to configure the ADC for unipolar or bipolar mode, enable or disable the buffer, or place the device into power-down mode. Table 9 outlines the bit desig- nations for the mode register. MR0 through MR7 indicate the bit locations, MR denoting the bits are in the mode register. MR7 denotes the first bit of the data stream. The number in brackets indicates the power-on/reset default status of that bit. Any write to the setup regis- ter resets the modulator and filter and sets the RDY bit. MR7 MR6 MR5 MR4 MR3 MR2 MR1 MR0 MD1(0) MD0(0) 0(0) 0(0) BO(0) U/B(0) BUF(1) 0(0) Table 9. Mode Register Bit Designations Bit Location Bit Name Description MR7–MR6 MD1–MD0 Mode Select Bits. These bits select between continuous conversion mode, single conversion mode, and standby mode. In continuous conversion mode, the ADC continuously performs conversions and places the result in the data register. RDY goes low when a conversion is complete. The user can read these conversions by placing the device in continuous read mode whereby the conversions are automatically placed on the DOUT line when SCLK pulses are applied. Alternatively, the user can instruct the ADC to output the conversion by writing to the communications register. After power-on, the first conversion is available after a period 2/ f while subsequent conversions are available at a frequency of f . In single ADC ADC conversion mode, the ADC is placed in power-down mode when conversions are not being performed. When single conversion mode is selected, the ADC powers up and performs a single conversion, which occurs after a period 2/fADC. The conversion result in placed in the data register, RDY goes low, and the ADC returns to power-down mode. The conversion remains in the data register and RDY remains active (low) until the data is read or another conversion is performed. See Table 10. Rev. A | Page 11 of 20

AD7791 Data Sheet Bit Location Bit Name Description MR5–MR4 0 This bit must be programmed with a Logic 0 for correct operation. MR3 BO Burnout Current Enable Bit. When this bit is set to 1 by the user, the 100 nA current sources in the signal path are enabled. When BO = 0, the burnout currents are disabled. The burnout currents can be enabled only when the buffer is active. MR2 U/B Unipolar/Bipolar Bit. Set by user to enable unipolar coding, i.e., zero differential input will result in 0x000000 output and a full-scale differential input will result in 0xFFFFFF output. Cleared by the user to enable bipolar coding. Negative full-scale differential input will result in an output code of 0x000000, zero differential input will result in an output code of 0x800000, and a positive full-scale differential input will result in an output code of 0xFFFFFF. MR1 BUF Configures the ADC for buffered or unbuffered mode of operation. If cleared, the ADC operates in un- buffered mode, lowering the power consumption of the device. If set, the ADC operates in buffered mode, allowing the user to place source impedances on the front end without contributing gain errors to the system. MR0 0 This bit must be programmed with a Logic 0 for correct operation. Table 10. Operating Modes MD1 MD0 Mode 0 0 Continuous Conversion Mode (De- fault) 0 1 Reserved 1 0 Single Conversion Mode 1 1 Power-Down Mode FILTER REGISTER (RS1, RS0 = 1, 0; POWER-ON/RESET = 0x04) The filter register is an 8-bit register from which data can be read or to which data can be written. This register is used to set the output word rate. Table 11 outlines the bit designations for the filter register. FR0 through FR7 indicate the bit locations, FR denoting the bits are in the filter register. FR7 denotes the first bit of the data stream. The number in brackets indicates the power-on/reset default status of that bit. FR7 FR6 FR5 FR4 FR3 FR2 FR1 FR0 0(0) 0(0) CDIV1(0) CDIV0(0) 0(0) FS2(1) FS1(0) FS0(0) Table 11. Filter Register Bit Designations Bit Location Bit Name Description FR7–FR6 0 These bits must be programmed with a Logic 0 for correct operation. FR5–FR4 CLKDIV1– These bits are used to operate the AD7791 in the lower power modes. The clock is internally divided and CDIV0 the power is reduced. In the low power modes, the update rates will scale with the clock frequency so that dividing the clock by 2 causes the update rate to be reduced by a factor of 2 also. 00 Normal Mode 01 Clock Divided by 2 10 Clock Divided by 4 11 Clock Divided by 8 FR3 0 This bit must be programmed with a Logic 0 for correct operation. FR2–FR0 FS2–FS0 These bits set the output word rate of the ADC. The update rate influences the 50 Hz/60 Hz rejection and the noise. See Table 12, which shows the allowable update rates when normal power mode is used. In the low power modes, the update rate is scaled with the clock frequency. For example, if the internal clock is divided by a factor of 2, the corresponding update rates will be divided by 2 also. Rev. A | Page 12 of 20

Data Sheet AD7791 Table 12. Update Rates FS2 FS1 FS0 f (Hz) f3dB (Hz) RMS Noise (µV) Rejection ADC 0 0 0 120 28 40 25 dB @ 60 Hz 0 0 1 100 24 25 25 dB @ 50 Hz 0 1 0 33.3 8 3.36 0 1 1 20 4.7 1.6 80 dB @ 60 Hz 1 0 0 16.6 4 1.5 65 dB @ 50 Hz/60 Hz (Default Setting) 1 0 1 16.7 4 1.5 80 dB @ 50 Hz 1 1 0 13.3 3.2 1.2 1 1 1 9.5 2.3 1.1 67 dB @ 50/60 Hz DATA REGISTER (RS1, RS0 = 1, 1; POWER-ON/RESET = 0x000000) The conversion result from the ADC is stored in this data register. This is a read-only register. On completion of a read operation from this register, the RDY bit/pin is set. Rev. A | Page 13 of 20

AD7791 Data Sheet ADC CIRCUIT INFORMATION OVERVIEW numbers given are for the bipolar input range with a reference of 2.5 V. These numbers are typical and generated with a differ- The AD7791 is a low power ADC that incorporates a ∑-Δ mod- ential input voltage of 0 V. The peak-to-peak resolution figures ulator, a buffer and on-chip digital filtering intended for the represent the resolution for which there will be no code flicker measurement of wide dynamic range, low frequency signals within a six-sigma limit. The output noise comes from two such as those in pressure transducers, weigh scales, and temper- sources. The first is the electrical noise in the semiconductor ature measurement applications. devices (device noise) used in the implementation of the modu- The part has one differential input that can be buffered or lator. The second is quantization noise, which is added when unbuffered. Buffering the input channel means that the part can the analog input is converted into the digital domain. The de- accommodate significant source impedances on the analog vice noise is at a low level and is independent of frequency. The input and that R, C filtering (for noise rejection or RFI reduc- quantization noise starts at an even lower level but rises rapidly tion) can be placed on the analog input, if required. The device with increasing frequency to become the dominant noise requires an external reference of 2.5 nominal. Figure 12 shows source. the basic connections required to operate the part. Table 13. Typical Peak-to-Peak Resolution (Effective POWER SUPPLY Resolution) vs. Update Rate 0.1F 10F Update Peak-toPeak Resolu- Effective Resolu- Rate tion tion 9.5 19.5 22 VDD 13.3 19 21.5 REFIN(+) IN+ 16.7 19 21.5 AD7791 16.6 19 21.5 OUT– OUT+ AIN(+) CS 20 18.5 21 DOUT/RDY MICROCONTROLLER 33.3 17.5 20 IN– AIN(–) SCLK 100 14.5 17 REFIN(–) 120 14 16.5 GND 04227-0-006 REDUCED CURRENT MODES Figure 12. Basic Connection Diagram The AD7791 has a current consumption of 160 μA maximum when operated with a 5 V power supply, the buffer enabled, and The output rate of the AD7791 (fADC) is user programmable the clock operating at its maximum speed. The clock frequency with the settling time equal to 2 × tADC. Normal mode rejection can be divided by a factor of 2, 4, or 8 before being applied to is the major function of the digital filter. Table 12 lists the avail- the modulator and filter, resulting in a reduction in the current able output rates from the AD7791. Simultaneous 50 Hz and consumption of the AD7791. Bits CDIV1 and CDIV0 in the filter 60 Hz rejection is optimized when the update rate equals register are used to enter these low power modes (see Table 14). 16.6 Hz as notches are placed at both 50 Hz and 60 Hz with this update rate (see Figure 6). When the internal clock is reduced, the update rate will also be reduced. For example, if the filter bits are set to give an update NOISE PERFORMANCE rate of 16.6 Hz when the AD7791 is operated in full power Table 13 shows the output rms noise, rms resolution, and peak- mode, the update rate will equal 8.3 Hz in divide by 2 mode. In to-peak resolution (rounded to the nearest 0.5 LSB) for the the low power modes, there may be some degradation in the different update rates and input ranges for the AD7791. The ADC performance. Table 14. Low Power Mode Selection CDIV[1:0] Clock Typ Current, Buffered (μA) Typ Current, Unbuffered (μA) 50 Hz/60 Hz Rejection (dB) 00 1 146 75 65 10 1/2 87 45 64 10 1/4 56 30 75 11 1/8 41 25 86 Rev. A | Page 14 of 20

Data Sheet AD7791 DIGITAL INTERFACE shift register while Figure 4 shows the timing for a write opera- tion to the input shift register. In all modes except continuous As previously outlined, the AD7791’s programmable functions read mode, it is possible to read the same word from the data are controlled using a set of on-chip registers. Data is written to register several times even though the DOUT/RDY line returns these registers via the part’s serial interface and read access to the on-chip registers is also provided by this interface. All high after the first read operation. However, care must be taken communications with the part must start with a write to the to ensure that the read operations have been completed before communications register. After power-on or reset, the device the next output update occurs. In continuous read mode, the expects a write to its communications register. The data written data register can be read only once. to this register determines whether the next operation is a read The serial interface can operate in 3-wire mode by tying CS low. operation or a write operation and also determines to which In this case, the SCLK, DIN, and DOUT/RDY lines are used to register this read or write operation occurs. Therefore, write communicate with the AD7791. The end of the conversion can access to any of the other registers on the part begins with a be monitored using the RDY bit in the status register. This write operation to the communications register followed by a write to the selected register. A read operation from any other scheme is suitable for interfacing to microcontrollers. If CS is register (except when continuous read mode is selected) starts required as a decoding signal, it can be generated from a port with a write to the communications register followed by a read pin. For microcontroller interfaces, it is recommended that operation from the selected register. SCLK idles high between data transfers. The AD7791’s serial interface consists of four signals: CS, DIN, The AD7791 can be operated with CS being used as a frame SCLK, and DOUT/RDY. The DIN line is used to transfer data synchronization signal. This scheme is useful for DSP interfac- es. In this case, the first bit (MSB) is effectively clocked out by into the on-chip registers while DOUT/RDY is used for access- CS since CS would normally occur after the falling edge of ing from the on-chip registers. SCLK is the serial clock input for SCLK in DSPs. The SCLK can continue to run between data the device and all data transfers (either on DIN or DOUT/RDY) transfers, provided the timing numbers are obeyed. occur with respect to the SCLK signal. The DOUT/ RDY pin operates as a Data Ready signal also, the line going low when a The serial interface can be reset by writing a series of 1s on the new data-word is available in the output register. It is reset high DIN input. If a Logic 1 is written to the AD7791 line for at least when a read operation from the data register is complete. It also 32 serial clock cycles, the serial interface is reset. This ensures goes high prior to the updating of the data register to indicate that in 3-wire systems, the interface can be reset to a known when not to read from the device to ensure that a data read is state if the interface gets lost due to a software error or some not attempted while the register is being updated. CS is used to glitch in the system. Reset returns the interface to the state in select a device. It can be used to decode the AD7791 in systems which it is expecting a write to the communications register. where several components are connected to the serial bus. This operation resets the contents of all registers to their power- on values. Figure 3 and Figure 4 show timing diagrams for interfacing to the AD7791 with CS being used to decode the part. Figure 3 The AD7791 can be configured to continuously convert or to shows the timing for a read operation from the AD7791’s out- perform a single conversion. See Figure 13 through Figure 15. put CS 0x10 0x82 0x38 DIN DOUT/RDY DATA SCLK 04227-0-007 Figure 13. Single Conversion Rev. A | Page 15 of 20

AD7791 Data Sheet Single Conversion Mode Continuous Conversion Mode In single conversion mode, the AD7791 is placed in shutdown This is the default power-up mode. The AD7791 will continu- mode between conversions. When a single conversion is initiat- ously convert, the RDY pin in the status register going low each ed by setting MD1 to 1 and MD0 to 0 in the mode register, the time a conversion is complete. If CS is low, the DOUT/RDY line AD7791 powers up, performs a single conversion, and then will also go low when a conversion is complete. To read a con- returns to shutdown mode. A conversion will require a time version, the user can write to the communications register, period of 2 × tADC. DOUT/RDY goes low to indicate the com- indicating that the next operation is a read of the data register. pletion of a conversion. When the data-word has been read The digital conversion will be placed on the DOUT/RDY pin as from the data register, DOUT/RDY will go high. If CS is low, soon as SCLK pulses are applied to the ADC. DOUT/RDY will DOUT/RDY will remain high until another conversion is initi- return high when the conversion is read. The user can read this ated and completed. The data register can be read several times, register additional times, if required. However, the user must if required, even when DOUT/ RDY has gone high. ensure that the data register is not being accessed at the comple- tion of the next conversion or else the new conversion word will be lost. CS 0x38 0x38 DIN DATA DATA DOUT/RDY SCLK 04227-0-009 Figure 14. Continuous Conversion Rev. A | Page 16 of 20

Data Sheet AD7791 Continuous Read Mode before the next conversion is complete. If the user has not read Rather than write to the communications register each time a the conversion before the completion of the next conversion or conversion is complete to access the data, the AD7791 can be if insufficient serial clocks are applied to the AD7791 to read placed in continuous read mode. By writing 001111XX to the the word, the serial output register is reset when the next con- communications register, the user needs only to apply the version is complete and the new conversion is placed in the appropriate number of SCLK cycles to the ADC and the 24-bit output serial register. word will automatically be placed on the DOUT/RDY line To exit the continuous read mode, the instruction 001110XX when a conversion is complete. must be written to the communications register while the RDY When DOUT/RDY goes low to indicate the end of a conver- pin is low. While in the continuous read mode, the ADC moni- tors activity on the DIN line so that it can receive the sion, sufficient SCLK cycles must be applied to the ADC and instruction to exit the continuous read mode. Additionally, a the data conversion will be placed on the DOUT/RDY line. reset will occur if 32 consecutive 1s are seen on DIN. Therefore, When the conversion is read, DOUT/RDY will return high DIN should be held low in continuous read mode until an in- until the next conversion is available. In this mode, the data can struction is to be written to the device. be read only once. Also, the user must ensure that the data- word is read CS 0x3C DIN DOUT/RDY DATA DATA DATA SCLK 04227-0-008 Figure 15. Continuous Read Rev. A | Page 17 of 20

AD7791 Data Sheet CIRCUIT DESCRIPTION ANALOG INPUT CHANNEL If the ADC is configured for bipolar mode, the analog input range on the AIN(+) input is 0 V to 5 V. The bipolar/unipolar The AD7791 has one differential analog input channel. This is option is chosen by programming the B/U bit in the mode connected to the on-chip buffer amplifier when the device is register. operated in buffered mode and directly to the modulator when the device is operated in unbuffered mode. In buffered mode DATA OUTPUT CODING (the BUF bit in the mode register is set to 1), the input channel When the ADC is configured for unipolar operation, the output feeds into a high impedance input stage of the buffer amplifier. code is natural (straight) binary with a zero differential input Therefore, the input can tolerate significant source impedances voltage resulting in a code of 00...00, a midscale voltage and is tailored for direct connection to external resistive-type resulting in a code of 100...000, and a full-scale input voltage sensors such as strain gauges or resistance temperature detec- resulting in a code of 111...111. The output code for any analog tors (RTDs). input voltage can be represented as When BUF = 0, the part is operated in unbuffered mode. This Code = 2N × (AIN/V ) results in a higher analog input current. Note that this REF unbuffered input path provides a dynamic load to the driving When the ADC is configured for bipolar operation, the output source. Therefore, resistor/capacitor combinations on the input code is offset binary with a negative full-scale voltage resulting pins can cause dc gain errors, depending on the output in a code of 000...000, a zero differential input voltage resulting impedance of the source that is driving the ADC input. Table 15 in a code of 100...000, and a positive full-scale input voltage shows the allowable external resistance/capacitance values for resulting in a code of 111...111. The output code for any analog unbuffered mode such that no gain error at the 20-bit level is input voltage can be represented as introduced. Code = 2N – 1 × [(AIN/VREF) + 1] Table 15. External R-C Combination for No 20-Bit Gain Error where AIN is the analog input voltage and N = 24. C (pF) R (Ω) REFERENCE INPUT 50 16.7K 100 9.6K The AD7791 has a fully differential input capability for the 500 2.2K channel. The common-mode range for these differential inputs 1000 1.1K is from GND to VDD. The reference input is unbuffered and, 5000 160 therefore, excessive R-C source impedances will introduce gain errors. The reference voltage REFIN (REFIN(+) – REFIN(–)) is 2.5 V nominal, but the AD7791 is functional with reference The absolute input voltage range in buffered mode is restricted voltages from 0.1 V to V . In applications where the excitation to a range between GND + 100 mV and V – 100 mV. Care DD DD (voltage or current) for the transducer on the analog input also must be taken in setting up the common-mode voltage so that drives the reference voltage for the part, the effect of the low these limits are not exceeded. Otherwise, there will be degrada- frequency noise in the excitation source will be removed tion in linearity and noise performance. because the application is ratiometric. If the AD7791 is used The absolute input voltage in unbuffered mode includes the in a nonratiometric application, a low noise reference should range between GND – 30 mV and VDD + 30 mV as a result of be used. being unbuffered. The negative absolute input voltage limit does Recommended 2.5 V reference voltage sources for the AD7791 allow the possibility of monitoring small true bipolar signals include the ADR381 and ADR391, which are low noise, low with respect to GND. power references. In a system that operates from a 2.5 V power BIPOLAR/UNIPOLAR CONFIGURATION supply, the reference voltage source will require some head- The analog input to the AD7791 can accept either unipolar or room. In this case, a 2.048 V reference such as the ADR380 can bipolar input voltage ranges. A bipolar input range does not be used, requiring only 300 mV of headroom. Also note that the imply that the part can tolerate negative voltages with respect to reference inputs provide a high impedance, dynamic load. system GND. Unipolar and bipolar signals on the AIN(+) input Because the input impedance of each reference input is are referenced to the voltage on the AIN(–) input. For example, dynamic, resistor/ capacitor combinations on these inputs can if AIN(–) is 2.5 V and the ADC is configured for unipolar cause dc gain errors, depending on the output impedance of the mode, the input voltage range on the AIN(+) pin is 2.5 V to 5 V. source that is driving the reference inputs. Rev. A | Page 18 of 20

Data Sheet AD7791 The printed circuit board that houses the AD7791 should be Reference voltage sources like those recommended above designed such that the analog and digital sections are separated (e.g., ADR391) will typically have low output impedances and and confined to certain areas of the board. A minimum etch are, therefore, tolerant to having decoupling capacitors on technique is generally best for ground planes because it gives REFIN(+) without introducing gain errors in the system. the best shielding. Deriving the reference input voltage across an external resistor will mean that the reference input sees a significant external It is recommended that the AD7791’s GND pin be tied to the source impedance. External decoupling on the REFIN pins AGND plane of the system. In any layout, it is important that would not be recommended in this type of circuit the user keep in mind the flow of currents in the system, ensur- configuration. ing that the return paths for all currents are as close as possible V MONITOR to the paths the currents took to reach their destinations. Avoid DD forcing digital currents to flow through the AGND sections of Along with converting external voltages, the analog input chan- the layout. nel can be used to monitor the voltage on the V pin. When DD the CH1 and CH0 bits in the communications register are set to The AD7791’s ground plane should be allowed to run under the 1, the voltage on the VDD pin is internally attenuated by 5 and AD7791 to prevent noise coupling. The power supply lines to the resultant voltage is applied to the ∑-∆ modulator using an the AD7791 should use as wide a trace as possible to provide internal 1.17 V reference for analog to digital conversion. This low impedance paths and reduce the effects of glitches on the is useful because variations in the power supply voltage can be power supply line. Fast switching signals such as clocks should monitored. be shielded with digital ground to avoid radiating noise to other sections of the board, and clock signals should never be run GROUNDING AND LAYOUT near the analog inputs. Avoid crossover of digital and analog Since the analog inputs and reference inputs of the ADC are signals. Traces on opposite sides of the board should run at differential, most of the voltages in the analog modulator are right angles to each other. This will reduce the effects of feed- common-mode voltages. The excellent common-mode rejec- through through the board. A microstrip technique is by far the tion of the part will remove common-mode noise on these best, but it is not always possible with a double-sided board. In inputs. The digital filter will provide rejection of broadband this technique, the component side of the board is dedicated to noise on the power supply, except at integer multiples of the ground planes, while signals are placed on the solder side. modulator sampling frequency. The digital filter also removes Good decoupling is important when using high resolution noise from the analog and reference inputs, provided that these noise sources do not saturate the analog modulator. As a result, ADCs. VDD should be decoupled with 10 µF tantalum in parallel the AD7791 is more immune to noise interference than a con- with 0.1 µF capacitors to GND. To achieve the best from these ventional high resolution converter. However, because the decoupling components, they should be placed as close as resolution of the AD7791 is so high, and the noise levels from possible to the device, ideally right up against the device. All the AD7791 are so low, care must be taken with regard to logic chips should be decoupled with 0.1 µF ceramic capacitors grounding and layout. to DGND. Rev. A | Page 19 of 20

AD7791 Data Sheet OUTLINE DIMENSIONS 3.10 3.00 2.90 10 6 5.15 3.10 4.90 3.00 4.65 2.90 1 5 PIN1 IDENTIFIER 0.50BSC 0.95 15°MAX 0.85 1.10MAX 0.75 0.70 0.15 0.30 6° 0.23 0.55 CO0P.0L5ANARITY 0.15 0° 0.13 0.40 0.10 COMPLIANTTOJEDECSTANDARDSMO-187-BA 091709-A Figure 16. 10-Lead Mini Small Outline Package [MSOP] (RM-10) Dimensions shown in millimeters ORDERING GUIDE Model1 Temperature Range Package Description Package Option Branding AD7791BRM –40°C to +105°C 10-Lead Mini Small Outline Package (MSOP) RM-10 COT AD7791BRMZ –40°C to +105°C 10-Lead Mini Small Outline Package (MSOP) RM-10 C44 AD7791BRM-REEL –40°C to +105°C 10-Lead Mini Small Outline Package (MSOP) RM-10 COT AD7791BRMZ-REEL –40°C to +105°C 10-Lead Mini Small Outline Package (MSOP) RM-10 C44 EVAL-AD7791EBZ Evaluation Board 1 Z = RoHS Compliant Part. ©2004–2013 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D04227-0-3/13(A) Rev. A | Page 20 of 20

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