Low Power, 2-Channel 24-Bit Sigma-Delta ADC Data Sheet AD7787 FEATURES APPLICATIONS Power Smart transmitters Supply: 2.5 V to 5.25 V operation Battery applications Normal mode: 75 µA max Portable instrumentation Power-down mode: 1 µA max Sensor measurement RMS noise: 1.1 µV at 9.5 Hz update rate Temperature measurement 19.5-bit p-p resolution (22 bits effective resolution) Pressure measurement Integral nonlinearity: 3.5 ppm typical Weigh scales Simultaneous 50 Hz and 60 Hz rejection 4 to 20 mA loops Internal clock oscillator Rail-to-rail input buffer GENERAL DESCRIPTION VDD monitor channel The AD7787 is a low power, complete analog front end for low Temperature range: −40°C to +105°C frequency measurement applications. It contains a low noise 10-lead MSOP 24-bit Σ-Δ ADC with one differential input and one single- ended input that can be buffered or unbuffered. INTERFACE The device operates from an internal clock. Therefore, the user 3-wire serial does not have to supply a clock source to the device. The output SPI®, QSPI™, MICROWIRE™, and DSP compatible data rate from the part is software programmable and can be Schmitt trigger on SCLK varied from 9.5 Hz to 120 Hz, with the rms noise equal to 1.1 µV at the lower update rate. The internal clock frequency can be divided by a factor of 2, 4, or 8, which leads to a reduction in the current consumption. The update rate, cutoff frequency, and settling time scales with the clock frequency. The part operates with a power supply from 2.5 V to 5.25 V. When operating from a 3 V supply, the power dissipation for the part is 225 µW maximum. It is housed in a 10-lead MSOP. FUNCTIONAL BLOCK DIAGRAM GND VDD REFIN AD7787 VDD DOUT/RDY SERIAL INTERFACE DIN AAIINN11((+–)) MUX BUF AΣD-∆C COLAONNTGDRICOL SCCSLK AIN2 GND CLOCK 04477-0-001 Figure 1. Rev. A Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Tel: 781.329.4700 ©2004–2013 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com

AD7787 Data Sheet TABLE OF CONTENTS Specifications ..................................................................................... 3 Overview ..................................................................................... 14 Timing Characteristics ..................................................................... 5 Noise Performance ..................................................................... 14 Absolute Maximum Ratings ............................................................ 7 Reduced Current Modes ........................................................... 14 ESD Caution .................................................................................. 7 Digital Interface .......................................................................... 15 Pin Configuration and Function Descriptions ............................. 8 Circuit Description......................................................................... 18 Typical Performance Characteristics ............................................. 9 Analog Input Channel ............................................................... 18 On-Chip Registers .......................................................................... 10 Bipolar/Unipolar Configuration .............................................. 18 Communications Register (RS1, RS0 = 0, 0) .......................... 10 Data Output Coding .................................................................. 18 Status Register (RS1, RS0 = 0, 0; Power-On/Reset Reference Input ........................................................................... 18 = 0×8C) ........................................................................................ 11 V Monitor ................................................................................ 19 DD Mode Register (RS1, RS0 = 0, 1; Power-On/Reset = 0×02) ......................................................................................... 12 Grounding and Layout .............................................................. 19 Applications ................................................................................ 19 Filter Register (RS1, RS0 = 1, 0; Power-On/Reset = 0×04) ......................................................................................... 13 Outline Dimensions ....................................................................... 20 Data Register (RS1, RS0 = 1, 1; Power-On/Reset Ordering Guide .......................................................................... 20 = 0×000000) ................................................................................ 13 ADC Circuit Information .............................................................. 14 REVISION HISTORY 3/13—Rev. 0 to Rev. A Changes to Figure 13 ....................................................................... 15 Change to Reference Input Section ............................................... 18 Updated Outline Dimensions ........................................................ 20 Changes to Ordering Guide ........................................................... 20 4/04—Revision 0: Initial Version Rev. A | Page 2 of 20

Data Sheet AD7787 SPECIFICATIONS Temperature range is −40°C to +105°C. V = 2.5 V to 5.25 V; REFIN = 2.5 V; GND = 0 V; CDIV1 = CDIV0 = 0; all specifications T to DD MIN T , unless otherwise noted. MAX Table 1. Parameter AD7787B Unit Test Conditions/Comments ADC CHANNEL SPECIFICATION Output Update Rate 9.5 Hz min nom 120 Hz max nom ADC CHANNEL No Missing Codes1 24 Bits min Update rate ≤ 20 Hz. Resolution 19.5 Bits p-p 9.5 Hz update rate. Output Noise 1.1 µV rms typ Integral Nonlinearity ±15 ppm of FSR max 3.5 ppm typ. Offset Error ±3 µV typ Offset Error Drift vs. Temperature ±10 nV/°C typ Full-Scale Error2 ±10 µV typ Gain Drift vs. Temperature ±0.5 ppm/°C typ Power Supply Rejection 90 dB min 100 dB typ, AIN = 1 V. ANALOG INPUTS Bipolar Input Voltage Range ±REFIN V nom Because AIN2 is single-ended, it can have a negative voltage of 100 mV minimum (see Page 18). Unipolar Voltage Range 0 to REFIN V nom Absolute AIN Voltage Limits1 GND + 100 mV V min Buffered mode. V – 100 mV V max DD Analog Input Current Buffered mode. Average Input Current1 ±1 nA max Average Input Current Drift ±5 pA/°C typ Absolute AIN Voltage Limits1, 3 GND – 100 mV V min Unbuffered mode. V + 30 mV V max DD Analog Input Current Unbuffered mode. Current varies with input voltage. Average Input Current ±400 nA/V typ Average Input Current Drift ±50 pA/V/°C typ Normal Mode Rejection1 @ 50 Hz, 60 Hz 65 dB min 73 dB typ, 50 ± 1 Hz, 60 ± 1 Hz, FS[2:0] = 1004. @ 50 Hz 80 dB min 90 dB typ, 50 ± 1 Hz, FS[2:0] = 1014. @ 60 Hz 80 dB min 90 dB typ, 60 ± 1 Hz, FS[2:0] = 0114. Common-Mode Rejection (AIN1) AIN = 1 V. @ DC 90 dB min 100 dB typ. @ 50 Hz, 60 Hz1 100 dB min 50 ± 1 Hz (FS[2:0] = 1014), 60 ± 1 Hz (FS[2:0] = 0114). REFERENCE INPUT REFIN Voltage 2.5 V nom Reference Voltage Range1 0.1 V min V V max DD Average Reference Input Current 0.5 µA/V typ Average Reference Input Current Drift ±0.03 nA/V/°C typ Normal Mode Rejection1 @ 50 Hz, 60 Hz 65 dB min 73 dB typ, 50 ± 1 Hz, 60 ± 1 Hz, FS[2:0] = 1004. @ 50 Hz 80 dB min 90 dB typ, 50 ± 1 Hz, FS[2:0] = 1014. @ 60 Hz 80 dB min 90 dB typ, 60 ± 1 Hz, FS[2:0] = 0114. Rev. A | Page 3 of 20

AD7787 Data Sheet Parameter AD7787B Unit Test Conditions/Comments LOGIC INPUTS All Inputs Except SCLK1 V , Input Low Voltage 0.8 V max V = 5 V. INL DD 0.4 V max V = 3 V. DD V , Input High Voltage 2.0 V min V = 3 V or 5 V. INH DD SCLK Only (Schmitt-Triggered Input)1 V(+) 1.4/2 V min/V max V = 5 V. T DD V(−) 0.8/1.4 V min/V max V = 5 V. T DD V(+) − V(−) 0.3/0.85 V min/V max V = 5 V. T T DD V(+) 0.9/2 V min/V max V = 3 V. T DD V(−) 0.4/1.1 V min/V max V = 3 V. T DD V(+) − V(−) 0.3/0.85 V min/V max V = 3 V. T T DD Input Currents ±1 µA max V = V or GND. IN DD Input Capacitance 10 pF typ All Digital Inputs. LOGIC OUTPUTS V , Output High Voltage1 V − 0.6 V min V = 3 V, I = 100 µA. OH DD DD SOURCE V , Output Low Voltage1 0.4 V max V = 3 V, I = 100 µA. OL DD SINK V , Output High Voltage1 4 V min V = 5 V, I = 200 µA. OH DD SOURCE V , Output Low Voltage1 0.4 V max V = 5 V, I = 1.6 mA. OL DD SINK Floating-State Leakage Current ±1 µA max Floating-State Output Capacitance 10 pF typ Data Output Coding Offset Binary POWER REQUIREMENTS5 Power Supply Voltage V − GND 2.5/5.25 V min/max DD Power Supply Currents I Current6 75 µA max 65 µA typ, V = 3.6 V, unbuffered mode. DD DD 145 µA max 130 µA typ, V = 3.6 V, buffered mode. DD 80 µA max 73 µA typ, V = 5.25 V, unbuffered mode. DD 160 µA max 145 µA typ, V = 5.25 V, buffered mode. DD I (Power-Down Mode) 1 µA max DD 1 Specification is not production tested but is supported by characterization data at initial product release. 2 Full-scale error applies to both positive and negative full scale and applies at the factory calibration conditions (VDD = 4 V). 3 The AD7787 can tolerate absolute analog input voltages down to GND − 200 mV but the leakage current will increase. 4 FS[2:0] are the three bits used in the filter register to select the output word rate. 5 Digital inputs equal to VDD or GND. 6 The current consumption can be further reduced by using the ADC in one of the low power modes (see Table 14). Rev. A | Page 4 of 20

Data Sheet AD7787 TIMING CHARACTERISTICS Sample tested during initial release to ensure compliance. All input signals are specified with t = t = 5 ns (10% to 90% of V ) and timed R F DD from a voltage level of 1.6 V (see Figure 3 and Figure 4). V = 2.5 V to 5.25 V; GND = 0 V, REFIN = 2.5 V, CDIV1 = CDIV0 = 0, Input Logic 0 = 0 V, Input Logic 1 = V , unless otherwise noted. DD DD Table 2. Parameter Limit at T , T (B Version) Unit Conditions/Comments MIN MAX t 100 ns min SCLK High Pulse Width 3 t 100 ns min SCLK Low Pulse Width 4 Read Operation t 0 ns min CS Falling Edge to DOUT/RDY Active Time 1 60 ns max V = 4.75 V to 5.25 V DD 80 ns max V = 2.5 V to 3.6 V DD t 1 0 ns min SCLK Active Edge to Data Valid Delay2 2 60 ns max V = 4.75 V to 5.25 V DD 80 ns max V = 2.5 V to 3.6 V DD t 3, 4 10 ns min Bus Relinquish Time after CS Inactive Edge 5 80 ns max t 100 ns max SCLK Inactive Edge to CS Inactive Edge 6 t 10 ns min SCLK Inactive Edge to DOUT/RDY High 7 Write Operation t 0 ns min CS Falling Edge to SCLK Active Edge Setup Time2 8 t 30 ns min Data Valid to SCLK Edge Setup Time 9 t 25 ns min Data Valid to SCLK Edge Hold Time 10 t 0 ns min CS Rising Edge to SCLK Edge Hold Time 11 1 These numbers are measured with the load circuit of Figure 2 and defined as the time required for the output to cross the VOL or VOH limits. 2 The SCLK active edge is the falling edge of SCLK. 3 These numbers are derived from the measured time taken by the data output to change 0.5 V when loaded with the circuit of Figure 2. The measured number is then extrapolated back to remove the effects of charging or discharging the 50 pF capacitor. This means that the times quoted in the timing characteristics are the true bus relinquish times of the part and, as such, are independent of external bus loading capacitances. 4 RDY returns high after a read of the ADC. In single conversion mode and continuous conversion mode, the same data can be read again, if required, while RDY is high, although care should be taken to ensure that subsequent reads do not occur close to the next output update. In continuous read mode, the digital word can be read only once. Rev. A | Page 5 of 20

AD7787 Data Sheet ISINK (1.6mA WITH VDD = 5V, 100A WITH VDD = 3V) TO OUTPUT 1.6V PIN 50pF I1S0O0URAC WE (I2T0H0 VADD W =I T3HV )VDD = 5V, 04477-0-002 Figure 2. Load Circuit for Timing Characterization CS (I) t1 t6 t5 DOUT/RDY (O) MSB LSB t2 t7 t3 SCLK (I) I = INPUT, O = OUTPUT t4 04477-0-003 Figure 3. Read Cycle Timing Diagram CS (I) t8 t11 SCLK (I) t9 t10 DIN (I) MSB LSB I = INPUT, O = OUTPUT 04477-0-004 Figure 4. Write Cycle Timing Diagram Rev. A | Page 6 of 20

Data Sheet AD7787 ABSOLUTE MAXIMUM RATINGS T = 25°C, unless otherwise noted. A Table 3. Parameter Rating V to GND −0.3 V to +7 V DD Stresses above those listed under Absolute Maximum Ratings Analog Input Voltage to GND −0.3 V to V + 0.3 V DD may cause permanent damage to the device. This is a stress Reference Input Voltage to GND −0.3 V to V + 0.3 V DD rating only; functional operation of the device at these or any Total AIN/REFIN Current (Indefinite) 30 mA other conditions above those listed in the operational sections Digital Input Voltage to GND −0.3 V to V + 0.3 V DD of this specification is not implied. Exposure to absolute Digital Output Voltage to GND −0.3 V to V + 0.3 V DD maximum rating conditions for extended periods may affect Operating Temperature Range −40°C to +105°C device reliability. Storage Temperature Range −65°C to +150°C Maximum Junction Temperature 150°C MSOP θ Thermal Impedance 206°C/W JA θ Thermal Impedance 44°C/W JC Lead Temperature, Soldering (10 sec) 300°C IR Reflow, Peak Temperature 220°C ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. Rev. A | Page 7 of 20

AD7787 Data Sheet PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SCLK 1 10 DIN CS 2 AD7787 9 DOUT/RDY AIN1(+) 3 TOP VIEW 8 VDD ARINE1F(I–N) 45 (Not to Scale) 76 GAINND2 04477-0-005 Figure 5. Pin Configuration Table 4. Pin Function Descriptions Pin No. Mnemonic Function 1 SCLK Serial Clock Input for Data Transfers to and from the ADC. The SCLK has a Schmitt-triggered input, making the interface suitable for opto-isolated applications. The serial clock can be continuous with all data transmitted in a continuous train of pulses. Alternatively, it can be a noncontinuous clock with the information being transmitted to or from the ADC in smaller batches of data. 2 CS Chip Select Input. This is an active low logic input used to select the ADC. CS can be used to select the ADC in systems with more than one device on the serial bus or as a frame synchronization signal in communicating with the device. CS can be hardwired low, allowing the ADC to operate in 3-wire mode with SCLK, DIN, and DOUT used to interface with the device. 3 AIN1(+) Analog Input. AIN1(+) is the positive terminal of the differential analog input pair AIN1(+)/AIN1(−). 4 AIN1(–) Analog Input. AIN1(−) is the negative terminal of the differential analog input pair AIN1(+)/AIN1(−). 5 REFIN Reference Input. REFIN can be anywhere between V and GND + 0.1 V. The nominal reference voltage is 2.5 V, but the DD part functions with a reference from 0.1 V to V . DD 6 AIN2 Analog Input. AIN2 is a single-ended analog input. 7 GND Ground Reference Point. 8 V Supply Voltage, 2.5 V to 5.25 V. DD 9 DOUT/RDY Serial Data Output/Data Ready Output. DOUT/RDY serves a dual purpose. It functions as a serial data output pin to access the output shift register of the ADC. The output shift register can contain data from any of the on-chip data or control registers. In addition, DOUT/RDY operates as a data ready pin, going low to indicate the completion of a conversion. If the data is not read after the conversion, the pin will go high before the next update occurs. The DOUT/RDY falling edge can be used as an interrupt to a processor, indicating that valid data is available. With an external serial clock, the data can be read using the DOUT/RDY pin. With CS low, the data/control word information is placed on the DOUT/RDY pin on the SCLK falling edge and is valid on the SCLK rising edge. The end of a conversion is also indicated by the RDY bit in the status register. When CS is high, the DOUT/RDY pin is three-stated, but the RDY bit remains active. Serial Data Input to the Input Shift Register on the ADC. Data in this shift register is transferred to the control registers 10 DIN within the ADC; the register selection bits of the communications register identifying the appropriate register. Rev. A | Page 8 of 20

Data Sheet AD7787 TYPICAL PERFORMANCE CHARACTERISTICS 0 9 VDD = 3V –10 8 V1.R1E8F7 5=H 2z. 0U4P8DVATE RATE –20 TA = 25°C –30 7 RMS NOISE = 1.25µF –40 6 E C –50 N E 5 dB–60 RR –70 CCU 4 O –80 3 –90 2 –––111201000 04477-0-012 01 04477-0-014 0 20 40 60 80 100 120 140 160 8388592 8388616 FREQUENCY (Hz) CODE Figure 6. Frequency Response with 16.6 Hz Update Rate Figure 9. Noise Histogram for Clock Divide-by-8 Mode (CDIV0 = CDIV1 = 1) VDD = 3V 8388616 100 VREF = 2.048V 9.5Hz UPDATE RATE TA = 25°C RMS NOISE = 1µV 80 E C N E60 RR DE U O CC C O40 20 83088591 83886104477-0-0109 8388592 V1T.AD1 D8= 7 =25 53H°VzC, U,V RPRMDEFAS = TN E2O .R0IS4AE8TV E= 1.25µF 04477-0-013 CODE 0 20 40 60 80 100 READ NO. Figure 7. Noise Distribution Histogram (CDIV1 = CDIV0 = 0) Figure 10. Noise Plot in Clock Divide-by-8 Mode (CDIV0 = CDIV1 = 1) 8388619 3.0 VDD = 5V UPDATE RATE = 16.6Hz TA = 25°C 2.5 V) 2.0 µ DE SE ( CO NOI 1.5 S M R 1.0 8388591 VTAD D= =2 53°VC, ,V RRMEFS = N 2O.0IS4E8V =, 19µ.5VHz UPDATE RATE 04477-0-011 0.05 04477-0-015 0 200 400 600 800 1000 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 READ NO. VREF (V) Figure 8. Typical Noise Plot with 16.6 Hz Update Rate (CDIV1 = CD1V0 = 0) Figure 11. RMS Noise vs. Reference Voltage Rev. A | Page 9 of 20

AD7787 Data Sheet ON-CHIP REGISTERS The ADC is controlled and configured via a number of on-chip registers, which are described on the following pages. In the following descriptions, set implies a Logic 1 state and cleared implies a Logic 0 state, unless otherwise noted. COMMUNICATIONS REGISTER (RS1, RS0 = 0, 0) The communications register is an 8-bit write-only register. All communications to the part must start with a write operation to the communications register. The data written to the communications register determines whether the next operation is a read or write operation and to which register this operation takes place. For read or write operations, once the subsequent read or write operation to the selected register is complete, the interface returns to where it expects a write operation to the communications register. This is the default state of the interface and, on power-up or after a reset, the ADC is in this default state waiting for a write operation to the communications register. In situations where the interface sequence is lost, a write operation of at least 32 serial clock cycles with DIN high returns the ADC to this default state by resetting the entire part. Table 5 outlines the bit designations for the communications register. CR0 through CR7 indicate the bit location, CR denoting the bits are in the communications register. CR7 denotes the first bit of the data stream. The number in the parenthesis indicates the power-on/reset default status of that bit. CR7 CR6 CR5 CR4 CR3 CR2 CR1 CR0 WEN (0) 0 (0) RS1 (0) RS0 (0) R/W (0) CREAD (0) CH1 (0) CH0 (0) Table 5. Communications Register Bit Designations Bit Bit Location Name Description CR7 WEN Write Enable Bit. A 0 must be written to this bit so that the write to the communications register actually occurs. If a 1 is the first bit written, the part does not clock on to subsequent bits in the register. It stays at this bit location until a 0 is written to this bit. Once a 0 is written to the WEN bit, the next seven bits are loaded to the communications register. CR6 0 This bit must be programmed to Logic 0 for correct operation. CR5 to RS1 to Register Address Bits. These address bits are used to select which of the ADC’s registers are being selected during CR4 RS0 this serial interface communication (see Table 6). CR3 R/W A 0 in this bit location indicates that the next operation is a write to a specified register. A 1 in this position indicates that the next operation is a read from the designated register. CR2 CREAD Continuous Read of the Data Register. When this bit is set to 1 (and the data register is selected), the serial interface is configured so that the data register can be continuously read, i.e., the contents of the data register are placed on the DOUT pin automatically when the SCLK pulses are applied. The communications register does not have to be written to for data reads. To enable continuous read mode, the instruction 00111100 (Channel AIN1) or 00111101 (Channel AIN2) must be written to the communications register. To exit the continuous read mode, the instruction 001110XX must be written to the communications register while the RDY pin is low. While in continuous read mode, the ADC monitors activity on the DIN line so that it can receive the instruction to exit continuous read mode. Additionally, a reset occurs if 32 consecutive 1s are seen on DIN. Therefore, DIN should be held low in continuous read mode until an instruction is to be written to the device. CR1 to CH1 to These bits are used to select the analog input channel. Channel AIN1 or AIN2 can be selected or an internal short CR0 CH0 (AIN1(−)/AIN1(−)) can be selected. Alternatively, the power supply can be selected, i.e., the ADC can measure the voltage on the power supply, which is useful for monitoring power supply variation. To perform this measurement, the power supply voltage is divided by 5 and then applied to the modulator for conversion. The ADC uses a 1.17 V ± 5% on-chip reference as the reference source when this channel is selected. Any change in channel resets the filter and a new conversion is started. Rev. A | Page 10 of 20

Data Sheet AD7787 Table 6. Register Selection RS1 RS0 Register Register Size 0 0 Communications Register during a Write Operation 8-Bit 0 0 Status Register during a Read Operation 8-Bit 0 1 Mode Register 8-Bit 1 0 Filter Register 8-Bit 1 1 Data Register 24-Bit Table 7. Channel Selection CH1 CH0 Channel 0 0 AIN1(+) − AIN1(−) 0 1 AIN2 1 0 AIN1(−) − AIN1(−) 1 1 V Monitor DD STATUS REGISTER (RS1, RS0 = 0, 0; POWER-ON/RESET = 0×8C) The status register is an 8-bit read-only register. To access the ADC status register, the user must write to the communications register, select the next operation to be a read, and load Bits RS1 and RS0 with 0s. Table 8 outlines the bit designations for the status register. SR0 through SR7 indicate the bit locations, SR denoting the bits are in the status register. SR7 denotes the first bit of the data stream. The number in the parenthesis indicates the power-on/reset default status of that bit. SR7 SR6 SR5 SR4 SR3 SR2 SR1 SR0 RDY (1) ERR (0) 0 (0) 0 (0) 1 (1) 1 (1) CH1 (0) CH0 (0) Table 8. Status Register Bit Designations Bit Bit Location Name Description SR7 RDY Ready Bit for ADC. Cleared when data is written to the ADC data register. The RDY bit is set automatically after the ADC data register has been read or a period of time before the data register is updated with a new conversion result to indicate to the user not to read the conversion data. It is also set when the part is placed in power-down mode. The end of a conversion is indicated by the DOUT/RDY pin also. This pin can be used as an alternative to the status register for monitoring the ADC for conversion data. SR6 ERR ADC Error Bit. This bit is written to at the same time as the RDY bit. Set to indicate that the result written to the ADC data register has been clamped to all 0s or all 1s. Error sources include overrange, underrange. Cleared by a write operation to start a conversion. SR5 to 0 These bits are automatically cleared. SR4 SR3 to 1 These bits are automatically set. SR2 SR1 to CH1 to These bits indicate which channel is being converted by the ADC. SR0 CH0 Rev. A | Page 11 of 20

AD7787 Data Sheet MODE REGISTER (RS1, RS0 = 0, 1; POWER-ON/RESET = 0×02) The mode register is an 8-bit register from which data can be read or to which data can be written. This register is used to configure the ADC for unipolar or bipolar mode, to enable or disable the buffer, or to place the device into power-down mode. Table 9 outlines the bit designations for the mode register. MR0 through MR7 indicate the bit locations, MR denoting the bits are in the mode register. MR7 denotes the first bit of the data stream. The number in the parenthesis indicates the power-on/reset default status of that bit. Any write to the setup register resets the modulator and filter and sets the RDY bit. MR7 MR6 MR5 MR4 MR3 MR2 MR1 MR0 MD1 (0) MD0 (0) 0 (0) 0 (0) BO (0) U/B (0) BUF (1) 0 (0) Table 9. Mode Register Bit Designations Bit Bit Location Name Description MR7 to MD1 to Mode Select Bits. These bits select between continuous conversion mode, single conversion mode, and standby MR6 MD0 mode. In continuous conversion mode, the ADC continuously performs conversions and places the result in the data register. RDY goes low when a conversion is complete. The user can read these conversions by placing the device in continuous read mode whereby the conversions are automatically placed on the DOUT line when SCLK pulses are applied. Alternatively, the user can instruct the ADC to output the conversion by writing to the communications register. After power-on, the first conversion is available after a period 2/f while subsequent ADC conversions are available at a frequency of f . In single conversion mode, the ADC is placed in power-down mode ADC when conversions are not being performed. When single conversion mode is selected, the ADC powers up and performs a single conversion, which occurs after a period 2/f . The conversion result is placed in the data register, ADC RDY goes low, and the ADC returns to power-down mode. The conversion remains in the data register and RDY remains active (low) until the data is read or another conversion is performed (see Table 10). MR5 to 0 These bits must be programmed with a Logic 0 for correct operation. MR4 MR3 BO Burnout Current Enable Bit. When this bit is set to 1 by the user, the 100 nA current sources in the signal path are enabled. When BO = 0, the burnout currents are disabled. The burnout currents can be enabled only when the buffer is active. MR2 U/B Unipolar/Bipolar Bit. Set by user to enable unipolar coding, i.e., zero differential input results in 0x000000 output and a full-scale differential input results in 0xFFFFFF output. Cleared by the user to enable bipolar coding. Negative full- scale differential input results in an output code of 0x000000, zero differential input results in an output code of 0x800000, and a positive full-scale differential input will result in an output code of 0xFFFFFF. MR1 BUF Configures the AD7787 for buffered or unbuffered mode of operation. If cleared, the ADC operates in unbuffered mode, lowering the power consumption of the device. If set, the device operates in buffered mode, allowing the user to place source impedances on the front end without contributing gain errors to the system. MR0 0 This bit must be programmed with a Logic 0 for correct operation. Table 10. Operating Modes MD1 MD0 Mode 0 0 Continuous Conversion Mode (Default) 0 1 Reserved 1 0 Single Conversion Mode 1 1 Power-Down Mode Rev. A | Page 12 of 20

Data Sheet AD7787 FILTER REGISTER (RS1, RS0 = 1, 0; POWER-ON/RESET = 0×04) The filter register is an 8-bit register from which data can be read or to which data can be written. This register is used to set the output word rate. Table 11 outlines the bit designations for the filter register. FR0 through FR7 indicate the bit locations, FR denoting the bits are in the filter register. FR7 denotes the first bit of the data stream. The number in the parenthesis indicates the power-on/reset default status of that bit. FR7 FR6 FR5 FR4 FR3 FR2 FR1 FR0 0 (0) 0 (0) CDIV1 (0) CDIV0 (0) 0 (0) FS2 (1) FS1 (0) FS0 (0) Table 11. Filter Register Bit Designations Bit Location Bit Name Description FR7 to 0 These bits must be programmed with a Logic 0 for correct operation. FR6 FR5 to CLKDIV1 These bits are used to operate the AD7787 in the lower power modes. The clock is internally divided and the FR4 to CDIV0 power is reduced. In the low power modes, the update rates will scale with the clock frequency so that dividing the clock by 2 causes the update rate to be reduced by a factor of 2 also. 00 Normal Mode 01 Clock Divided by 2 10 Clock Divided by 4 11 Clock Divided by 8 FR3 0 This bit must be programmed with a Logic 0 for correct operation. FR2 to FS2 to FS0 These bits set the output word rate of the ADC. The update rate influences the 50 Hz/60 Hz rejection and the FR0 noise. Table 12 shows the allowable update rates when normal power mode is used. In the low power modes, the update rate is scaled with the clock frequency. For example, if the internal clock is divided by a factor of 2, the corresponding update rates are divided by 2 also. Table 12. Update Rates FS2 FS1 FS0 f (Hz) f3dB (Hz) RMS Noise (µV) Rejection ADC 0 0 0 120 28 40 25 dB @ 60 Hz 0 0 1 100 24 25 25 dB @ 50 Hz 0 1 0 33.3 8 3.36 0 1 1 20 4.7 1.6 80 dB @ 60 Hz 1 0 0 16.6 4 1.5 65 dB @ 50 Hz/60 Hz (Default Setting) 1 0 1 16.7 4 1.5 80 dB @ 50 Hz 1 1 0 13.3 3.2 1.2 1 1 1 9.5 2.3 1.1 67 dB @ 50 Hz/60 Hz DATA REGISTER (RS1, RS0 = 1, 1; POWER-ON/RESET = 0×000000) The conversion result from the ADC is stored in this data register. This is a read-only register. On completion of a read operation from this register, the RDY bit/pin is set. Rev. A | Page 13 of 20

AD7787 Data Sheet ADC CIRCUIT INFORMATION OVERVIEW differential input voltage of 0 V. The peak-to-peak resolution figures represent the resolution for which there is no code The AD7787 is a low power ADC that incorporates an Σ-Δ flicker within a six-sigma limit. The output noise comes from modulator, a buffer, and an on-chip digital filter intended for two sources. The first is the electrical noise in the semiconductor the measurement of wide dynamic range, low frequency signals, devices (device noise) used in the implementation of the such as those in pressure transducers, weigh scales, and modulator. The second is quantization noise, which is added when temperature measurement applications. the analog input is converted into the digital domain. The device noise is at a low level and is independent of frequency. The The part has one differential input and one single-ended input. The quantization noise starts at an even lower level but rises rapidly inputs can be operated in buffered or unbuffered mode. Buffering with increasing frequency to become the dominant noise source. the input channel means that the part can accommodate significant source impedances on the analog input .The device requires an external reference of 2.5 nominal. Figure 12 shows the basic Table 13. Typical Peak-to-Peak Resolution connections required to operate the part. (Effective Resolution) vs. Update Rate POWER Peak-to-Peak Effective SUPPLY Update Rate Resolution Resolution 0.1F 10F 9.5 19.5 22 13.3 19 21.5 VDD 16.7 19 21.5 REFIN 16.6 19 21.5 IN+ AD7787 20 18.5 21 OUT– OUT+ AIN+ CS 33.3 17.5 20 DOUT/RDY MICROCONTROLLER 100 14.5 17 IN– AIN– SCLK 120 14 16.5 10k DIN AIN2 THERMISTOR GND 04477-0-006 RThEeD AUDC7E78D7 ChaUs Ra RcuErNreTn tM coOnDsuEmSp tion of 160 μA maximum Figure 12. Basic Connection Diagram when operated with a 5 V power supply, the buffer enabled, and The output rate of the AD7787 (fADC) is user programmable the clock operating at its maximum speed. The clock frequency with the settling time equal to 2 × tADC. Normal mode rejection can be divided by a factor of 2, 4, or 8 before being applied to is the major function of the digital filter. Table 12 lists the the modulator and filter, resulting in a reduction in the current available update rates from the AD7787. Simultaneous 50 Hz consumption of the AD7787. Bits CDIV1 and CDIV0 in the and 60 Hz rejection is optimized when the update rate equals filter register are used to enter these low power modes (see 16.6 Hz as notches are placed at both 50 Hz and 60 Hz with this Table 14). update rate (see Figure 6). When the internal clock is reduced, the update rate is also NOISE PERFORMANCE reduced. For example, if the filter bits are set to give an update Table 13 shows the output rms noise, rms resolution, and peak- rate of 16.6 Hz when the AD7787 is operated in full power to-peak resolution (rounded to the nearest 0.5 LSB) for the mode, the update rate equals 8.3 Hz in divide-by-2 mode. In the different update rates and input ranges for the AD7787. The low power modes, there may be some degradation in the ADC numbers given are for the bipolar input range with a reference performance. of 2.5 V. These numbers are typical and generated with a Table 14. Low Power Mode Selection CDIV[1:0] Clock Typ Current, Buffered (μA) Typ Current, Unbuffered (μA) 50 Hz/60 Hz Rejection (dB) 00 1 146 75 65 10 1/2 87 45 64 10 1/4 56 30 75 11 1/8 41 25 86 Rev. A | Page 14 of 20

Data Sheet AD7787 DIGITAL INTERFACE operation to the input shift register. In all modes, except As previously outlined, the AD7787’s programmable functions continuous read mode, it is possible to read the same word from are controlled using a set of on-chip registers. Data is written to the data register several times even though the DOUT/RDY line these registers via the part’s serial interface and read access to the on-chip registers is also provided by this interface. All returns high after the first read operation. However, care must be communications with the part must start with a write to the taken to ensure that the read operations have been completed communications register. After power-on or reset, the device before the next output update occurs. In continuous read mode, the expects a write to its communications register. The data written data register can only be read once. to this register determines whether the next operation is a read The serial interface can operate in 3-wire mode by tying CS low. operation or a write operation and also determines to which In this case, the SCLK, DIN, and DOUT/RDY lines are used to register this read or write operation occurs. Therefore, write communicate with the AD7787. The end of the conversion can access to any of the other registers on the part begins with a be monitored using the RDY bit in the status register. This write operation to the communications register followed by a write to the selected register. A read operation from any other scheme is suitable for interfacing to microcontrollers. If CS is register (except when continuous read mode is selected) starts required as a decoding signal, it can be generated from a port with a write to the communications register followed by a read pin. For microcontroller interfaces, it is recommended that operation from the selected register. SCLK idle high between data transfers. The AD7787’s serial interface consists of four signals: CS, DIN, The AD7787 can be operated with CS being used as a frame SCLK, and DOUT/RDY. The DIN line is used to transfer data synchronization signal. This scheme is useful for DSP into the on-chip registers while DOUT/RDY is used for interfaces. In this case, the first bit (MSB) is effectively clocked out by CS, because CS would normally occur after the falling accessing data from the on-chip registers. SCLK is the serial clock input for the device and all data transfers (either on DIN edge of SCLK in DSPs. The SCLK can continue to run between or DOUT/RDY) occur with respect to the SCLK signal. data transfers, provided the timing numbers are obeyed. The serial interface can be reset by writing a series of 1s to the The DOUT/ RDY pin operates as a data-ready signal as well as DIN input. If a Logic 1 is written to the AD7787 line for at least a DOUT pin. Each time a conversion is available in the output 32 serial clock cycles, the serial interface is reset. In 3-wire register, DOUT/RDY goes low. DOUT/RDY resets high when a systems, this ensures that the interface can be reset to a known read operation from the data register is completed. It also goes state if the interface gets lost due to a software error or some high prior to the updating of the data register to indicate when glitch in the system. Reset returns the interface to the state in not to read from the device to ensure that a data read is not which it is expecting a write to the communications register. attempted while the register is being updated. CS is used to This operation resets the contents of all registers to their power- select a device. It can be used to decode the AD7787 in systems on values. where several components are connected to the serial bus. The AD7787 can be configured to continuously convert or to Figure 3 and Figure 4 show timing diagrams for interfacing to perform a single conversion (see Figure 13 through Figure 15). the AD7787 with CS being used to decode the part. Figure 3 shows the timing for a read operation from the AD7787’s output shift register, while Figure 4 shows the timing for a write CS 0x10 0x82 0x38 DIN DOUT/RDY DATA SCLK 04477-0-007 Figure 13. Single Conversion Rev. A | Page 15 of 20

AD7787 Data Sheet Single Conversion Mode Continuous Conversion Mode In single conversion mode, the AD7787 is placed in shutdown This is the default power-up mode. The AD7787 will mode between conversions. When a single conversion is continuously converts with the RDY pin in the status register initiated by setting MD1 to 1 and MD0 to 0 in the mode going low each time a conversion is complete. If CS is low, the register, the AD7787 powers up, performs a single conversion, DOUT/RDY line also goes low when a conversion is complete. and then returns to shutdown mode. When a single conversion To read a conversion, the user can write to the communications is initiated, the AD7787’s oscillator requires 1 ms to power up register, indicating that the next operation is a read of the data and settle. The AD7787 then performs a conversion which register. The digital conversion is placed on the DOUT/RDY requires 2 × tADC. DOUT/RDY is high while the conversion is pin as soon as SCLK pulses are applied to the ADC. being performed and goes low to indicate the completion of the DOUT/RDY returns high when the conversion is read. The conversion. When the data word has been read from the data user can read this register additional times, if required. register, DOUT/RDY goes high. If CS is low, DOUT/RDY However, the user must ensure that the data register is not being remains high until another conversion is initiated and accessed at the completion of the next conversion or the new completed. The data register can be read several times, if conversion word is lost. required, even when DOUT/RDY has gone high. CS 0x38 0x38 DIN DATA DATA DOUT/RDY SCLK 04477-0-009 Figure 14. Continuous Conversion Rev. A | Page 16 of 20

Data Sheet AD7787 Continuous Read Mode be read once. Also, the user must ensure that the data-word is read before the next conversion is complete. If the user has not Rather than write to the communications register each time a read the conversion before the completion of the next conversion is complete to access the data, the AD7787 can be conversion, or if insufficient serial clocks are applied to the placed in continuous read mode. By writing 00111100 AD7787 to read the word, the serial output register is reset (Channel AIN1) or 00111101 (Channel AIN2) to the when the next conversion is complete, and the new conversion communications register, the user only needs to apply the is placed in the output serial register. appropriate number of SCLK cycles to the ADC, and the 24-bit word is automatically placed on the DOUT/RDY line when a To exit the continuous read mode, the instruction 001110XX conversion is complete. must be written to the communications register while the RDY pin is low. While in the continuous read mode, the ADC When DOUT/RDY goes low to indicate the end of a monitors activity on the DIN line so that it can receive the conversion, sufficient SCLK cycles must be applied to the ADC, instruction to exit the continuous read mode. Additionally, a and the data conversion is placed on the DOUT/RDY line. reset occurs if 32 consecutive 1s are seen on DIN. Therefore, When the conversion is read, DOUT/RDY returns high until DIN should be held low in continuous read mode until an the next conversion is available. In this mode, the data can only instruction is written to the device. CS 0x3C DIN DOUT/RDY DATA DATA DATA SCLK 04477-0-008 Figure 15. Continuous Read Rev. A | Page 17 of 20

AD7787 Data Sheet CIRCUIT DESCRIPTION ANALOG INPUT CHANNEL The AD7787 has two analog input channels that are connected to the on-chip buffer amplifier when the device is operated in The voltage on AIN2 is referenced to GND. Therefore, when buffered mode and directly to the modulator when the device is bipolar mode is selected and the part is operated in unbuffered operated in unbuffered mode. In buffered mode (the BUF bit in mode, the voltage on AIN2 can vary from GND − 100 mV to the mode register is set to 1), the input channel feeds into a high +2.5 V. In unipolar mode, the voltage on AIN2 can vary from impedance input stage of the buffer amplifier. Therefore, the 0 V to 2.5 V. The bipolar/unipolar option is chosen by input can tolerate significant source impedances and is tailored programming the U/B bit in the mode register. for direct connection to external resistive-type sensors, such as strain gauges or resistance temperature detectors (RTDs). DATA OUTPUT CODING When BUF = 0, the part is operated in unbuffered mode. When the ADC is configured for unipolar operation, the output This results in a higher analog input current. Note that this code is natural (straight) binary with a zero differential input unbuffered input path provides a dynamic load to the driving voltage resulting in a code of 00...00, a midscale voltage source. Therefore, resistor/capacitor combinations on the input resulting in a code of 100...000, and a full-scale input voltage pins can cause dc gain errors, depending on the output resulting in a code of 111...111. The output code for any analog impedance of the source that is driving the ADC input. Table 15 input voltage can be represented as shows the allowable external resistance/capacitance values for the unbuffered mode such that no gain error at the 20-bit level Code2NAIN/V  REF is introduced. When the ADC is configured for bipolar operation, the output code is offset binary with a negative full-scale voltage resulting Table 15. External R-C Combination for No 20-Bit Gain in a code of 000...000, a zero differential input voltage resulting Error in a code of 100...000, and a positive full-scale input voltage C (pF) R (Ω) resulting in a code of 111...111. The output code for any analog 50 16.7 k input voltage can be represented as 100 9.6 k 500 2.2 k Code2N1AIN/V 1 1000 1.1 k REF 5000 160 where AIN is the analog input voltage and N = 24. REFERENCE INPUT The absolute input voltage range in buffered mode is restricted to a range between GND + 100 mV and V − 100 mV. Care The AD7787 has a single-ended reference that is 2.5 V nominal, DD must be taken in setting up the common-mode voltage so that but the AD7787 is functional with reference voltages from 0.1 V these limits are not exceeded. Otherwise, there is degradation in to VDD. In applications where the excitation (voltage or current) linearity and noise performance. for the transducer on the analog input also drives the reference voltage for the part, the effect of the low frequency noise in the The absolute input voltage in unbuffered mode includes the excitation source is removed because the application is range between GND − 100 mV and VDD + 30 mV resulting ratiometric. If the AD7787 is used in a nonratiometric from being unbuffered. The negative absolute input voltage application, a low noise reference should be used. limit does allow the possibility of monitoring small true bipolar signals with respect to GND. Recommended 2.5 V reference voltage sources for the AD7787 include the ADR381 and ADR391, which are low noise, low BIPOLAR/UNIPOLAR CONFIGURATION power references. In a system that operates from a 2.5 V power The analog input to the AD7787 can accept either unipolar or supply, the reference voltage source requires some headroom. In bipolar input voltage ranges. Unipolar and bipolar signals on this case, a 2.048 V reference, such as the ADR380, can be used, the AIN1(+) input are referenced to the voltage on the AIN(−) requiring only 300 mV of headroom. Also note that the input. For example, if AIN1(−) is 2.5 V and the ADC is reference input provides a high impedance, dynamic load. configured for unipolar mode, the input voltage range on the Because the input impedance of the reference input is dynamic, AIN1(+) pin is 2.5 V to 5 V when REFIN = 2.5 V. If the ADC is resistor/capacitor combinations on this input can cause dc gain configured for bipolar mode, the analog input range on the errors, depending on the output impedance of the source AIN1(+) input is 0 V to 5 V. driving the reference inputs. Rev. A | Page 18 of 20

Data Sheet AD7787 Reference voltage sources like those previously recommended, possible to the paths the currents took to reach their e.g., ADR391, will typically have low output impedances and destinations. Avoid forcing digital currents to flow through the are, therefore, tolerant to having decoupling capacitors on AGND sections of the layout. REFIN without introducing gain errors in the system. Deriving The AD7787’s ground plane should be allowed to run under the the reference input voltage across an external resistor means AD7787 to prevent noise coupling. The power supply lines to that the reference input sees a significant external source the AD7787 should use as wide a trace as possible to provide impedance. External decoupling on the REFIN pin is not low impedance paths and reduce the effects of glitches on the recommended in this type of circuit configuration. power supply line. Fast switching signals, such as clocks, should V MONITOR be shielded with digital ground to avoid radiating noise to other DD sections of the board, and clock signals should never be run Along with converting external voltages, the AD7787 can near the analog inputs. Avoid crossover of digital and analog monitor the voltage on the V pin. When the CH1 and CH0 DD signals. Traces on opposite sides of the board should run at bits in the communications register are set to 1, the voltage on right angles to each other. This reduces the effects of the V pin is internally attenuated by 5 and the resultant DD feedthrough through the board. A microstrip technique is by far voltage is applied to the Σ-Δ modulator using an internal the best, but it is not always possible with a double-sided board. 1.17 V reference for the analog-to-digital conversion. This is In this technique, the component side of the board is dedicated useful because variations in the power supply voltage can be to ground planes, while signals are placed on the solder side. monitored. GROUNDING AND LAYOUT Good decoupling is important when using high resolution ADCs. V should be decoupled with 10 μF tantalum in parallel DD The digital filter provides rejection of broadband noise on the with 0.1 μF capacitors to GND. To achieve the best from these power supply, except at integer multiples of the modulator decoupling components, they should be placed as close as sampling frequency. The digital filter also removes noise from possible to the device, ideally right up against the device. All the analog and reference inputs, provided that these noise logic chips should be decoupled with 0.1 μF ceramic capacitors sources do not saturate the analog modulator. As a result, the to DGND. AD7787 is more immune to noise interference than a conventional high resolution converter. However, because the APPLICATIONS resolution of the AD7787 is so high, and the noise levels from Battery Monitoring the AD7787 are so low, care must be taken with regard to In battery monitoring, the battery current and voltage are grounding and layout. measured. The current is passed through a 100 μΩ resistor. The printed circuit board that houses the AD7787 should be Because the current is from −200 A to +2000 A, the result is a designed such that the analog and digital sections are separated voltage from −20 mV to +200 mV. Channel AIN1 of the and confined to certain areas of the board. A minimum etch AD7787 can be connected directly to the shunt resistor to technique is generally best for ground planes because it gives measure this current. The battery voltage can vary from 12 V to the best shielding. 42 V with peaks up to 60 V. This voltage is attenuated using an external resistor network before being applied to the AD7787. It is recommended that the AD7787’s GND pin be tied to the The buffers onboard the AD7787 mean that channel AIN2 can AGND plane of the system. In any layout, it is important that be connected directly to the high impedance attenuator circuit the user keep in mind the flow of currents in the system, without introducing gain errors. ensuring that the return paths for all currents are as close as GND VDD REFIN AD7787 DOUT/RDY SERIAL AIN1(+) INTERFACE DIN AND + – –200A TO R10S0HUNT AIN1(–) MUX AD-C COLNOTGRICOL SCCSLK 12V OR 42V +2000A AIN2 (60V PEAK) ATTENUATION CIRCUIT 04477-0-016 Figure 16. Battery Monitoring Rev. A | Page 19 of 20

AD7787 Data Sheet OUTLINE DIMENSIONS 3.10 3.00 2.90 10 6 5.15 3.10 4.90 3.00 4.65 2.90 1 5 PIN1 IDENTIFIER 0.50BSC 0.95 15°MAX 0.85 1.10MAX 0.75 0.70 0.15 0.30 6° 0.23 0.55 CO0P.0L5ANARITY 0.15 0° 0.13 0.40 0.10 COMPLIANTTOJEDECSTANDARDSMO-187-BA 091709-A Figure 17. 10-Lead Mini Small Outline Package [MSOP] (RM-10) Dimensions shown in millimeters ORDERING GUIDE Models1 Temperature Range Package Description Package Option Branding AD7787BRM −40°C to +105°C 10-Lead Mini Small Outline Package (MSOP) RM-10 C1T AD7787BRMZ −40°C to +105°C 10-Lead Mini Small Outline Package (MSOP) RM-10 C42 AD7787BRM-REEL −40°C to +105°C 10-Lead Mini Small Outline Package (MSOP) RM-10 C1T AD7787BRMZ-RL −40°C to +105°C 10-Lead Mini Small Outline Package (MSOP) RM-10 C42 EVAL-AD7787EB Evaluation Board 1 Z = RoHS Compliant Part. ©2004–2013 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D04477-0-3/13(A) Rev. A | Page 20 of 20