24-Bit Capacitance-to-Digital Converter with Temperature Sensor AD7747 FEATURES GENERAL DESCRIPTION Capacitance-to-digital converter The AD7747 is a high-resolution, Σ-Δ capacitance-to-digital New standard in single chip solutions converter (CDC). The capacitance to be measured is connected Interfaces to single or differential grounded sensors directly to the device inputs. The architecture features inherent Resolution down to 20 aF (that is, up to 19.5-bit ENOB) high resolution (24-bit no missing codes, up to 19.5-bit effective Accuracy: 10 fF resolution), high linearity (±0.01%), and high accuracy (±10 fF Linearity: 0.01% factory calibrated). The AD7747 capacitance input range is Common-mode (not changing) capacitance up to 17 pF ±8 pF (changing), and it can accept up to 17 pF common-mode Full-scale (changing) capacitance range ±8 pF capacitance (not changing), which can be balanced by a program- Update rate: 5 Hz to 45 Hz mable on-chip digital-to-capacitance converter (CAPDAC). Simultaneous 50 Hz and 60 Hz rejection at 8.1 Hz update The AD7747 is designed for single-ended or differential Active shield for shielding sensor connection capacitive sensors with one plate connected to ground. For Temperature sensor on-chip floating (not grounded) capacitive sensors, the AD7745 or Resolution: 0.1°C, accuracy: ±2°C AD7746 are recommended. Voltage input channel Internal clock oscillator The part has an on-chip temperature sensor with a resolution of 2-wire serial interface (I2C® compatible) 0.1°C and accuracy of ±2°C. The on-chip voltage reference and Power the on-chip clock generator eliminate the need for any external 2.7 V to 5.25 V single-supply operation components in capacitive sensor applications. The part has a 0.7 mA current consumption standard voltage input that, together with the differential reference Operating temperature: −40°C to +125°C input, allows easy interface to an external temperature sensor, 16-lead TSSOP package such as an RTD, thermistor, or diode. APPLICATIONS The AD7747 has a 2-wire, I2C-compatible serial interface. The part can operate with a single power supply of 2.7 V to 5.25 V. Automotive, industrial, and medical systems for It is specified over the automotive temperature range of Pressure measurement −40°C to +125°C and is housed in a 16-lead TSSOP package. Position sensing Proximity sensing Level sensing Flow metering Impurity detection FUNCTIONAL BLOCK DIAGRAM VDD TEMP SENSOR GECNLEORCAKTOR AD7747 VIN(+) VIN(–) 24-BIT Σ-Δ DIGITAL I2C SDA MUX GENERATOR FILTER SERIAL INTERFACE SCL CIN1(+) CONTROL LOGIC CIN1(–) CALIBRATION RDY SHLD VOLTAGE CAP DAC 1 REFERENCE EXCITATION CAP DAC 2 REFIN(+) REFIN(–) GND 05469-001 Figure 1. Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Tel: 781.329.4700 www.analog.com Trademarks and registered trademarks are the property of their respective owners. Fax: 781.461.3113 ©2007 Analog Devices, Inc. All rights reserved.

AD7747 TABLE OF CONTENTS Features..............................................................................................1 Cap DAC A Register..................................................................19 Applications.......................................................................................1 Cap DAC B Register...................................................................19 General Description.........................................................................1 Cap Offset Calibration Register...............................................20 Functional Block Diagram..............................................................1 Cap Gain Calibration Register..................................................20 Revision History...............................................................................2 Volt Gain Calibration Register.................................................20 Specifications.....................................................................................3 Circuit Description.........................................................................21 Timing Specifications..................................................................5 Overview.....................................................................................21 Absolute Maximum Ratings............................................................6 Capacitance-to-Digital Converter............................................21 ESD Caution..................................................................................6 Active AC Shield Concept.........................................................21 Pin Configuration and Function Descriptions.............................7 CAPDAC.....................................................................................21 Typical Performance Characteristics.............................................8 Single-Ended Capacitive Configuration.................................22 Output Noise and Resolution Specifications..............................11 Differential Capacitive Configuration.....................................22 Serial Interface................................................................................12 Parasitic Capacitance.................................................................23 Read Operation...........................................................................12 Parasitic Resistance....................................................................23 Write Operation..........................................................................12 Parasitic Serial Resistance.........................................................23 AD7747 Reset..............................................................................13 Capacitive Gain Calibration.....................................................23 General Call.................................................................................13 Capacitive System Offset Calibration......................................24 Register Descriptions.....................................................................14 Internal Temperature Sensor....................................................24 Status Register.............................................................................15 External Temperature Sensor...................................................24 Cap Data Register.......................................................................15 Voltage Input...............................................................................25 VT Data Register........................................................................15 V Monitor................................................................................25 DD Cap Setup Register.....................................................................16 Typical Application Diagram....................................................26 VT Setup Register.......................................................................16 Outline Dimensions.......................................................................27 EXC Setup Register....................................................................17 Ordering Guide..........................................................................27 Configuration Register..............................................................18 REVISION HISTORY 1/07—Revision 0: Initial Version Rev. 0 | Page 2 of 28

AD7747 SPECIFICATIONS V = 2.7 V to 3.6 V or 4.75 V to 5.25 V; GND = 0 V; EXC = ±V × 3/8; −40°C to +125°C, unless otherwise noted. DD DD Table 1. Parameter Min Typ Max Unit Test Conditions/Comments CAPACITIVE INPUT Conversion Input Range ±8.192 pF1 Factory calibrated Integral Nonlinearity (INL)2 ±0.01 % of FSR1 No Missing Codes2 24 Bit Conversion time ≥ 124 ms Resolution, p-p 16.5 Bit Conversion time 124 ms, see Table 5 Resolution Effective 19.1 Bit Conversion time 124 ms, see Table 5 Output Noise, rms 11.0 aF/√Hz Conversion time 124 ms, see Table 5 Absolute Error3 ±10 fF1 25°C, V = 5 V, after offset calibration DD Offset Error4, 5 32 aF1 After system offset calibration, excluding effect of noise4 System Offset Calibration Range5 ±1 pF Offset Deviation over Temperature2 0.4 fF See Figure 6 Gain Error6 0.02 0.11 % of FS1 25°C, V = 5 V DD Gain Drift vs. Temperature2 −23 −26 −29 ppm of FS/°C Power Supply Rejection2 0.5 4 fF/V Normal Mode Rejection5 72 dB 50 Hz ± 1%, conversion time 124 ms 60 dB 60 Hz ± 1%, conversion time 124 ms CAPDAC Full Range 17 21 pF 6-bit CAPDAC Differential Nonlinearity (DNL) 0.3 LSB See Figure 16 Drift vs. Temperature2 26 ppm of FS/°C EXCITATION Frequency 16 kHz AC Voltage Across Capacitance ±V × 3/8 V To be configured via digital interface DD Average DC Voltage Across Capacitance V /2 V DD TEMPERATURE SENSOR7 V internal REF Resolution 0.1 °C Error2 ±0.5 ±2 °C Internal temperature sensor ±2 °C External sensing diode8 VOLTAGE INPUT7 V internal or V = 2.5 V REF REF Differential VIN Voltage Range ±V V REF Absolute VIN Voltage2 GND − 0.03 V + 0.03 V DD Integral Nonlinearity (INL) ±3 ±15 ppm of FS No Missing Codes2 24 Bit Conversion time = 122.1 ms Resolution, p-p 16 Bits Conversion time = 62 ms, see Table 6 and Table 7 Output Noise 3 μV rms Conversion time = 62 ms, see Table 6 and Table 7 Offset Error ±3 μV Offset Drift vs. Temperature 15 nV/°C Full-Scale Error2, 9 0.025 0.1 % of FS Full-Scale Drift vs. Temperature 5 ppm of FS/°C Internal reference 0.5 ppm of FS/°C External reference Average VIN Input Current 300 nA/V Analog VIN Input Current Drift ±50 pA/V/°C Power Supply Rejection 80 dB Internal reference, V = V /2 IN REF 90 dB External reference, V = V /2 IN REF Rev. 0 | Page 3 of 28

AD7747 Parameter Min Typ Max Unit Test Conditions/Comments Normal Mode Rejection5 75 dB 50 Hz ± 1%, conversion time = 122.1 ms 50 dB 60 Hz ± 1%, conversion time = 122.1 ms Common-Mode Rejection2 95 dB V = 1 V IN INTERNAL VOLTAGE REFERENCE Voltage 1.169 1.17 1.171 V T = 25°C A Drift vs. Temperature 5 ppm/°C EXTERNAL VOLTAGE REFERENCE INPUT Differential REFIN Voltage2 0.1 2.5 V V DD Absolute REFIN Voltage2 GND − 0.03 V + 0.03 V DD Average REFIN Input Current 400 nA/V Average REFIN Input Current Drift ±50 pA/V/°C Common-Mode Rejection 80 dB SERIAL INTERFACE LOGIC INPUTS (SCL, SDA) V Input High Voltage 2.1 V IH V Input Low Voltage 0.8 V IL Hysteresis 150 mV Input Leakage Current (SCL) ±0.1 ±1 μA OPEN-DRAIN OUTPUT (SDA) V Output Low Voltage 0.4 V I = −6.0 mA OL SINK I Output High Leakage Current 0.1 1 μA V = V OH OUT DD LOGIC OUTPUT (RDY) V Output Low Voltage 0.4 V I = 1.6 mA, V = 5 V OL SINK DD V Output High Voltage 4.0 V I = 200 μA, V = 5 V OH SOURCE DD V Output Low Voltage 0.4 V I = 100 μA, V = 3 V OL SINK DD V Output High Voltage V − 0.6 V I = 100 μA, V = 3 V OH DD SOURCE DD POWER REQUIREMENTS V -to-GND Voltage 4.75 5.25 V V = 5 V, nominal DD DD 2.7 3.6 V V = 3.3 V, nominal DD I Current 850 μA Digital inputs equal to V or GND DD DD 750 μA V = 5 V DD 700 μA V = 3.3 V DD I Current Power-Down Mode 0.5 2 μA Digital inputs equal to V or GND DD DD 1 Capacitance units: 1 pF = 10−12 F; 1 fF = 10−15 F; 1 aF = 10−18 F. Full scale (FS) = 8.192 pF; full-scale range (FSR) = ±8.192 pF. 2 Specification is not production tested, but is supported by characterization data at initial product release. 3 Factory calibrated. The absolute error includes factory gain calibration error, integral nonlinearity error, and offset error after system offset calibration, all at 25°C. At different temperatures, compensation for gain drift over temperature is required. 4 The capacitive input offset can be eliminated using a system offset calibration. The accuracy of the system offset calibration is limited by the offset calibration register LSB size (32 aF) or by converter + system p-p noise during the system capacitive offset calibration, whichever is greater. To minimize the effect of the converter + system noise, longer conversion times should be used for system capacitive offset calibration. The system capacitance offset calibration range is ±1 pF; the larger offset can be removed using CAPDACs. 5 Specification is not production tested, but guaranteed by design. 6 The gain error is factory calibrated at 25°C. At different temperatures, compensation for gain drift over temperature is required. 7 The VTCHOP bit in the VT SETUP register must be set to 1 for the specified temperature sensor and voltage input performance. 8 Using an external temperature sensing diode 2N3906, with nonideality factor nf = 1.008, connected as in Figure 37, with total serial resistance <100 Ω. 9 Full-scale error applies to both positive and negative full scale. Rev. 0 | Page 4 of 28

AD7747 TIMING SPECIFICATIONS V = 2.7 V to 3.6 V, or 4.75 V to 5.25 V; GND = 0 V; Input Logic 0 = 0 V; Input Logic 1 = V ; −40°C to +125°C, unless otherwise noted. DD DD Table 2. Parameter Min Typ Max Unit Test Conditions/Comments SERIAL INTERFACE1, 2 See Figure 2 SCL Frequency 0 400 kHz SCL High Pulse Width, t 0.6 μs HIGH SCL Low Pulse Width, t 1.3 μs LOW SCL, SDA Rise Time, t 0.3 μs R SCL, SDA Fall Time, t 0.3 μs F Hold Time (Start Condition), t 0.6 μs After this period, the first clock is generated HD;STA Setup Time (Start Condition), t 0.6 μs Relevant for repeated start condition SU;STA Data Setup Time, t 0.1 μs SU;DAT Setup Time (Stop Condition), t 0.6 μs SU;STO Data Hold Time, t (Master) 0 μs HD;DAT Bus-Free Time (Between Stop and Start Condition, t ) 1.3 μs BUF 1 Sample tested during initial release to ensure compliance. 2 All input signals are specified with input rise/fall times = 3 ns, measured between the 10% and 90% points. Timing reference points at 50% for inputs and outputs. Output load = 10 pF. t t R F tLOW tHD;STA SCL tHIGH tSU;STA tSU;STO t tHD;DAT tSU;DAT HD;STA SDA P tBUF S S P 05469-002 Figure 2. Serial Interface Timing Diagram Rev. 0 | Page 5 of 28

AD7747 ABSOLUTE MAXIMUM RATINGS T = 25°C, unless otherwise noted. A Table 3. Stresses above those listed under Absolute Maximum Ratings Parameter Rating may cause permanent damage to the device. This is a stress Positive Supply Voltage V to GND −0.3 V to +6.5 V DD rating only and functional operation of the device at these or Voltage on any Input or Output Pin to −0.3 V to V + 0.3 V DD any other conditions above those indicated in the operational GND section of this specification is not implied. Exposure to absolute ESD Rating (ESD Association Human Body 2000 V maximum rating conditions for extended periods may affect Model, S5.1) device reliability. Operating Temperature Range −40°C to +125°C Storage Temperature Range −65°C to +150°C Junction Temperature 150°C ESD CAUTION TSSOP Package θ 128°C/W JA (Thermal Impedance-to-Air) TSSOP Package θ 14°C/W JC (Thermal Impedance-to-Case) Peak Reflow Soldering Temperature Pb Free (20 sec to 40 sec) 260°C Rev. 0 | Page 6 of 28

AD7747 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SCL 1 16 SDA RDY 2 15 NC SHLD 3 14 VDD AD7747 TST 4 13 GND TOP VIEW REFIN(+) 5 (Not to Scale) 12 VIN(–) REFIN(–) 6 11 VIN(+) CIN1(–) 7 10 NC CIN1(+) N8C = NO CONNECT9 NC 05469-003 Figure 3. Pin Configuration Table 4. Pin Function Descriptions Pin No. Mnemonic Description 1 SCL Serial Interface Clock Input. Connects to the master clock line. Requires pull-up resistor if not already provided in the system. 2 RDY Logic Output. A falling edge on this output indicates that a conversion on enabled channel(s) has been finished and the new data is available. Alternatively, the status register can be read via the 2-wire serial interface and the relevant bit(s) decoded to query the finished conversion. If not used, this pin should be left as an open circuit. 3 SHLD Capacitive Input Active AC Shielding. To eliminate the CIN parasitic capacitance to ground, the SHLD signal can be used for shielding the connection between the sensor and CIN. If not used, this pin should be left as an open circuit. 4 TST This pin must be left as an open circuit for proper operation. 5, 6 REFIN(+), Differential Voltage Reference Input for the Voltage Channel (ADC). Alternatively, the on-chip internal reference REFIN(−) can be used for the voltage channel. These reference input pins are not used for conversion on capacitive channel(s) (CDC). If not used, these pins can be left as an open circuit or connected to GND. 7 CIN1(−) CDC Negative Capacitive Input. The measured capacitance is connected between the CIN1(−) pin and GND. If not used, this pin should be left as an open circuit. 8 CIN1(+) CDC Positive Capacitive Input. The measured capacitance is connected between the CIN1(+) pin and GND. If not used, this pin should be left as an open circuit. 9, 10 NC Not Connected. These pins should be left as an open circuit. 11, 12 VIN(+), VIN(−) Differential Voltage Input for the Voltage Channel (ADC). These pins are also used to connect an external temperature sensing diode. If not used, these pins can be left as an open circuit or connected to GND. 13 GND Ground Pin. 14 VDD Power Supply Voltage. This pin should be decoupled to GND, using a low impedance capacitor, for example in combination with a 10 μF tantalum and a 0.1 μF multilayer ceramic. 15 NC Not Connected. This pin should be left as an open circuit. 16 SDA Serial Interface Bidirectional Data. Connects to the master data line. Requires a pull-up resistor if not provided elsewhere in the system. Rev. 0 | Page 7 of 28

AD7747 TYPICAL PERFORMANCE CHARACTERISTICS 80 10 60 0 40 –10 m) 20 R (fF) p O p 0 R –20 INL ( –20 AP ER C –30 2.7V –40 3.0V –40 ––6800 05469-004 –50 35..30VV 05469-007 –8 –7 –6 –5 –4 –3 –2 –1 0 1 2 3 4 5 6 7 8 0 50 100 150 200 250 300 350 400 450 500 550 600 INPUT CAPACITANCE (pF) CAPACITANCE SHLD TO GND (pF) Figure 4. Capacitance Input Integral Nonlinearity; Figure 7. Capacitance Input Error vs. Capacitance Between SHLD and GND; VDD = 5 V, CAPDAC = 0x3F CIN(+) to GND = 8 pF, VDD = 2.7 V, 3 V, 3.3 V, and 5 V 2000 10 GAIN TC ≈ –28ppm/ºC 0 1000 N ERROR (ppm)–10000 AP ERROR (fF) ––2100 GAI C –30 2.7V –2000 3.0V –40 3.3V –3000 05469-005 –50 5.0V 05469-008 –50 –25 0 25 50 75 100 125 150 0 50 100 150 200 250 300 350 400 450 500 550 600 TEMPERATURE (ºC) CAPACITANCE SHLD TO GND (pF) Figure 5. Capacitance Input Gain Drift vs. Temperature; Figure 8. Capacitance Input Error vs. Capacitance Between SHLD and GND; VDD = 5 V, CIN(+) to GND = 8 pF CIN(+) to GND = 25 pF, VDD = 2.7 V, 3 V, 3.3 V, and 5 V .20 10 .15 0 .10 T ERROR (fF) ––00...0105050 ERROR (fF) ––2100 FFSE –0.15 CAP –30 O 2.7V –0.20 3.0V –40 3.3V ––00..2305 05469-006 –50 5.0V 05469-009 –50 –25 0 25 50 75 100 125 150 0 50 100 150 200 250 300 350 400 450 500 550 600 TEMPERATURE (ºC) CAPACITANCE CIN TO SHLD (pF) Figure 6. Capacitance Input Offset Drift vs. Temperature; Figure 9. Capacitance Input Error vs. Capacitance Between CIN(+) and SHLD; VDD = 5 V, CIN(+) Open CIN(+) to GND = 8 pF, VDD = 2.7 V, 3 V, 3.3 V, and 5V Rev. 0 | Page 8 of 28

AD7747 150 1.0 0.8 100 0.6 0.4 F) 50 F) R (f R (p 0.2 O O RR 0 RR 0 CAP E –50 CAP E–0.2 –0.4 –0.6 –100 –150 05469-010 ––01..80 05469-066 0 10 100 1k 0.01 0.1 1.0 10.0 100 PARALLEL RESISTANCE (MΩ) SHLDTO GND RESISTANCE (MΩ) Figure 10. Capacitance Input Error vs. Parallel Resistance; Figure 13. Capacitance Input Error vs. Resistance Between SHLD and GND; CIN(+) to GND = 8 pF, VDD = 5 V CIN(+) to GND = 8 pF; VDD = 5 V 0 10 –100 0 8 pF –200 –10 –20 –300 F) F) –30 25 pF R (f–400 R (f O O –40 R–500 R R R E E –50 P –600 P CA CA –60 –700 –70 –800 –80 –1–090000 05469-058 ––19000 05469-067 0 25 50 75 100 125 150 175 200 1 10 100 CIN TO SHLD RESISTANCE (kΩ) SERIAL RESISTANCE (kΩ) Figure 11. Capacitance Input Error vs. Resistance Between CIN1(+) and SHLD; Figure 14. Capacitance Input Error vs. Serial Resistance; CIN(+) to GND = 8 pF, VDD= 5 V CIN(+) to GND = 8 pF and 25pF, VDD = 5 V 100 0.2 0 –100 0 –200 F)–300 F) OR (f–400 OR (f R R –0.2 ER–500 ER P P CA–600 CA –700 –0.4 –800 –1–090000 05469-059 –0.6 05469-062 0.091 0.27 0.48 0.96 5 25 100 2.5 3.0 3.5 4.0 4.5 5.0 5.5 CIN TO SHLD RESISTANCE (MΩ) VDD (V) Figure 12. Capacitance Input Error vs. Resistance Between CIN(+) and SHLD; Figure 15. Capacitance Input Power Supply Rejection (PSR); CIN(+) to GND = 25 pF, VDD = 5 V CIN(+) to GND = 8 pF Rev. 0 | Page 9 of 28

AD7747 200 0 150 –20 100 C DNL (fF) 500 N (dB) ––4600 A AI D G AP –50 C –80 –100 –100 ––210500 05469-050 –120 05469-051 0 8 16 24 32 40 48 56 64 0 100 200 300 400 500 600 700 800 900 1k CAPDAC CODE INPUT SIGNAL FREQUENCY (Hz) Figure 16. CAPDAC Differential Nonlinearity (DNL) Figure 19. Capacitive Channel Frequency Response; Conversion Time = 22 ms 2.0 0 1.5 –20 1.0 –40 0.5 OR (°C) 0 N (dB) –60 R AI R G E –0.5 –80 –1.0 –100 ––12..50 05469-034 –120 05469-052 –50 –25 0 25 50 75 100 125 150 0 25 50 75 100 125 150 175 200 TEMPERATURE (°C) INPUT SIGNAL FREQUENCY (Hz) Figure 17. Internal Temperature Sensor Error vs. Temperature Figure 20. Capacitive Channel Frequency Response; Conversion Time = 124 ms 1.0 0 0.5 –20 0 –40 –0.5 OR (°C) –1.0 N (dB) –60 R AI R G E –1.5 –80 –2.0 –100 ––23..50 05469-035 –120 05469-039 –50 –25 0 25 50 75 100 125 150 0 50 100 150 200 250 300 350 400 TEMPERATURE (°C) INPUT SIGNAL FREQUENCY (Hz) Figure 18. External Temperature Sensor Error vs. Temperature Figure 21. Voltage Channel Frequency Response; Conversion Time = 122.1 ms Rev. 0 | Page 10 of 28

AD7747 OUTPUT NOISE AND RESOLUTION SPECIFICATIONS The AD7747 resolution is limited by noise. The noise Table 6 and Table 7 show typical noise performance and performance varies with the selected conversion time. resolution for the voltage channel. These numbers were generated from 1000 data samples acquired in continuous Table 5 shows typical noise performance and resolution for the conversion mode with VIN pins shorted to ground. capacitive channel. These numbers were generated from 1000 data samples acquired in continuous conversion mode, at an RMS noise represents the standard deviation and p-p noise excitation of 16 kHz, ±V × 3/8, and with all CIN and SHLD represents the difference between minimum and maximum DD pins connected only to the evaluation board (no external results in the data. Effective resolution is calculated from rms capacitors). noise, and p-p resolution is calculated from p-p noise. Table 5. Typical Capacitive Input Noise and Resolution vs. Conversion Time (Bold line represents default setting) Conversion Output Data −3 dB Frequency RMS Noise RMS P-P Effective Resolution P-P Resolution Time (ms) Rate (Hz) (Hz) (aF/√Hz) Noise (aF) Noise (aF) (Bits) (Bits) 22.0 45.5 43.6 28.8 190 821 16.4 14.3 23.9 41.9 39.5 23.2 146 725 16.8 14.5 40.0 25.0 21.8 11.1 52 411 18.3 15.3 76.0 13.2 10.9 11.2 37 262 18.7 15.9 124.0 8.1 6.9 11.0 29 174 19.1 16.5 154.0 6.5 5.3 10.4 24 173 19.3 16.5 184.0 5.4 4.4 10.0 21 141 19.6 16.8 219.3 4.6 4.0 9.0 18 126 19.9 17.0 Table 6. Typical Voltage Input Noise and Resolution vs. Conversion Time, Internal Voltage Reference Conversion Output Data −3 dB Frequency RMS Noise P-P Noise Effective Resolution P-P Resolution Time (ms) Rate (Hz) (Hz) (μV) (μV) (Bits) (Bits) 20.1 49.8 26.4 11.4 62 17.6 15.2 32.1 31.2 15.9 7.1 42 18.3 15.7 62.1 16.1 8.0 4.0 28 19.1 16.3 122.1 8.2 4.0 3.0 20 19.5 16.8 Table 7. Typical Voltage Input Noise and Resolution vs. Conversion Time, External 2.5 V Voltage Reference Conversion Output Data −3 dB Frequency RMS Noise P-P Noise Effective Resolution P-P Resolution Time (ms) Rate (Hz) (Hz) (μV) (μV) (Bits) (Bits) 20.1 49.8 26.4 14.9 95 18.3 15.6 32.1 31.2 15.9 6.3 42 19.6 16.8 62.1 16.1 8.0 3.3 22 20.5 17.7 122.1 8.2 4.0 2.1 15 21.1 18.3 Rev. 0 | Page 11 of 28

AD7747 SERIAL INTERFACE The AD7747 supports an I2C-compatible 2-wire serial interface. In continuous conversion mode, the address pointer’s auto- The two wires on the I2C bus are called SCL (clock) and SDA incrementer should be used for reading a conversion result. (data). These two wires carry all addressing, control, and data That means the three data bytes should be read using one information one bit at a time over the bus to all connected multibyte read transaction rather than three separate single byte peripheral devices. The SDA wire carries the data, while the transactions. The single byte data read transaction may result in SCL wire synchronizes the sender and receiver during the data the data bytes from two different results being mixed. The same transfer. I2C devices are classified as either master or slave devices. applies for six data bytes if both the capacitive and the A device that initiates a data transfer message is called a master, voltage/temperature channel are enabled. while a device that responds to this message is called a slave. The user can also access any unique register (address) on a one- To control the AD7747 device on the bus, the following to-one basis without having to update all the registers. The protocol must be followed. First, the master initiates a data address pointer register’s contents cannot be read. transfer by establishing a start condition, defined by a high-to- If an incorrect address pointer location is accessed, or if the user low transition on SDA while SCL remains high. This indicates allows the auto-incrementer to exceed the required register that the start byte follows. This 8-bit start byte is made up of a address, the following applies: 7-bit address plus an R/W bit indicator. • In read mode, the AD7747 continues to output various All peripherals connected to the bus respond to the start internal register contents until the master device issues a condition and shift in the next 8 bits (7-bit address + R/W bit). no acknowledge, start, or stop condition. The address The bits arrive MSB first. The peripheral that recognizes the pointer auto-incrementer’s contents are reset to point to transmitted address responds by pulling the data line low the status register at Address 0x00 when a stop condition is during the ninth clock pulse. This is known as the acknowledge received at the end of a read operation. This allows the bit. All other devices withdraw from the bus at this point and status register to be read (polled) continually without maintain an idle condition. An exception to this is the general having to constantly write to the address pointer. call address, which is described later in this document. The idle condition is where the device monitors the SDA and SCL lines • In write mode, the data for the invalid address is not waiting for the start condition and the correct address byte. The loaded into the AD7747 registers, but an acknowledge is R/W bit determines the direction of the data transfer. A Logic 0 issued by the AD7747. LSB in the start byte means that the master writes information WRITE OPERATION to the addressed peripheral. In this case, the AD7747 becomes a When a write is selected, the byte following the start byte is slave receiver. A Logic 1 LSB in the start byte means that the always the register address pointer (subaddress) byte, which master reads information from the addressed peripheral. In this points to one of the internal registers on the AD7747. The case, the AD7747 becomes a slave transmitter. In all instances, the address pointer byte is automatically loaded into the address AD7747 acts as a standard slave device on the I2C bus. pointer register and acknowledged by the AD7747. After the The start byte address for the AD7747 is 0x90 for a write and address pointer byte acknowledge, a stop condition, a repeated 0x91 for a read. start condition, or another data byte can follow from the master. READ OPERATION A stop condition is defined by a low-to-high transition on SDA When a read is selected in the start byte, the register that is while SCL remains high. If a stop condition is ever encountered currently addressed by the address pointer is transmitted on to by the AD7747, it returns to its idle condition and the address the SDA line by the AD7747. This is then clocked out by the pointer is reset to Address 0x00. master device and the AD7747 awaits an acknowledge from the If a data byte is transmitted after the register address pointer master. byte, the AD7747 loads this byte into the register that is If an acknowledge is received from the master, the address auto- currently addressed by the address pointer register, sends an incrementer automatically increments the address pointer acknowledge, and the address pointer auto-incrementer register and outputs the next addressed register content on to automatically increments the address pointer register to the the SDA line for transmission to the master. If no acknowledge next internal register address. Thus, subsequent transmitted is received, the AD7747 returns to the idle state and the address data bytes are loaded into sequentially incremented addresses. pointer is not incremented. If a repeated start condition is encountered after the address The address pointer’s auto-incrementer allows block data to be pointer byte, all peripherals connected to the bus respond written or read from the starting address and subsequent exactly as outlined above for a start condition, that is, a repeated incremental addresses. start condition is treated the same as a start condition. When a master device issues a stop condition, it relinquishes control of Rev. 0 | Page 12 of 28

AD7747 the bus, allowing another master device to take control of the GENERAL CALL bus. Therefore, a master wanting to retain control of the bus When a master issues a slave address consisting of seven 0s with issues successive start conditions known as repeated start the eighth bit (R/W bit) set to 0, this is known as the general call conditions. address. The general call address is for addressing every device AD7747 RESET connected to the I2C bus. The AD7747 acknowledges this address and read in the following data byte. To reset the AD7747 without having to reset the entire I2C bus, an explicit reset command is provided. This uses a particular If the second byte is 0x06, the AD7747 is reset, completely address pointer word as a command word to reset the part and uploading all default values. The AD7747 does not respond to upload all default settings. The AD7747 does not respond to the the I2C bus commands (do not acknowledge) during the default I2C bus commands (do not acknowledge) during the default values upload for approximately 150 μs (200 μs maximum). values upload for approximately 150 μs (max 200 μs). The AD7747 does not acknowledge any other general call The reset command address word is 0xBF. commands. SDATA SCLOCKSTASRTA1D–D7R R/8W AC9K SUB1A–7DDRE8SS A9CK 1–D7ATA8 AC9K STPOP 05469-011 Figure 22. Bus Data Transfer WRITE S SLAVEADDR A(S) SUBADDR A(S) DATA A(S) DATA A(S) P SEQUENCE LSB = 1 LSB = 0 READ S SLAVEADDR A(S) SUBADDR A(S) S SLAVEADDR A(S) DATA A(M) DATA A(M) P SEQUENCE SP == SSTTAORPT B BITIT AA((SM)) ==AACCKKNNOOWWLLEEDDGGEE BBYY SMLAASVTEER AA((SM)) == NNOOAACCKKNNOOWWLLEEDDGGEE BBYY SMLAASVTEER 05469-012 Figure 23. Write and Read Sequences Rev. 0 | Page 13 of 28

AD7747 REGISTER DESCRIPTIONS The master can write to or read from all of the AD7747 registers and a read/write operation is selected, the address pointer except the address pointer register, which is a write-only register is set up. The address pointer register determines from register. The address pointer register determines which register or to which register the operation takes place. A read/write the next read or write operation accesses. All communications operation is performed from/to the target address, which then with the part through the bus start with an access to the address increments to the next address until a stop command on the bus pointer register. After the part has been accessed over the bus is performed. Table 8. Register Summary Address Pointer Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register (Dec) (Hex) Dir Default Value Status 0 0x00 R – – – – – RDY RDYVT RDYCAP 0 0 0 0 0 1 1 1 Cap Data H 1 0x01 R Capacitive channel data—high byte, 0x00 Cap Data M 2 0x02 R Capacitive channel data—middle byte, 0x00 Cap Data L 3 0x03 R Capacitive channel data—low byte, 0x00 VT Data H 4 0x04 R Voltage/temperature channel data—high byte, 0x00 VT Data M 5 0x05 R Voltage/temperature channel data—middle byte, 0x00 VT Data L 6 0x06 R Voltage/temperature channel data—low byte, 0x00 Cap Setup 7 0x07 R/W CAPEN – CAPDIFF – – – – – 0 0 0 0 0 0 0 0 VT Setup 8 0x08 R/W VTEN VTMD1 VTMD0 EXTREF – – VTSHORT VTCHOP 0 0 0 0 0 0 0 0 EXC Setup 9 0x09 R/W – – – – EXCDAC EXCEN EXCLVL1 EXCLVL0 0 0 0 0 0 0 1 1 Configuration 10 0x0A R/W VTFS1 VTFS0 CAPFS2 CAPFS1 CAPFS0 MD2 MD1 MD0 1 0 1 0 0 0 0 0 Cap DAC A 11 0x0B R/W DACAENA – DACA—6-Bit Value 0 0 0x00 Cap DAC B 12 0x0C R/W DACBENB – DACB—6-Bit Value 0 0 0x00 Cap Offset H 13 0x0D R/W Capacitive offset calibration—high byte, 0x80 Cap Offset L 14 0x0E R/W Capacitive offset calibration—low byte, 0x00 Cap Gain H 15 0x0F R/W Capacitive gain calibration—high byte, factory calibrated Cap Gain L 16 0x10 R/W Capacitive gain calibration—low byte, factory calibrated Volt Gain H 17 0x11 R/W Voltage gain calibration—high byte, factory calibrated Volt Gain L 18 0x12 R/W Voltage gain calibration—low byte, factory calibrated Rev. 0 | Page 14 of 28

AD7747 STATUS REGISTER Address Pointer 0x00, Read Only, Default Value 0x07 This register indicates the status of the converter. The status register can be read via the 2-wire serial interface to query a finished conversion. The RDY pin reflects the status of the RDY bit. Therefore, the RDY pin high-to-low transition can be used as an alternative indication of the finished conversion. Table 9. Status Register Bit Map Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Mnemonic – – – – – RDY RDYVT RDYCAP Default 0 0 0 0 0 1 1 1 Table 10. Bit Mnemonic Description 7 to 3 – Not used, always read 0. 2 RDY RDY = 0 indicates that conversion on the enabled channel(s) is complete and new unread data is available. If both capacitive and voltage/temperature channels are enabled, the RDY bit is changed to 0 after conversion on both channels is complete. The RDY bit returns to 1 either when data is read or prior to finishing the next conversion. If, for example, only the capacitive channel is enabled, then the RDY bit reflects the RDYCAP bit. 1 RDYVT RDYVT = 0 indicates that a conversion on the voltage/temperature channel is complete and new unread data is available. 0 RDYCAP RDYCAP = 0 indicates that a conversion on the capacitive channel is complete and new unread data is available. CAP DATA REGISTER VT DATA REGISTER 24 Bits, Address Pointer 0x01, 0x02, 0x03, Read-Only, 24 Bits, Address Pointer 0x04, 0x05, 0x06, Read-Only, Default Value 0x000000 Default Value 0x000000 This register contains the capacitive channel output data. The This register contains the voltage/temperature channel output register is updated after finished conversion on the capacitive data. The register is updated after finished conversion on the channel, with one exception: When the serial interface read voltage channel or temperature channel, with one exception: operation from the Cap Data register is in progress, the data When the serial interface read operation from the VT Data register is not updated and the new capacitance conversion register is in progress, the data register is not updated and the result is lost. new voltage/temperature conversion result is lost. The stop condition on the serial interface is considered to be the The stop condition on the serial interface is considered to be the end of the read operation. Therefore, to prevent data corruption, end of the read operation. Therefore, to prevent data corruption, all three bytes of the data register should be read sequentially all three bytes of the data register should be read sequentially using the register address pointer auto-increment feature of the using the register address pointer auto-increment feature of the serial interface. serial interface. To prevent losing some of the results, the Cap Data register For voltage input, Code 0 represents negative full scale (−V ), REF should be read before the next conversion on the capacitive the 0x800000 code represents zero scale (0 V), and the channel is finished. 0xFFFFFF code represents positive full scale (+V ). REF The 0x000000 code represents negative full scale (−8.192 pF), To prevent losing some of the results, the VT Data register the 0x800000 code represents zero scale (0 pF), and the should be read before the next conversion on the voltage/ 0xFFFFFF code represents positive full scale (+8.192 pF). temperature channel is complete. For the temperature sensor, the temperature can be calculated from code using the following equation: Temperature (°C) = (Code/2048) − 4096 Rev. 0 | Page 15 of 28

AD7747 CAP SETUP REGISTER Address Pointer 0x07, Default Value 0x00 Capacitive channel setup. Table 11. Cap Setup Register Bit Map Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Mnemonic CAPEN – CAPDIFF – – – – – Default 0 0 0 0 0 0 0 0 Table 12. Bit Mnemonic Description 7 CAPEN CAPEN = 1 enables capacitive channel for single conversion, continuous conversion, or calibration. 6 – This bit must be 0 for proper operation. 5 CAPDIFF This bit must be set to 1 for proper operation. 4 to 0 – These bits must be 0 for proper operation. VT SETUP REGISTER Address Pointer 0x08, Default Value 0x00 Voltage/Temperature channel setup. Table 13. VT Setup Register Bit Map Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Mnemonic VTEN VTMD1 VTMD0 EXTREF – – VTSHORT VTCHOP Default 0 0 0 0 0 0 0 0 Table 14. Bit Mnemonic Description 7 VTEN VTEN = 1 enables voltage/temperature channel for single conversion, continuous conversion, or calibration. 6 VTMD1 Voltage/temperature channel input configuration. 5 VTMD0 VTMD1 VTMD0 Channel Input 0 0 Internal temperature sensor 0 1 External temperature sensor diode 1 0 V monitor DD 1 1 External voltage input (VIN) 4 EXTREF EXTREF = 1 selects an external reference voltage connected to REFIN(+), REFIN(−) for the voltage input or the V monitor. DD EXTREF = 0 selects the on-chip internal reference. The internal reference must be used with the internal temperature sensor for proper operation. 3 to 2 – These bits must be 0 for proper operation. 1 VTSHORT VTSHORT = 1 internally shorts the voltage/temperature channel input for test purposes. 0 VTCHOP = 1 VTCHOP = 1 sets internal chopping on the voltage/temperature channel. The VTCHOP bit must be set to 1 for the specified voltage/temperature channel performance. Rev. 0 | Page 16 of 28

AD7747 EXC SETUP REGISTER Address Pointer 0x09, Default Value 0x03 Capacitive channel excitation setup. Table 15. EXC Setup Bit Map Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Mnemonic – – – – EXCDAC EXCEN EXCLVL1 EXCLVL0 Default 0 0 0 0 0 0 1 1 Table 16. Bit Mnemonic Description 7 to 4 – These bits must be 0 for proper operation. 3 EXCDAC CAPDAC excitation. This bit must be set to 1 for the proper capacitive channel operation. 2 EXCEN CIN and AC SHLD excitation. This bit must be set to 1 for the proper capacitive channel operation. 1 EXCLVL1, Excitation Voltage Level. Must be set to ±V × 3/8 to allow operation for specified performance. DD 0 EXCLVL0 EXCLVL1 EXCLVL0 Voltage on Cap EXC Low Level EXC High Level 0 0 ±V /8 V × 3/8 V × 5/8 DD DD DD 0 1 ±V /4 V × 1/4 V × 3/4 DD DD DD 1 0 ±V × 3/8 V × 1/8 V × 7/8 DD DD DD 1 1 ±V /2 0 V DD DD Rev. 0 | Page 17 of 28

AD7747 CONFIGURATION REGISTER Address Pointer 0x0A, Default Value 0xA0 Converter update rate and mode of operation setup. Table 17. Configuration Register Bit Map Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Mnemonic VTFS1 VTFS0 CAPFS2 CAPFS1 CAPFS0 MD2 MD1 MD0 Default 0 0 0 0 0 0 0 0 Table 18. Bit Mnemonic Description 7 VTFS1 Voltage/temperature channel digital filter setup—conversion time/update rate setup. 6 VTFS0 VTCHOP = 1 VTFS1 VTFS0 Conversion Time (ms) Update Rate (Hz) −3 dB Frequency (Hz) 0 0 20.1 49.8 26.4 0 1 32.1 31.2 15.9 1 0 62.1 16.1 8.0 1 1 122.1 8.2 4.0 5 CAPFS2 Capacitive channel digital filter setup—conversion time/update rate setup. 4 CAPFS1 CAPFS2 CAPFS1 CAPFS0 Conversion Time (ms) Update Rate −3 dB Frequency (Hz) 3 CAPFS0 0 0 0 22.0 45.5 43.6 0 0 1 23.9 41.9 39.5 0 1 0 40.0 25.0 21.8 0 1 1 76.0 13.2 10.9 1 0 0 124.0 8.1 6.9 1 0 1 154.0 6.5 5.3 1 1 0 184.0 5.5 4.4 1 1 1 219.3 4.6 4.0 2 MD2 Converter mode of operation setup. 1 MD1 MD2 MD1 MD0 Mode 0 MD0 0 0 0 Idle 0 0 1 Continuous conversion 0 1 0 Single conversion 0 1 1 Power-down 1 0 0 – 1 0 1 Capacitance system offset calibration 1 1 0 Capacitance or voltage system gain calibration 1 1 1 – Rev. 0 | Page 18 of 28

AD7747 CAP DAC A REGISTER Address Pointer 0x0B, Default Value 0x00 Capacitive DAC setup. Table 19. Cap DAC A Register Bit Map Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Mnemonic DACAENA – DACA—6-Bit Value Default 0 0 0x00 Table 20. Bit Mnemonic Description 7 DACAENA DACAENA = 1 connects capacitive DACA to the positive capacitance input. 6 – This bit must be 0 for proper operation. 5 to 1 DACA DACA value, Code 0x00 ≈ 0 pF, Code 0x3F ≈ full range. CAP DAC B REGISTER Address Pointer 0x0C, Default Value 0x00 Capacitive DAC setup. Table 21. Cap DAC B Register Bit Map Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Mnemonic DACBENB – DACB—6-Bit Value Default 0 0 0x00 Table 22. Bit Mnemonic Description 7 DACBENB DACBENB = 1 connects capacitive DACB to the negative capacitance input. 6 – This bit must be 0 for proper operation. 5 to 1 DACB DACB value, Code 0x00 ≈ 0 pF, Code 0x3F ≈ full range. Rev. 0 | Page 19 of 28

AD7747 CAP OFFSET CALIBRATION REGISTER CAP GAIN CALIBRATION REGISTER 16 Bits, Address Pointer 0x0D, 0x0E, 16 Bits, Address Pointer 0x0F, 0x10, Default Value 0x8000 Default Value 0xXXXX The capacitive offset calibration register holds the capacitive Capacitive gain calibration register. The register holds the channel zero-scale calibration coefficient. The coefficient is capacitive channel full-scale factory calibration coefficient. used to digitally remove the capacitive channel offset. The VOLT GAIN CALIBRATION REGISTER register value is updated automatically following the execution 16 Bits, Address Pointer 0x11,0x12, of a capacitance offset calibration. The capacitive offset calibra- Default Value 0xXXXX tion resolution (cap offset register LSB) is less than 32 aF; the full range is ±1 pF. Voltage gain calibration register. The register holds the voltage channel full-scale factory calibration coefficient. Rev. 0 | Page 20 of 28

AD7747 CIRCUIT DESCRIPTION VDD ACTIVE AC SHIELD CONCEPT The AD7747 measures capacitance between CIN and ground. TEMP SENSOR GECNLEORCAKTOR AD7747 That means any capacitance to ground on signal path between VIN(+) the AD7747 CIN pin(s) and sensor is included in the AD7747 VIN(–) 24-BIT Σ-Δ DIGITAL I2C SDA conversion result. MUX GENERATOR FILTER SERIAL INTERFACE SCL CIN1(+) The parasitic capacitance of the sensor connections can easily CONTROL LOGIC be in the same, if not even higher, order as the capacitance of CIN1(–) CALIBRATION RDY the sensor itself. If that parasitic capacitance is stable, it can be SHLD VOLTAGE treated as a nonchanging capacitive offset. However, the para- CAP DAC 1 REFERENCE EXCITATION sitic capacitance of sensor connections is often changing as a CAP DAC 2 result of mechanical movement, changing ambient temperature, REFIN(+) REFIN(–) GND 05469-013 acomnbvieernsti ohnu mreisduiltty a, netdc .m Tahye ssieg cnhifaincagnestl yar ceo smeepnr oams disreif tth ien styhset em Figure 24. AD7747 Block Diagram accuracy. OVERVIEW To eliminate the CIN parasitic capacitance to ground, the The AD7747 core is a high precision converter consisting of a AD7747 SHLD signal can be used for shielding the connection second-order (Σ-Δ or charge balancing) modulator and a third- between the sensor and CIN, as shown in Figure 25. The SHLD order digital filter. It works as a CDC for the capacitive inputs output is basically the same signal waveform as the excitation of and as a classic ADC for the voltage input or for the voltage the CIN pin; the SHLD is driven to the same voltage potential from a temperature sensor. as the CIN pin. Therefore, there is no ac current between CIN In addition to the converter, the AD7747 integrates a multi- and SHLD pins, and any capacitance between these pins does plexer, an excitation source and CAPDACs for the capacitive not affect the CIN charge transfer. Ideally, the CIN to SHLD inputs, a temperature sensor and a voltage reference for the capacitance does not have any contribution to the AD7747 result. voltage and temperature inputs, a complete clock generator, To get the best result, locate the AD7747 as close as possible to a control and calibration logic, and an I2C-compatible serial the capacitive sensor. Keep the connection between the sensor interface. and AD7747 CIN pin, and also the return path between sensor CAPACITANCE-TO-DIGITAL CONVERTER ground and the AD7747 GND pin, short. Shield the PCB track to the CIN pin and connect the shielding to the AD7747 SHLD Figure 25 shows the CDC simplified functional diagram. The pin. In addition, if a shielded cable is used for sensor connection, measured capacitance C is connected between the Σ-Δ modu- X the shield should be connected to the AD7747 SHLD pin. lator input and ground. A square-wave excitation signal is applied on the C during the conversion and the modulator CAPDAC X continuously samples the charge going through the CX. The The AD7747 CDC full-scale input range is ±8.192 pF. For sim- digital filter processes the modulator output, which is a stream plicity of calculation, however, the following text and figures use of 0s and 1s containing the information in 0 and 1 density. The ±8 pF. The part can accept a higher capacitance on the input data from the digital filter is scaled, applying the calibration and the common-mode or offset (nonchanging component) coefficients, and the final result can be read through the serial capacitance can be balanced by programmable on-chip CAPDACs. interface. CAPACITANCETO DIGITAL CONVERTER CAPDAC(+) (CDC) CIN(+) CLOCK GENERATOR CDC DATA CIN(–) DATA CIN 24-BIT Σ-Δ DIGITAL MODULATOR FILTER CAPDAC(–) CX CY EXCITATION CX SHLD 05469-014 SHLD 05649-015 Figure 25. CDC Simplified Block Diagram Figure 26. Using a CAPDAC Rev. 0 | Page 21 of 28

AD7747 The CAPDAC can be understood as a negative capacitance Figure 29 shows how to shift the input range further, up to connected internally to the CIN pin. There are two independent 25 pF absolute value of capacitance connected to the CIN(+). CAPDACs, one connected to the CIN(+) and the second con- nected to the CIN(−). The relation between the capacitance 0x000000 CAPDAC(+) TO input and output data can be expressed as 17pF 0xFFFFFF DATA ≈ (C −CAPDAC(+))−(C −CAPDAC(−)) CIN(+) DATA X Y CAPDIFF=1 ±8pF CIN(–) CDC The CAPDACs have a 6-bit resolution, monotonic transfer function, are well matched to each other, and have a defined temperature coefficient. The CAPDAC full range (absolute CAPDAC(–) 0pF value) is not factory calibrated and can vary up to ±20% with CX 9...25pF tFhigeu mrea n1u6 foafc ttuhrei ntygp picraolc pesesr.f oSreme tahnec eS pcehcairfaiccatetiroisntsi csse. ction and (17pF ± 8pF) SHLD 05469-018 SINGLE-ENDED CAPACITIVE CONFIGURATION Figure 29. Using CAPDAC in Single-Ended Configuration The AD7747 can be used for interfacing to a single-ended DIFFERENTIAL CAPACITIVE CONFIGURATION capacitive sensor. In this configuration the sensor should be When the AD7747 is used for interfacing to a differential connected to one of the AD7747 CIN pins, for example CIN(+) capacitive sensor, each of the two input capacitances, C and C X Y, and the other pin should be left open circuit. Note that the must be less than 8 pF (without using the CAPDACs) or must CAPDIFF bit in the Cap Setup register must be set to 1 at all be less than 25 pF and balanced by the CAPDACs. Balancing times for the correct operation. by the CAPDACs means that both C − CAPDAC(+) and X It is recommended to guard the unused CIN input with the CY − CAPDAC(−) are less than 8 pF. active shield to ensure the best performance in terms of noise, If the unbalanced capacitance connected to CIN pins is higher offset, and offset drift. than 8 pF, the CDC introduces a gain error, an offset error, and The CDC (without using the CAPDACs) measure the positive nonlinearity error. (or the negative) input capacitance in the range of 0 pF to 8 pF See the examples shown in Figure 30, Figure 31, and Figure 32. (see Figure 27). 0x000000 CAPDAC(+) 0x8T0O0000 COAFPFDAC(+) 0xFTFOFFFF OFF 0xFFFFFF CIN(+) DATA CIN(+) DATA ±8pF CIN(–) CAPDIFF=1 CDC CAPDIFF=1 0...8pF CIN(–) CDC CAPDAC(–) CAPDAC(–) CX CY OFF CX OFF 0...8pF 0...8pF 0...8pF SHLD 05469-016 Figure 30. CSDHCL DDifferential Input Configuration 05469-019 Figure 27. CDC Single-Ended Input Configuration The CAPDAC can be used for programmable shifting of the input range. The example in Figure 28 shows how to use the full 0x000000 CAPDAC(+) TO ±8 pF CDC span to measure capacitance between 0 pF to 16 pF. 17pF 0xFFFFFF CIN(+) DATA 0x000000 ±8pF C8pAFPDAC(+) 0xFTFOFFFF CIN(–) CAPDIFF=1 CDC CIN(+) DATA CAPDIFF=1 ±8pF CAPDAC(–) CIN(–) CDC 17pF CX CY 13...21pF 13...21pF C0.X..16pF C0pAFPDAC(–) (17pF ± 4pF) (17pF ± 4pF) SHLD 05469-020 Figure 31. Using CAPDAC in Differential Configuration SHLD 05469-017 Figure 28. Using CAPDAC in Single-Ended Configuration Rev. 0 | Page 22 of 28

AD7747 Parasitic resistances, as shown in Figure 34, cause leakage 0x000000 CAPDAC(+) TO currents, which affect the CDC result. The AD7747 CDC 17pF 0xFFFFFF measures the charge transfer between the CIN pin and ground. CIN(+) DATA Any resistance connected in parallel to the measured ±8pF CIN(–) CAPDIFF=1 CDC capacitance, CX, such as the parasitic resistance, RP1, also transfers charge. Therefore, the parallel resistor is seen as an additional capacitance in the output data. A resistance in the CAPDAC(–) CX CY 17pF range of RP1 ≥ 10 MΩ causes an offset error in the CDC result. 9 TO 25pF 17pF An offset calibration can be used to compensate for the effect of (17pF ± 8pF) SHLD 05469-021 sRmP1a ≤ll 1le0a MkaΩge, creusrureltns tisn. Aa ghaiignh eerrr loera,k aang eo fcfusertr eenrtr otor, garnodu an d, Figure 32. Using CAPDAC in Differential Configuration nonlinearity error. See Figure 10 in the Typical Performance PARASITIC CAPACITANCE Characteristics section. The CDC architecture used in the AD7747 measures the A parasitic resistance, R P2, between SHLD and ground, as well capacitance CX connected between the CIN pin and ground. as RP3 between the CIN pin and the active shield, as shown in Most applications use the active shield to avoid external influ- Figure 34, cause a leakage current, which affects the CDC result ences during the CDC. However, any parasitic capacitance, C , and is seen as an offset in the data. An offset calibration can be P as shown in Figure 33, can affect the CDC result. used to compensate for effect of the small leakage current caused by a resistance R and R ≥ 200 kΩ. See Figure 11, P2 P3 Figure 12, and Figure 13 in the Typical Performance DATA CIN Characteristics section. CDC PARASITIC SERIAL RESISTANCE CP1 CX CP2 CP3 SHLD 05469-041 RS CIN CDC DATA Figure 33. Parasitic Capacitance A parasitic capacitance, C , coupled in between CIN and CX P1 ground adds directly to the value of the capacitance C and, tbhreartieofonr me, itghhet CbDe sCu frfeiscuieltn its t:o D cAoTmAp e≈n CsaXt e+ fCorP 1a. Asmn aolfl fpsXeatr acsailtii-c SHLD 05469-043 Figure 35. Parasitic Serial Resistance capacitance (C ≤ 1pF). For a larger parasitic capacitance, the P1 The AD7747 CDC result is affected by a resistance in series CAPDAC can be used to compensate, followed by an offset with the measured capacitance. The serial resistance should be calibration to ensure the full range of ±8pF is available for less than 10 kΩ for the specified performance. See Figure 14 in the system. the Typical Performance Characteristics section. Other parasitic capacitances, such as C between active shield P2 CAPACITIVE GAIN CALIBRATION and ground as well as C between the CIN pin and SHLD, P3 could influence the conversion result. However, the graphs in The AD7747 gain is factory calibrated for the full scale of the Typical Performance Characteristics section show that the ±8.192 pF in the production for each part individually. The effect of parasitic capacitance of type C /C below 250 pF is factory gain coefficient is stored in a one-time programmable P2 P3 insignificant to the CDC result. Figure 7 and Figure 8 show the (OTP) memory and is copied to the capacitive gain register at gain error caused by C . Figure 9 shows the gain error caused power-up or after reset. P2 by C . P3 The gain can be changed by executing a capacitance gain calibra- PARASITIC RESISTANCE tion mode, for which an external full-scale capacitance needs to be connected to the capacitance input, or by writing a user value to the capacitive gain register. This change would be only DATA CIN CDC temporary, and the factory gain coefficient would be reloaded back after power-up or reset. The part is tested and specified for RP1 CX RP2 RP3 use only with the default factory calibration coefficient. SHLD 05649-042 Figure 34. Parasitic Resistance on CIN Rev. 0 | Page 23 of 28

AD7747 CAPACITIVE SYSTEM OFFSET CALIBRATION where: The capacitive offset is dominated by the parasitic offset in the K is Boltzmann’s constant (1.38 × 10−23). application, such as the initial capacitance of the sensor, any T is the absolute temperature in Kelvin. parasitic capacitance of tracks on the board, and the capacitance q is the charge on the electron (1.6 × 10−19 coulombs). of any other connections between the sensor and the CDC. N is the ratio of the two currents. Therefore, the AD7747 is not factory calibrated for capacitive nf is the ideality factor of the thermal diode. offset. It is the user’s responsibility to calibrate the system The AD7747 uses an on-chip transistor to measure the capacitance offset in the application. temperature of the silicon chip inside the package. The Σ-Δ Any offset in the capacitance input larger than ±1 pF should ADC converts the ΔVBE to digital; the data are scaled using first be removed using the on-chip CAPDACs. The small offset factory calibration coefficients. Thus, the output code is within ±1 pF can then be removed by using the capacitance proportional to temperature. offset calibration register. Code Temperature(°C)= −4096 One method of adjusting the offset is to connect a zero-scale 2048 capacitance to the input and execute the capacitance offset The AD7747 has a low power consumption resulting in only a calibration mode. The calibration sets the midpoint of the small effect due to the part self-heating (less than 0.5°C at ±8.192 pF range (that is, Output Code 0x800000) to that V = 5 V). DD zero-scale input. If the capacitive sensor can be considered to be at the same Another method is to calculate and write the offset calibration temperature as the AD7747 chip, the internal temperature register value; the LSB value is 31.25 aF (8.192 pF/217). sensor can be used as a system temperature sensor. That means The offset calibration register is reloaded by the default value at the complete system temperature drift compensation can be power-on or after reset. Therefore, if the offset calibration is not based on the AD7747 internal temperature sensor without need repeated after each system power-up, the calibration coefficient for any additional external components. See Figure 17 in the value should be stored by the host controller and reloaded as Typical Performance Characteristics section. part of the AD7747 setup. EXTERNAL TEMPERATURE SENSOR INTERNAL TEMPERATURE SENSOR VDD EXTERNAL INTERNAL TEMPERATURE SENSOR TEMPERATURE VDD SENSOR I ... N × I I N × I CLOCK GENERATOR GECNLEORCAKTOR 2N3906 RS1 VIN(+) DIGITAL DATA ΔVBE RS2 VIN(–) M2O4D-BUILTA ΣT-OΔR FIALNTDER DIGITAL DATA SCALING ΔVBE M2O4D-BUILTA ΣT-OΔR FIALNTDER VOLTAGE VOLTAGE SCALING REFERENCE 05469-027 REFERENCE 05469-026 The AD7F7ig4u7r ep 3r7o.v Tirdaenss istthoer aosp atnio Enx toerfn uasl iTnemg paenr aetxutreer Sneanls otrr ansistor Figure 36. Internal Temperature Sensor as a temperature sensor in the system. The ΔV method, which BE The temperature sensing method used in the AD7747 is to is similar to the internal temperature sensor method, is used. measure a difference in ΔVBE voltage of a transistor operated at However, it is modified to compensate for the serial resistance two different currents (see Figure 36). The ΔVBE change with of connections to the sensor. Total serial resistance (RS1 + RS2 in temperature is linear and can be expressed as Figure 37) up to 100 Ω is compensated. The VIN(−) pin must KT be grounded for proper external temperature sensor operation. ΔV =(n ) ×ln(N) BE f q The AD7747 is factory calibrated for Transistor 2N3906 with the ideality factor n = 1.008. f See Figure 18 in the Typical Performance Characteristics section. Rev. 0 | Page 24 of 28

AD7747 VOLTAGE INPUT The AD7747 Σ-Δ core can work as a high resolution (up to 21 ENOB) classic ADC with a fully differential voltage input. VDD The ADC can be used either with the on-chip high precision, ANALOGTO DIGITAL CONVERTER (ADC) low drift, 1.17 V voltage reference, or with an external reference connected to the fully differential reference input pins. The voltage and reference inputs are continuously sampled by CLOCK GENERATOR a Σ-Δ modulator during the conversion. Therefore, the input VIN(+) DATA source impedance should be kept low. See the application RT RTD 24-BIT Σ-Δ DIGITAL example in Figure 38. VIN(–) MODULATOR FILTER V MONITOR DD Along with converting external voltages, the AD7747 Σ-Δ ADC REFIN(+) VOLTAGE can be used for monitoring the V voltage. The voltage from REFERENCE DD RREF the VDD pin is internally attenuated by 6. REFIN(–) GND 05469-028 Figure 38. Resistive Temperature Sensor Connected to the Voltage Input Rev. 0 | Page 25 of 28

AD7747 TYPICAL APPLICATION DIAGRAM 3V/5V + POWERSUPPLY 0.1µF 10µF 10kΩ 10kΩ VDD TEMP SENSOR GECNLEORCAKTOR AD7747 SHYSOTSETM VIN(+) SDA VIN(–) MUX G2E4N-BEIRTAΣT-OΔR DFIIGLTITEARL SEIR2CIAL SCL CIN1(+) INTERFACE RDY CIN1(–) CONTROLLOGIC CALIBRATION SHLD VOLTAGE CAPDAC1 REFERENCE EXCITATION CAPDAC2 REFIN(+) REFIN(–) GND 05469-029 Figure 39. Basic Application Diagram for a Differential Capacitive Sensor Rev. 0 | Page 26 of 28

AD7747 OUTLINE DIMENSIONS 5.10 5.00 4.90 16 9 4.50 6.40 4.40 BSC 4.30 1 8 PIN 1 1.20 MAX 0.15 0.20 0.05 0.09 0.75 0.30 8° 0.60 B0.S6C5 0.19 SEATING 0° 0.45 PLANE COPLANARITY 0.10 COMPLIANT TO JEDEC STANDARDS MO-153-AB Figure 40. 16-Lead Thin Shrink Small Outline Package [TSSOP] (RU-16) Dimensions shown in millimeters ORDERING GUIDE Model Temperature Range Package Description Package Option AD7747ARUZ1 −40°C to +125°C 16-Lead TSSOP RU-16 AD7747ARUZ-REEL1 −40°C to +125°C 16-Lead TSSOP RU-16 AD7747ARUZ-REEL71 −40°C to +125°C 16-Lead TSSOP RU-16 EVAL-AD7747EBZ1 Evaluation Board 1 Z = Pb-free part. Rev. 0 | Page 27 of 28

AD7747 NOTES Purchase of licensed I2C components of Analog Devices or one of its sublicensed Associated Companies conveys a license for the purchaser under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips. ©2007 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D05469-0-1/07(0) Rev. 0 | Page 28 of 28

Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: A nalog Devices Inc.: AD7747ARUZ-REEL7 AD7747ARUZ-REEL EVAL-AD7747EBZ AD7747ARUZ