a Bridge Transducer ADC AD7730/AD7730L The modulator output is processed by a low pass programmable KEY FEATURES digital filter, allowing adjustment of filter cutoff, output rate and Resolution of 230,000 Counts (Peak-to-Peak) Offset Drift: 5 nV/(cid:2)C settling time. Gain Drift: 2ppm/(cid:2)C The part features two buffered differential programmable gain Line Frequency Rejection: >150dB analog inputs as well as a differential reference input. The part Buffered Differential Inputs operates from a single +5V supply. It accepts four unipolar Programmable Filter Cutoffs analog input ranges: 0 mV to +10mV, +20mV, +40mV and Specified for Drift Over Time +80mV and four bipolar ranges: ±10mV, ±20mV, ±40mV Operates with Reference Voltages of 1V to 5V and±80mV. The peak-to-peak resolution achievable directly from the part is 1 in 230,000 counts. An on-chip 6-bit DAC ADDITIONAL FEATURES allows the removal of TARE voltages. Clock signals for synchro- Two-Channel Programmable Gain Front End nizing ac excitation of the bridge are also provided. On-Chip DAC for Offset/TARE Removal FASTStep™ Mode The serial interface on the part can be configured for three-wire AC or DC Excitation operation and is compatible with microcontrollers and digital Single Supply Operation signal processors. The AD7730 contains self-calibration and system calibration options, and features an offset drift of less APPLICATIONS than 5 nV/°C and a gain drift of less than 2 ppm/°C. Weigh Scales The AD7730 is available in a 24-pin plastic DIP, a 24-lead Pressure Measurement SOIC and 24-lead TSSOP package. The AD7730L is available in a 24-lead SOIC and 24-lead TSSOP package. GENERAL DESCRIPTION The AD7730 is a complete analog front end for weigh-scale and NOTE pressure measurement applications. The device accepts low- The description of the functions and operation given in this data level signals directly from a transducer and outputs a serial sheet apply to both the AD7730 and AD7730L. Specifications digital word. The input signal is applied to a proprietary pro- and performance parameters differ for the parts. Specifications grammable gain front end based around an analog modulator. for the AD7730L are outlined in Appendix A. FUNCTIONAL BLOCK DIAGRAM AVDD DVDD REF IN(–) REF IN(+) AD7730 VBIAS REFERENCE DETECT AVDD STANDBY AIN1(+) SIGMA-DELTA A/D CONVERTER AIN1(–) 100nA BUFFER SIGMA- PROGRAMMABLE SYNC DELTA DIGITAL + MUX PGA MODULATOR FILTER +/– AIN2(+)/D1 100nA 6-BIT CLOCK MCLK IN AIN2(–)/D0 AGND DAC SERIAL INTERFACE GENERATION MCLK OUT AND CONTROL LOGIC REGISTER BANK SCLK CS CALIBRATION MICROCONTROLLER DIN ACX AC DOUT EXCITATION ACX CLOCK AGND DGND POL RDY RESET FASTStep is a trademark of Analog Devices, Inc. REV.B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. which may result from its use. No license is granted by implication or Tel: 781/329-4700 World Wide Web Site: http://www.analog.com otherwise under any patent or patent rights of Analog Devices. Fax:781/461-3113 © Analog Devices, Inc., 2012

AD7730–SPECIFICATIONS (AV = +5V, DV = +3V or +5V; REF IN(+) = AV ; REFIN(–) = AGND = DGND = DD DD DD 0V; f = 4.9152 MHz. All specifications T to T unless otherwise noted.) CLK IN MIN MAX Parameter B Version1 Units Conditions/Comments STATIC PERFORMANCE (CHP = 1) No Missing Codes2 24 Bits min Output Noise and Update Rates2 See Tables I & II Integral Nonlinearity 18 ppm of FSR max Offset Error2 See Note 3 Offset Error and Offset Drift Refer to Both Offset Drift vs. Temperature2 5 nV/°C typ Unipolar Offset and Bipolar Zero Errors Offset Drift vs. Time4 25 nV/1000Hours typ Positive Full-Scale Error2, 5 See Note 3 Positive Full-Scale Drift vs Temp2, 6, 7 2 ppm of FS/°C max Positive Full-Scale Drift vs Time4 10 ppm of FS/1000 Hours typ Gain Error2, 8 See Note 3 Gain Drift vs. Temperature2, 6, 9 2 ppm/°C max Gain Drift vs. Time4 10 ppm/1000 Hours typ Bipolar Negative Full-Scale Error2 See Note 3 Negative Full-Scale Drift vs. Temp2, 6 2 ppm of FS/°C max Power Supply Rejection 120 dB typ Measured with Zero Differential Voltage Common-Mode Rejection (CMR) 120 dB min At DC. Measured with Zero Differential Voltage Analog Input DC Bias Current2 50 nA max Analog Input DC Bias Current Drift2 100 pA/°C typ Analog Input DC Offset Current2 10 nA max Analog Input DC Offset Current Drift2 50 pA/°C typ STATIC PERFORMANCE (CHP = 0)2 No Missing Codes 24 Bits min SKIP = 010 Output Noise and Update Rates See Tables III & IV Integral Nonlinearity 18 ppm of FSR max Offset Error See Note 3 Offset Error and Offset Drift Refer to Both Offset Drift vs. Temperature6 0.5 μV/°C typ Unipolar Offset and Bipolar Zero Errors Offset Drift vs. Time4 2.5 μV/1000Hours typ Positive Full-Scale Error5 See Note 3 Positive Full-Scale Drift vs. Temp6, 7 0.6 μV/°C typ Positive Full-Scale Drift vs. Time4 3 μV/1000 Hours typ Gain Error8 See Note 3 Gain Drift vs. Temperature6, 9 2 ppm/°C typ Gain Drift vs. Time4 10 ppm/1000 Hours typ Bipolar Negative Full-Scale Error See Note 3 Negative Full-Scale Drift vs. Temp 0.6 μV/°C typ Power Supply Rejection 90 dB typ Measured with Zero Differential Voltage Common-Mode Rejection (CMR) on AIN 100 dB typ At DC. Measured with Zero Differential Voltage CMR on REF IN 120 dB typ At DC. Measured with Zero Differential Voltage Analog Input DC Bias Current 60 nA max Analog Input DC Bias Current Drift 150 pA/°C typ Analog Input DC Offset Current 30 nA max Analog Input DC Offset Current Drift 100 pA/°C typ ANALOG INPUTS/REFERENCE INPUTS Normal-Mode 50 Hz Rejection2 88 dB min From 49 Hz to 51 Hz Normal-Mode 60 Hz Rejection2 88 dB min From 59 Hz to 61 Hz Common-Mode 50 Hz Rejection2 120 dB min From 49 Hz to 51 Hz Common-Mode 60 Hz Rejection2 120 dB min From 59 Hz to 61 Hz Analog Inputs Differential Input Voltage Ranges11 Assuming 2.5 V or 5 V Reference with HIREF Bit Set Appropriately 0 to +10 or ±10 mV nom Gain = 250 0 to +20 or ±20 mV nom Gain = 125 0 to +40 or ±40 mV nom Gain = 62.5 0 to +80 or ±80 mV nom Gain = 31.25 Absolute/Common-Mode Voltage12 AGND + 1.2 V V min AV – 0.95V V max DD Reference Input REF IN(+) – REF IN(–) Voltage +2.5 V nom HIREF Bit of Mode Register = 0 REF IN(+) – REF IN(–) Voltage +5 V nom HIREF Bit of Mode Register = 1 Absolute/Common-Mode Voltage13 AGND – 30mV V min AV + 30mV V max DD NO REF Trigger Voltage 0.3 V min NO REF Bit Active If V Below This Voltage REF 0.65 V max NO REF Bit Inactive If V Above This Voltage REF REV. B –2–

AD7730/AD7730L Parameter B Version1 Units Conditions/Comments LOGIC INPUTS Input Current ±10 μA max All Inputs Except SCLK and MCLK IN V , Input Low Voltage 0.8 V max DV = +5V INL DD V , Input Low Voltage 0.4 V max DV = +3V INL DD V , Input High Voltage 2.0 V min INH SCLK Only (Schmitt Triggered Input) V 1.4/3 V min to V max DV = +5V T+ DD V 1/2.5 V min to V max DV = +3V T+ DD V 0.8/1.4 V min to V max DV = +5V T– DD V 0.4/1.1 V min to V max DV = +3V T– DD V – V 0.4/0.8 V min to V max DV = +5V T+ T– DD V – V 0.4/0.8 V min to V max DV = +3V T+ T– DD MCLK IN Only V , Input Low Voltage 0.8 V max DV = +5V INL DD V , Input Low Voltage 0.4 V max DV = +3V INL DD V , Input High Voltage 3.5 V min DV = +5V INH DD V , Input High Voltage 2.5 V min DV = +3V INH DD LOGIC OUTPUTS (Including MCLK OUT) V , Output Low Voltage I = 800μA Except for MCLK OUT14; OL SINK 0.4 V max V 15 = +5V DD V , Output Low Voltage I = 100μA Except for MCLK OUT14; OL SINK 0.4 V max V 15 = +3V DD V , Output High Voltage I = 200 μA Except for MCLK OUT14; OH SOURCE 4.0 V min V 15 = +5V DD V , Output High Voltage I = 100 μA Except for MCLK OUT14; OH SOURCE V – 0.6 V V min V 15 = +3V DD DD Floating State Leakage Current ±10 μA max Floating State Output Capacitance2 6 pF typ TRANSDUCER BURNOUT AIN1(+) Current –100 nA nom AIN1(–) Current 100 nA nom Initial Tolerance @ 25°C ±10 % typ Drift2 0.1 %/°C typ OFFSET (TARE) DAC Resolution 6 Bit LSB Size 2.3/2.6 mV min/mV max 2.5 mV Nominal with 5 V Reference (REF IN/2000) DAC Drift16 2.5 ppm/°C max DAC Drift vs. Time4, 16 25 ppm/1000 Hours typ Differential Linearity –0.25/+0.75 LSB max Guaranteed Monotonic SYSTEM CALIBRATION Positive Full-Scale Calibration Limit17 1.05× FS V max FS Is the Nominal Full-Scale Voltage (10 mV, 20 mV, 40 mV or 80 mV) Negative Full-Scale Calibration Limit17 –1.05× FS V max Offset Calibration Limit18 –1.05× FS V max Input Span17 0.8× FS V min 2.1× FS V max POWER REQUIREMENTS Power Supply Voltages AV – AGND Voltage +4.75 to +5.25 V min to V max DD DV Voltage +2.7 to +5.25 V min to V max With AGND = 0 V DD Power Supply Currents External MCLK. Digital I/Ps = 0 V or DV DD AV Current (Normal Mode) 10.3 mA max All Input Ranges Except 0 mV to +10 mV and ±10 mV DD AV Current (Normal Mode) 22.3 mA max Input Ranges of 0 mV to +10 mV and ±10 mV Only DD DV Current (Normal Mode) 1.3 mA max DV of 2.7 V to 3.3 V DD DD DV Current (Normal Mode) 2.7 mA max DV of 4.75 V to 5.25 V DD DD AV + DV Current (Standby Mode) 25 μA max Typically 10μA. External MCLK IN = 0 V or DV DD DD DD Power Dissipation AV = DV = +5V. Digital I/Ps = 0 V or DV DD DD DD Normal Mode 65 mW max All Input Ranges Except 0 mV to +10 mV and ±10 mV 125 mW max Input Ranges of 0 mV to +10 mV and ±10 mV Only Standby Mode 125 μW max Typically 50μW. External MCLK IN = 0 V or DV DD REV. B –3–

AD7730/AD7730L NOTES 11Temperature range: –40°C to +85°C. 12Sample tested during initial release. 13The offset (or zero) numbers with CHP = 1 are typically 3μV precalibration. Internal zero-scale calibration reduces this by about 1μV. Offset numbers with CHP = 0 can be up to 1mV precalibration. Internal zero-scale calibration reduces this to 2μV typical. System zero-scale calibration reduces offset numbers with CHP = 1 and CHP = 0 to the order of the noise. Gain errors can be up to 3000 ppm precalibration with CHP = 0 and CHP = 1. Performing internal full-scale calibrations on the 80 mV range reduces the gain error to less than 100ppm for the 80 mV and 40 mV ranges, to about 250 ppm for the 20 mV range and to about 500 ppm on the 10 mV range. System full-scale calibration reduces this to the order of the noise. Positive and negative full-scale errors can be calculated from the offset and gain errors. 14These numbers are generated during life testing of the part. 15Positive Full-Scale Error includes Offset Errors (Unipolar Offset Error or Bipolar Zero Error) and applies to both unipolar and bipolar input ranges. See Terminology. 16Recalibration at any temperature will remove these errors. 17Full-Scale Drift includes Offset Drift (Unipolar Offset Drift or Bipolar Zero Drift) and applies to both unipolar and bipolar input ranges. 18Gain Error is a measure of the difference between the measured and the ideal span between any two points in the transfer function. The two points used to calculate the gain error are positive full scale and negative full scale. See Terminology. 19Gain Error Drift is a span drift and is effectively the drift of the part if zero-scale calibrations only were performed. 10No Missing Codes performance with CHP = 0 and SKIP = 1 is reduced below 24 bits for SF words lower than 180 decimal. 11The analog input voltage range on the AIN1(+) and AIN2(+) inputs is given here with respect to the voltage on the AIN1(–) and AIN2(–) inputs respectively. 12The common-mode voltage range on the input pairs applies provided the absolute input voltage specification is obeyed. 13The common-mode voltage range on the reference input pair (REF IN(+) and REF IN(–)) applies provided the absolute input voltage specification is obeyed. 14These logic output levels apply to the MCLK OUT output only when it is loaded with a single CMOS load. 15VDD refers to DVDD for all logic outputs expect D0, D1, ACX and ACX where it refers to AVDD. In other words, the output logic high for these four outputs is determined by AVDD. 16This number represents the total drift of the channel with a zero input and the DAC output near full scale. 17After calibration, if the input voltage exceeds positive full scale, the converter will output all 1s. If the input is less than negative full scale, the device outputs all 0s. 18These calibration and span limits apply provided the absolute input voltage specification is obeyed. The offset calibration limit applies to both the unipolar zero point and the bipolar zero point. Specifications subject to change without notice. (AV = +4.75V to +5.25V; DV = +2.7V to +5.25 V; AGND = DGND = 0 V; f = 4.9152MHz; TIMING CHARACTERISTICS1, 2 DD DD CLK IN Input Logic 0 = 0 V, Logic 1 = DV unless otherwise noted). DD Limit at T to T MIN MAX Parameter (B Version) Units Conditions/Comments Master Clock Range 1 MHz min For Specified Performance 5 MHz max t 50 ns min SYNC Pulsewidth 1 t 50 ns min RESET Pulsewidth 2 Read Operation t 0 ns min RDY to CS Setup Time 3 t 0 ns min CS Falling Edge to SCLK Active Edge Setup Time3 4 t 4 0 ns min SCLK Active Edge to Data Valid Delay3 5 60 ns max DV = +4.75 V to +5.25 V DD 80 ns max DV = +2.75 V to +3.3 V DD t 4, 5 0 ns min CS Falling Edge to Data Valid Delay 5A 60 ns max DV = +4.75 V to +5.25 V DD 80 ns max DV = +2.7 V to +3.3 V DD t 100 ns min SCLK High Pulsewidth 6 t 100 ns min SCLK Low Pulsewidth 7 t 0 ns min CS Rising Edge to SCLK Inactive Edge Hold Time3 8 t 6 10 ns min Bus Relinquish Time after SCLK Inactive Edge3 9 80 ns max t 100 ns max SCLK Active Edge to RDY High3, 7 10 Write Operation t 0 ns min CS Falling Edge to SCLK Active Edge Setup Time3 11 t 30 ns min Data Valid to SCLK Edge Setup Time 12 t 25 ns min Data Valid to SCLK Edge Hold Time 13 t 100 ns min SCLK High Pulsewidth 14 t 100 ns min SCLK Low Pulsewidth 15 t 0 ns min CS Rising Edge to SCLK Edge Hold Time 16 NOTES 1Sample tested during initial release to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of DV ) and timed from a voltage level of 1.6 V. DD 2See Figures 18 and 19. 3SCLK active edge is falling edge of SCLK with POL = 1; SCLK active edge is rising edge of SCLK with POL = 0. 4These numbers are measured with the load circuit of Figure 1 and defined as the time required for the output to cross the V or V limits. OL OH 5This specification only comes into play if CS goes low while SCLK is low (POL = 1) or if CS goes low while SCLK is high (POL = 0). It is primarily required for interfacing to DSP machines. 6These numbers are derived from the measured time taken by the data output to change 0.5V when loaded with the circuit of Figure 1. The measured number is then extrapolated back to remove effects of charging or discharging the 50 pF capacitor. This means that the times quoted in the timing characteristics are the true bus relinquish times of the part and as such are independent of external bus loading capacitances. 7RDY returns high after the first read from the device after an output update. The same data can be read again, if required, while RDY is high, although care should be taken that subsequent reads do not occur close to the next output update. REV. B –4–

AD7730/AD7730L ABSOLUTE MAXIMUM RATINGS* Plastic DIP Package, Power Dissipation . . . . . . . 450 mW (TA = +25°C unless otherwise noted) θLJeAa Td hTeermmaple Irmatupreed a(Snoceld e.r .i n. g. ,. 1. 0. .s e. c.) . .. .. .. .. .. .. . 1 0+52°6C0/°WC AV to AGND . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V DD TSSOP Package, Power Dissipation . . . . . . . . . . 450 mW AVDD to DGND . . . . . . . . . . . . . . . . . . . . . . . –0.3V to +7V θ Thermal Impedance . . . . . . . . . . . . . . . . . 128°C/W DV to AGND . . . . . . . . . . . . . . . . . . . . . . . –0.3V to +7V JA DD Lead Temperature, Soldering DVDD to DGND . . . . . . . . . . . . . . . . . . . . . . . –0.3V to +7V Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . +215°C AGND to DGND . . . . . . . . . . . . . . . . . . . . . . –5V to +0.3V Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . +220°C AV to DV . . . . . . . . . . . . . . . . . . . . . . . . . –2V to +5V DD DD SOIC Package, Power Dissipation . . . . . . . . . . . . 450 mW Analog Input Voltage to AGND . . . . –0.3 V to AVDD+ 0.3V θ Thermal Impedance . . . . . . . . . . . . . . . . . . 75°C/W Reference Input Voltage to AGND . . –0.3 V to AV + 0.3V JA DD Lead Temperature, Soldering AIN/REF IN Current (Indefinite) . . . . . . . . . . . . . . . . 30 mA Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . +215°C Digital Input Voltage to DGND . . . . –0.3 V to DVDD+ 0.3 V Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . +220°C Digital Output Voltage to DGND . . . –0.3 V to DV + 0.3 V DD Output Voltage (ACX, ACX, D0, D1) to DGND *Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to AV + 0.3 V DD operation of the device at these or any other conditions above those listed in Operating Temperature Range the operational sections of this specification is not implied. Exposure to Industrial (B Version) . . . . . . . . . . . . . . . –40°C to +85°C absolute maximum rating conditions for extended periods may affect device Storage Temperature Range . . . . . . . . . . . –65°C to +150°C reliability. Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . +150°C ISINK(800(cid:3)A AT DVDD= +5V 100(cid:3)A AT DVDD= +3V) TO OUTPUT +1.6V PIN 50pF ISOURCE(200(cid:3)A AT DVDD = +5V 100(cid:3)A AT DVDD= +3V) Figure 1.Load Circuit for Access Time and Bus Relinquish Time CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily WARNING! accumulate on the human body and test equipment and can discharge without detection. Although the AD7730 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD ESD SENSITIVE DEVICE precautions are recommended to avoid performance degradation or loss of functionality. REV. B –5–

AD7730/AD7730L DIFFERENTIAL PROGRAMMABLE BUFFER AMPLIFIER PROGRAMMABLE GAIN REFERENCE SSIIGGMMAA- DDEELLTTAA AADDCC DIGITAL FILTER AMPLIFIER IINPNRPPUEUTSTTHSE ESE NXAT BTTALIMESULGR FPOAEFNEW EHFADIROILANG R NGASH CMO T SIEMHUPIGSELPRN IECAFIDEIFNEAIACRNLACONEGT UNTAIHPMEIONP PLPL+ARIU1FRO0TI EmG ARRRVNA AADTNML OGFLM OE+OASU8W0B RFmSL RB EVFOI POGMOUALRINAR VTOOHBPFPLEEAATE RRNCARETOIGAL FMEIITSTEI IAO CNRDTANAEIFEN.NL FSTL CBE HYREERE A+ IE SN2RTNE.PIE5OTLUVFIMEATE OCE LRTRT TEOAE RN+N DTI5CCDH VTEEO AABBEERREENNCC TTCCHHNNIIRHHRIIOOTTEOOEE E TTMM PPSCCHHSIIPPITSTSEIEGGEEUUSS SMSMDDEERRIINNIIARR GAGEETTGG RR-M MOODDEE OOCC AEANNERRRROOL- LSSEEDDSSTDDTUUMMEEAAEERRLLOO.SS EETTAAVV..SSAA DDEETT C22HH C DD44 EE CRCR BBAIAIFFIINTTNTTSS SEAOTTLUTWLLTOAIPONWU FG(STSSAT TE USAPIEMTPGR DFEOSEIA T GGAFTEURINLEPRADT RMEM EWA ORM3HT )DITENIECH GAHA NO THDFAS SEE PAGE 24 SEE PAGE 24 SEE PAGE 25 SESEE EP APGAGE E26 SEE PAGE 26 BURNOUT CURRENTS TWO 100nA BURNOUT CURRENTS ALLOW THE USER TRTOAN ESADSUILCYE RD EHTAESC BT UIFR ANT AVDD DVDD REF IN(–) REF IN(+) STANDBY MODE OUT OR GONE OPEN-CIRCUIT THE STANDBY MODE REDUCES SEE PAGE 25 VBIAS REFERENCE DETECT AD7730 POWER CONSUMPTION TO 5(cid:3)A AIN1(+) AVDD SIGMA-DELTA A/D CONVERTER STANDBY SEE PAGE 33 AIN1(–) SIGMA- PROGRAMMABLE SYNC CLOCK OSCILLATOR + DELTA DIGITAL CIRCUIT MUX PGA MODULATOR FILTER +/– THE CLOCK SOURCE FOR THE AIN2(+)/D1 BUFFER PART CAN BE PROVIDED BY AN 6-BIT CLOCK MCLK IN EBXYT ECRONNANLELCYT-AINPGP LAI ECDR YCSLTOACLK O ORR AIN2(–)/D0 AGND DAC SERIAL INTERFACE GENERATION MCLK OUT CERAMIC RESONATOR ACROSS AND CONTROL LOGIC THE CLOCK PINS REGISTER BANK SCLK SEE PAGE 32 CS CALIBRATION ANALOG MULTIPLEXER MICROCONTROLLER DIN ACX AC MATU HTLWET IOTPW-LCEOHX ADENIRFN FSEEWLR IDETCNIFHTFIEEASRL E OINNNPTEUIA OTLF ACX EXCCLITOACTKION DOUT CHANNELS TO THE BUFFER SERIAL INTERFACE AMPLIFIER. THE MULTIPLEXER IS CONTROLLED VIA THE SERIAL AGND DGND POL RDY RESET SPI*-COMPATIBLE OR DSP- INTERFACE COMPATIBLE SERIAL INTERFACE WHICH CAN BE OPERATED FROM SEE PAGE 24 JUST THREE WIRES. ALL FUNCTIONS ON THE PART CAN BE ACCESSED VIA THE SERIAL INTERFACE SEE PAGE 35 AC EXCITATION OUTPUT DRIVERS OFFSET/TARE DAC REGISTER BANK FOR AC-EXCITED BRIDGE THE SECOND ANALOG INPUT ALLOWS A PROGRAMMED THIRTEEN REGISTERS CONTROL APPLICATIONS, THE ACX CHANNEL CAN BE VOLTAGE TO BE EITHER ADDED ALL FUNCTIONS ON THE PART AND OUTPUTS PROVIDE SIGNALS RECONFIGURED TO BECOME TWO OR SUBTRACTED FROM THE PROVIDE STATUS INFORMATION THAT CAN BE USED TO SWITCH OUTPUT DIGITAL PORT LINES ANALOG INPUT SIGNAL BEFORE AND CONVERSION RESULTS THE POLARITY OF THE BRIDGE WHICH CAN BE PROGRAMMED IT IS APPLIED TO THE PGA EXCITATION VOLTAGE OVER THE SERIAL INTERFACE SEE PAGE 11 SEE PAGE 24 SEE PAGE 41 SEE PAGE 33 *SPI IS A TRADEMARK OF MOTOROLA, INC. Figure 2.Detailed Functional Block Diagram REV. B –6–

AD7730/AD7730L INPUT CHOPPING SINC3 FILTER SKIP MODE 22-TAP FIR FILTER THE ANALOG INPUT TO THE PART CAN BE THE FIRST STAGE OF THE DIGITAL FILTERING IN SKIP MODE, THERE IS NO SECOND IN NORMAL OPERATING MODE, THE CHOPPED. IN CHOPPING MODE, WITH ON THE PART IS THE SINC3 FILTER. THE STAGE OF FILTERING ON THE PART. THE SECOND STAGE OF THE DIGITAL FILTERING AC EXCITATION DISABLED, THE INPUT OUTPUT UPDATE RATE AND BANDWIDTH SINC3 FILTER IS THE ONLY FILTERING ON THE PART IS A FIXED 22-TAP FIR CHOPPING IS INTERNALTO THE DEVICE. IN OF THIS FILTER CAN BE PROGRAMMED. IN PERFORMED ON THE PART. FILTER. IN SKIP MODE, THIS FIR FILTER IS CHOPPING MODE, WITH AC EXCITATION SKIP MODE, THE SINC3 FILTER IS THE BYPASSED. WHEN FASTSTEP™MODE IS TO EBNEA PBELREFDO, RTHMEE DC HEOXPTEPRINNGA ILS TAOS STHUEM EPDART ONLY FILTERING PERFORMED ON THE PART. SEE PAGE 29 DETECETNEADB, LTEHDE ASNECDO AN SDT SETPA INGPEU FTIL ITSERING PAENRDF ONROM INEDTE. TRHNEA LIN IPNUPTU TC HCOHOPPPIPNIGNG C AISN SEE PAGE 26 UNIST IPLE TRHFEO ORUMTEPDU BTY O TFH TEH IFSI LFTILETRER BE DISABLED, IF DESIRED. HAS FULLY SETTLED. SEE PAGE 26 SEE PAGE 27 SKIP PGA + ANALOG CHOP BUFFER SIGMA-DELTA SINC3 FILTER CHOP 22-TAP OUTPUT DIGITAL INPUT MODULATOR FIR FILTER SCALING OUTPUT FASTSTEP OUTPUT SCALING FILTER BUFFER PGA + SIGMA-DELTA MODULATOR OUTPUT CHOPPING THE OUTPUT WORD FROM THE DIGITAL FILTER IS SCALED BY THE CALIBRATION ONT-HCEH IIPN PBUETF OSRIGEN BAELI NISG B AUPFPFLEIREEDD TO THEO PFR TOHGER PAAMRMTA IBSL INE CGOARINP OCRAAPTAEBDILITY TOHFE FOILUTTEPRUITN GO FO TNH TEH FEI RPSATR TS TCAAGNE COEFAFISC ITEHNET SC OBNEVFEORRSEI OBNE IRNEGS PURLOTV.IDED THE SAMPLING CAPACITOR OF THE AROUND THE SIGMA-DELTA MODULATOR. BE CHOPPED. IN CHOPPING MODE, SIGMA-DELTA MODULATOR. THIS THE MODULATOR PROVIDES A HIGH- REGARDLESS OF WHETHER AC SEE PAGE 29 ISOLATES THE SAMPLING CAPACITOR FREQUENCY 1-BIT DATA STREAM EXCITATION IS ENABLED OR DISABLED, CHARGING CURRENTS FROM THE TO THE DIGITAL FILTER. THE OUTPUT CHOPPING IS ANALOG INPUT PINS. PERFORMED. THE CHOPPING CAN FASTSTEP FILTER SEE PAGE 26 BE DISABLED, IF DESIRED. SEE PAGE 24 WHEN FASTSTEP MODE IS ENABLED SEE PAGE 26 AND A STEP CHANGE ON THE INPUT HAS BEEN DETECTED, THE SECOND STAGE FILTERING IS PERFORMED BY THE FASTSTEP FILTER UNTIL THE FIR FILTER HAS FULLY SETTLED. SEE PAGE 29 Figure 3.Signal Processing Chain PIN CONFIGURATION SCLK 1 24 DGND MCLK IN 2 23 DVDD MCLK OUT 3 22 DIN POL 4 21 DOUT SYNC 5 20 RDY AD7730 RESET 6 19 CS TOP VIEW VBIAS 7 (Not to Scale) 18 STANDBY AGND 8 17 ACX AVDD 9 16 ACX AIN1(+) 10 15 REF IN(–) AIN1(–) 11 14 REF IN(+) AIN2(+)/D1 12 13 AIN2(–)/D0 PIN FUNCTION DESCRIPTIONS Pin No. Mnemonic Function 1 SCLK Serial Clock. Schmitt-Triggered Logic Input. An external serial clock is applied to this input to transfer serial data to or from the AD7730. This serial clock can be a continuous clock with all data transmitted in a con- tinuous train of pulses. Alternatively, it can be a noncontinuous clock with the information being transmitted to or from the AD7730 in smaller batches of data. 2 MCLK IN Master Clock signal for the device. This can be provided in the form of a crystal/resonator or external clock. A crystal/resonator can be tied across the MCLK IN and MCLK OUT pins. Alternatively, the MCLK IN pin can be driven with a CMOS-compatible clock and MCLK OUT left unconnected. The AD7730 is specified with a clock input frequency of 4.9152 MHz while the AD7730L is specified with a clock input frequency of 2.4576 MHz. REV. B –7–

AD7730/AD7730L Pin No. Mnemonic Function 3 MCLK OUT When the master clock for the device is a crystal/resonator, the crystal/resonator is connected between MCLKIN and MCLKOUT. If an external clock is applied to the MCLK IN, MCLK OUT provides an inverted clock sig- nal. This clock can be used to provide a clock source for external circuits and MCLKOUT is capable of driving one CMOS load. If the user does not require it, MCLK OUT can be turned off with the CLKDIS bit of the Mode Register. This ensures that the part is not burning unnecessary power driving capacitance on the MCLK OUT pin. 4 POL Clock Polarity. Logic Input. This determines the polarity of the serial clock. If the active edge for the proces- sor is a high-to-low SCLK transition, this input should be low. In this mode, the AD7730 puts out data on the DATA OUT line in a read operation on a low-to-high transition of SCLK and clocks in data from the DATA IN line in a write operation on a high-to-low transition of SCLK. In applications with a noncontinuous serial clock (such as most microcontroller applications), this means that the serial clock should idle low between data transfers. If the active edge for the processor is a low-to-high SCLK transition, this input should be high. In this mode, the AD7730 puts out data on the DATA OUT line in a read operation on a high-to-low transi- tion of SCLK and clocks in data from the DATA IN line in a write operation on a low-to-high transition of SCLK. In applications with a noncontinuous serial clock (such as most microcontroller applications), this means that the serial clock should idle high between data transfers. 5 SYNC Logic Input that allows for synchronization of the digital filters and analog modulators when using a number of AD7730s. While SYNC is low, the nodes of the digital filter, the filter control logic and the calibration control logic are reset and the analog modulator is also held in its reset state. SYNC does not affect the digital interface but does reset RDY to a high state if it is low. While SYNC is asserted, the Mode Bits may be set up for a subsequent operation which will commence when the SYNC pin is deasserted. 6 RESET Logic Input. Active low input that resets the control logic, interface logic, digital filter, analog modulator and all on-chip registers of the part to power-on status. Effectively, everything on the part except for the clock oscillator is reset when the RESET pin is exercised. 7 V Analog Output. This analog output is an internally-generated voltage used as an internal operating bias point. BIAS This output is not for use external to the AD7730 and it is recommended that the user does not connect any- thing to this pin. 8 AGND Ground reference point for analog circuitry. 9 AV Analog Positive Supply Voltage. The AV to AGND differential is 5V nominal. DD DD 10 AIN1(+) Analog Input Channel 1. Positive input of the differential, programmable-gain primary analog input pair. The differential analog input ranges are 0 mV to +10 mV, 0 mV to +20 mV, 0 mV to +40 mV and 0 mV to +80 mV in unipolar mode, and ±10 mV, ±20 mV, ±40 mV and ±80 mV in bipolar mode. 11 AIN1(–) Analog Input Channel 1. Negative input of the differential, programmable gain primary analog input pair. 12 AIN2(+)/D1 Analog Input Channel 2 or Digital Output 1. This pin can be used either as part of a second analog input channel or as a digital output bit as determined by the DEN bit of the Mode Register. When selected as an analog input, it is the positive input of the differential, programmable-gain secondary analog input pair. The analog input ranges are 0 mV to +10 mV, 0 mV to +20 mV, 0 mV to +40 mV and 0 mV to +80 mV in unipo- lar mode and ±10 mV, ±20 mV, ±40 mV and ±80 mV in bipolar mode. When selected as a digital output, this output can programmed over the serial interface using bit D1 of the Mode Register. 13 AIN2(–)/D0 Analog Input Channel 2 or Digital Output 0. This pin can be used either as part of a second analog input channel or as a digital output bit as determined by the DEN bit of the Mode Register. When selected as an analog input, it is the negative input of the differential, programmable-gain secondary analog input pair. When selected as a digital output, this output can programmed over the serial interface using bit D0 of the Mode Register. 14 REF IN(+) Reference Input. Positive terminal of the differential reference input to the AD7730. REF IN(+) can lie anywhere between AV and AGND. The nominal reference voltage (the differential voltage between REF DD IN(+) and REFIN(–)) should be +5 V when the HIREF bit of the Mode Register is 1 and +2.5 V when the HIREF bit of the Mode Register is 0. 15 REF IN(–) Reference Input. Negative terminal of the differential reference input to the AD7730. The REF IN(–) poten- tial can lie anywhere between AV and AGND. DD 16 ACX Digital Output. Provides a signal that can be used to control the reversing of the bridge excitation in ac- excited bridge applications. When ACX is high, the bridge excitation is taken as normal and when ACX is low, the bridge excitation is reversed (chopped). If AC = 0 (ac mode turned off) or CHP = 0 (chop mode turned off), the ACX output remains high. 17 ACX Digital Output. Provides a signal that can be used to control the reversing of the bridge excitation in ac- excited bridge applications. This output is the complement of ACX. In ac mode, this means that it toggles in anti-phase with ACX . If AC = 0 (ac mode turned off) or CHP = 0 (chop mode turned off), the ACX output remains low. When toggling, it is guaranteed to be nonoverlapping with ACX. The non-overlap interval, when both ACX and ACX are low, is one master clock cycle. REV. B –8–

AD7730/AD7730L Pin No. Mnemonic Function 18 STANDBY Logic Input. Taking this pin low shuts down the analog and digital circuitry, reducing current consumption to the 5μA range. The on-chip registers retain all their values when the part is in standby mode. 19 CS Chip Select. Active low Logic Input used to select the AD7730. With this input hardwired low, the AD7730 can operate in its three-wire interface mode with SCLK, DIN and DOUT used to interface to the device. CS can be used to select the device in systems with more than one device on the serial bus or as a frame synchro- nization signal in communicating with the AD7730. 20 RDY Logic Output. Used as a status output in both conversion mode and calibration mode. In conversion mode, a logic low on this output indicates that a new output word is available from the AD7730 data register. The RDY pin will return high upon completion of a read operation of a full output word. If no data read has taken place after an output update, the RDY line will return high prior to the next output update, remain high while the update is taking place and return low again. This gives an indication of when a read operation should not be initiated to avoid initiating a read from the data register as it is being updated. In calibration mode, RDY goes high when calibration is initiated and it returns low to indicate that calibration is complete. A number of different events on the AD7730 set the RDY high and these are outlined in Table XVIII. 21 DOUT Serial Data Output with serial data being read from the output shift register on the part. This output shift register can contain information from the calibration registers, mode register, status register, filter register, DAC register or data register, depending on the register selection bits of the Communications Register. 22 DIN Serial Data Input with serial data being written to the input shift register on the part. Data from this input shift register is transferred to the calibration registers, mode register, communications register, DAC register or filter registers depending on the register selection bits of the Communications Register. 23 DV Digital Supply Voltage, +3V or +5 V nominal. DD 24 DGND Ground reference point for digital circuitry. TERMINOLOGY BIPOLAR NEGATIVE FULL-SCALE ERROR INTEGRAL NONLINEARITY This is the deviation of the first code transition from the ideal This is the maximum deviation of any code from a straight line AIN(+) voltage (AIN(–) – V /GAIN + 0.5 LSB) when operat- REF passing through the endpoints of the transfer function. The end- ing in the bipolar mode. Negative full-scale error is a summation points of the transfer function are zero scale (not to be confused of zero error and gain error. with bipolar zero), a point 0.5 LSB below the first code transi- tion (000 . . . 000 to 000 . . . 001) and full scale, a point 0.5 LSB POSITIVE FULL-SCALE OVERRANGE above the last code transition (111 . . . 110 to 111 . . . 111). The Positive Full-Scale Overrange is the amount of overhead avail- error is expressed as a percentage of full scale. able to handle input voltages on AIN(+) input greater than AIN(–) + V /GAIN (for example, noise peaks or excess volt- REF POSITIVE FULL-SCALE ERROR ages due to system gain errors in system calibration routines) with- Positive Full-Scale Error is the deviation of the last code transition out introducing errors due to overloading the analog modulator (111 . . . 110 to 111 . . . 111) from the ideal AIN(+) voltage or overflowing the digital filter. (AIN(–) + V /GAIN – 3/2 LSBs). It applies to both unipolar REF and bipolar analog input ranges. Positive full-scale error is a NEGATIVE FULL-SCALE OVERRANGE summation of offset error and gain error. This is the amount of overhead available to handle voltages on AIN(+) below AIN(–) – V /GAIN without overloading the REF UNIPOLAR OFFSET ERROR analog modulator or overflowing the digital filter. Unipolar Offset Error is the deviation of the first code transition from the ideal AIN(+) voltage (AIN(–) + 0.5 LSB) when oper- OFFSET CALIBRATION RANGE ating in the unipolar mode. In the system calibration modes, the AD7730 calibrates its offset with respect to the analog input. The Offset Calibration BIPOLAR ZERO ERROR Range specification defines the range of voltages the AD7730 This is the deviation of the midscale transition (0111 . . . 111 to can accept and still accurately calibrate offset. 1000 . . . 000) from the ideal AIN(+) voltage (AIN(–) – 0.5 LSB) when operating in the bipolar mode. FULL-SCALE CALIBRATION RANGE This is the range of voltages that the AD7730 can accept in the GAIN ERROR system calibration mode and still calibrate full scale correctly. This is a measure of the span error of the ADC. It is a measure of the difference between the measured and the ideal span be- INPUT SPAN tween any two points in the transfer function. The two points In system calibration schemes, two voltages applied in sequence used to calculate the gain error are full scale and zero scale. to the AD7730’s analog input define the analog input range. The input span specification defines the minimum and maxi- mum input voltages, from zero to full scale, the AD7730 can accept and still accurately calibrate gain. REV. B –9–

AD7730/AD7730L OUTPUT NOISE AND RESOLUTION SPECIFICATION The AD7730 can be programmed to operate in either chop mode or nonchop mode. The chop mode can be enabled in ac-excited or dc-excited applications; it is optional in dc-excited applications, but chop mode must be enabled in ac-excited applications. These options are discussed in more detail in later sections. The chop mode has the advantage of lower drift numbers and better noise im- munity, but the noise is approximately 20% higher for a given –3 dB frequency and output data rate. It is envisaged that the majority of weigh-scale users of the AD7730 will operate the part in chop mode to avail themselves of the excellent drift performance and noise immunity when chopping is enabled. The following tables outline the noise performance of the part in both chop and nonchop modes over all input ranges for a selection of output rates. Settling time refers to the time taken to get an output that is 100% settled to new value. Output Noise (CHP = 1) This mode is the primary mode of operation of the device. Table I shows the output rms noise for some typical output update rates and –3 dB frequencies for the AD7730 when used in chopping mode (CHP of Filter Register = 1) with a master clock frequency of 4.9152 MHz. These numbers are typical and are generated at a differential analog input voltage of 0 V. The output update rate is selected via the SF0 to SF11 bits of the Filter Register. Table II, meanwhile, shows the output peak-to-peak resolution in counts for the same output update rates. The numbers in brackets are the effective peak-to-peak resolution in bits (rounded to the nearest 0.5 LSB). It is important to note that the numbers in Table II represent the resolution for which there will be no code flicker within a six-sigma limit. They are not calculated based on rms noise, but on peak-to-peak noise. The numbers are generated for the bipolar input ranges. When the part is operated in unipolar mode, the output noise will be the same as the equivalent bipolar input range. As a result, the numbers in Table I will remain the same for unipolar ranges while the numbers in Table II will change. To calculate the numbers for Table II for unipolar input ranges simply divide the peak-to-peak resolution number in counts by two or subtract one from the peak-to-peak resolution number in bits. Table I. Output Noise vs. Input Range and Update Rate (CHP = 1) Typical Output RMS Noise in nV Output –3 dB SF Settling Time Settling Time Input Range Input Range Input Range Input Range Data Rate Frequency Word Normal Mode Fast Mode = (cid:4)80 mV = (cid:4)40 mV = (cid:4)20 mV = (cid:4)10 mV 50Hz 1.97Hz 2048 460 ms 60 ms 115 75 55 40 100Hz 3.95Hz 1024 230ms 30ms 155 105 75 60 150Hz 5.92Hz 683 153 ms 20 ms 200 135 95 70 200Hz* 7.9Hz 512 115ms 15ms 225 145 100 80 400Hz 15.8Hz 256 57.5ms 7.5ms 335 225 160 110 *Power-On Default Table II. Peak-to-Peak Resolution vs. Input Range and Update Rate (CHP = 1) Peak-to-Peak Resolution in Counts (Bits) Output –3 dB SF Settling Time Settling Time Input Range Input Range Input Range Input Range Data Rate Frequency Word Normal Mode Fast Mode = (cid:4)80 mV = (cid:4)40 mV = (cid:4)20 mV = (cid:4)10 mV 50Hz 1.97Hz 2048 460 ms 60 ms 230k (18) 175k (17.5) 120k (17) 80k (16.5) 100Hz 3.95Hz 1024 230ms 30ms 170k (17.5) 125k (17) 90k (16.5) 55k (16) 150Hz 5.92Hz 683 153 ms 20 ms 130k (17) 100k (16.5) 70k (16) 45k (15.5) 200Hz* 7.9Hz 512 115ms 15ms 120k (17) 90k (16.5) 65k (16) 40k (15.5) 400Hz 15.8Hz 256 57.5ms 7.5ms 80k (16.5) 55k (16) 40k (15.5) 30k (15) *Power-On Default Output Noise (CHP = 0) Table III shows the output rms noise for some typical output update rates and –3 dB frequencies for the AD7730 when used in non- chopping mode (CHP of Filter Register = 0) with a master clock frequency of 4.9152 MHz. These numbers are typical and are gen- erated at a differential analog input voltage of 0 V. The output update rate is selected via the SF0 to SF11 bits of the Filter Register. Table IV, meanwhile, shows the output peak-to-peak resolution in counts for the same output update rates. The numbers in brackets are the effective peak-to-peak resolution in bits (rounded to the nearest 0.5 LSB). It is important to note that the numbers in Table IV represent the resolution for which there will be no code flicker within a six-sigma limit. They are not calculated based on rms noise, but on peak-to-peak noise. The numbers are generated for the bipolar input ranges. When the part is operated in unipolar mode, the output noise will be the same as the equivalent bipolar input range. As a result, the numbers in Table III will remain the same for unipolar ranges while the numbers in Table IV will change. To calculate the number for Table IV for unipolar input ranges simply divide the peak-to-peak resolution number in counts by two or subtract one from the peak-to-peak resolution number in bits. REV. B –10–

AD7730/AD7730L Table III. Output Noise vs. Input Range and Update Rate (CHP = 0) Typical Output RMS Noise in nV Output –3 dB SF Settling Time Settling Time Input Range Input Range Input Range Input Range Data Rate Frequency Word Normal Mode Fast Mode = (cid:4)80 mV = (cid:4)40 mV = (cid:4)20 mV = (cid:4)10 mV 150Hz 5.85Hz 2048 166 ms 26.6 ms 160 110 80 60 200Hz 7.8Hz 1536 125ms 20ms 190 130 95 75 300Hz 11.7Hz 1024 83.3ms 13.3ms 235 145 100 80 600Hz 23.4Hz 512 41.6ms 6.6ms 300 225 135 110 1200Hz 46.8Hz 256 20.8ms 3.3ms 435 315 210 150 Table IV. Peak-to-Peak Resolution vs. Input Range and Update Rate (CHP = 0) Peak-to-Peak Resolution in Counts (Bits) Output –3 dB SF Settling Time Settling Time Input Range Input Range Input Range Input Range Data Rate Frequency Word Normal Mode Fast Mode = (cid:4)80 mV = (cid:4)40 mV = (cid:4)20 mV = (cid:4)10 mV 150Hz 5.85Hz 2048 166 ms 26.6 ms 165k (17.5) 120k (17) 80k (16.5) 55k (16) 200Hz 7.8Hz 1536 125 ms 20 ms 140k (17) 100k (16.5) 70k (16) 45k (15.5) 300Hz 11.7Hz 1024 83.3 ms 13.3 ms 115k (17) 90k (16.5) 65k (16) 40k (15.5) 600Hz 23.4Hz 512 41.6 ms 6.6 ms 90k (16.5) 60k (16) 50k (15.5) 30k (15) 1200Hz 46.8Hz 256 20.8 ms 3.3 ms 60k (16) 43k (15.5) 32k (15) 20k (14.5) ON-CHIP REGISTERS The AD7730 contains thirteen on-chip registers which can be accessed via the serial port of the part. These registers are summarized in Figure 4 and in Table V and described in detail in the following sections. COMMUNICATIONS REGISTER DIN DIN RS2 RS1 RS0 DOUT DOUT STATUS REGISTER DOUT DATA REGISTER DIN DOUT MODE REGISTER REGISTER SELECT DIN DECODER DOUT FILTER REGISTER DIN DOUT DAC REGISTER DIN DOUT OFFSET REGISTER (x3) DIN DOUT GAIN REGISTER (x3) DIN DOUT TEST REGISTER Figure 4.Register Overview REV. B –11–

AD7730/AD7730L Table V. Summary of On-Chip Registers Power-On/Reset Register Name Type Size Default Value Function Communications Write Only 8 Bits Not Applicable All operations to other registers are initiated through Register the Communications Register. This controls whether subsequent operations are read or write operations WEN ZERO RW1 RW0 ZERO RS2 RS1 RS0 and also selects the register for that subsequent operation. Most subsequent operations return con- trol to the Communications Register except for the continuous read mode of operation. Status Register Read Only 8 Bits CX Hex Provides status information on conversions, calibra- tions, settling to step inputs, standby operation and RDY STDY STBY NOREF MS3 MS2 MS1 MS0 the validity of the reference voltage. Data Register Read Only 16 Bits or 24 Bits 000000 Hex Provides the most up-to-date conversion result from the part. Register length can be programmed to be 16 bits or 24 bits. Mode Register Read/Write 16 Bits 01B0 Hex Controls functions such as mode of operation, uni- polar/bipolar operation, controlling the function of MD2 MD1 MD0 B/U DEN D1 D0 WL AIN2(+)/D1 and AIN2(-)/D0, burnout current, HIREF ZERO RN1 RN0 CLKDIS BO CH1 CH0 Data Register word length and disabling of MCLK OUT. It also contains the reference selection bit, the range selection bits and the channel selection bits. Filter Register Read/Write 24 Bits 200010 Hex Controls the amount of averaging in the first stage filter, selects the fast step and skip modes and con- SF11 SF10 SF9 SF8 SF7 SF6 SF5 SF4 trols the ac excitation and chopping modes on the part. SF3 SF2 SF1 SF0 ZERO ZERO SKIP FAST ZERO ZERO AC CHP DL3 DL2 DL1 DL0 DAC Register Read/Write 8 Bits 20 Hex Provides control of the amount of correction per- formed by the Offset/TARE DAC. ZERO ZERO DAC5 DAC4 DAC3 DAC2 DAC1 DAC0 Offset Register Read/Write 24 Bits 800000 Hex Contains a 24-bit word which is the offset calibration coefficient for the part. The contents of this register are used to provide offset correction on the output from the digital filter. There are three Offset Regis- ters on the part and these are associated with the input channels as outlined in Table XIII. Gain Register Read/Write 24 Bits 59AEE7 Hex Contains a 24-bit word which is the gain calibration coefficient for the part. The contents of this register are used to provide gain correction on the output from the digital filter. There are three Gain Registers on the part and these are associated with the input channels as outlined in Table XIII. Test Register Read/Write 24 Bits 000000 Hex Controls the test modes of the part which are used when testing the part. The user is advised not to change the contents of this register. REV. B –12–

AD7730/AD7730L Communications Register (RS2–RS0 = 0, 0, 0) The Communications Register is an 8-bit write-only register. All communications to the part must start with a write operation to the Communications Register. The data written to the Communications Register determines whether the next operation is a read or write operation, the type of read operation, and to which register this operation takes place. For single-shot read or write operations, once the subsequent read or write operation to the selected register is complete, the interface returns to where it expects a write op- eration to the Communications Register. This is the default state of the interface, and on power-up or after a RESET, the AD7730 is in this default state waiting for a write operation to the Communications Register. In situations where the interface sequence is lost, a write operation of at least 32 serial clock cycles with DIN high, returns the AD7730 to this default state by resetting the part. Table VI outlines the bit designations for the Communications Register. CR0 through CR7 indicate the bit location, CR denot- ing the bits are in the Communications Register. CR7 denotes the first bit of the data stream. Table VI. Communications Register CR7 CR6 CR5 CR4 CR3 CR2 CR1 CR0 WEN ZERO RW1 RW0 ZERO RS2 RS1 RS0 Bit Bit Location Mnemonic Description CR7 WEN Write Enable Bit. A 0 must be written to this bit so the write operation to the Communications Register actually takes place. If a 1 is written to this bit, the part will not clock on to subsequent bits in the register. It will stay at this bit location until a 0 is written to this bit. Once a 0 is writ- ten to the WEN bit, the next seven bits will be loaded to the Communications Register. CR6 ZERO A zero must be written to this bit to ensure correct operation of the AD7730. CR5, CR4 RW1, RW0 Read/Write Mode Bits. These two bits determine the nature of the subsequent read/write opera- tion. Table VII outlines the four options. Table VII. Read/Write Mode RW1 RW0 Read/Write Mode 0 0 Single Write to Specified Register 0 1 Single Read of Specified Register 1 0 Start Continuous Read of Specified Register 1 1 Stop Continuous Read Mode With 0, 0 written to these two bits, the next operation is a write operation to the register specified by bits RS2, RS1, RS0. Once the subsequent write operation to the specified register has been com- pleted, the part returns to where it is expecting a write operation to the Communications Register. With 0,1 written to these two bits, the next operation is a read operation of the register specified by bits RS2, RS1, RS0. Once the subsequent read operation to the specified register has been completed, the part returns to where it is expecting a write operation to the Communications Register. Writing 1,0 to these bits, sets the part into a mode of continuous reads from the register speci- fied by bits RS2, RS1, RS0. The most likely registers with which the user will want to use this function are the Data Register and the Status Register. Subsequent operations to the part will consist of read operations to the specified register without any intermediate writes to the Com- munications Register. This means that once the next read operation to the specified register has taken place, the part will be in a mode where it is expecting another read from that specified register. The part will remain in this continuous read mode until 30 Hex has been written to the Communications Register. When 1,1 is written to these bits (and 0 written to bits CR3 through CR0), the continuous read mode is stopped and the part returns to where it is expecting a write operation to the Communi- cations Register. Note, the part continues to look at the DIN line on each SCLK edge during continuous read mode to determine when to stop the continuous read mode. Therefore, the user must be careful not to inadvertently exit the continuous read mode or reset the AD7730 by writing a series of 1s to the part. The easiest way to avoid this is to place a logic 0 on the DIN line while the part is in continuous read mode. Once the part is in continuous read mode, the user should ensure that an integer multiple of 8 serial clocks should have taken place before attempting to take the part out of continuous read mode. REV. B –13–

AD7730/AD7730L Bit Bit Location Mnemonic Description CR3 ZERO A zero must be written to this bit to ensure correct operation of the AD7730. CR2–CR0 RS2–RS0 Register Selection Bits. RS2 is the MSB of the three selection bits. The three bits select which register type the next read or write operation operates upon as shown in Table VIII. Table VIII. Register Selection RS2 RS1 RS0 Register 0 0 0 Communications Register (Write Operation) 0 0 0 Status Register (Read Operation) 0 0 1 Data Register 0 1 0 Mode Register 0 1 1 Filter Register 1 0 0 DAC Register 1 0 1 Offset Register 1 1 0 Gain Register 1 1 1 Test Register Status Register (RS2–RS0 = 0, 0, 0); Power-On/Reset Status: CX Hex The Status Register is an 8-bit read-only register. To access the Status Register, the user must write to the Communications Register selecting either a single-shot read or continuous read mode and load bits RS2, RS1, RS0 with 0, 0, 0. Table IX outlines the bit desig- nations for the Status Register. SR0 through SR7 indicate the bit location, SR denoting the bits are in the Status Register. SR7 denotes the first bit of the data stream. Figure 5 shows a flowchart for reading from the registers on the AD7730. The number in brackets indicates the power-on/reset default status of that bit. Table IX. Status Register SR7 SR6 SR5 SR4 SR3 SR2 SR1 SR0 RDY (1) STDY (1) STBY (0) NOREF (0) MS3 (X) MS2 (X) MS1 (X) MS0 (X) Bit Bit Location Mnemonic Description SR7 RDY Ready Bit. This bit provides the status of the RDY flag from the part. The status and function of this bit is the same as the RDY output pin. A number of events set the RDY bit high as indi- cated in Table XVIII. SR6 STDY Steady Bit. This bit is updated when the filter writes a result to the Data Register. If the filter is inFASTStepmode (see Filter Register section) and responding to a step input, the STDY bit remains high as the initial conversion results become available. The RDY output and bit are set low on these initial conversions to indicate that a result is available. If theSTDY is high, however, it indicates that the result being provided is not from a fully settled second-stage FIR filter. When the FIR filter has fully settled, the STDY bit will go low coincident with RDY. If the part is never placed into its FASTStep mode, the STDY bit will go low at the first Data Register read and it is not cleared by subsequent Data Register reads. A number of events set the STDY bit high as indicated in Table XVIII. STDY is set high along withRDY by all events in the table except a Data Register read. SR5 STBY Standby Bit. This bit indicates whether the AD7730 is in its Standby Mode or normal mode of operation. The part can be placed in its standby mode using the STANDBY input pin or by writing 011 to the MD2 to MD0 bits of the Mode Register. The power-on/reset status of this bit is 0 assuming the STANDBY pin is high. SR4 NOREF No Reference Bit. If the voltage between the REF IN(+) and REF IN(–) pins is below 0.3 V, or either of these inputs is open-circuit, the NOREF bit goes to 1. If NOREF is active on comple- tion of a conversion, the Data Register is loaded with all 1s. If NOREF is active on completion of a calibration, updating of the calibration registers is inhibited. SR3–SR0 MS3–MS0 These bits are for factory use. The power-on/reset status of these bits vary, depending on the factory-assigned number. REV. B –14–

AD7730/AD7730L Data Register (RS2–RS0 = 0, 0, 1); Power On/Reset Status: 000000 Hex The Data Register on the part is a read-only register which contains the most up-to-date conversion result from the AD7730. Fig- ure5 shows a flowchart for reading from the registers on the AD7730. The register can be programmed to be either 16 bits or 24bits wide, determined by the status of the WL bit of the Mode Register. The RDY output and RDY bit of the Status Register are set low when the Data Register is updated. The RDY pin and RDY bit will return high once the full contents of the register (either 16bits or 24bits) have been read. If the Data Register has not been read by the time the next output update occurs, the RDY pin and RDY bit will go high for at least 100 × t , indicating when a read from the Data Register should not be initiated to avoid a transfer from CLK IN the Data Register as it is being updated. Once the updating of the Data Register has taken place, RDY returns low. If the Communications Register data sets up the part for a write operation to this register, a write operation must actually take place in order to return the part to where it is expecting a write operation to the Communications Register (the default state of the inter- face). However, the 16 or 24 bits of data written to the part will be ignored by the AD7730. Mode Register (RS2–RS0 = 0, 1, 0); Power On/Reset Status: 01B0Hex The Mode Register is a 16-bit register from which data can be read or to which data can be written. This register configures the operating modes of the AD7730, the input range selection, the channel selection and the word length of the Data Register. TableX outlines the bit designations for the Mode Register. MR0 through MR15 indicate the bit location, MR denoting the bits are in the Mode Register. MR15 denotes the first bit of the data stream. The number in brackets indicates the power-on/reset default status of that bit. Figure 5 shows a flowchart for reading from the registers on the AD7730 and Figure 6 shows a flowchart for writ- ing to the registers on the part. Table X. Mode Register MR15 MR14 MR13 MR12 MR11 MR10 MR9 MR8 MD2 (0) MD1 (0) MD0 (0) B/U (0) DEN (0) D1 (0) D0 (0) WL (1) MR7 MR6 MR5 MR4 MR3 MR2 MR1 MR0 HIREF (1) ZERO (0) RN1 (1) RN0 (1) CLKDIS (0) BO (0) CH1 (0) CH0 (0) Bit Bit Location Mnemonic Description MR15–MR13 MD2–MD0 Mode Bits. These three bits determine the mode of operation of the AD7730 as outlined in Table XI. The modes are independent, such that writing new mode bits to the Mode Register will exit the part from the mode in which it is operating and place it in the new requested mode immediately after the Mode Register write. The function of the mode bits is described in more detail below. Table XI. Operating Modes MD2 MD1 MD0 Mode of Operation 0 0 0 Sync (Idle) Mode Power-On/Reset Default 0 0 1 Continuous Conversion Mode 0 1 0 Single Conversion Mode 0 1 1 Power-Down (Standby) Mode 1 0 0 Internal Zero-Scale Calibration 1 0 1 Internal Full-Scale Calibration 1 1 0 System Zero-Scale Calibration 1 1 1 System Full-Scale Calibration REV. B –15–

AD7730/AD7730L MD2 MD1 MD0 Operating Mode 0 0 0 Sync (Idle) Mode. In this mode, the modulator and filter are held in reset mode and the AD7730 is not processing any new samples or data. Placing the part in this mode is equivalent to exerting the SYNC input pin. However, exerting the SYNC pin does not actually force these mode bits to 0, 0, 0. The part returns to this mode after a calibration or after a conversion in Single Conversion Mode. This is the default condition of these bits after Power-On/Reset. 0 0 1 Continuous Conversion Mode. In this mode, the AD7730 is continuously processing data and providing conversion results to the Data Register at the programmed output update rate (as determined by the Filter Register). For most applications, this would be the normal operating mode of the AD7730. 0 1 0 Single Conversion Mode. In this mode, the AD7730 performs a single conversion, updates the Data Register, returns to the Sync Mode and resets the mode bits to 0, 0, 0. The result of the single conversion on the AD7730 in this mode will not be provided until the full settling time of the filter has elapsed. 0 1 1 Power-Down (Standby) Mode. In this mode, the AD7730 goes into its power-down or standby state. Placing the part in this mode is equivalent to exerting the STANDBY input pin. However, exerting STANDBY does not actually force these mode bits to 0, 1, 1. 1 0 0 Zero-Scale Self-Calibration Mode. This activates zero-scale self-calibration on the channel selected by CH1 and CH0 of the Mode Register. This zero-scale self-calibration is performed at the selected gain on internally shorted (zeroed) inputs. When this zero-scale self-calibration is complete, the part updates the contents of the appropriate Offset Calibration Register and returns to Sync Mode with MD2, MD1 and MD0 returning to 0, 0, 0. The RDY output and bit go high when calibration is initiated and return low when this zero-scale self-calibration is complete to indicate that the part is back in Sync Mode and ready for further operations. 1 0 1 Full-Scale Self-Calibration Mode. This activates full-scale self-calibration on the channel selected by CH1 and CH0 of the Mode Register. This full-scale self-calibration is performed at the selected gain on an internally-generated full-scale signal. When this full-scale self-calibration is complete, the part updates the contents of the appropriate Gain Calibration Register and Offset Calibration Register and returns to Sync Mode with MD2, MD1 and MD0 returning to 0, 0, 0. The RDY output and bit go high when calibration is initiated and return low when this full-scale self-calibration is complete to indicate that the part is back in Sync Mode and ready for further operations. 1 1 0 Zero-Scale System Calibration Mode. This activates zero scale system calibration on the channel selected by CH1 and CH0 of the Mode Register. Calibration is performed at the selected gain on the input volt- age provided at the analog input during this calibration sequence. This input voltage should remain stable for the duration of the calibration. When this zero-scale system calibration is complete, the part updates the contents of the appropriate Offset Calibration Register and returns to Sync Mode with MD2, MD1 and MD0 returning to 0, 0, 0. The RDY output and bit go high when calibration is initiated and return low when this zero-scale calibration is complete to indicate that the part is back in Sync Mode and ready for further operations. 1 1 1 Full-Scale System Calibration Mode. This activates full-scale system calibration on the selected input channel. Calibration is performed at the selected gain on the input voltage provided at the analog input during this calibration sequence. This input voltage should remain stable for the duration of the calibra- tion. When this full-scale system calibration is complete, the part updates the contents of the appropriate Gain Calibration Register and returns to Sync Mode with MD2, MD1 and MD0 returning to 0, 0, 0. TheRDY output and bit go high when calibration is initiated and return low when this full-scale calibra- tion is complete to indicate that the part is back in Sync Mode and ready for further operations. REV. B –16–

AD7730/AD7730L Bit Bit Location Mnemonic Description MR12 B/U Bipolar/Unipolar Bit. A 0 in this bit selects bipolar operation and the output coding is 00...000 for negative full-scale input, 10...000 for zero input, and 11...111 for positive full-scale input. A 1 in this bit selects unipolar operation and the output coding is 00...000 for zero input and 11...111 for positive full-scale input. MR11 DEN Digital Output Enable Bit. With this bit at 1, the AIN2(+)/D1 and AIN2(–)/D0 pins assume their digital output functions and the output drivers connected to these pins are enabled. In this mode, the user effectively has two port bits which can be programmed over the serial interface. MR10–MR9 D1–D0 Digital Output Bits. These bits determine the digital outputs on the AIN2(+)/D1 and AIN2(–)/D0 pins, respectively, when the DEN bit is a 1. For example, a 1 written to the D1 bit of the Mode Register (with the DEN bit also a 1) will put a logic 1 on the AIN2(+)/D1 pin. This logic 1 will remain on this pin until a 0 is written to the D1 bit (in which case the AIN2(+)/D1 pin goes to a logic 0) or the digital output function is disabled by writing a 0 to the DEN bit. MR8 WL Data Word Length Bit. This bit determines the word length of the Data Register. A 0 in this bit selects 16-bit word length when reading from the data register (i.e., RDY returns high after 16 serial clock cycles in the read operation). A 1 in this bit selects 24-bit word length for the Data Register. MR7 HIREF High Reference Bit. This bit should be set in accordance with the reference voltage which is being used on the part. If the reference voltage is 5 V, the HIREF bit should be set to 1. If the reference voltage is 2.5 V, the HIREF bit should be set to a 0. With the HIREF bit set correctly for the appropriate applied reference voltage, the input ranges are 0 mV to +10mV, +20mV, +40mV and +80mV for unipolar operation and ±10mV, ±20mV, ±40mV and ±80mV for bipolar operation. It is possible for a user with a 2.5 V reference to set the HIREF bit to a 1. In this case, the part is oper- ating with a 2.5 V reference but assumes it has a 5 V reference. As a result, the input ranges on the part become 0 to +5mV, +10mV, +20mV and +40mV for unipolar operation and ±5mV, ±10mV, ±20mV and ±40mV for bipolar operation. However, the output noise from the part (in nV) will re- main unchanged so the resolution of the part (in counts) will halve. MR6 ZERO A zero must be written to this bit to ensure correct operation of the AD7730. MR5–MR4 RN1–RN0 Input Range Bits. These bits determine the analog input range for the selected analog input. The dif- ferent input ranges are outlined in Table XII. The table is valid for a reference voltage of 5 V with the HIREF bit at 1, or for a reference voltage of 2.5 V with the HIREF bit at a logic 0. Table XII. Input Range Selection Input Range RN1 RN0 B/U Bit = 0 B/U Bit = 1 0 0 –10 mV to +10 mV 0 mV to +10 mV 0 1 –20 mV to +20 mV 0 mV to +20 mV 1 0 –40 mV to +40 mV 0 mV to +40 mV 1 1 –80 mV to +80 mV 0 mV to +80 mV Power-On/Reset Default Note that the input range given in the above table is the range that appears at the input of the PGA after the DAC offset value has been applied. If the DAC adjusts out no offset (DAC Register is 0010 0000), then this is also the input voltage range at the analog input pins. If, for example, the DAC sub- tracts out 50 mV of offset and the part is being operated in bipolar mode with RN1 and RN0 at 0, 0, the actual input voltage range at the analog input is +40 mV to +60 mV. MR3 CLKDIS Master Clock Disable Bit. A 1 in the bit disables the master clock from appearing at the MCLK OUT pin. When disabled, the MCLK OUT pin is forced low. It allows the user the flexibility of using the MCLK OUT as a clock source for other devices in the system or of turning off the MCLK OUT as a power saving feature. When using an external master clock at the MCLK IN pin, the AD7730 contin- ues to have internal clocks and will convert normally with the CLKDIS bit active. When using a crystal oscillator or ceramic resonator across the MCLK IN and MCLK OUT pins, the AD7730 clock is stopped and no conversions take place when the CLKDIS bit is active. REV. B –17–

AD7730/AD7730L Bit Bit Location Mnemonic Description MR2 BO Burnout Current Bit. A 1 in this bit activates the burnout currents. When active, the burnout currents connect to the selected analog input pair, one source current to the AIN(+) input and one sink current to the AIN(–) input. A 0 in this bit turns off the on-chip burnout currents. MR1–MR0 CH1–CH0 Channel Selection Bits. These bits select the analog input channel to be converted or calibrated as outlined in Table XIII. With CH1 at 1 and CH0 at 0, the part looks at the AIN1(–) input internally shorted to itself. This can be used as a test method to evaluate the noise performance of the part with no external noise sources. In this mode, the AIN1(–) input should be connected to an external voltage within the allowable common-mode range of the part. The Offset and Gain Calibration Registers on the part are paired. There are three pairs of calibration registers labelled Register Pair 0 through Regis- ter Pair 2. These are assigned to the input channel pairs as outlined in Table XIII. Table XIII. Channel Selection Input Channel Pair CH1 CH0 Positive Input Negative Input Calibration Register Pair 0 0 AIN1(+) AIN1(–) Register Pair 0 0 1 AIN2(+) AIN2(–) Register Pair 1 1 0 AIN1(–) AIN1(–) Register Pair 0 1 1 AIN1(–) AIN2(–) Register Pair 2 Filter Register (RS2-RS0 = 0, 1, 1); Power-On/Reset Status: 200010Hex The Filter Register is a 24-bit register from which data can be read or to which data can be written. This register determines the amount of averaging performed by the filter and the mode of operation of the filter. It also sets the chopping mode and the delay associated with chopping the inputs. Table XIV outlines the bit designations for the Filter Register. FR0 through FR23 indicate the bit location, FR denoting the bits are in the Filter Register. FR23 denotes the first bit of the data stream. The number in brackets indicates the power-on/reset default status of that bit. Figure 5 shows a flowchart for reading from the registers on the AD7730 and Figure 6 shows a flowchart for writing to the registers on the part. Table XIV. Filter Register FR23 FR22 FR21 FR20 FR19 FR18 FR17 FR16 SF11 (0) SF10 (0) SF9 (1) SF8 (0) SF7 (0) SF6 (0) SF5 (0) SF4 (0) FR15 FR14 FR13 FR12 FR11 FR10 FR9 FR8 SF3 (0) SF2 (0) SF1 (0) SF0 (0) ZERO (0) ZERO (0) SKIP (0) FAST (0) FR7 FR6 FR5 FR4 FR3 FR2 FR1 FR0 ZERO (0) ZERO (0) AC (0) CHP (1) DL3 (0) DL2 (0) DL1 (0) DL0 (0) Bit Bit Location Mnemonic Description FR23–FR12 SF11–SF0 Sinc3 Filter Selection Bits. The AD7730 contains two filters: a sinc3 filter and an FIR filter. The 12bits programmed to SF11 through SF0 set the amount of averaging the sinc3 filter performs. As a result, the number programmed to these 12 bits affects the –3 dB frequency and output update rate from the part (see Filter Architecture section). The allowable range for SF words depends on whether the part is operated with CHOP on or off and SKIP on or off. Table XV outlines the SF ranges for different setups. All output update rates will be one-half those quoted in Table XV for the AD7730L operating with a 2.4576 MHz clock. REV. B –18–

AD7730/AD7730L Table XV. SF Ranges CHOP SKIP SF Range Output Update Rate Range (Assuming 4.9152 MHz Clock) 0 0 2048 to 150 150 Hz to 2.048 kHz 1 0 2048 to 75 50 Hz to 1.365 kHz 0 1 2048 to 40 150 Hz to 7.6 kHz 1 1 2048 to 20 50 Hz to 5.12 kHz Bit Bit Location Mnemonic Description FR11–FR10 ZERO A zero must be written to these bits to ensure correct operation of the AD7730. FR9 SKIP FIR Filter Skip Bit. With a 0 in this bit, the AD7730 performs two stages of filtering before shipping a result out of the filter. The first is a sinc3 filter followed by a 22-tap FIR filter. With a 1 in this bit, the FIR filter on the part is bypassed and the output of the sinc3 is fed directly as the output result of the AD7730’s filter (see Filter Architecture for more details on the filter implementation). FR8 FAST FASTStep Mode Enable Bit. A 1 in this bit enables the FASTStep mode on the AD7730. In this mode, if a step change on the input is detected, the FIR calculation portion of the filter is suspended and replaced by a simple moving average on the output of the sinc3 filter. Initially, two outputs from the sinc3 filter are used to calculate an AD7730 output. The number of sinc3 outputs used to calculate the moving average output is increased (from 2 to 4 to 8 to 16) until theSTDY bit goes low. When the FIR filter has fully settled after a step, the STDY bit will become active and the FIR filter is switched back into the processing loop (see Filter Architec- ture section for more details on the FASTStep mode). FR7–FR6 ZERO A zero must be written to these bits to ensure correct operation of the AD7730. FR5 AC AC Excitation Bit. If the signal source to the AD7730 is ac-excited, a 1 must be placed in this bit. For dc-excited inputs, this bit must be 0. The ac bit has no effect if CHP is 0. With the ac bit at 1, the AD7730 assumes that the voltage at the AIN(+)/AIN(–) and REF IN(+)/REF IN(–) input terminals are reversed on alternate input sampling cycles (i.e. chopped). Note that when the AD7730 is performing internal zero-scale or full-scale calibrations, the ac bit is treated as a 0, i.e., the device performs these self-calibrations with dc excitation. FR4 CHP Chop Enable Bit. This bit determines if the chopping mode on the part is enabled. A 1 in this bit location enables chopping on the part. When the chop mode is enabled, the part is effectively chopped at its input and output to remove all offset and offset drift errors on the part. If offset performance with time and temperature are important parameters in the design, it is recom- mended that the user enable chopping on the part. If the input signal is dc-excited, the user has the option of operating the part in either chop or nonchop mode. If the input signal is ac-excited, both the ac bit and the CHP bit must be set to 1. The chop rate on the ACX and ACX signals is one half of the programmed output rate of the part and thus the chopping frequency varies with the programmed output rate. FR3–FR0 DL3–DL0 Delay Selection Bits. These four bits program the delay (in modulator cycles) to be inserted after each chop edge when the CHP bit is 1. One modulator cycle is MCLK IN/16 and is 3.25 μs at MCLK IN = 4.9152MHz. A delay should only be required when in ac mode. Its purpose is to cater for external delays between the switching signals (ACX and ACX) and when the analog inputs are actually switched and settled. During the specified number of cycles (between 0 and 15), the modulator is held in reset and the filter does not accept any inputs. If CHP = 1, the output rate is (MCLK IN/ 16 × (DL + 3 × SF) where DL is the value loaded to bits DL0–DL3. The chop rate is always one half of the output rate. This chop period takes into account the programmed delay and the fact that the sinc3 filter must settle every chop cycle. With CHP = 0, the output rate is 1/SF. REV. B –19–

AD7730/AD7730L DAC Register (RS2–RS0 = 1, 0, 0); Power On/Reset Status: 20Hex The DAC Register is an 8-bit register from which data can either be read or to which data can be written. This register provides the code for the offset-compensation DAC on the part. Table XVI outlines the bit designations for the DAC Register. DR0 through DR7 indicate the bit location, DR denoting the bits are in the DAC Register. DR7 denotes the first bit of the data stream. The number in brackets indicates the power-on/reset default status of that bit. Figure 5 shows a flowchart for reading from the registers on the AD7730 and Figure 6 shows a flowchart for writing to the registers on the part. Table XVI. DAC Register DR7 DR6 DR5 DR4 DR3 DR2 DR1 DR0 ZERO (0) ZERO (0) DAC5 (1) DAC4 (0) DAC3 (0) DAC2 (0) DAC1 (0) DAC0 (0) Bit Bit Location Mnemonic Description DR7–DR6 ZERO A zero must be written to these bits to ensure correct operation of the AD7730. DR5–DR0 DAC5–DAC0 DAC Selection Bits. These bits program the output of the offset DAC. The DAC is effectively 6 bits with one sign bit (DAC5) and five magnitude bits. With DAC5 at 1, the DAC output subtracts from the analog input before it is applied to the PGA. With DAC5 at 0, the DAC output adds to the analog input before it is applied to the PGA. The DAC output is given by (V /62.5)× (D/32) = (V /2000)× D where D is the decimal equivalent of bits DAC4 to REF REF DAC0. Thus, for a 5 V reference applied across the REF IN pins, the DAC resolution is 2.5 mV and offsets in the range –77.5 mV to +77.5 mV can be removed from the analog input signal before it is applied to the PGA. Note, that the HIREF bit has no effect on the DAC range or resolution, it controls the ADC range only. Offset Calibration Register (RS2–RS0 = 1, 0, 1); Power-On/Reset Status: 800000Hex The AD7730 contains three 24-bit Offset Calibration Registers, labelled Offset Calibration Register 0 to Offset Calibration Reg- ister2, to which data can be written and from which data can be read. The three registers are totally independent of each other. The Offset Calibration Register is used in conjunction with the associated Gain Calibration Register to form a register pair. The calibration register pair used to scale the output is as outlined in Table XIII. The Offset Calibration Register is updated after an offset calibration routine (1, 0, 0 or 1, 1, 0 loaded to the MD2, MD1, MD0 bits of the Mode Register). During subsequent conversions, the contents of this register are subtracted from the filter output prior to gain scaling being performed on the word. Figure 5 shows a flowchart for reading from the registers on the AD7730 and Figure 6 shows a flowchart for writing to the regis- ters on the part. Gain Calibration Register (RS2–RS0 = 1, 1, 0); Power-On/Reset Status: 593CEA The AD7730 contains three 24-bit Gain Calibration Registers, labelled Gain Calibration Register 0 to Gain Calibration Register 2, to which data can be written and from which data can be read. The three registers are totally independent of each other. The Gain Calibration Register is used in conjunction with the associated Offset Calibration Register to form a register pair. The calibration register pair used to scale the output is as outlined in Table XIII. The Gain Calibration Register is updated after a gain calibration routine (1, 0, 1 or 1, 1, 1 loaded to the MD2, MD1, MD0 bits of the Mode Register). During subsequent con- versions, the contents of this register are used to scale the number which has already been offset corrected with the Offset Cali- bration Register contents. Figure 5 shows a flowchart for reading from the registers on the AD7730 and Figure 6 shows a flowchart for writing to the registers on the part. Test Register (RS2–RS0 = 1, 1, 1); Power-On/Reset Status: 000000Hex The AD7730 contains a 24-bit Test Register to which data can be written and from which data can be read. The contents of this Test Register are used in testing the device. The user is advised not to change the status of any of the bits in this register from the default (Power-On or RESET) status of all 0s as the part will be placed in one of its test modes and will not operate correctly. If the part enters one of its test modes, exercising RESET or writing 32 successive 1s to the part will exit the AD7730 from the mode and return all register contents to their power-on/reset status. Note, if the part is placed in one of its test modes, it may not be possible to read back the contents of the Test Register depending on the test mode in which the part has been placed. REV. B –20–

AD7730/AD7730L READING FROM AND WRITING TO THE ON-CHIP REGISTERS The AD7730 contains a total of thirteen on-chip registers. These registers are all accessed over a three-wire interface. As a result, addressing of registers is via a write operation to the topmost register on the part, the Communications Register. Figure 5 shows a flowchart for reading from the different registers on the part summarizing the sequence and the words to be written to access each of the registers. Figure 6 gives a flowchart for writing to the different registers on the part, again summarizing the sequence and words to be written to the AD7730. START Byte W Byte Y Byte Z Register (Hex) (Hex) (Hex) Status Register 10 20 30 CONTINUOUS READS OF YES Data Register 11 21 30 REGISTER REQUIRED? Mode Register 12 22 30 Filter Register 13 N/A* N/A* DAC Register 14 N/A* N/A* NO Offset Register 15 N/A* N/A* WRITEBYTE W TO Gain Register 16 N/A* N/A* COMMUNICATIONS REGISTER (SEE ACCOMPANYING TABLE) Test Register 17 N/A* N/A* WRITEBYTE Y TO COMMUNICATIONS REGISTER *N/A= Not Applicable. Continuous reads of these registers does not make sense (SEE ACCOMPANYING TABLE) as the register contents would remain the same since they are only changed by a READ REGISTER write operation. READ REGISTER STOP NO CONTINUOUS READ OPERATION? YES WRITEBYTE Z TO COMMUNICATIONS REGISTER (SEE ACCOMPANYING TABLE) Figure 5.Flowchart for Reading from the AD7730 Registers START Register Byte Y (Hex) Communications Register 00 Data Register Read Only Register WRITEBYTE Y TO COMMUNICATIONS REGISTER Mode Register 02 (SEE ACCOMPANYING TABLE) Filter Register 03 DAC Register 04 WRITE TO REGISTER Offset Register 05 Gain Register 06 Test Register User is advised not to change contents of Test Register. END Figure 6.Flowchart for Writing to the AD7730 Registers REV. B –21–

AD7730/AD7730L CALIBRATION OPERATION SUMMARY The AD7730 contains a number of calibration options as outlined previously. Table XVII summarizes the calibration types, the operations involved and the duration of the operations. There are two methods of determining the end of calibration. The first is to monitor the hardware RDY pin using either interrupt-driven or polling routines. The second method is to do a software poll of the RDY bit in the Status Register. This can be achieved by setting up the part for continuous reads of the Status Register once a calibra- tion has been initiated. The RDY pin and RDY bit go high on initiating a calibration and return low at the end of the calibration routine. At this time, the MD2, MD1, MD0 bits of the Mode Register have returned to 0, 0, 0. The FAST and SKIP bits are treated as 0 for the calibration sequence so the full filter is always used for the calibration routines. See Calibration section for full detail. Table XVII. Calibration Operations MD2, MD1, Duration to RDY Duration to RDY Calibration Type MD0 Low (CHP = 1) Low (CHP = 0) Calibration Sequence Internal Zero-Scale 1, 0, 0 22 × 1/Output Rate 24 × 1/Output Rate Calibration on internal shorted input with PGA set for selected input range. The ac bit is ignored for this calibra- tion sequence. The sequence is performed with dc excitation. The Offset Calibration Register for the selected channel is updated at the end of this calibration sequence. For full self- calibration, this calibration should be preceded by an Internal Full-Scale calibration. For applications which require an Internal Zero-Scale and System Full-Scale calibration, this Internal Zero-Scale calibration should be performed first. Internal Full-Scale 1, 0, 1 44 × 1/Output Rate 48 × 1/Output Rate Calibration on internally-generated input full-scale with PGA set for selected input range. The ac bit is ignored for this calibration sequence. The sequence is performed with dc excitation. The Gain Calibration Register for the selected channel is updated at the end of this calibration sequence. It is recommended that internal full-scale calibrationsare performed on the 80mV range, regardless of the subsequent operating range, to optimize the post- calibration gain error. This calibration should be followed by either an Internal Zero-Scale or System Zero-Scale calibration. This zero-scale calibration should be performed at the operating input range. System Zero-Scale 1, 1, 0 22 × 1/Output Rate 24 × 1/Output Rate Calibration on externally applied input voltage with PGA set for selected input range. The input applied is assumed to be the zero scale of the system. If ac = 1, the system continues to use ac excitation for the duration of the calibration. For full system calibration, this System Zero- Scale calibration should be performed first. For applications which require a System Zero-Scale and Internal Full-Scale calibration, this calibration should be preceded by the Internal Full-Scale calibration. The Offset Calibration Register for the selected channel is updated at the end of this calibration sequence. System Full-Scale 1, 1, 1 22 × 1/Output Rate 24 × 1/Output Rate Calibration on externally-applied input voltage with PGA set for selected input range. The input applied is assumed to be the full-scale of the system. If ac = 1, the system continues to use ac excitation for the duration of the calibration. This calibration should be preceded by a System Zero-Scale or Internal Zero-Scale calibration. The Gain Calibration Register for the selected channel is updated at the end of this calibration sequence. REV. B –22–

AD7730/AD7730L CIRCUIT DESCRIPTION registers. The output noise performance and peak-to-peak reso- The AD7730 is a sigma-delta A/D converter with on-chip digital lution of the part varies with gain and with the output rate as filtering, intended for the measurement of wide dynamic range, shown in Tables I to IV. low-frequency signals such as those in weigh-scale, strain-gage, The analog inputs are buffered on-chip allowing the part to pressure transducer or temperature measurement applications. handle significant source impedances on the analog input. This It contains a sigma-delta (or charge-balancing) ADC, a calibra- means that external R, C filtering (for noise rejection or RFI tion microcontroller with on-chip static RAM, a clock oscillator, reduction) can be placed on the analog inputs if required. Both a digital filter and a bidirectional serial communications port. analog channels are differential, with a common-mode voltage The part consumes 13mA of power supply current with a standby range that comes within 1.2V of AGND and 0.95V of AV . mode which consumes only 25μA. The part operates from a single DD The reference input is also differential and the common-mode +5 V supply. The clock source for the part can be provided via an range here is from AGND to AV . DD external clock or by connecting a crystal oscillator or ceramic resonator across the MCLKIN and MCLKOUT pins. The part contains a 6-bit DAC that is controlled via on-chip registers. This DAC can be used to remove TARE values of up The part contains two programmable-gain fully differential analog to±80mV from the analog input signal range. The resolution input channels. The part handles a total of eight different input on this TARE function is 1.25mV for a +2.5 V reference and ranges which are programmed via the on-chip registers. There are 2.5 mV with a +5 V reference. four differential unipolar ranges: 0 mV to +10mV, 0 mV to +20mV, 0 mV to +40mV and 0 mV to +80mV and four differen- The AD7730 can accept input signals from a dc-excited bridge. tial bipolar ranges: ±10mV, ±20mV, ±40mV and ±80mV. It can also handle input signals from an ac-excited bridge by using the ac excitation clock signals (ACX and ACX) to switch The AD7730 employs a sigma-delta conversion technique to the supplies to the bridge. ACX and ACX are nonoverlapping realize up to 24 bits of no missing codes performance. The clock signals used to synchronize the external ac supplies that sigma-delta modulator converts the sampled input signal into a drive the transducer bridge. These ACX clocks are demodulated digital pulse train whose duty cycle contains the digital informa- on the AD7730 input. tion. A digital low-pass filter processes the output of the sigma- delta modulator and updates the data register at a rate that can The AD7730 contains a number of hardware and software be programmed over the serial interface. The output data from events that set or reset status flags and bits in registers. Table the part is accessed over this serial interface. The cutoff frequency XVIII summarizes which blocks and flags are affected by the and output rate of this filter can be programmed via on-chip different events. Table XVIII. Reset Events Set Registers Mode Filter Analog Reset Serial Set RDY SetSTDY Event to Default Bits Reset Power-Down Interface Pin/Bit Bit Power-On Reset Yes 000 Yes Yes Yes Yes Yes RESET Pin Yes 000 Yes No Yes Yes Yes STANDBY Pin No As Is Yes Yes No Yes Yes Mode 011 Write No 011 Yes Yes No Yes Yes SYNC Pin No As Is Yes No No Yes Yes Mode 000 Write No 000 Yes No No Yes Yes Conversion or No New Initial No No Yes Yes Cal Mode Write Value Reset Clock 32 1s Yes 000 Yes No Yes Yes Yes Data Register Read No As Is No No No Yes No REV. B –23–

AD7730/AD7730L ANALOG INPUT Offset DAC Analog Input Channels The purpose of the Offset DAC is to either add or subtract an The AD7730 contains two differential analog input channels, a offset so the input range at the input to the PGA is as close as primary input channel, AIN1, and a secondary input channel, possible to the nominal. If the output of the 6-bit Offset DAC is AIN2. The input pairs provide programmable gain, differential 0V, the differential voltage ranges that appear at the analog channels which can handle either unipolar or bipolar input input to the part will also appear at the input to the PGA. If, signals. It should be noted that the bipolar input signals are however, the Offset DAC has an output voltage other than 0V, referenced to the respective AIN(–) input of the input pair. The the input range to the analog inputs will differ from that applied secondary input channel can also be reconfigured as two digital to the input of the PGA. output port bits. The Offset DAC has five magnitude bits and one sign bit. The A two-channel differential multiplexer switches one of the two sign bit determines whether the value loaded to the five magni- input channels to the on-chip buffer amplifier. This multiplexer tude bits is added to or subtracted from the voltage at the ana- is controlled by the CH0 and CH1 bits of the Mode Register. log input pins. Control of the Offset DAC is via the DAC When the analog input channel is switched, the RDY output Register which is discussed previously in the On-Chip Registers goes high and the settling time of the part must elapse before a section. With a 5V reference applied between the REFIN pins, valid word from the new channel is available in the Data Regis- the resolution of the Offset DAC is 2.5mV with a range that ter (indicated by RDY going low). allows addition or subtraction of 77.5mV. With a 2.5V refer- Buffered Inputs ence applied between the REFIN pins, the resolution of the Offset DAC is 1.25mV with a range that allows addition or The output of the multiplexer feeds into a high impedance input subtraction of 38.75mV. stage of the buffer amplifier. As a result, the analog inputs can handle significant source impedances. This buffer amplifier has Following is an example of how the Offset DAC works. If the an input bias current of 50nA (CHP = 1) and 60nA (CHP = 0). differential input voltage range the user had at the analog input This current flows in each leg of the analog input pair. The pins was +20 mV to +30mV, the Offset DAC should be pro- offset current on the part is the difference between the input grammed to subtract 20mV of offset so the input range to the bias on the legs of the input pair. This offset current is less than PGA is 0 mV to +10mV. If the differential input voltage range 10nA (CHP = 1) and 30 nA (CHP = 0). Large source resis- the user had at the analog input pins was –60 mV to +20mV, tances result in a dc offset voltage developed across the source the Offset DAC should be programmed to add 20mV of offset so resistance on each leg, but matched impedances on the analog the input range to the PGA is ±40mV. input legs will reduce the offset voltage to that generated by the Bipolar/Unipolar Inputs input offset current. The analog inputs on the AD7730 can accept either unipolar or Analog Input Ranges bipolar input voltage ranges. Bipolar input ranges do not imply The absolute input voltage range is restricted to between that the part can handle negative voltages with respect to system AGND+ 1.2V to AVDD – 0.95V, which also places restrictions ground on its analog inputs unless the AGND of the part is also on the common-mode range. Care must be taken in setting up biased below system ground. Unipolar and bipolar signals on the common-mode voltage and input voltage range so these the AIN(+) input are referenced to the voltage on the respective limits are not exceeded, otherwise there will be a degradation in AIN(–) input. For example, if AIN(–) is +2.5V and the AD7730 is linearity performance. configured for an analog input range of 0 to +10mV with no DAC offset correction, the input voltage range on the AIN(+) In some applications, the analog input range may be biased input is +2.5V to +2.51V. Similarly, if AIN(–) is +2.5V and the either around system ground or slightly below system ground. In AD7730 is configured for an analog input range of ±80mV such cases, the AGND of the AD7730 must be biased negative with no DAC offset correction, the analog input range on the with respect to system ground so the analog input voltage does AIN(+) input is +2.42V to +2.58 V (i.e., 2.5V ± 80mV). not go within 1.2 V of AGND. Care should taken to ensure that the differential between either AVDD or DVDD and this biased Bipolar or unipolar options are chosen by programming the B/U AGND does not exceed 5.5V. This is discussed in more detail bit of the Mode Register. This programs the selected channel in the Applications section. for either unipolar or bipolar operation. Programming the chan- Programmable Gain Amplifier nel for either unipolar or bipolar operation does not change any of the input signal conditioning; it simply changes the data The output from the buffer amplifier is summed with the output output coding and the points on the transfer function where of the 6-bit Offset DAC before it is applied to the input of the calibrations occur. When the AD7730 is configured for unipolar on-chip programmable gain amplifier (PGA). The PGA can operation, the output coding is natural (straight) binary with a handle four different unipolar input ranges and four bipolar zero differential voltage resulting in a code of 000...000, a ranges. With the HIREF bit of the Mode Register at 0 and a midscale voltage resulting in a code of 100...000 and a full- +2.5V reference (or the HIREF bit at 1 and a +5V reference), scale input voltage resulting in a code of 111...111. When the the unipolar ranges are 0 mV to +10mV, 0 mV to +20mV, AD7730 is configured for bipolar operation, the coding is offset 0 mV to +40mV, and 0 mV to +80mV, while the bipolar ranges are±10mV, ±20mV, ±40mV and ±80mV. These are the binary with a negative full scale voltage resulting in a code of 000...000, a zero differential voltage resulting in a code of nominal ranges that should appear at the input to the on-chip 100...000 and a positive full scale voltage resulting in a code PGA. of 111...111. REV. B –24–

AD7730/AD7730L Burnout Currents The AD7730 contains two 100nA constant current generators, AVDD DVDD REF IN(+) one source current from AV to AIN(+) and one sink current DD from AIN(–) to AGND. The currents are switched to the se- REF IN(–) lected analog input pair. Both currents are either on or off, EXCITATION IN+ AIN1(+) AD7730 VOLTAGE = +5V depending on the BO bit of the Mode Register. These currents AIN1(–) can be used in checking that a transducer is still operational OUT+ OUT– before attempting to take measurements on that channel. If the IN– currents are turned on, allowed flow in the transducer, a mea- surement of the input voltage on the analog input taken and the AGND DGND voltage measured is full scale, it indicates that the transducer has gone open-circuit. If the voltage measured is 0 V, it indicates that the transducer has gone short circuit. For normal operation, Figure 7.Ratiometric Generation of Reference in DC- these burnout currents are turned off by writing a 0 to the BO Excited Bridge Application bit. The current sources work over the normal absolute input voltage range specifications. AVDD DVDD REF IN(+) REFERENCE INPUT REF IN(–) The AD7730’s reference inputs, REFIN(+) and REFIN(–), IN+ provide a differential reference input capability. The common- EXCITATION AIN1(+) VOLTAGE = +5V AIN1(–) mode range for these differential inputs is from AGND to OUT+ OUT– AD7730 AV . The nominal reference voltage, V (REFIN(+)— DD REF REFIN(–)), for specified operation is +2.5V with the HIREF IN– bit at 0 V and +5V with the HIREF bit at 1. The part is also functional with V of +2.5V with the HIREF bit at 1. This REF ACX results in a halving of all input ranges. The resolution in nV will AC ACX EXCITATION be unaltered but will appear halved in terms of counts. CLOCK Both reference inputs provide a high impedance, dynamic load. The typical average dc input leakage current over temperature AGND DGND is 8.5μA with HIREF=1 and V =+5V, and 2.5μA with REF Figure 8.Ratiometric Generation of Reference in AC- HIREF=0 and V =+2.5V. Because the input impedance of REF Excited Bridge Application each reference input is dynamic, external resistance/capacitance combinations on these inputs may result in gain errors on the application. In this case, both the reference voltage for the part part. and the excitation voltage for the transducer are chopped. Once again, the HIREF bit should be set to 1. The AD7730 can be operated in either ac or dc mode. If the bridge excitation is fixed dc, the AD7730 should be operated in If the AD7730 is not used in a ratiometric application, a low dc mode. If the analog input and the reference inputs are externally noise reference should be used. Recommended 2.5 V reference chopped before being applied to the part the AD7730 should be voltage sources for the AD7730 include the AD780, REF43 operated in ac mode and not dc mode. In ac mode, it is assumed and REF192. If any of these references are used as the reference that both the analog inputs and reference inputs are chopped source for the AD7730, the HIREF bit should be set to 0. It is and as a result change phase every alternate chopping cycle. If generally recommended to decouple the output of these references the chopping is synchronized by the AD7730 (using the ACX to further reduce the noise level. signals to control the chopping) the part then takes into account Reference Detect the reversal of the analog input and reference input signals. The AD7730 includes on-chip circuitry to detect if the part The output noise performance outlined in Tables I through IV has a valid reference for conversions or calibrations. If the volt- is for an analog input of 0V and is unaffected by noise on the age between the REF IN(+) and REF IN(–) pins goes below reference. To obtain the same noise performance as shown in 0.3V or either the REF IN(+) or REF IN(–) inputs is open the noise tables over the full input range requires a low noise circuit, the AD7730 detects that it no longer has a valid reference. reference source for the AD7730. If the reference noise in the In this case, the NO REF bit of the Status Register is set to a 1. bandwidth of interest is excessive, it will degrade the performance If the AD7730 is performing normal conversions and the NO of the AD7730. In applications where the excitation voltage for REF bit becomes active, the part places all ones in the Data the bridge transducer on the analog input also drives the refer- Register. Therefore, it is not necessary to continuously monitor ence voltage for the part, the effect of the noise in the excita- the status of the NO REF bit when performing conversions. It is tion voltage will be removed as the application is ratiometric. only necessary to verify its status if the conversion result read Figure 7 shows how the reference voltage can be connected in a from the Data Register is all 1s. ratiometric fashion in a dc-excited bridge application. In this case, the excitation voltage for the AD7730 and the transducer is a dc voltage. The HIREF bit of the Mode Register should be set to 1. Figure 8 meanwhile shows how the reference can be connected in a ratiometric fashion in an ac-excited bridge REV. B –25–

AD7730/AD7730L If the AD7730 is performing either an offset or gain calibration First Stage Filter and the NOREF bit becomes active, the updating of the respec- The first stage filter is a low-pass, sinc3 or (sinx/x)3filter whose tive calibration register is inhibited to avoid loading incorrect primary function is to remove the quantization noise introduced coefficients to this register. If the user is concerned about verify- at the modulator. The cutoff frequency and output rate of this ing that a valid reference is in place every time a calibration is filter is programmed via the SF0 to SF11 bits of the Filter Reg- performed, then the status of the NOREF bit should be checked ister. The frequency response for this first stage filter is shown in at the end of the calibration cycle. Figure 10. The response of this first stage filter is similar to that of an averaging filter but with a sharper roll-off. The output rate SIGMA-DELTA MODULATOR for the filter corresponds with the positioning of the first notch A sigma-delta ADC generally consists of two main blocks, an of the filter’s frequency response. Thus, for the plot of Figure 10, analog modulator and a digital filter. In the case of the AD7730, where the output rate is 600Hz (f = 4.9152 MHz and CLK IN the analog modulator consists of a difference amplifier, an inte- SF = 512), the first notch of the filter is at 600Hz. The notches grator block, a comparator and a feedback DAC as illustrated in of this sinc3filter are repeated at multiples of the first notch. The Figure 9. In operation, the analog signal sample is fed to the filter provides attenuation of better than 100dB at these notches. difference amplifier along with the output of the feedback DAC. Programming a different cutoff frequency via SF0 – SF11 does The difference between these two signals is integrated and fed to not alter the profile of the filter response; it changes the fre- the comparator. The output of the comparator provides the quency of the notches as outlined in the Filter Registers section. input to the feedback DAC so that the system functions as a This response is repeated at either side of the input sampling negative feedback loop that tries to minimize the difference frequency (307 kHz) and at either side of multiples of the input signal. The digital data that represents the analog input voltage sampling frequency. is contained in the duty cycle of the pulse train appearing at the output of the comparator. This duty cycle data can be recovered 0 as a data word using the digital filter. The sampling frequency of –10 the modulator loop is many times higher than the bandwidth of –20 the input signal. The integrator in the modulator shapes the –30 quantization noise (which results from the analog-to-digital –40 conversion) so that the noise is pushed toward one half of the B –50 modulator frequency. The digital filter then bandlimits the re- – d –60 sponse to a frequency significantly lower than one half of the AIN –70 modulator frequency. In this manner, the 1-bit output of the G –80 comparator is translated into a bandlimited, low noise output –90 from the AD7730. –100 –110 ANALOG DIFFERENCE INPUT AMP COMPARATOR –120 0 200 400 600 800 1000 1200 1400 1600 1800 INTEGRATOR DIGITAL FREQUENCY – Hz FILTER Figure 10.Frequency Response of First Stage Filter The first stage filter has two basic modes of operation. The DAC DIGITAL DATA primary mode of operation for weigh-scale applications is chop mode, which is achieved by placing a 1 in the CHP bit of the Figure 9.Sigma-Delta Modulator Block Diagram Filter Register. The part should be operated in this mode when drift and noise rejection are important criteria in the application. DIGITAL FILTERING The alternative mode of operation is the nonchop mode, with Filter Architecture CHP at 0, which would be used when higher throughput rates The output of the modulator feeds directly into the digital filter. are a concern or in applications where the reduced rejection at This digital filter consists of two portions, a first stage filter and the chopping frequency in chop mode is an issue. a second stage filter. The first stage filter is a sinc3, low-pass filter. The cutoff frequency and output rate of this first stage Nonchop Mode filter is programmable. The second stage filter has three distinct With chop mode disabled on the AD7730, the first stage filter modes of operation. In its normal mode, it provides a low-pass continuously processes input data and produces a result at an FIR filter that processes the output of the first stage filter. When output rate determined by the SF word. Operating in nonchop a step change is detected on the analog input, this second stage mode can result in a 20% reduction in noise for a given band- filter enters a second mode where it performs a variable number width, but without the excellent drift and noise rejection ben- of averages for some time after the step change and then the efits which accrue from chopping the part. The output update second stage filter switches back to the FIR filter. The third and first notch of this first stage filter correspond and are deter- option for the second stage filter is that it is completely bypassed mined by the relationship: so the only filtering provided on the AD7730 is the first stage. f 1 The various filter stages and options are discussed in the follow- OutputRate= CLKIN × ing sections. 16 SF whereSF is the decimal equivalent of the data loaded to the SF bits of the Filter Register and f is the master clock frequency. CLK IN REV. B –26–

AD7730/AD7730L Chop Mode 0 With chop mode enabled on the AD7730, the signal processing –10 chain is synchronously chopped at the analog input and at the –20 output of the first stage filter. This means that for each output –30 of the first stage filter to be computed, the full settling time of –40 the filter has to elapse. This results in an output rate from the B –50 filter that is three times lower than for a given SF word than for – d –60 nonchop mode. The output update and first notch of this first AIN –70 stagefilter correspond and are determined by the relationship: G –80 –90 f 1 OutputRate= CLKIN × –100 16 3×SF –110 whereSF is the decimal equivalent of the data loaded to the SF –120 0 10 20 30 40 50 60 70 80 90 100 bits of the Filter Register and fCLK IN is the master clock frequency. FREQUENCY – Hz Second Stage Filter Figure 11.Detailed Full Frequency Response of AD7730 As stated earlier, the second stage filter has three distinct modes (Second Stage Filter as Normal FIR, Chop Enabled) of operation which result in a different overall filter profile for Figure 12 shows the frequency response for the same set of the part. The modes of operation of the second stage filter are conditions as for Figure 11, but in this case the response is discussed in the following sections along with the different filter shown out to 600Hz. This response shows that the attenuation profiles which result. of input frequencies close to 200Hz and 400Hz is significantly Normal FIR Operation less than at other input frequencies. These “peaks” in the fre- The normal mode of operation of the second stage filter is as a quency response are a by-product of the chopping of the input. 22-tap low-pass FIR filter. This second stage filter processes the The plot of Figure 12 is the amplitude for different input fre- output of the first stage filter and the net frequency response of quencies. Note that because the output rate is 200Hz for the the filter is simply a product of the filter response of both filters. conditions under which Figure 12 is plotted, if something ex- The overall filter response of the AD7730 is guaranteed to have isted in the input frequency domain at 200Hz, it would be no overshoot. aliased and appear in the output frequency domain at dc. Figure 11 shows the full frequency response of the AD7730 when 0 the second stage filter is set for normal FIR operation. This –10 response is for chop mode enabled with the decimal equivalent of the word in the SF bits set to 512 and a master clock frequency –20 of 4.9152MHz. The response will scale proportionately with –30 master clock frequency. The response is shown from dc to –40 100Hz. The rejection at 50Hz ±1Hz and 60Hz ± 1Hz is B –50 d better than 88 dB. N – –60 AI –70 The –3 dB frequency for the frequency response of the AD7730 G –80 with the second stage filter set for normal FIR operation and –90 chop mode enabled is determined by the following relationship: –100 f 1 –110 f =0.0395× CLKIN × 3dB 16 3×SF –1200 50 100 150 200 250 300 350 400 450 500 550 600 FREQUENCY – Hz In this case, f = 7.9 Hz and the stopband, where the attenua- 3 dB Figure 12.Expanded Full Frequency Response of AD7730 tion is greater than 64.5 dB, is determined by: (Second Stage Filter as Normal FIR, Chop Enabled) f 1 f =0.14× CLKIN × STOP 16 3×SF In this case, f = 28 Hz. STOP REV. B –27–

AD7730/AD7730L Because of this effect, care should be taken in choosing an out- The –3 dB frequency for the frequency response of the AD7730 put rate that is close to the line frequency in the application. If with the second stage filter set for normal FIR operation and the line frequency is 50 Hz, an output update rate of 50 Hz chop mode enabled, is determined by the following relationship: should not be chosen as it will significantly reduce the AD7730’s line frequency rejection (the 50 Hz will appear as a dc effect f =0.039× fCLKIN × 1 with only 6 dB attenuation). Choosing an output rate of 55 Hz 3dB 16 SF will result in a 6 dB—attenuated aliased frequency of 5 Hz with In this case, f = 7.8 Hz and the stop band, where the attentua- only a further 25 dB attenuation based on the filter profile. This 3 dB tion is greater than 64.5 dB, is determined by: number is based on the filter roll-off and Figure 11 can be used as a reference by dividing the frequency scale by a factor of 4. f 1 Choosing 57 Hz as the output rate will give better than 90 dB f =0.14× CLKIN × STOP 16 SF attenuation of the aliased line frequency which appears as a 7 Hz signal. Similarly, multiples of the line frequency should be In this case, f = 28 Hz. 3 dB avoided as the output rate because harmonics of the line fre- Figure 14 shows the frequency response for the same set of quency will not be fully attenuated. The programmability of the conditions as for Figure 13, but in this case the response is AD7730’s output rate should allow the user to readily choose an shown out to 600Hz. This plot is comparable to that of Figure output rate that overcomes this issue. An alternative is to use 12. The most notable difference is the absence of the peaks in the part in nonchop mode. the response at 200Hz and 400Hz. As a result, interference at Figure 13 shows the frequency response for the AD7730 with these frequencies will be effectively eliminated before being the second stage filter set for normal FIR operation, chop mode aliased back to dc. disabled, the decimal equivalent of the word in the SF bits set to 1536 and a master clock frequency of 4.9152MHz. The response 0 is analogous to that of Figure 11, with the three-times-larger SF –10 word producing the same 200Hz output rate. Once again, the –20 response will scale proportionally with master clock frequency. –30 The response is shown from dc to 100Hz. The rejection at –40 50Hz ± 1Hz, and 60Hz ± 1Hz is better than 88 dB. B –50 d – –60 0 N AI –70 –10 G –80 –20 –90 –30 –100 –40 –110 dB –50 –120 – –60 0 50 100 150 200 250 300 350 400 450 500 550 600 N FREQUENCY – Hz AI –70 G Figure 14.Expanded Full Frequency Response of AD7730 –80 (Second Stage Filter as Normal FIR, Chop Disabled) –90 –100 –110 –120 0 10 20 30 40 50 60 70 80 90 100 FREQUENCY – Hz Figure 13.Detailed Full Frequency Response of AD7730 (Second Stage Filter as Normal FIR, Chop Disabled) REV. B –28–

AD7730/AD7730L FASTStep Mode InFASTStepmode, the part has settled to the new value much The second mode of operation of the second stage filter is in faster. With chopping enabled, the FASTStepmode settles to FASTStepmode which enables it to respond rapidly to step its value in two outputs, while the normal mode settling takes inputs. This FASTStepmode is enabled by placing a 1 in the 23 outputs. Between the second and 23rd output, the FASTStep FAST bit of the Filter Register. If the FAST bit is 0, the part mode produces a settled result, but with additional noise com- continues to process step inputs with the normal FIR filter as pared to the specified noise level for its operating conditions. It the second stage filter. With FASTStepmode enabled, the starts at a noise level that is comparable to SKIP mode and as second stage filter will continue to process steady state inputs the averaging increases ends up at the specified noise level. The with the filter in its normal FIR mode of operation. However, complete settling time to where the part is back within the the part is continuously monitoring the output of the first stage specified noise number is the same for FASTStepmode and filter and comparing it with the second previous output. If the normal mode. As can be seen from Figure 13, the FASTStep difference between these two outputs is greater than a predeter- mode gives a much earlier indication of where the output chan- mined threshold (1% of full scale), the second stage filter switches nel is going and its new value. This feature is very useful in to a simple moving average computation. When the step change weighing applications to give a much earlier indication of the is detected, the STDY bit of the Status Register goes to 1 and weight, or in an application scanning multiple channels where will not return to 0 until the FIR filter is back in the processing the user does not have to wait the full settling time to see if a loop. channel has changed value. The initial number of averages in the moving average computa- SKIP Mode tion is either 2 (chop enabled) or 1 (chop disabled). The num- The final method for operating the second stage filter is where it ber of averages will be held at this value as long as the threshold is bypassed completely. This is achieved by placing a 1 in the is exceeded. Once the threshold is no longer exceeded (the step SKIP bit of the Filter Register. When SKIP mode is enabled, it on the analog input has settled), the number of outputs used to means that the only filtering on the part is the first stage, sinc3, compute the moving average output is increased. The first and filter. As a result, the complete filter profile is as described ear- second outputs from the first stage filter where the threshold is lier for the first stage filter and illustrated in Figure 10. no longer exceeded is computed as an average by two, then four In SKIP mode, because there is much less processing of the data outputs with an average of four, eight outputs with an average of to derive each individual output, the normal mode settling time eight, and six outputs with an average of 16. At this time, the for the part is shorter. As a consequence of the lesser filtering, second stage filter reverts back to its normal FIR mode of opera- however, the output noise from the part will be significantly tion. When the second stage filter reverts back to the normal FIR, higher for a given SF word. For example with a 20 mV, an SF theSTDY bit of the Status Register goes to 0. word of 1536 and CHP = 0, the output rms noise increases Figure 15 shows the different responses to a step input with from 80 nV to 200 nV. With a 10 mV input range, an SF word FASTStep mode enabled and disabled. The vertical axis shows of 1024 and CHP = 1, the output rms noise goes from 60 nV to the code value returned by the AD7730 and indicates the set- 200 nV. tling of the output to the input step change. The horizontal axis With chopping disabled and SKIP mode enabled, each output shows the number of outputs it takes for that settling to occur. from the AD7730 is a valid result in itself. However, with chop- The positive input step change occurs at the fifth output. In ping enabled and SKIP mode enabled, the outputs from the FASTStepmode, the output has settled to the final value by the AD7730 must be handled in pairs as each successive output is eighth output. In normal mode, the output has not reached from reverse chopping polarities. close to its final value until after the 25th output. CALIBRATION 20000000 The AD7730 provides a number of calibration options which can be programmed via the MD2, MD1 and MD0 bits of the Mode Register. The different calibration options are outlined in 15000000 the Mode Register and Calibration Operations sections. A cali- bration cycle may be initiated at any time by writing to these bits of the Mode Register. Calibration on the AD7730 removes ODE 10000000 offset and gain errors from the device. C The AD7730 gives the user access to the on-chip calibration registers allowing the microprocessor to read the device’s cali- 5000000 bration coefficients and also to write its own calibration coeffi- cients to the part from prestored values in E2PROM. This gives the microprocessor much greater control over the AD7730’s 0 calibration procedure. It also means that the user can verify that 0 5 10 15 20 25 the device has performed its calibration correctly by comparing NUMBER OF OUTPUTS the coefficients after calibration with prestored values in Figure 15.Step Response for FASTStepand Normal E2PROM. The values in these calibration registers are 24 bits Operation wide. In addition, the span and offset for the part can be adjusted by the user. REV. B –29–

AD7730/AD7730L Internally in the AD7730, the coefficients are normalized before simply performed a zero-scale calibration and updated the Off- being used to scale the words coming out of the digital filter. set Calibration Register for the selected channel. The user must The offset calibration register contains a value which, when write either 0, 0, 1 or 0, 1, 0 to the MD2, MD1, MD0 bits of the normalized, is subtracted from all conversion results. The gain Mode Register to initiate a conversion. If RDY is low before (or calibration register contains a value which, when normalized, is goes low during) the calibration command write to the Mode multiplied by all conversion results. The offset calibration coeffi- Register, it may take up to one modulator cycle (MCLKIN/32) cient is subtracted from the result prior to the multiplication by beforeRDY goes high to indicate that calibration is in progress. the gain coefficient. Therefore,RDY should be ignored for up to one modulator cycle after the last bit of the calibration command is written to The AD7730 offers self-calibration or system calibration facili- the Mode Register. ties. For full calibration to occur on the selected channel, the on- chip microcontroller must record the modulator output for two For bipolar input ranges in the internal zero-scale calibrating different input conditions. These are “zero-scale” and “full- mode, the sequence is very similar to that just outlined. In this scale” points. These points are derived by performing a conver- case, the zero-scale point is exactly the same as above but since sion on the different input voltages provided to the input of the the part is configured for bipolar operation, the output code for modulator during calibration. The result of the “zero-scale” zero differential input is 800000 Hex in 24-bit mode. calibration conversion is stored in the Offset Calibration Regis- The internal zero-scale calibration needs to be performed as ter for the appropriate channel. The result of the “full-scale” one part of a two part full calibration. However, once a full calibration conversion is stored in the Gain Calibration Register calibration has been performed, additional internal zero-scale for the appropriate channel. With these readings, the microcon- calibrations can be performed by themselves to adjust the troller can calculate the offset and the gain slope for the input to part’szero-scale point only. When performing a two step full output transfer function of the converter. Internally, the part calibration care should be taken as to the sequence in which the works with 33 bits of resolution to determine its conversion two steps are performed. If the internal zero-scale calibration is result of either 16 bits or 24 bits. one part of a full self-calibration, then it should take place after The sequence in which the zero-scale and full-scale calibration an internal full-scale calibration. If it takes place in association occurs depends upon the type of full-scale calibration being with a system full-scale calibration, then this internal zero-scale performed. The internal full-scale calibration is a two-step cali- calibration should be performed first. bration that alters the value of the Offset Calibration Register. Internal Full-Scale Calibration Thus, the user must perform a zero-scale calibration (either An internal full-scale calibration is initiated on the AD7730 by internal or system) after an internal full-scale calibration to correct writing the appropriate values (1, 0, 1) to the MD2, MD1 and the Offset Calibration Register contents. When using system MD0 bits of the Mode Register. In this calibration mode, the full-scale calibration, it is recommended that the zero-scale full-scale point used in determining the calibration coefficients is calibration (either internal or system) is performed first. with an internally-generated full-scale voltage. This full-scale Since the calibration coefficients are derived by performing a voltage is derived from the reference voltage for the AD7730 conversion on the input voltage provided, the accuracy of the and the PGA is set for the selected gain (as per the RN1, RN0 calibration can only be as good as the noise level the part pro- bits in the Mode Register) for this internal full-scale calibration vides in normal mode. To optimize the calibration accuracy, it conversion. is recommended to calibrate the part at its lowest output rate In order to meet the post-calibration numbers quoted in the where the noise level is lowest. The coefficients generated at any specifications, it is recommended that internal full-scale calibra- output update rate will be valid for all selected output update tions be performed on the 80mV range. This applies even if the rates. This scheme of calibrating at the lowest output update subsequent operating mode is on the 10mV, 20mV or 40mV rate does mean that the duration of calibration is longer. input ranges. Internal Zero-Scale Calibration The internal full-scale calibration is a two-step sequence that An internal zero-scale calibration is initiated on the AD7730 by runs when an internal full-scale calibration command is written writing the appropriate values (1, 0, 0) to the MD2, MD1 and to the AD7730. One part of the calibration is a zero-scale cali- MD0 bits of the Mode Register. In this calibration mode with a bration and as a result, the contents of the Offset Calibration unipolar input range, the zero-scale point used in determining Register are altered during this Internal Full-Scale Calibration. the calibration coefficients is with the inputs of the differential The user must therefore perform a zero-scale calibration (either pair internally shorted on the part (i.e., AIN(+) = AIN(–) = internal or system) AFTER the internal full-scale calibration. Externally-Applied AIN(–) voltage). The PGA is set for the This zero-scale calibration should be performed at the operating input selected gain (as per the RN1, RN0 bits in the Mode Register) range. This means that internal full-scale calibrations cannot be for this internal zero-scale calibration conversion. performed in isolation. The calibration is performed with dc excitation regardless of the The calibration is performed with dc excitation regardless of the status of the ac bit. The duration time of the calibration de- status of the ac bit. The duration time of the calibration de- pends upon the CHP bit of the Filter Register. With CHP = 1, pends upon the CHP bit of the Filter Register. With CHP = 1, the duration is 22 × 1/Output Rate; with CHP = 0, the duration the duration is 44 × 1/Output Rate; with CHP = 0, the duration is 24 × 1/Output Rate. At this time the MD2, MD1 and MD0 is 48 × 1/Output Rate. At this time the MD2, MD1 and MD0 bits in the Mode Register return to 0, 0, 0 (Sync or Idle Mode bits in the Mode Register return to 0, 0, 0 (Sync or Idle Mode for the AD7730). The RDY line goes high when calibration is for the AD7730). The RDY line goes high when calibration is initiated and returns low when calibration is complete. Note initiated and returns low when calibration is complete. Note that the part has not performed a conversion at this time; it has that the part has not performed a conversion at this time. The REV. B –30–

AD7730/AD7730L user must write either 0, 0, 1 or 0, 1, 0 to the MD2, MD1, System Full-Scale Calibration MD0 bits of the Mode Register to initiate a conversion. If A system full-scale calibration is initiated on the AD7730 by RDY is low before (or goes low during) the calibration com- writing the appropriate values (1, 1, 1) to the MD2, MD1 and mand write to the Mode Register, it may take up to one modulator MD0 bits of the Mode Register. System full-scale calibration is cycle (MCLKIN/32) before RDY goes high to indicate that performed using the system's positive full-scale voltage. This calibration is in progress. Therefore, RDY should be ignored for full-scale voltage must be set up before the calibration is initi- up to one modulator cycle after the last bit of the calibration ated, and it must remain stable throughout the calibration step. command is written to the Mode Register. The system full-scale calibration is performed at the selected gain (as per the RN1, RN0 bits in the Mode Register). System Zero-Scale Calibration System calibration allows the AD7730 to compensate for system The calibration is performed with either ac or dc excitation, gain and offset errors as well as its own internal errors. System depending on the status of the ac bit. The duration time of the calibration performs the same slope factor calculations as self- calibration depends upon the CHP bit of the Filter Register. calibration, but uses voltage values presented by the system to With CHP = 1, the duration is 22 × 1/Output Rate; with CHP = the AIN inputs for the zero- and full-scale points. 0, the duration is 24 × 1/Output Rate. At this time the MD2, MD1 and MD0 bits in the Mode Register return to 0, 0, 0 A system zero-scale calibration is initiated on the AD7730 by (Sync or Idle Mode for the AD7730). The RDY line goes high writing the appropriate values (1, 1, 0) to the MD2, MD1 and when calibration is initiated, and returns low when calibration is MD0 bits of the Mode Register. In this calibration mode, with a complete. Note that the part has not performed a conversion at unipolar input range, the zero-scale point used in determin- this time; it has simply performed a full-scale calibration and ing the calibration coefficients is the bottom end of the trans- updated the Gain Calibration Register for the selected channel. fer function. The system’s zero-scale point is applied to the AD7730’s AIN input before the calibration step and this voltage The user must write either 0, 0, 1 or 0, 1, 0 to the MD2, MD1, must remain stable for the duration of the system zero-scale MD0 bits of the Mode Register to initiate a conversion. If RDY calibration. The PGA is set for the selected gain (as per the is low before (or goes low during) the calibration command RN1, RN0 bits in the Mode Register) for this system zero-scale write to the Mode Register, it may take up to one modulator calibration conversion. The allowable range for the system zero- cycle (MCLKIN/32) before RDY goes high to indicate that scale voltage is discussed in the Span and Offsets Section. calibration is in progress. Therefore, RDY should be ignored for up to one modulator cycle after the last bit of the calibration The calibration is performed with either ac or dc excitation, command is written to the Mode Register. depending on the status of the AC bit. The duration time of the calibration depends upon the CHP bit of the Filter Register. The system full-scale calibration needs to be performed as one With CHP = 1, the duration is 22 × 1/Output Rate; with part of a two part full calibration. Once a full calibration has CHP = 0, the duration is 24 × 1/Output Rate. At this time the been performed, however, additional system full-scale calibra- MD2, MD1 and MD0 bits in the Mode Register return to tions can be performed by themselves to adjust the part's gain 0, 0, 0 (Sync or Idle Mode for the AD7730). The RDY line calibration point only. When performing a two-step full calibra- goes high when calibration is initiated and returns low when tion care should be taken as to the sequence in which the two calibration is complete. Note that the part has not performed a steps are performed. A system full-scale calibration should not conversion at this time; it has simply performed a zero-scale be carried out unless the part contains valid zero-scale coeffi- calibration and updated the Offset Calibration Register for the cients. Therefore, an internal zero-scale calibration or a system selected channel. The user must write either 0, 0, 1 or 0, 1, 0 to zero-scale calibration must be performed before the system full- the MD2, MD1, MD0 bits of the Mode Register to initiate a scale calibration when a full two-step calibration operation is conversion. If RDY is low before (or goes low during) the cali- being performed. bration command write to the Mode Register, it may take up to Span and Offset Limits one modulator cycle (MCLKIN/32) before RDY goes high to Whenever a system calibration mode is used, there are limits indicate that calibration is in progress. Therefore, RDY should on the amount of offset and span which can be accommodated. be ignored for up to one modulator cycle after the last bit of the The overriding requirement in determining the amount of offset calibration command is written to the Mode Register. and gain which can be accommodated by the part is the require- For bipolar input ranges in the system zero-scale calibrating ment that the positive full-scale calibration limit is ≤1.05× FS, mode, the sequence is very similar to that just outlined. In this where FS is 10mV, 20 mV, 40mV or 80mV depending on the case, the zero-scale point is the midpoint of the AD7730’s RN1, RN0 bits in the Mode Register. This allows the input transfer function. range to go 5% above the nominal range. The built-in head- room in the AD7730’s analog modulator ensures that the part The system zero-scale calibration needs to be performed as one will still operate correctly with a positive full-scale voltage that is part of a two part full calibration. However, once a full calibra- 5% beyond the nominal. tion has been performed, additional system zero-scale calibra- tions can be performed by themselves to adjust the part’s zero-scale point only. When performing a two-step full calibra- tion care should be taken as to the sequence in which the two steps are performed. If the system zero-scale calibration is one part of a full system calibration, then it should take place before a system full-scale calibration. If it takes place in association with an internal full-scale calibration, then this system zero-scale calibration should be performed after the full-scale calibration. REV. B –31–

AD7730/AD7730L The range of input span in both the unipolar and bipolar modes The power dissipation and temperature drift of the AD7730 are has a minimum value of 0.8×FS and a maximum value of low and no warm-up time is required before the initial calibra- 2.1×FS. However, the span (which is the difference between tion is performed. If, however, an external reference is being the bottom of the AD7730’s input range and the top of its input used, this reference must have stabilized before calibration is range) has to take into account the limitation on the positive initiated. Similarly, if the clock source for the part is generated full-scale voltage. The amount of offset which can be accommo- from a crystal or resonator across the MCLK pins, the start-up dated depends on whether the unipolar or bipolar mode is being time for the oscillator circuit should elapse before a calibration used. Once again, the offset has to take into account the limita- is initiated on the part (see below). tion on the positive full-scale voltage. In unipolar mode, there is Drift Considerations considerable flexibility in handling negative (with respect to The AD7730 uses chopper stabilization techniques to minimize AIN(–)) offsets. In both unipolar and bipolar modes, the range input offset drift. Charge injection in the analog multiplexer and of positive offsets that can be handled by the part depends on dc leakage currents at the analog input are the primary sources the selected span. Therefore, in determining the limits for sys- of offset voltage drift in the part. The dc input leakage current is tem zero-scale and full-scale calibrations, the user has to ensure essentially independent of the selected gain. Gain drift within that the offset range plus the span range does exceed 1.05×FS. the converter depends primarily upon the temperature tracking This is best illustrated by looking at a few examples. of the internal capacitors. It is not affected by leakage currents. If the part is used in unipolar mode with a required span of When operating the part in CHOP mode (CHP = 1), the signal 0.8×FS, the offset range the system calibration can handle is chain including the first-stage filter is chopped. This chopping from –1.05× FS to +0.25× FS. If the part is used in unipolar reduces the overall offset drift to 5 nV/°C. Integral and differen- mode with a required span of FS, the offset range the system cali- tial linearity errors are not significantly affected by temperature bration can handle is from –1.05× FS to +0.05× FS. Similarly, if changes. the part is used in unipolar mode and required to remove an offset of 0.2×FS, the span range the system calibration can Care must also be taken with external drift effects in order to handle is 0.85×FS. achieve optimum drift performance. The user has to be espe- cially careful to avoid, as much as possible, thermocouple effects If the part is used in bipolar mode with a required span of from junctions of different materials. Devices should not be ±0.4×FS, the offset range the system calibration can handle is placed in sockets when evaluating temperature drift, there from –0.65×FS to +0.65×FS. If the part is used in bipolar should be no links in series with the analog inputs and care mode with a required span of ±FS, the offset range the system must be taken as to how the input voltage is applied to the input calibration can handle is from –0.05× FS to +0.05 × FS. Simi- pins. The true offset drift of the AD7730 itself can be evaluated larly, if the part is used in bipolar mode and required to remove by performing temperature drift testing of the part with the an offset of ±0.2× FS, the span range the system calibration can AIN(–)/AIN(–) input channel arrangement (i.e., internal shorted handle is ±0.85× FS. Figure 16 summarizes the span and offset input, test mode). ranges. USING THE AD7730 1.05(cid:5) FS. UPPER LIMIT. AD7730’s INPUT Clocking and Oscillator Circuit VOLTAGE CANNOT EXCEED THIS The AD7730 requires a master clock input, which may be an GAIN CALIBRATIONS EXPAND OR external CMOS compatible clock signal applied to the MCLKIN CONTRACT THE AD7730’s INPUT pin with the MCLKOUT pin left unconnected. Alternatively, a AD7730 RANGE INPUT RANGE crystal or ceramic resonator of the correct frequency can be (0.8(cid:5) FS TO 2.1 (cid:5) FS) 0V DIFFERENTIAL connected between MCLKIN and MCLKOUT in which case NOMINAL ZERO-SCALE POINT the clock circuit will function as an oscillator, providing the clock source for the part. The input sampling frequency, the modulator sampling frequency, the –3dB frequency, output ZERO-SCALE CALIBRATIONS update rate and calibration time are all directly related to the MOVE INPUT RANGE UP OR DOWN master clock frequency, f . Reducing the master clock –1.05 (cid:5) FS. LVOOWLTEARG LEI MCIATN. ANDO7T7 E30X’Cs EINEPDU TTHIS frequency by a factor of tCwLoK wINill halve the above frequencies and Figure 16.Span and Offset Limits update rate and double the calibration time. Power-Up and Calibration The crystal or ceramic resonator is connected across the MCLK On power-up, the AD7730 performs an internal reset which sets IN and MCLK OUT pins, as per Figure 17. Capacitors C1 and the contents of the internal registers to a known state. There are C2 may or may not be required and may vary in value depend- default values loaded to all registers after a power-on or reset. ing on the crystal/resonator manufacturer's recommendations. The default values contain nominal calibration coefficients for The AD7730 has a capacitance of 5 pF on MCLK IN and 13pF the calibration registers. To ensure correct calibration for the on MCLK OUT so, in most cases, capacitors C1 and C2 will device, a calibration routine should be performed after power-up. not be required to get the crystal/resonator operating at its cor- rect frequency. REV. B –32–

AD7730/AD7730L Reset Input MCLK IN TheRESET input on the AD7730 resets all the logic, the digital C1 CRYSTAL OR filter and the analog modulator while all on-chip registers are CREERSOAMNAICTOR AD7730 reset to their default state. RDY is driven high and the AD7730 ignores all communications to any of its registers while the C2 MCLK OUT RESET input is low. When the RESET input returns high, the AD7730 starts to process data and RDY will return low after the filter has settled indicating a valid new word in the data Figure 17.Crystal/Resonator Connections register. However, the AD7730 operates with its default setup The on-chip oscillator circuit also has a start-up time associated conditions after a RESET and it is generally necessary to set up all with it before it has attained its correct frequency and correct registers and carry out a calibration after a RESET command. voltage levels. The typical start-up time for the circuit is 6ms, The AD7730’s on-chip oscillator circuit continues to function with a DV of +5V and 8ms with a DV of +3V. DD DD even when the RESET input is low. The master clock signal The AD7730’s master clock appears on the MCLK OUT pin of continues to be available on the MCLK OUT pin. Therefore, in the device. The maximum recommended load on this pin is one applications wherethe system clock is provided by the AD7730’s CMOS load. When using a crystal or ceramic resonator to gen- clock, the AD7730 produces an uninterrupted master clock erate the AD7730’s clock, it may be desirable to then use this duringRESET commands. clock as the clock source for the system. In this case, it is recom- Standby Mode mended that the MCLK OUT signal is buffered with a CMOS TheSTANDBY input on the AD7730 allows the user to place buffer before being applied to the rest of the circuit. the part in a power-down mode when it is not required to pro- System Synchronization vide conversion results. The part can also be placed in its TheSYNC input allows the user to reset the modulator and standby mode by writing 0, 1, 1 to the MD2, MD1, MD0 bits digital filter without affecting any of the setup conditions on the of the Mode Register. The AD7730 retains the contents of all its part. This allows the user to start gathering samples of the ana- on-chip registers (including the Data Register) while in standby log input from a known point in time, i.e., the rising edge of mode. Data can still be read from the part in Standby Mode. SYNC. The STBY bit of the Status Register indicates whether the part If multiple AD7730s are operated from a common master clock, is in standby or normal operating mode. When the STANDBY they can be synchronized to update their output registers simul- pin is taken high, the part returns to operating as it had been taneously. A falling edge on the SYNC input resets the digital prior to the STANDBY pin going low. filter and analog modulator and places the AD7730 into a con- TheSTANDBY input (or 0, 1, 1 in the MD2, MD1, MD0 bits) sistent, known state. While the SYNC input is low, the AD7730 does not affect the digital interface. It does, however, set the will be maintained in this state. On the rising edge of SYNC, RDY bit and pin high and also sets the STDY bit high. When the modulator and filter are taken out of this reset state and on STANDBY goes high again, RDY and STDY remain high until the next clock edge the part starts to gather input samples again. set low by a conversion or calibration. In a system using multiple AD7730s, a common signal to their SYNC inputs will synchronize their operation. This would nor- Placing the part in standby mode, reduces the total current to 10μA typical when the part is operated from an external master mally be done after each AD7730 has performed its own cali- clock provided this master clock is stopped. If the external clock bration or has had calibration coefficients loaded to it. The continues to run in standby mode, the standby current increases output updates will then be synchronized with the maximum to 400μA typical. If a crystal or ceramic resonator is used as the possible difference between the output updates of the individual clock source, then the total current in standby mode is 400μA AD7730s being one MCLK IN cycle. typical. This is because the on-chip oscillator circuit continues Single-Shot Conversions to run when the part is in its standby mode. This is important in TheSYNC input can also be used as a start convert command applications where the system clock is provided by the AD7730’s allowing the AD7730 to be operated in a conventional converter clock, so that the AD7730 produces an uninterrupted master fashion. In this mode, the rising edge of SYNC starts conversion clock even when it is in its standby mode. and the falling edge of RDY indicates when conversion is com- Digital Outputs plete. The disadvantage of this scheme is that the settling time The AD7730 has two digital output pins, D0 and D1. When the of the filter has to be taken into account for every data register DEN bit of the Mode Register is set to 1, these digital outputs update. assume the logic status of bits D0 and D1 of the Mode Register. Writing 0, 1, 0 to the MD2, MD1, MD0 bits of the Mode regis- It gives the user access to two digital port pins which can be ter has the same effect. This initiates a single conversion on the programmed over the normal serial interface of the AD7730. AD7730 with the part returning to idle mode at the end of The two outputs obtain their supply voltage from AV , DD conversion. Once again, the full settling-time of the filter has to thus the outputs operate to 5 V levels even in cases where elapse before the Data Register is updated. DV = +3 V. DD REV. B –33–

AD7730/AD7730L POWER SUPPLIES and analog signals. Traces on opposite sides of the board should There is no specific power sequence required for the AD7730, run at right angles to each other. This will reduce the effects of either the AV or the DV supply can come up first. While feedthrough through the board. A microstrip technique is by far DD DD the latch-up performance of the AD7730 is very good, it is the best but is not always possible with a double-sided board. In important that power is applied to the AD7730 before signals at this technique, the component side of the board is dedicated to REFIN, AIN or the logic input pins in order to avoid latch-up ground planes while signals are placed on the solder side. caused by excessive current. If this is not possible, the current Good decoupling is important when using high resolution that flows in any of these pins should be limited to less than 30 ADCs. All analog supplies should be decoupled with 10μF mA per pin and less than 100 mA cumulative. If separate sup- tantalum in parallel with 0.1μF ceramic capacitors to AGND. plies are used for the AD7730 and the system digital circuitry, To achieve the best from these decoupling components, they the AD7730 should be powered up first. If it is not possible to have to be placed as close as possible to the device, ideally right guarantee this, current limiting resistors should be placed in up against the device. All logic chips should be decoupled with series with the logic inputs to again limit the current to less than 0.1μF disc ceramic capacitors to DGND. In systems where a 30 mA per pin and less than 100 mA total. common supply voltage is used to drive both the AV and DD Grounding and Layout DV of the AD7730, it is recommended that the system’s DD Since the analog inputs and reference input are differential, AV supply is used. This supply should have the recom- DD most of the voltages in the analog modulator are common-mode mended analog supply decoupling capacitors between the AV DD voltages. The excellent common-mode rejection of the part will pin of the AD7730 and AGND and the recommended digital remove common-mode noise on these inputs. The analog and supply decoupling capacitor between the DV pin of the DD digital supplies to the AD7730 are independent and separately AD7730 and DGND. pinned out to minimize coupling between the analog and digital Evaluating the AD7730 Performance sections of the device. The digital filter will provide rejection of A recommended layout for the AD7730 is outlined in the evalu- broadband noise on the power supplies, except at integer mul- ation board for the AD7730. The evaluation board package tiples of the modulator sampling frequency or multiples of the includes a fully assembled and tested evaluation board, docu- chop frequency in chop mode. The digital filter also removes mentation, software for controlling the board over the printer noise from the analog and reference inputs provided those noise port of a PC and software for analyzing the AD7730’s perfor- sources do not saturate the analog modulator. As a result, the mance on the PC. The evaluation board order number is AD7730 is more immune to noise interference than a conven- EVAL-AD7730EB. tional high resolution converter. However, because the resolu- tion of the AD7730 is so high and the noise levels from the Noise levels in the signals applied to the AD7730 may also AD7730 so low, care must be taken with regard to grounding affect performance of the part. The AD7730 allows two tech- and layout. niques for evaluating the true performance of the part, indepen- dent of the analog input signal. These schemes should be used The printed circuit board that houses the AD7730 should be after a calibration has been performed on the part. designed so the analog and digital sections are separated and confined to certain areas of the board. This facilitates the use of The first method is to select the AIN1(–)/AIN1(–) input chan- ground planes that can be easily separated. A minimum etch nel arrangement. In this case, the differential inputs to the technique is generally best for ground planes as it gives the best AD7730 are internally shorted together to provide a zero differ- shielding. Digital and analog ground planes should only be ential voltage for the analog modulator. External to the device, joined in one place. If the AD7730 is the only device requiring the AIN1(–) input should be connected to a voltage which is an AGND to DGND connection, the ground planes should within the allowable common-mode range of the part. be connected at the AGND and DGND pins of the AD7730. If The second scheme is to evaluate the part with a voltage near the AD7730 is in a system where multiple devices require AGND input full scale. This can be achieved by again using input pair to DGND connections, the connection should still be made at AIN1(–), but by adding a differential voltage via the TARE one point only, a star ground point that should be established as DAC. This allows the user to evaluate noise performance with a closely as possible to the AD7730. near full-scale voltage. Avoid running digital lines under the device as these will couple The software in the evaluation board package allows the user to noise onto the die. The analog ground plane should be allowed look at the noise performance in terms of counts, bits and nV. to run under the AD7730 to avoid noise coupling. The power Once the user has established that the noise performance of the supply lines to the AD7730 should use as large a trace as pos- part is satisfactory in this mode, an external input voltage can sible to provide low impedance paths and reduce the effects of then be applied to the device incorporating more of the signal glitches on the power supply line. Fast switching signals such as chain. clocks should be shielded with digital ground to avoid radiating noise to other sections of the board and clock signals should never be run near the analog inputs. Avoid crossover of digital REV. B –34–

AD7730/AD7730L SERIAL INTERFACE data transfer when the POL input is high and should idle low The AD7730’s programmable functions are controlled via a set between data transfers when the POL input is low. For POL = 1, of on-chip registers. Access to these registers is via the part’s the first falling edge of SCLK clocks data from the microcontrol- serial interface. After power-on or RESET, the device expects a ler onto the DIN line of the AD7730. It is then clocked into the write to its Communications Register. The data written to this input shift register on the next rising edge of SCLK. For POL = 0, register determines whether the next operation to the part is a the first clock edge that clocks data from the microcontroller read or a write operation and also determines to which register onto the DIN line of the AD7730 is a rising edge. It is then this read or write operation occurs. Therefore, write access to clocked into the input shift register on the next falling edge of one of the control registers on the part starts with a write opera- SCLK. tion to the Communications Register followed by a write to the In other microcontroller applications which require a decoding selected register. Reading from the part’s on-chip registers can of the AD7730, CS can be generated from a port line. In this take the form of either a single or continuous read. A single read case,CS would go low well in advance of the first falling edge of from a register consists of a write to the Communications Regis- SCLK (POL = 1) or the first rising edge of SCLK (POL = 0). ter (with RW1 = 0 and RW0 = 1) followed by the read from the Clocking of each bit of data is as just described. specified register. To perform continuous reads from a register, In DSP applications, the SCLK is generally a continuous clock. write to the Communications Register (with RW1 = 1 and In these applications, the CS input for the AD7730 is generated RW0 = 0) to place the part in continuous read mode. The speci- from a frame synchronization signal from the DSP. For proces- fied register can then be read from continuously until a write sors with the rising edge of SCLK as the active edge, the POL operation to the Communications Register (with RW1 = 1 and input should be tied high. For processors with the falling edge of RW0 = 1) which takes the part out of continuous read mode. SCLK as the active edge, the POL input should be tied low. In When operating in continuous read mode, the part is continu- these applications, the first edge after CS goes low is the active ously monitoring its DIN line. The DIN line should therefore edge. The MSB of the data to be shifted into the AD7730 must be permanently low to allow the part to stay in continuous read be set up prior to this first active edge. mode. Figure 5 and Figure 6, shown previously, indicate the correct flow diagrams when reading and writing from the Read Operation AD7730’s registers. The reading of data from the part is from an output shift regis- The AD7730’s serial interface consists of five signals, CS, ter. On initiation of a read operation, data is transferred from SCLK, DIN, DOUT and RDY. The DIN line is used for the specified register to the output shift register. This is a paral- transferring data into the on-chip registers while the DOUT line lel shift and is transparent to the user. Figure 19 shows a timing is used for accessing data from the on-chip registers. SCLK is diagram for a read operation from the output shift register of the the serial clock input for the device and all data transfers (either AD7730. With the POL input at a logic high, the data is clocked on DIN or DOUT) take place with respect to this SCLK signal. out of the output shift register on the falling edge of SCLK. With the POL input at a logic low, the data is clocked out of the Write Operation output shift register on the rising edge of SCLK. The transfer of data into the part is to an input shift register. On Figure 19 also shows the CS input being used to decode the completion of a write operation, data is transferred to the speci- read operation to the AD7730. However, this CS input can be fied register. This internal transfer will not take place until the used in a number of different ways. It is possible to operate the correct number of bits for the specified register have been part in three-wire mode where the CS input is permanently tied loaded to the input shift register. For example, the transfer of low. In this case, the SCLK line should idle high between data data from the input shift register takes place after eight serial transfer when the POL input is high, and should idle low be- clock cycles for a DAC Register write, while the transfer of data tween data transfers when the POL input is low. For POL = 1, from the input shift register takes place after 24 serial clock the first falling edge of SCLK clocks data from the output shift cycles when writing to the Filter Register. Figure 18 shows a register onto the DOUT line of the AD7730. It is then clocked timing diagram for a write operation to the input shift register of into the microcontroller on the next rising edge of SCLK. For the AD7730. With the POL input at a logic high, the data is POL = 0, the first clock edge that clocks data from the AD7730 latched into the input shift register on the rising edge of SCLK. onto the DOUT line is a rising edge. It is then clocked into the With the POL input at a logic low, the data is latched into the microcontroller on the next falling edge of SCLK. input shift register on the falling edge of SCLK. Figure 18 also shows the CS input being used to decode the In other microcontroller applications which require a decoding write operation to the AD7730. However, this CS input can be of the AD7730, CS can be generated from a port line. In this case,CS would go low well in advance of the first falling edge of used in a number of different ways. It is possible to operate the part in three-wire mode where the CS input is tied low perma- SCLK (POL = 1) or the first rising edge of SCLK (POL = 0). Clocking of each bit of data is as just described. nently. In this case, the SCLK line should idle high between REV. B –35–

AD7730/AD7730L In DSP applications, the SCLK is generally a continuous clock. TheRDY line is used as a status signal to indicate when data is In these applications, the CS input for the AD7730 is generated ready to be read from the AD7730’s data register. RDY goes from a frame synchronization signal from the DSP. In these low when a new data word is available in the data register. It is applications, the first edge after CS goes low is the active edge. reset high when a read operation from the data register is com- The MSB of the data to be shifted into the DSP must be set up plete. It also goes high prior to the updating of the data register prior to this first active edge. Unlike microcontroller applica- to indicate when a read from the data register should not be tions, the DSP does not provide a clock edge to clock the MSB initiated. This is to ensure that the transfer of data from the data from the AD7730. In this case, the CS of the AD7730 places register to the output shift register does not occur while the data the MSB on the DOUT line. For processors with the rising edge register is being updated. It is possible to read the same data of SCLK as the active edge, the POL input should be tied high. twice from the output register even though the RDY line returns In this case, the DSP takes data on the rising edge. If CS goes high after the first read operation. Care must be taken, however, low while SCLK is low, the MSB is clocked out on the DOUT to ensure that the read operations are not initiated as the next line from the CS. Subsequent data bits are clocked from the output update is about to take place. falling edge of SCLK. For processors with the falling edge of For systems with a single data line, the DIN and DOUT lines SCLK as the active edge, the POL input should be tied low. In on the AD7730 can be connected together, but care must be this case, the DSP takes data on the falling edge. If CS goes low taken in this case not to place the part in continuous read mode while SCLK is high, the MSB is clocked out on the DOUT line as the part monitors DIN while supplying data on DOUT and from the CS. Subsequent data bits are clocked from the rising as a result, it may not be possible to take the part out of its edge of SCLK. continuous read mode. RDY t3 t10 CS t4 t6 t8 SCLK (POL = 1) t 7 t 6 SCLK (POL = 0) t t 7 5 t5A t9 DOUT MSB LSB Figure 18.Read Cycle Timing Diagram CS t11 t14 t16 SCLK (POL = 1) t15 t14 SCLK (POL = 0) t15 t12 t13 DIN MSB LSB Figure 19.Write Cycle Timing Diagram REV. B –36–

AD7730/AD7730L CONFIGURING THE AD7730 The AD7730 contains twelve on-chip registers that can be accessed via the serial interface. Figure 5 and Figure 6 have outlined a flowchart for the reading and writing of these registers. Table XIX and Table XX outline sample pseudo-code for some commonly used routines. The required operating conditions will dictate the values loaded to the Mode, Filter and DAC Registers. The values given here are for example purposes only. Table XIX. Pseudo-Code for Initiating a Self-Calibration after Power-On/Reset Write 03 Hex to Serial Port1 /* Writes to Communications Register Setting Next Operation as Write to Filter Register*/ Write 800010 Hex to Serial Port1 /* Writes to Filter Register Setting a 50 Hz Output Rate in CHOP Mode*/ Write 04 Hex to Serial Port1 /* Writes to Communications Register Setting Next Operation as Write to DAC Register*/ Write 23 Hex to Serial Port1 /* Writes to DAC Register Setting a Subtraction Value of 7.5 mV (5 V Refer- ence) on the TARE DAC*/ Write 02 Hex to Serial Port /* Writes to Communications Register Setting Next Operation as Write to Mode Register*/ Write B180 Hex to Serial Port /* Writes to Mode Register Initiating Internal Full-Scale Calibration for 0 mV to +10 mV Input Range*/ Wait for RDY Low /* Wait for RDY pin to go low to indicate end of calibration cycle*/ Write 02 Hex to Serial Port /* Writes to Communications Register Setting Next Operation as Write to Mode Register*/ Write 9180 Hex to Serial Port /* Writes to Mode Register Initiating Internal Zero-Scale Calibration for 0 mV to +10 mV Input Range*/ Wait for RDY Low /* Wait for RDY pin to go low to indicate end of calibration cycle*/ /* The part has now completed self-calibration and is in idle mode*/ 1This operation is not necessary if the default values of the Filter Register or the DAC Register are the values used in the application. Table XX. Pseudo-Code for Setting Up AD7730 for Continuous Conversion and Continuous Read Operation Write 02 Hex to Serial Port /* Writes to Communications Register Setting Next Operation as Write to Mode Register*/ Write 2180 Hex to Serial Port /* Writes to Mode Register Starting Continuous Conversions for 0 mV to +10 mV Input Range*/ Write 21 Hex to Serial Port /* Writes to Communications Register Setting Next Operation as Continuous Read From Data Register*/ Set DIN Line of AD7730 Low /* Ensures Part is not Reset While in Continuous Read Mode*/ READ_DATA: Wait for RDY Low /* Wait for RDY pin to go low to Indicate Output Update*/ Read 24-Bit Data From Serial Port /* Read Conversion Result from AD7730's Data Register*/ Loop to READ_DATA Until All Data Gathered Write 30 Hex to Serial Port /* Ends Continuous Read Operation and Places Part in Mode Where It Expects Write to Communications Register*/ REV. B –37–

AD7730/AD7730L MICROCOMPUTER/MICROPROCESSOR INTERFACING The 68HC11 is configured in the master mode with its CPOL The AD7730’s flexible serial interface allows for easy interface bit set to a logic zero and its CPHA bit set to a logic one. When to most microcomputers and microprocessors. The pseudo-code the 68HC11 is configured like this, its SCLK line idles low of Table XIX and Table XX outline typical sequences for inter- betweendata transfers. Therefore, the POL input of the AD7730 facing a microcontroller or microprocessor to the AD7730. should be hardwired low. For systems where it is preferable that Figures 20, 21 and 22 show some typical interface circuits. the SCLK idle high, the CPOL bit of the 68HC11 should be set to a Logic 1 and the POL input of the AD7730 should be hard- The serial interface on the AD7730 has the capability of operat- wired to a logic high. ing from just three wires and is compatible with SPI interface protocols. The three-wire operation makes the part ideal for The AD7730 is not capable of full duplex operation. If the isolated systems where minimizing the number of interface lines AD7730 is configured for a write operation, no data appears on minimizes the number of opto-isolators required in the system. the DATA OUT lines even when the SCLK input is active. When the AD7730 is configured for continuous read operation, Register lengths on the AD7730 vary from 8 to 16 to 24 bits. data presented to the part on the DATA IN line is monitored to The8-bit serial ports of most microcontrollers can handle determine when to exit the continuous read mode. communication with these registers as either one, two or three 8-bit transfers. DSP processors and microprocessors generally transfer 16 bits of data in a serial data operation. Some of these DVDD DVDD processors, such as the ADSP-2105, have the facility to program SS the amount of cycles in a serial transfer. This allows the user to SYNC tailor the number of bits in any transfer to match the register RESET 68HC11 length of the required register in the AD7730. In any case, AD7730 writing 32 bits of data to a 24-bit register is not an issue provided SCK SCLK the final eight bits of the word are all 1s. This is because the MISO DATA OUT part returns to the Communications Register following a write operation. MOSI DATA IN Even though some of the registers on the AD7730 are only eight CS bits in length, communicating with two of these registers in POL successive write operations can be handled as a single 16-bit data transfer if required. For example, if the DAC Register is to be updated, the processor must first write to the Communica- Figure 20.AD7730 to 68HC11 Interface tions Register (saying that the next operation is a write to the AD7730 to 8051 Interface Mode Register) and then write eight bits to the DAC Register. An interface circuit between the AD7730 and the 8XC51 mi- This can all be done in a single 16-bit transfer, if required, be- crocontroller is shown in Figure 21. The diagram shows the cause once the eight serial clocks of the write operation to the minimum number of interface connections with CS on the Communications Register have been completed, the part imme- AD7730 hardwired low. In the case of the 8XC51 interface, the diately sets itself up for a write operation to the DAC Register. minimum number of interconnects is just two. In this scheme, theRDY bit of the Status Register is monitored to determine AD7730 to 68HC11 Interface when the Data Register is updated. The alternative scheme, Figure 20 shows an interface between the AD7730 and the which increases the number of interface lines to three, is to 68HC11 microcontroller. The diagram shows the minimum (three-wire) interface with CS on the AD7730 hardwired low. monitor the RDY output line from the AD7730. The monitor- In this scheme, the RDY bit of the Status Register is monitored ing of the RDY line can be done in two ways. First, RDY can be connected to one of the 8XC51’s port bits (such as P1.0), which to determine when the Data Register is updated. An alternative is configured as an input. This port bit is then polled to deter- scheme, which increases the number of interface lines to four, is to monitor the RDY output line from the AD7730. The moni- mine the status of RDY. The second scheme is to use an inter- toring of the RDY line can be done in two ways. First, RDY can rupt driven system, in which case the RDY output is connected to the INT1 input of the 8XC51. For interfaces that require be connected to one of the 68HC11’s port bits (such as PC0), control of the CS input on the AD7730, one of the port bits of which is configured as an input. This port bit is then polled to determine the status of RDY. The second scheme is to use an the 8XC51 (such as P1.1), which is configured as an output, interrupt driven system, in which case the RDY output is con- can be used to drive the CS input. nected to the IRQ input of the 68HC11. For interfaces which The 8XC51 is configured in its Mode 0 serial interface mode. require control of the CS input on the AD7730, one of the port Its serial interface contains a single data line. As a result, the bits of the 68HC11 (such as PC1), which is configured as an DATA OUT and DATA IN pins of the AD7730 should be output, can be used to drive the CS input. connected together. This means that the AD7730 must not be REV. B –38–

AD7730/AD7730L configured for continuous read operation when interfacing to AD7730 to ADSP-2103/ADSP-2105 Interface the 8XC51. The serial clock on the 8XC51 idles high between data Figure 22 shows an interface between the AD7730 and the transfers and therefore the POL input of the AD7730 should be ADSP-2105 DSP processor. In the interface shown, the RDY hardwired to a logic high. The 8XC51 outputs the LSB first in a bit of the Status Register is again monitored to determine when write operation while the AD7730 expects the MSB first so the the Data Register is updated. The alternative scheme is to use data to be transmitted has to be rearranged before being written an interrupt driven system, in which case the RDY output is to the output serial register. Similarly, the AD7730 outputs the connected to the IRQ2 input of the ADSP-2105. The RFS and MSB first during a read operation while the 8XC51 expects the TFS pins of the ADSP-2105 are configured as active low out- LSB first. Therefore, the data read into the serial buffer needs to puts and the ADSP-2105 serial clock line, SCLK, is also config- be rearranged before the correct data word from the AD7730 is ured as an output. The POL pin of the AD7730 is hardwired available in the accumulator. low. Because the SCLK from the ADSP-2105 is a continuous clock, the CS of the AD7730 must be used to gate off the clock DVDD once the transfer is complete. The CS for the AD7730 is active when either the RFS or TFS outputs from the ADSP-2105 are SYNC active. The serial clock rate on the ADSP-2105 should be lim- ited to 3MHz to ensure correct operation with the AD7730. RESET 8XC51 AD7730 POL DVDD P3.0 DATA OUT SYNC DATA IN RESET P3.1 SCLK ADSP-2105 RFS AD7730 CS TFS CS DR DATA OUT Figure 21.AD7730 to 8XC51 Interface DT DATA IN SCLK SCLK POL Figure 22.AD7730 to ADSP-2105 Interface REV. B –39–

AD7730/AD7730L APPLICATIONS can be used with the excitation voltage and analog ground con- The on-chip PGA allows the AD7730 to handle analog input nected local to the AD7730’s REF IN(+) and REF IN(–) termi- voltage ranges as low as 10 mV full scale. This allows the user to nals. Illustrating a major advantage of the AD7730, the 5 V connect a transducer directly to the input of the AD7730. The excitation voltage for the bridge can be used directly as the refer- AD7730 is primarily targeted for weigh-scale and load-cell ence voltage for the AD7730, eliminating the need for precision applications. The majority of the applications have a strain- matched resistors in generating a scaled-down reference. gage transducer whose resistance changes when subjected to The application is a ratiometric one with variations in the exci- mechanical stress. Normally, the gages are configured in a tation voltage being reflected in variations in the analog input Wheatstone bridge arrangement. The strain gage is a passive voltage and reference voltage of the AD7730. Because the device and requires an excitation voltage (or in some cases a AD7730 is a truly ratiometric part, with the reference voltage current) to derive a voltage output. Two types of voltage excita- and excitation voltages equal, it is possible to evaluate its total tion can be provided for the bridge: dc excitation or ac excita- excitation voltage rejection. This is unlike other converters tion. These are discussed in the following sections. While the which give a separate indication of the rejection of reference, desire in most applications is to provide a single supply solution analog inputs and power supply. The combined (total) rejection (something that is aided by the AD7730’s single supply capabil- for the AD7730 when moving the excitation voltage (which was ity), some applications provide a bipolar excitation voltage in also the power supply voltage) was better than 115 dB when order to increase the output voltage from the bridge. In such evaluated with a load cell simulator. cases, the input voltage applied to the AD7730 can be slightly Drift considerations are a primary concern for load cell applica- negative with respect to ground. Figure 23 shows how to config- tions. It is recommended for these applications that the AD7730 ure the AD7730 to handle this type of input signal. is operated in CHOP mode to accrue the benefits of the excel- DC Excitation of Bridge lent drift performance of the part in CHOP mode. A common In dc-excitation applications, the excitation voltage provided for source of unwanted drift effects are parasitic thermocouples. the bridge is a fixed dc voltage. Connections between the AD7730 Thermocouple effects are generated every time there is a junc- and the bridge are very straightforward in this type of applica- tion of two dissimilar metals. All components in the signal path tion as illustrated in Figure 23. The bridge configuration shown should be chosen to minimize thermocouple effects. IC sockets is a six-lead configuration with separate return leads for the and link options should be avoided as much as possible. While reference lines. This allows a force/sense effect on the load cell it is impossible to remove all thermocouple effects, attempts should excitation voltage, eliminating voltage drops caused by the exci- be made to equalize the thermocouples on each leg of the differen- tation current flowing through the lead resistances. In applica- tial input to minimize the differential voltage generated. tions where the lead lengths are short, a four-wire configuration EXCITATION VOLTAGE = +5V AVDD DVDD REF IN(+) AD7730 REF IN(–) IN+ SIGMA-DELTA A/D CONVERTER AIN1(+) STANDBY AIN1(–) BUFFER SIGMA- PROGRAMMABLE SYNC OUT+ OUT– + DELTA DIGITAL MUX PGA MODULATOR FILTER +/– IN– MCLK IN AIN2(+)/D1 6-BIT CLOCK AIN2(–)/D0 DAC SERIAL INTERFACE GENERATION AND CONTROL LOGIC MCLK OUT REGISTER BANK SCLK CS CALIBRATION MICROCONTROLLER DIN ACX AC EXCITATION DOUT ACX CLOCK AGND DGND POL RDY RESET Figure 23.Typical Connections for DC-Excited Bridge Application REV. B –40–

AD7730/AD7730L Long lead lengths from the bridge to the AD7730 facilitate the discrete matched bipolar or MOS transistors, or a dedicated pickup of mains frequency on the analog input, the reference bridge driver chip such as the 4427 from Micrel can be used to input and the power supply. The analog inputs to the AD7730 perform the task. are buffered, which allows the user to connect whatever noise Since the analog input voltage and the reference voltage are reduction capacitors are necessary in the application. The AD7730 reversed on alternate cycles, the AD7730 must be synchronized boasts excellent common-mode and normal- mode rejection of with this reversing of the excitation voltage. To allow the mains frequency on both the analog and reference inputs. In AD7730 to synchronize itself with this switching, it provides the CHOP mode, care must be taken in choosing the output update logic control signals for the switching of the excitation voltage. rate so it does not result in reducing line frequency rejection These signals are the nonoverlapping CMOS outputs ACX (see DIGITAL FILTERING section). The input offset current andACX. on the AD7730 is 10 nA maximum which results in a maxi- mum, dc offset voltage of 1.75 mV in a 350 Ω bridge applica- One of the problems encountered with ac-excitation is the set- tling time associated with the analog input signals after the tion. Care should taken with inserting large source impedances excitation voltage is switched. This is particularly true in appli- on the reference input pins as these inputs are not buffered and cations where there are long lead lengths from the bridge to the the source impedances can result in gain errors. AD7730. It means that the converter could encounter errors In many load-cell applications, a portion of the dynamic range because it is processing signals which are not fully settled. The of the bridge output is consumed by a pan weight or tare weight. AD7730 addresses this problem by allowing the user to program In such applications, the 6-bit TARE DAC of the AD7730 can a delay of up to 48.75 μs between the switching of the ACX be used to adjust out this tare weight as outlined previously. signals and the processing of data at the analog inputs. This is AC Excitation of Bridge achieved using the DL bits of the Filter Register. AC excitation of the bridge addresses many of the concerns with The AD7730 also scales the ACX switching frequency in accor- thermocouple, offset and drift effects encountered in dc-excited dance with the output update rate. This avoids situations where applications. In ac-excitation, the polarity of the excitation volt- the bridge is switched at an unnecessarily faster rate than the age to the bridge is reversed on alternate cycles. The result is the system requires. elimination of dc errors at the expense of a more complex sys- The fact that the AD7730 can handle reference voltages which tem design. Figure 24 outlines the connections for an ac-excited are the same as the excitation voltages is particularly useful in bridge application based on the AD7730. ac-excitation where resistor divider arrangements on the The excitation voltage to the bridge must be switched on reference input add to the settling time associated with the alternate cycles. Transistors T1 to T4 in Figure 24 perform switching. the switching of the excitation voltage. These transistors can be EXCITATION VOLTAGE = +5V T1 T2 AVDD DVDD REF IN(+) AD7730 REF IN(–) IN+ SIGMA-DELTA A/D CONVERTER AIN1(+) STANDBY AIN1(–) BUFFER SIGMA- PROGRAMMABLE SYNC OUT+ OUT– + DELTA DIGITAL MUX PGA MODULATOR FILTER +/– IN– AIN2(+)/D1 MCLK IN 6-BIT CLOCK AIN2(–)/D0 DAC SERIAL INTERFACE GENERATION AND CONTROL LOGIC MCLK OUT T3 T4 REGISTER BANK SCLK CS CALIBRATION ACX MICROCONTROLLER DIN AC DOUT ACX EXCITATION CLOCK AGND DGND POL RDY RESET Figure 24.Typical Connections for AC-Excited Bridge Application REV. B –41–

AD7730/AD7730L Bipolar Excitation of the Bridge a minimum of 1.2 V. The 10 V excitation voltage must be re- As mentioned previously, some applications will require that the duced to 5 V before being applied as the reference voltage for AD7730 handle inputs from a bridge that is excited by a bipolar the AD7730. voltage. The number of applications requiring this are limited, The resistor string R1, R2 and R3, takes the 10 V excitation but with the addition of some external components the AD7730 voltage and generates differential voltage of nominally 5 V. is capable of handling such signals. Figure 25 outlines one ap- Amplifiers A1 and A2 buffer the resistor string voltages and proach to the problem. provide the AV and AGND voltages as well as the REF IN(+) DD The example shown is a dc-excited bridge that is driven from and REF IN(–) voltages for the AD7730. The differential ±5V supplies. In such a circuit, two issues must be addressed. reference voltage for the part is +5 V. The AD7730 retains its The first is how to get the AD7730 to handle input voltages ratiometric operation with this reference voltage varying in sym- near or below ground and the second is how to take the 10 V pathy with the analog input voltage. excitation voltage which appears across the bridge and generate The values of the resistors in the resistor string can be changed a suitable reference voltage for the AD7730. The circuit of Figure to allow a larger DV voltage. For example, if R1 = 3 kΩ, DD 25 attempts to address these two issues simultaneously. R2 = 10 kΩ and R3 = 7 kΩ, the AV and AGND voltages DD The AD7730’s analog and digital supplies can be split such that become +3.5 V and –1.5 V respectively. This allows the AD7730 AV and DV can be at separate potentials and AGND and to be used with a +3.6 V DV voltage while still allowing the DD DD DD DGND can also be at separate potentials. The only stipulation analog input range to be within the specified common-mode is that AV or DV must not exceed the AGND by 5.5 V. range. DD DD In Figure 25, the DV is operated at +3 V, which allows the DD An alternate scheme to this is to generate the AV and AGND DD AGND to go down to –2.5 V with respect to system ground. voltages from regulators or Zener diodes driven from the +5 V This means that all logic signals to the part must not exceed 3 V and –5 V supplies respectively. The reference voltage for the with respect to system ground. The AV is operated at +2.5 V DD part would be generated in the same manner as just outlined but with respect to system ground. amplifiers A1 and A2 would not be required to buffer the volt- The bridge is excited with 10 V across its inputs. The output of ages as they are now only driving the reference pins of the the bridge is biased around the midpoint of the excitation volt- AD7730. However, care must be taken in this scheme to ensure ages which in this case is system ground or 0 V. In order for the that the REF IN(+) voltage does not exceed AV and that the DD common-mode voltage of the analog inputs to sit correctly, the REF IN(–) voltage does not go below AGND. AGND of the AD7730 must be biased below system ground by +3V 1/2 OP284 DVDD +5V OR 1/2 OP213 AVDD R1 +5V AD7730 5k REF IN(+) A1 IN+ –5V SIGMA-DELTA A/D CONVERTER STANDBY AIN1(+) R2 BUFFER SIGMA- PROGRAMMABLE SYNC OUT– 10k AIN1(–) + DELTA DIGITAL OUT+ MUX PGA MODULATOR FILTER +/– +5V IN– REF IN(–) MCLK IN A2 6-BIT CLOCK 5Rk3 –5V AGND DAC ASNEDR CIAOLN ITNRTOELR FLAOCGEIC GENERATION MCLK OUT –5V 1/2 OP284 REGISTER BANK SCLK OR 1/2 OP213 CS CALIBRATION MICROCONTROLLER DIN DOUT DGND POL RDY RESET ALL VOLTAGE VALUES ARE WITH SYSTEM RESPECT TO SYSTEM GROUND. GROUND Figure 25.AD7730 with Bipolar Excitation of the Bridge REV. B –42–

APPENDIX A AD7730L SPECIFICATIONS –43–

a APPENDIX–AD7730L* LOW POWER GENERAL DESCRIPTION The AD7730L is a complete low power analog front-end for BRIDGE TRANSDUCER ADC weigh-scale and pressure measurement applications. The device accepts low level signals directly from a transducer and outputs KEY FEATURES a serial digital word. The input signal is applied to a proprietary Resolution of 110,000 Counts (Peak-to-Peak) programmable gain front end based around an analog modula- Power Consumption: 15 mW typ tor. The modulator output is processed by a low pass program- Offset Drift: < 1 ppm/(cid:2)C mable digital filter, allowing adjustment of filter cutoff, output Gain Drift: 3ppm/(cid:2)C rate and settling-time. Line Frequency Rejection: >150dB Buffered Differential Inputs The part features two buffered differential programmable gain Programmable Filter Cutoffs analog inputs as well as a differential reference input. The part Specified for Drift Over Time operates from a single +5V supply and typically consumes less Operates with Reference Voltages of 1V to 5V than 3 mA. It accepts four unipolar analog input ranges: 0 mV to +10mV, +20mV, +40mV and +80mV and four bipolar ADDITIONAL FEATURES ranges±10mV, ±20mV, ±40mV and ±80mV. The peak-to- Two-Channel Programmable Gain Front End peak resolution achievable directly from the part is 1 in 110,000 On-Chip DAC for Offset/TARE Removal counts. An on-chip 6-bit DAC allows the removal of TARE FASTStep Mode voltages. Clock signals for synchronizing ac excitation of the AC or DC Excitation bridge are also provided. Single Supply Operation The serial interface on the part can be configured for three-wire APPLICATIONS operation and is compatible with microcontrollers and digital Portable Weigh Scales signal processors. The AD7730L contains self-calibration and system calibration options and features an offset drift of less than 5 nV/°C and a gain drift of less than 3 ppm/°C. The part is available in a 24-lead SOIC and 24-lead TSSOP package. FUNCTIONAL BLOCK DIAGRAM AVDD DVDD REF IN(–) REF IN(+) AD7730L VBIAS REFERENCE DETECT AVDD STANDBY AIN1(+) SIGMA-DELTA A/D CONVERTER AIN1(–) 100nA BUFFER SIGMA- PROGRAMMABLE SYNC DELTA DIGITAL + MUX PGA MODULATOR FILTER – AIN2(+)/D1 100nA 6-BIT CLOCK MCLK IN AIN2(–)/D0 AGND DAC SERIAL INTERFACE GENERATION MCLK OUT AND CONTROL LOGIC REGISTER BANK SCLK CS DIN ACX AC EXCITATION DOUT ACX CLOCK AGND DGND POL RDY RESET *Protected by U.S. Patent No: 5, 134, 401. Other Patent Applications Filed. REV. B –44–

AD7730L–SPECIFICATIONS AD7730/AD7730L (AV = +5V, DV = +3V or +5V; REF IN(+) = DD DD AV ; REFIN(–) = AGND = DGND = 0V; f = 2.4576 MHz. All specifications T to T unless otherwise noted.) DD CLK IN MIN MAX Parameter B Version1 Units Conditions/Comments STATIC PERFORMANCE (CHP = 1) No Missing Codes2 24 Bits min Output Noise and Update Rates2 See Tables XXI & XXII Integral Nonlinearity 22 ppm of FSR max Offset Error2 See Note 3 Offset Error and Offset Drift Refer to Both Offset Drift vs. Temperature2 5 nV/°C typ Unipolar Offset and Bipolar Zero Errors Offset Drift vs. Time4 25 nV/1000Hours typ Positive Full-Scale Error2, 5 See Note 3 Positive Full-Scale Drift vs Temp2, 6, 7 3 ppm of FS/°C max Positive Full-Scale Drift vs Time4 10 ppm of FS/1000 Hours typ Gain Error2, 8 See Note 3 Gain Drift vs. Temperature2, 6, 9 3 ppm/°C max Gain Drift vs. Time4 10 ppm/1000 Hours typ Bipolar Negative Full-Scale Error2 See Note 3 Negative Full-Scale Drift vs. Temp2, 6 3 ppm of FS/°C max Power Supply Rejection 120 dB typ Measured with Zero Differential Voltage Common-Mode Rejection (CMR) 118 dB min At DC. Measured with Zero Differential Voltage Analog Input DC Bias Current2 40 nA max Analog Input DC Bias Current Drift2 100 pA/°C typ Analog Input DC Offset Current2 10 nA max Analog Input DC Offset Current Drift2 50 pA/°C typ STATIC PERFORMANCE (CHP = 0)2 No Missing Codes 24 Bits min SKIP = 010 Output Noise and Update Rates See Tables XXIII & XXIV Integral Nonlinearity 22 ppm of FSR max Offset Error See Note 3 Offset Error and Offset Drift Refer to Both Offset Drift vs. Temperature6 0.5 μV/°C typ Unipolar Offset and Bipolar Zero Errors Offset Drift vs. Time4 2.5 μV/1000Hours typ Positive Full-Scale Error5 See Note 3 Positive Full-Scale Drift vs. Temp6, 7 0.6 μV/°C typ Positive Full-Scale Drift vs. Time4 3 μV/1000 Hours typ Gain Error8 See Note 3 Gain Drift vs. Temperature6, 9 2 ppm/°C typ Gain Drift vs. Time4 10 ppm/1000 Hours typ Bipolar Negative Full-Scale Error See Note 3 Negative Full-Scale Drift vs. Temp 0.6 μV/°C typ Power Supply Rejection 90 dB typ Measured with Zero Differential Voltage Common-Mode Rejection (CMR) on AIN 105 dB typ At DC. Measured with Zero Differential Voltage CMR on REF IN 100 dB typ At DC. Measured with Zero Differential Voltage Analog Input DC Bias Current 50 nA max Analog Input DC Bias Current Drift 150 pA/°C typ Analog Input DC Offset Current 25 nA max Analog Input DC Offset Current Drift 75 pA/°C typ ANALOG INPUTS/REFERENCE INPUTS Normal-Mode 50 Hz Rejection2 88 dB min From 49 Hz to 51 Hz Normal-Mode 60 Hz Rejection2 88 dB min From 59 Hz to 61 Hz Common-Mode 50 Hz Rejection2 120 dB min From 49 Hz to 51 Hz Common-Mode 60 Hz Rejection2 120 dB min From 59 Hz to 61 Hz Analog Inputs Differential Input Voltage Ranges11 Assuming 2.5 V or 5 V Reference with HIREF Bit Set Appropriately 0 to +10 or ±10 mV nom Gain = 250 0 to +20 or ±20 mV nom Gain = 125 0 to +40 or ±40 mV nom Gain = 62.5 0 to +80 or ±80 mV nom Gain = 31.25 Absolute/Common-Mode Voltage12 AGND + 1.2 V V min AV – 0.95V V max DD Reference Input REF IN(+) – REF IN(–) Voltage +2.5 V nom HIREF Bit of Mode Register = 0 REF IN(+) – REF IN(–) Voltage +5 V nom HIREF Bit of Mode Register = 1 Absolute/Common-Mode Voltage13 AGND – 30mV V min AV + 30mV V max DD NO REF Trigger Voltage 0.3 V min NO REF Bit Active If V Below This Voltage REF 0.65 V max NO REF Bit Inactive If V Above This Voltage REF REV. B –45–

AD7730/AD7730L Parameter B Version1 Units Conditions/Comments LOGIC INPUTS Input Current ±10 μA max All Inputs Except SCLK and MCLK IN V , Input Low Voltage 0.8 V max DV = +5V INL DD V , Input Low Voltage 0.4 V max DV = +3V INL DD V , Input High Voltage 2.0 V min INH SCLK Only (Schmitt Trigerred Input) V 1.4/3 V min to V max DV = +5V T+ DD V 1/2.5 V min to V max DV = +3V T+ DD V 0.8/1.4 V min to V max DV = +5V T– DD V 0.4/1.1 V min to V max DV = +3V T– DD V – V 0.4/0.8 V min to V max DV = +5V T+ T– DD V – V 0.4/0.8 V min to V max DV = +3V T+ T– DD MCLK IN Only V , Input Low Voltage 0.8 V max DV = +5V INL DD V , Input Low Voltage 0.4 V max DV = +3V INL DD V , Input High Voltage 3.5 V min DV = +5V INH DD V , Input High Voltage 2.5 V min DV = +3V INH DD LOGIC OUTPUTS (Including MCLK OUT) V , Output Low Voltage I = 800μA Except for MCLK OUT14; OL SINK 0.4 V max V 15 = +5V DD V , Output Low Voltage I = 100μA Except for MCLK OUT14; OL SINK 0.4 V max V 15 = +3V DD V , Output High Voltage I = 200 μA Except for MCLK OUT14; OH SOURCE 4.0 V min V 15 = +5V DD V , Output High Voltage I = 100 μA Except for MCLK OUT14; OH SOURCE V – 0.6 V V min V 15 = +3V DD DD Floating State Leakage Current ±10 μA max Floating State Output Capacitance2 9 pF typ TRANSDUCER BURNOUT AIN1(+) Current –100 nA nom AIN1(–) Current 100 nA nom Initial Tolerance @ 25°C ±10 % typ Drift2 0.1 %/°C typ OFFSET (TARE) DAC Resolution 6 Bit LSB Size 2.3/2.6 mV min/mV max 2.5 mV Nominal with 5 V Reference (REF IN/2000) DAC Drift16 3.5 ppm/°C max DAC Drift vs. Time4, 16 25 ppm/1000 Hours typ Differential Linearity ±0.75 LSB max Guaranteed Monotonic SYSTEM CALIBRATION Positive Full-Scale Calibration Limit17 1.05× FS V max FS Is the Nominal Full-Scale Voltage (10 mV, 20 mV, 40 mV or 80 mV) Negative Full-Scale Calibration Limit17 –1.05× FS V max Offset Calibration Limit18 –1.05× FS V max Input Span17 0.8× FS V min 2.1× FS V max POWER REQUIREMENTS Power Supply Voltages AV – AGND Voltage +4.75 to +5.25 V min to V max DD DV Voltage +2.7 to +5.25 V min to V max With AGND = 0 V DD Power Supply Currents External MCLK. Digital I/Ps = 0 V or DV DD AV Current (Normal Mode) 3.7 mA max All Input Ranges Except 0 mV to +10 mV and ±10 mV, DD Typically 2.7 mA AV Current (Normal Mode) 5.5 mA max Input Ranges of 0 mV to +10 mV and ±10 mV Only, DD Typically 4 mA DV Current (Normal Mode) 0.45 mA max DV of 2.7 V to 3.3 V, Typically 0.3 mA DD DD DV Current (Normal Mode) 1 mA max DV of 4.75 V to 5.25 V, Typically 0.75 mA DD DD AV + DV Current (Standby Mode) 21 μA max Typically 13μA. External MCLK IN = 0 V or DV DD DD DD Power Dissipation AV = DV = +5V. Digital I/Ps = 0 V or DV DD DD DD Normal Mode 23.5 mW max All Input Ranges Except 0 mV to +10 mV and ±10 mV, Typically 15 mW 32.5 mW max Input Ranges of 0 mV to +10 mV and ±10 mV Only, Typically 23.75 mW Standby Mode 105 μW max Typically 65μW. External MCLK IN = 0 V or DV DD REV. B –46–

AD7730/AD7730L NOTES 11Temperature range: –40°C to +85°C. 12Sample tested during initial release. 13The offset (or zero) numbers with CHP = 1 are typically 3μV precalibration. Internal zero-scale calibration reduces this by about 1μV. Offset numbers with CHP = 0 can be up to 1mV precalibration. Internal zero-scale calibration reduces this to 2μV typical. System zero-scale calibration reduces offset numbers with CHP = 1 and CHP = 0 to the order of the noise. Gain errors can be up to 3000 ppm precalibration with CHP = 0 and CHP = 1. Performing internal full-scale calibrations on the 80 mV range reduces the gain error to less than 100ppm for the 80 mV and 40 mV ranges, to about 250 ppm for the 20 mV range and to about 500 ppm on the 10 mV range. System full-scale calibration reduces this to the order of the noise. Positive and negative full-scale errors can be calculated from the offset and gain errors. 14These numbers are generated during life testing of the part. 15Positive Full-Scale Error includes Offset Errors (Unipolar Offset Error or Bipolar Zero Error) and applies to both unipolar and bipolar input ranges. 16Recalibration at any temperature will remove these errors. 17Full-Scale Drift includes Offset Drift (Unipolar Offset Drift or Bipolar Zero Drift) and applies to both unipolar and bipolar input ranges. 18Gain Error is a measure of the difference between the measured and the ideal span between any two points in the transfer function. The two points used to calculate the gain error are positive full scale and negative full scale. See Terminology. 19Gain Error Drift is a span drift and is effectively the drift of the part if zero-scale calibrations only were performed. 10No Missing Codes performance with CHP = 0 and SKIP = 1 is reduced below 24 bits for SF words lower than 180 decimal. 11The analog input voltage range on the AIN1(+) and AIN2(+) inputs is given here with respect to the voltage on the AIN1(–) and AIN2(–) inputs respectively. 12The common-mode voltage range on the input pairs applies provided the absolute input voltage specification is obeyed. 13The common-mode voltage range on the reference input pair (REF IN(+) and REF IN(–)) applies provided the absolute input voltage specification is obeyed. 14These logic output levels apply to the MCLK OUT output only when it is loaded with a single CMOS load. 15VDD refers to DVDD for all logic outputs expect D0, D1, ACX and ACX where it refers to AVDD. In other words, the output logic high for these four outputs is determined by AVDD. 16This number represents the total drift of the channel with a zero input and the DAC output near full scale. 17After calibration, if the input voltage exceeds positive full scale, the converter will output all 1s. If the input is less than negative full scale, the device outputs all 0s. 18These calibration and span limits apply provided the absolute input voltage specification is obeyed. The offset calibration limit applies to both the unipolar zero point and the bipolar zero point. Specifications subject to change without notice. (AV = +4.75V to +5.25V; DV = +3V to +5.25 V; AGND = DGND = 0 V; f = 2.4576MHz; TIMING CHARACTERISTICS1, 2 DD DD CLK IN Input Logic 0 = 0 V, Logic 1 = DV unless otherwise noted). DD Limit at T to T MIN MAX Parameter (B Version) Units Conditions/Comments Master Clock Range 1 MHz min For Specified Performance 5 MHz max t 50 ns min SYNC Pulsewidth 1 t 50 ns min RESET Pulsewidth 2 Read Operation t 0 ns min RDY to CS Setup Time 3 t 0 ns min CS Falling Edge to SCLK Active Edge Setup Time3 4 t 4 0 ns min SCLK Active Edge to Data Valid Delay3 5 60 ns max DV = +4.75 V to +5.25 V DD 80 ns max DV = +2.75 V to +3.3 V DD t 4, 5 0 ns min CS Falling Edge to Data Valid Delay 5A 60 ns max DV = +4.75 V to +5.25 V DD 80 ns max DV = +2.7 V to +3.3 V DD t 100 ns min SCLK High Pulsewidth 6 t 100 ns min SCLK Low Pulsewidth 7 t 0 ns min CS Rising Edge to SCLK Inactive Edge Hold Time3 8 t 6 10 ns min Bus Relinquish Time after SCLK Inactive Edge3 9 80 ns max t 100 ns max SCLK Active Edge to RDY High3, 7 10 Write Operation t 0 ns min CS Falling Edge to SCLK Active Edge Setup Time3 11 t 30 ns min Data Valid to SCLK Edge Setup Time 12 t 25 ns min Data Valid to SCLK Edge Hold Time 13 t 100 ns min SCLK High Pulsewidth 14 t 100 ns min SCLK Low Pulsewidth 15 t 0 ns min CS Rising Edge to SCLK Edge Hold Time 16 NOTES 1Sample tested during initial release to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of DV ) and timed from a voltage level of 1.6 V. DD 2See Figures 18 and 19. 3SCLK active edge is falling edge of SCLK with POL = 1; SCLK active edge is rising edge of SCLK with POL = 0. 4These numbers are measured with the load circuit of Figure 1 and defined as the time required for the output to cross the V or V limits. OL OH 5This specification only comes into play if CS goes low while SCLK is low (POL = 1) or if CS goes low while SCLK is high (POL = 0). It is primarily required for interfacing to DSP machines. 6These numbers are derived from the measured time taken by the data output to change 0.5V when loaded with the circuit of Figure 1. The measured number is then extrapolated back to remove effects of charging or discharging the 50 pF capacitor. This means that the times quoted in the timing characteristics are the true bus relinquish times of the part and as such are independent of external bus loading capacitances. 7RDY returns high after the first read from the device after an output update. The same data can be read again, if required, while RDY is high, although care should be taken that subsequent reads do not occur close to the next output update. REV. B –47–

AD7730/AD7730L OUTPUT NOISE AND RESOLUTION SPECIFICATION The AD7730L can be programmed to operate in either chop mode or nonchop mode. The chop mode can be enabled in ac-excited or dc-excited applications; it is optional in dc-excited applications, but chop mode must be enabled in ac-excited applications. These options are discussed in more detail in earlier sections. The chop mode has the advantage of lower drift numbers and better noise immunity, but the noise is approximately 20% higher for a given –3 dB frequency and output data rate. It is envisaged that the major- ity of weigh-scale users of the AD7730L will operate the part in chop mode to avail themselves of the excellent drift performance and noise immunity when chopping is enabled. The following tables outline the noise performance of the part in both chop and nonchop modes over all input ranges for a selection of output rates. Output Noise (CHP = 1) This mode is the primary mode of operation of the device. Table XXI shows the output rms noise for some typical output update rates and –3 dB frequencies for the AD7730 when used in chopping mode (CHP of Filter Register = 1) with a master clock frequency of 2.4576 MHz. These numbers are typical and are generated at a differential analog input voltage of 0 V. The output update rate is selected via the SF0 to SF11 bits of the Filter Register. Table XXII, meanwhile, shows the output peak-to-peak resolu- tion in counts for the same output update rates. The numbers in brackets are the effective peak-to-peak resolution in bits (rounded to the nearest 0.5 LSB). It is important to note that the numbers in Table XXII represent the resolution for which there will be no code flicker within a six-sigma limit. They are not calculated based on rms noise, but on peak-to-peak noise. The numbers are generated for the bipolar input ranges. When the part is operated in unipolar mode, the output noise will be the same as the equivalent bipolar input range. As a result, the numbers in Table XXI will remain the same for unipolar ranges while the numbers in Table II will change. To calculate the numbers for Table XXII for unipolar input ranges simply divide the peak-to-peak resolution number in counts by two or subtract one from the peak-to-peak resolution number in bits. Table XXI. Output Noise vs. Input Range and Update Rate (CHP = 1) Typical Output RMS Noise in nV Output –3 dB SF Settling Time Settling Time Input Range Input Range Input Range Input Range Data Rate Frequency Word Normal Mode Fast Mode = (cid:4)80 mV = (cid:4)40 mV = (cid:4)20 mV = (cid:4)10 mV 25Hz 0.98Hz 2048 920 ms 120 ms 245 140 105 70 50Hz 1.97Hz 1024 460ms 60ms 340 220 160 100 75Hz 2.96Hz 683 306 ms 40 ms 420 270 170 110 100Hz* 3.95Hz 512 230ms 30ms 500 290 180 130 200Hz 7.9Hz 256 115ms 15ms 650 490 280 165 *Power-On Default Table XXII. Peak-to-Peak Resolution vs. Input Range and Update Rate (CHP = 1) Peak-to-Peak Resolution in Counts (Bits) Output –3 dB SF Settling Time Settling Time Input Range Input Range Input Range Input Range Data Rate Frequency Word Normal Mode Fast Mode = (cid:4)80 mV = (cid:4)40 mV = (cid:4)20 mV = (cid:4)10 mV 25Hz 0.98Hz 2048 920 ms 120 ms 110k (17) 94k (16.5) 64k (16) 46k (15.5) 50Hz 1.97Hz 1024 460ms 60ms 80k (16.5) 60k (16) 42k (15.5) 33k (15) 75Hz 2.96Hz 683 306 ms 40 ms 62k (16) 50k (15.5) 39k (15) 31k (15) 100Hz* 3.95Hz 512 230ms 30ms 53k (15.5) 46k (15.5) 36k (15) 25k (14.5) 200Hz 7.9Hz 256 115ms 15ms 44k (15.5) 27k (15) 24k (14.5) 20k (14.5) *Power-On Default Output Noise (CHP = 0) Table XXIII shows the output rms noise for some typical output update rates and –3 dB frequencies for the AD7730L when used in nonchopping mode (CHP of Filter Register = 0) with a master clock frequency of 2.4576 MHz. These numbers are typical and are generated at a differential analog input voltage of 0 V. The output update rate is selected via the SF0 to SF11 bits of the Filter Regis- ter. Table XXIV, meanwhile, shows the output peak-to-peak resolution in counts for the same output update rates. The numbers in brackets are the effective peak-to-peak resolution in bits (rounded to the nearest 0.5 LSB). It is important to note that the numbers in Table XXIV represent the resolution for which there will be no code flicker within a six-sigma limit. They are not calculated based on rms noise, but on peak-to-peak noise. The numbers are generated for the bipolar input ranges. When the part is operated in unipolar mode, the output noise will be the same as the equivalent bipolar input range. As a result, the numbers in Table XXIII will remain the same for unipolar ranges while the numbers in Table XXIV will change. To calculate the number for Table XXIV for unipolar input ranges simply divide the peak- to-peak resolution number in counts by two or subtract one from the peak-to-peak resolution number in bits. REV. B –48–

AD7730/AD7730L Table XXIII. Output Noise vs. Input Range and Update Rate (CHP = 0) Typical Output RMS Noise in nV Output –3 dB SF Settling Time Settling Time Input Range Input Range Input Range Input Range Data Rate Frequency Word Normal Mode Fast Mode = (cid:4)80 mV = (cid:4)40 mV = (cid:4)20 mV = (cid:4)10 mV 75Hz 2.9Hz 2048 332 ms 53.2 ms 320 215 135 100 100Hz 3.9Hz 1536 250ms 40ms 325 245 160 110 150Hz 5.85Hz 1024 166ms 26.6ms 410 275 180 130 300Hz 11.7Hz 512 83ms 13.3ms 590 370 265 180 600Hz 23.4Hz 256 41.6 ms 6.6ms 910 580 350 220 Table XXIV. Peak-to-Peak Resolution vs. Input Range and Update Rate (CHP = 0) Peak-to-Peak Resolution in Counts (Bits) Output –3 dB SF Settling Time Settling Time Input Range Input Range Input Range Input Range Data Rate Frequency Word Normal Mode Fast Mode = (cid:4)80 mV = (cid:4)40 mV = (cid:4)20 mV = (cid:4)10 mV 75Hz 2.9Hz 2048 332 ms 53.2 ms 85k (16.5) 62k (16) 49k (15.5) 33k (15) 100Hz 3.9Hz 1536 250 ms 40 ms 82k (16.5) 55k (15.5) 42k (15.5) 30k (15) 150Hz 5.85Hz 1024 166 ms 26.6 ms 65k (16) 48k (15.5) 36k (15) 25k (14.5) 300Hz 11.7Hz 512 83 ms 13.3 ms 45k (15.5) 36k (15) 25k (14.5) 18k (14) 600Hz 23.4Hz 256 41.6 ms 6.63 ms 30k (15) 23k (14.5) 19k (14) 15k (14) REV. B –49–

AD7730/AD7730L PAGE INDEX SERIAL INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 Topic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Page Write Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 Read Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . .1 CONFIGURING THE AD7730 . . . . . . . . . . . . . . . . . . . . .37 AD7730 SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . .2 MICROCOMPUTER/MICROPROCESSOR TIMING CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . .4 INTERFACING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38 ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . .5 AD7730 to 68HC11 Interface . . . . . . . . . . . . . . . . . . . . .38 ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AD7730 to 8051 Interface . . . . . . . . . . . . . . . . . . . . . . . .38 DETAILED FUNCTIONAL BLOCK DIAGRAM . . . . . . .6 AD7730 to ADSP-2105 Interface . . . . . . . . . . . . . . . . . .39 SIGNAL PROCESSING CHAIN . . . . . . . . . . . . . . . . . . . . .7 APPLICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 PIN CONFIGURATION . . . . . . . . . . . . . . . . . . . . . . . . . . .7 DC Excitation of Bridge . . . . . . . . . . . . . . . . . . . . . . . . . .40 PIN FUNCTION DESCRIPTION . . . . . . . . . . . . . . . . . . .7 AC Excitation of Bridge . . . . . . . . . . . . . . . . . . . . . . . . . .41 TERMINOLOGY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 Bipolar Excitation of Bridge . . . . . . . . . . . . . . . . . . . . . . .42 OUTPUT NOISE AND RESOLUTION APPENDIX A–AD7730L SPECIFICATIONS . . . . . . . . . .43 SPECIFICATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45 ON-CHIP REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . .11 INDEX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50 Summary Of On-Chip Registers . . . . . . . . . . . . . . . . . . . .12 OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . .51 Communications Register . . . . . . . . . . . . . . . . . . . . . . . .13 Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 TABLE INDEX Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 Table Title Page Mode Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 Table I. Output Noise vs. Input Range and Filter Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 Update Rate (CHP = 1) 10 DAC Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 Table II. Peak-to-Peak Resolution vs. Input Range Offset Calibration Register . . . . . . . . . . . . . . . . . . . . . . . .20 and Update Rate (CHP = 1) 10 Gain Calibration Register . . . . . . . . . . . . . . . . . . . . . . . . .20 Table III. Output Noise vs. Input Range and Test Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 Update Rate (CHP = 0) 11 READING FROM AND WRITING TO THE Table IV. Peak-to-Peak Resolution vs. Input Range ON-CHIP REGISTERS. . . . . . . . . . . . . . . . . . . . . . . . . .21 and Update Rate (CHP = 0) 11 CALIBRATION OPERATION SUMMARY . . . . . . . . . . .22 Table V. Summary of On-Chip Registers 12 CIRCUIT DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . .23 Table VI. Communications Register 13 ANALOG INPUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 Table VII. Read/Write Mode 13 Analog Input Channels . . . . . . . . . . . . . . . . . . . . . . . . . .24 Table VIII. Register Selection 14 Analog Input Ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 Table IX. Status Register 14 Bipolar/Unipolar Inputs . . . . . . . . . . . . . . . . . . . . . . . . . .24 Table X. Mode Register 15 Burnout Currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 Table XI. Operating Modes 15 REFERENCE INPUT . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 Table XII. Input Range Selection 17 Reference Detect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 Table XIII. Channel Selection 18 SIGMA-DELTA MODULATOR . . . . . . . . . . . . . . . . . . . .26 Table XIV. Filter Register 18 DIGITAL FILTERING . . . . . . . . . . . . . . . . . . . . . . . . . . .26 Table XV. SF Ranges 19 Filter Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 Table XVI. DAC Register 20 First Stage Filter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 Table XVII. Calibration Operations 22 Second Stage Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 Table XVIII. Reset Events 23 CALIBRATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 Table XIX. Pseudo-Code for Initiating a Internal Zero-Scale Calibration . . . . . . . . . . . . . . . . . . . .30 Self-Calibration after Power-On/Reset 37 Internal Full-Scale Calibration . . . . . . . . . . . . . . . . . . . . .30 Table XX. Pseudo-Code for Setting Up AD7730 for System Zero-Scale Calibration . . . . . . . . . . . . . . . . . . . . .31 Continuous Conversion and Continuous System Full-Scale Calibration . . . . . . . . . . . . . . . . . . . . .31 Read Operation 37 Span and Offset Limits . . . . . . . . . . . . . . . . . . . . . . . . . .31 Table XXI. Output Noise vs. Input Range and Power-Up and Calibration . . . . . . . . . . . . . . . . . . . . . . . .32 Update Rate (CHP = 1) 48 Drift Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 Table XXII. Peak-to-Peak Resolution vs. Input Range USING THE AD7730 . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 and Update Rate (CHP = 1) 48 Clocking and Oscillator Circuit . . . . . . . . . . . . . . . . . . . .32 Table XXIII. Output Noise vs. Input Range and System Synchronization . . . . . . . . . . . . . . . . . . . . . . . . . .33 Update Rate (CHP = 0) 49 Single-Shot Conversions . . . . . . . . . . . . . . . . . . . . . . . . .33 Table XXIV. Peak-to-Peak Resolution vs. Input Range Reset Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 and Update Rate (CHP = 0) 49 Standby Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 Digital Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 POWER SUPPLIES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 Grounding and Layout . . . . . . . . . . . . . . . . . . . . . . . . . . .34 Evaluating the AD7730 Performance . . . . . . . . . . . . . . . .34 –50– REV. A

AD7730/AD7730L OUTLINE DIMENSIONS 1.280 (32.51) 1.250 (31.75) 1.230 (31.24) 24 13 0.280 (7.11) 0.250 (6.35) 1 12 0.240 (6.10) 0.325 (8.26) 0.310 (7.87) 0.100 (2.54) 0.300 (7.62) BSC 0.060 (1.52) 0.195 (4.95) 0.210 (5.33) MAX 0.130 (3.30) MAX 0.115 (2.92) 0.015 0.150 (3.81) (0.38) 0.015 (0.38) 0.130 (3.30) MIN GAUGE 0.115 (2.92) SEATING PLANE 00..001140 ((00..3265)) PLANE 0.022 (0.56) 0.008 (0.20) 0.005 (0.13) 0.430 (10.92) 0.018 (0.46) MIN MAX 0.014 (0.36) 0.070 (1.78) 0.060 (1.52) 0.045 (1.14) COMPLIANTTO JEDEC STANDARDS MS-001 CONTROLLING DIMENSIONSARE IN INCHES; MILLIMETER DIMENSIONS (RCINOEFRPENAREREREN NLCTEEHA EODSNSEL MSY)AAAYNR BDEE AR CROOEU NNNFODIGETUDAR-POEPFDRFOA INSPC RWHIAH ETOEQL UFEIO VORAR LU EHSNAETL ISFN FLDOEEARSDIGSN.. 071006-A 24-Lead Plastic Dual In-Line Package [PDIP] Narrow Body (N-24-1) Dimensions shown in inches and (millimeters) 15.60(0.6142) 15.20(0.5984) 24 13 7.60(0.2992) 7.40(0.2913) 1 10.65(0.4193) 12 10.00(0.3937) 0.75(0.0295) 45° 2.65(0.1043) 0.25(0.0098) 0.30(0.0118) 2.35(0.0925) 8° 0.10(0.0039) 0° COPLANARITY 0.10 1.27B(0S.C0500) 00..5311((00..00210212)) SPLEAATNIENG 00..3230((00..00103709)) 10..2470((00..00510507)) COMPLIANTTOJEDECSTANDARDSMS-013-AD C(RINOEFNPEATRRREOENNLCLTEIHNEOGSNDELISYM)AEANNRDSEIAORRNOESUNANORDETEDAIN-POMPFRIFLOLMPIMIRLELIATIMTEEERTFSEO;RIRNECUQHSUEDIVIINMAELDENENSSTIIOGSNNFS.OR 12-09-2010-A 24-Lead Standard Small Outline Package [SOIC_W] Wide Body (RW-24) Dimensions shown in millimeters and (inches) REV. B –51–

AD7730/AD7730L 7.90 7.80 7.70 24 13 4.50 4.40 4.30 6.40 BSC 1 12 PIN 1 0.65 1.20 BSC MAX 0.15 0.05 8° 0.75 0.30 SEATING 0.20 0° 0.60 0.19 PLANE 0.09 0.45 0.10 COPLANARITY COMPLIANT TO JEDEC STANDARDS MO-153-AD 24-Lead Thin Shrink Small Outline Package [TSSOP] (RU-24) Dimensions shown in millimeters ORDERING GUIDE Model1 Temperature Range Package Description Package Options AD7730BN −40°C to +85°C 24-Lead Plastic Dual In-Line Package [PDIP] N-24-1 AD7730BNZ −40°C to +85°C 24-Lead Plastic Dual In-Line Package [PDIP] N-24-1 AD7730BR −40°C to +85°C 24-Lead Standard Small Outline Package [SOIC_W] RW-24 AD7730BR-REEL −40°C to +85°C 24-Lead Standard Small Outline Package [SOIC_W] RW-24 AD7730BR-REEL7 −40°C to +85°C 24-Lead Standard Small Outline Package [SOIC_W] RW-24 AD7730BRZ −40°C to +85°C 24-Lead Standard Small Outline Package [SOIC_W] RW-24 AD7730BRZ-REEL −40°C to +85°C 24-Lead Standard Small Outline Package [SOIC_W] RW-24 AD7730BRZ-REEL7 −40°C to +85°C 24-Lead Standard Small Outline Package [SOIC_W] RW-24 AD7730BRU −40°C to +85°C 24-Lead Thin Shrink Small Outline Package [TSSOP] RU-24 AD7730BRU-REEL −40°C to +85°C 24-Lead Thin Shrink Small Outline Package [TSSOP] RU-24 AD7730BRU-REEL7 −40°C to +85°C 24-Lead Thin Shrink Small Outline Package [TSSOP] RU-24 AD7730BRUZ −40°C to +85°C 24-Lead Thin Shrink Small Outline Package [TSSOP] RU-24 AD7730BRUZ-REEL −40°C to +85°C 24-Lead Thin Shrink Small Outline Package [TSSOP] RU-24 AD7730BRUZ-REEL7 −40°C to +85°C 24-Lead Thin Shrink Small Outline Package [TSSOP] RU-24 EVAL-AD7730EBZ Evaluation Board AD7730LBR −40°C to +85°C 24-Lead Standard Small Outline Package [SOIC_W] RW-24 AD7730LBR-REEL7 −40°C to +85°C 24-Lead Standard Small Outline Package [SOIC_W] RW-24 AD7730LBRZ −40°C to +85°C 24-Lead Standard Small Outline Package [SOIC_W] RW-24 AD7730LBRZ-REEL −40°C to +85°C 24-Lead Standard Small Outline Package [SOIC_W] RW-24 AD7730LBRU −40°C to +85°C 24-Lead Thin Shrink Small Outline Package [TSSOP] RU-24 AD7730LBRU-REEL −40°C to +85°C 24-Lead Thin Shrink Small Outline Package [TSSOP] RU-24 AD7730LBRU-REEL7 −40°C to +85°C 24-Lead Thin Shrink Small Outline Package [TSSOP] RU-24 AD7730LBRUZ −40°C to +85°C 24-Lead Thin Shrink Small Outline Package [TSSOP] RU-24 AD7730LBRUZ-REEL −40°C to +85°C 24-Lead Thin Shrink Small Outline Package [TSSOP] RU-24 AD7730LBRUZ-REEL7 −40°C to +85°C 24-Lead Thin Shrink Small Outline Package [TSSOP] RU-24 EVAL-AD7730LEBZ Evaluation Board 1 Z = RoHS Compliant Part. –52– REV. B

AD7730/AD7730L REVISION HISTORY 6/12—Rev. A to Rev. B Changed Differential Linearity from −0.25/0.75 LSB to ±0.75 LSB .......................................................................................... 46 Changes to Ordering Guide ........................................................... 52 1/98—Rev. 0 to Rev. A ©2012 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D01189-0-6/12(B) REV. B –53–

Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: A nalog Devices Inc.: AD7730BRZ-REEL AD7730BR AD7730BR-REEL AD7730LBRUZ AD7730BRU AD7730BRU-REEL7 AD7730LBRZ-REEL EVAL-AD7730LEBZ AD7730BNZ AD7730LBR-REEL7 AD7730LBRZ AD7730BRUZ-REEL EVAL-AD7730EBZ AD7730BRZ-REEL7 AD7730BRUZ AD7730BRZ AD7730BR-REEL7 AD7730LBRU AD7730LBRUZ-REEL AD7730BRUZ-REEL7 AD7730LBRUZ-REEL7 AD7730LBR AD7730LBRU-REEL AD7730BRU-REEL AD7730LBRU-REEL7