a 8-/10-Channel, Low Voltage, (cid:1) (cid:2) Low Power, - ADCs AD7708/AD7718 FEATURES GENERAL DESCRIPTION 8-/10-Channel, High Resolution (cid:1)-(cid:2) ADCs The AD7708/AD7718 are complete analog front-ends for low AD7708 Has 16-Bit Resolution frequency measurement applications. The AD7718 contains a AD7718 Has 24-Bit Resolution 24-bit Σ-∆ ADC with PGA and can be configured as 4/5 fully- Factory-Calibrated differential input channels or 8/10 pseudo-differential input Single Conversion Cycle Setting channels. Two pins on the device are configurable as analog Programmable Gain Front End inputs or reference inputs. The AD7708 is a 16-bit version of Simultaneous 50 Hz and 60 Hz Rejection the AD7718. Input signal ranges from 20 mV to 2.56V can be VREF Select™ Allows Absolute and Ratiometric directly converted using these ADCs. Signals can be converted Measurement Capability directly from a transducer without the need for signal conditioning. Operation Can Be Optimized for The device operates from a 32 kHz crystal with an on-board PLL Analog Performance (CHOP = 0) or generating the required internal operating frequency. The output Channel Throughput (CHOP = 1) data rate from the part is software programmable. The peak-to- INTERFACE peak resolution from the part varies with the programmed gain 3-Wire Serial and output data rate. SPITM, QSPITM, MICROWIRETM, and DSP-Compatible The part operates from a single 3 V or 5 V supply. When operating Schmitt Trigger on SCLK from 3 V supplies, the power dissipation for the part is 3.84 mW typ. POWER Both parts are pin-for-pin compatible allowing an upgradable Specified for Single 3 V and 5 V Operation path from 16 to 24 bits without the need for hardware modifica- Normal: 1.28 mA Typ @ 3 V tions. The AD7708/AD7718 are housed in 28-lead SOIC and Power-Down: 30 (cid:3)A (32 kHz Crystal Running) TSSOP packages. On-Chip Functions Rail-to-Rail Input Buffer and PGA 2-Bit Digital I/O Port APPLICATIONS Industrial Process Control Instrumentation Pressure Transducers Portable Instrumentation Smart Transmitters FUNCTIONAL BLOCK DIAGRAM DVDD DGND REFIN2(+)/AIN9 REFIN1(+) REFIN2(–)/AIN10 REFIN1(–) XTAL1XTAL2 OSC AND PLL AIN1 AIN2 AIN3 POS BUF AIN4 REFIN(+) REFIN(–) DOUT AAIINN56 MUX NEG BUF PGA (cid:1)-(cid:2) ADC* INSTEERRIFAALCE DSCINLK AIN7 *AD7708 16-BIT ADC COANNTDROL CS AIN8 *AD7718 24-BIT ADC LOGIC RDY RESET AINCOM AVDD AD7708/AD7718 I/O PORT AVDD AGND P2 P1 SPI and QSPI are trademarks of Motorola Inc. MICROWIRE is a trademark of National Semiconductor Corp. VREF Select is a trademark of Analog Devices, Inc. REV.0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. may result from its use. No license is granted by implication or otherwise Tel: 781/329-4700 www.analog.com under any patent or patent rights of Analog Devices. Fax: 781/326-8703 © Analog Devices, Inc., 2001

AD7708/AD7718 TABLE OF CONTENTS FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 User Nonprogrammable Test Registers . . . . . . . . . . . . . . . .31 FUNCTIONAL BLOCK DIAGRAM . . . . . . . . . . . . . . . . .1 Configuring the AD7708/AD7718 . . . . . . . . . . . . . . . . . . . .32 GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . .1 DIGITAL INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . .34 AD7718 SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . .3 MICROCOMPUTER/MICROPROCESSOR INTERFACING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 AD7708 SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . .6 AD7708/AD7718 to 68HC11 Interface . . . . . . . . . . . . . . . .34 TIMING CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . .9 AD7708/AD7718-to-8051 Interface . . . . . . . . . . . . . . . . . .35 ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . .10 AD7708/AD7718-to-ADSP-2103/ADSP-2105 Interface . . .36 ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 BASIC CONFIGURATION . . . . . . . . . . . . . . . . . . . . . . . .36 PIN FUNCTION DESCRIPTIONS . . . . . . . . . . . . . . . . .12 Analog Input Channels . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 PIN CONFIGURATION . . . . . . . . . . . . . . . . . . . . . . . . . .13 Single-Ended Operation . . . . . . . . . . . . . . . . . . . . . . . . . . .37 ADC CIRCUIT INFORMATION . . . . . . . . . . . . . . . . . . .15 Chop Mode of Operation (CHOP = 0) . . . . . . . . . . . . . . . .37 Signal Chain Overview (CHOP Enabled, CHOP = 0) . . .15 Nonchop Mode of Operation (CHOP = 1) . . . . . . . . . . . . .38 ADC NOISE PERFORMANCE CHOP ENABLED (CHOP = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 Programmable Gain Amplifier . . . . . . . . . . . . . . . . . . . . . . .38 Signal Chain Overview (CHOP Disabled CHOP = 1) . . .19 Bipolar/Unipolar Configuration . . . . . . . . . . . . . . . . . . . . . .38 ADC NOISE PERFORMANCE CHOP DISABLED Data Output Coding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38 (CHOP = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 Oscillator Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 ON-CHIP REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . .22 Reference Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 Communications Register . . . . . . . . . . . . . . . . . . . . . . . . . .25 RESET Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 Power-Down Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 Mode Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 Operating Characteristics when Addressing the Grounding and Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 Mode and Control Registers . . . . . . . . . . . . . . . . . . . . . . .28 APPLICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41 ADC Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 Data Acquisition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41 Filter Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 Programmable Logic Controllers . . . . . . . . . . . . . . . . . . . . .41 I/O Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 Converting Single-Ended Inputs. . . . . . . . . . . . . . . . . . . . .42 ADC Data Result Register . . . . . . . . . . . . . . . . . . . . . . . . . .30 Combined Ratiometric and Absolute Value Unipolar Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 Measurement System . . . . . . . . . . . . . . . . . . . . . . . . . . . .42 Bipolar Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 Optimizing Throughput while Maximizing 50 Hz ADC Offset Calibration Coefficient Registers . . . . . . . . . . .31 and 60 Hz Rejection in a Multiplexed Data Acquisition System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43 ADC Gain Calibration Coefficient Register . . . . . . . . . . . . .31 OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . .44 ID Register (ID) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 –2– REV. 0

AD7708/AD7718 AD7718 SPECIFICATIONS1 (AV = 2.7 V to 3.6V or 4.75 V to 5.25 V, DV = 2.7 V to 3.6V or 4.75 V to 5.25 V, DD DD REFIN(+) = 2.5 V; REFIN(–) = AGND; AGND = DGND = 0 V; XTAL1/XTAL2 = 32.768 kHz Crystal Input Buffer Enabled. All specifications T to MIN T unless otherwise noted.) MAX Parameter B Grade Unit Test Conditions AD7718 (CHOP DISABLED) Output Update Rate 16.06 Hz min CHOP = 1 1.365 kHz max No Missing Codes2 24 Bits min Resolution 13 Bits p-p ±20 mV Range, SF = 69 18 Bits p-p ±2.56V Range, SF = 69 Output Noise and Update Rates See Tables in ADC Description Integral Nonlinearity ±10 ppm of FSR max 2 ppm Typical Offset Error3 Table VII µV typ Offset Error is in the order of the noise for the programmed gain and update rate following a calibration Offset Error Drift vs. Temp4 ±200 nV/°C typ Full-Scale Error3 ±10 µV typ Gain Drift vs. Temp4 ±0.5 ppm/°C typ Negative Full-Scale Error ±0.003 % FSR max ANALOG INPUTS Differential Input Full-Scale Voltage ±1.024 × REFIN/GAIN V nom REFIN Refers to Both REFIN1 and REFIN2. REFIN = REFIN(+) –REFIN(–) GAIN = 1 to 128 Absolute AIN Voltage Limits AGND + 100 mV V min AIN1–AIN10 and AINCOM with AV – 100 mV V max NEGBUF = 1 DD Absolute AINCOM Voltage Limits AGND – 30 mV V min NEGBUF = 0 AV + 30 mV V max DD Analog Input Current AIN1–AIN10 and AINCOM with NEGBUF = 1 DC Input Current2 ±1 nA max DC Bias Current Drift ±5 pA/°C typ AINCOM Input Current NEGBUF = 0 DC Input Current2 ±125 nA/V typ ±2.56V Range DC Bias Current Drift ±2 pA/V/°C typ Normal-Mode Rejection2 @ 50 Hz 100 dB min 50 Hz ±1 Hz, SF Word = 82 @ 60 Hz 100 dB min 60 Hz± 1 Hz, SF Word = 68 Common-Mode Rejection @ DC 90 dB min 100 dB typ, Analog Input = 1 V, Input Range = ±2.56V 110 dB typ on ±20 mV Range @ 50 Hz 100 dB typ 50 Hz ±1 Hz, SF Word = 82 @ 60 Hz 100 dB typ 60 Hz ±1 Hz, SF Word = 68 REFERENCE INPUTS (REFIN1 AND REFIN2) REFIN(+) to REFIN(–) Voltage 2.5 V nom REFIN Refers to Both REFIN1 and REFIN2 REFIN(+) to REFIN(–) Range2 1 V min AV V max DD REFIN Common-Mode Range AGND – 30 mV V min AV + 30 mV V max DD Reference DC Input Current 0.5 µA/V typ Reference DC Input Current Drift ±0.1 nA/V/°C typ Normal-Mode Rejection2 @ 50 Hz 100 dB min 50 Hz ± 1 Hz, SF Word = 82 @ 60 Hz 100 dB min 60 Hz ± 1 Hz, SF Word = 68 Common-Mode Rejection Input Range = ±2.56V @ DC 100 dB typ Analog Input = 1 V. Input Range = ±2.56V @ 50 Hz 100 dB typ @ 60 Hz 100 dB typ REV. 0 –3–

AD7718–SPECIFICATIONS1 (AV = 2.7 V to 3.6V or 4.75 V to 5.25 V, DV = 2.7 V to 3.6V or 4.75 V to 5.25 V, REFIN(+) = DD DD 2.5 V ; REFIN(–) = AGND; AGND = DGND = 0 V; XTAL1/XTAL2 = 32.768 kHz Crystal Input Buffer Enabled. All specifications T to T unless otherwise noted.) MIN MAX Parameter B Grade Unit Test Conditions AD7718 (CHOP ENABLED) Output Update Rate 5.4 Hz min CHOP = 0 105 Hz max No Missing Codes2 24 Bits min 20 Hz Update Rate Resolution 13 Bits p-p ±20 mV Range, 20 Hz Update Rate 18 Bits p-p ±2.56V Range, 20 Hz Update Rate Output Noise and Update Rates See Tables in ADC Description Integral Nonlinearity ±10 ppm of FSR max 2 ppm Typical Offset Error3 ±3 µV typ Offset Error Drift vs. Temp4 10 nV/°C typ Full-Scale Error3 ±10 µV/°C typ Gain Drift vs. Temp4 ±0.5 ppm/°C typ ANALOG INPUTS Differential Input Full-Scale Voltage ±1.024 × REFIN/GAIN V nom REFIN Refers to Both REFIN1 and REFIN2. REFIN = REFIN(+) REFIN(–) GAIN = 1 to 128 Range Matching ±2 µV typ Analog Input = 18 mV Absolute AIN Voltage Limits AGND + 100 mV V min AIN1–AIN10 and AINCOM with AV – 100 mV V max NEGBUF = 1 DD Absolute AINCOM Voltage Limits AGND – 30 mV V min NEGBUF = 0 AV + 30 mV V max DD Analog Input Current AIN1–AIN10 and AINCOM with NEGBUF = 1 DC Input Current2 ±1 nA max DC Input Current Drift ±5 pA/°C typ AINCOM Input Current NEGBUF = 0 DC Input Current2 ±125 nA/V typ ±2.56V Range DC Bias Current Drift ±2 pA/V/°C typ Normal-Mode Rejection2 @ 50 Hz 100 dB min 50 Hz ± 1 Hz, SF Word = 82 @ 60 Hz 100 dB min 60Hz ± 1 Hz, SF Word = 68 Common-Mode Rejection @ DC 90 dB min 100 dB typ, Analog Input = 1 V, Input Range = ±2.56V 110 dB typ on ±20 mV Range @ 50 Hz2 100 dB min 50 Hz ± 1 Hz, 20 Hz Update Rate @ 60 Hz2 100 dB min 60 Hz ± 1 Hz, 20 Hz Update Rate REFERENCE INPUTS (REFIN1 AND REFIN2) REFIN(+) to REFIN(–) Voltage 2.5 V nom REFIN Refers to Both REFIN1 and REFIN2 REFIN(+) to REFIN(–) Range2 1 V min AV V max DD REFIN Common-Mode Range AGND – 30 mV V min AV + 30 mV V max DD Reference DC Input Current2 ±0.5 µA/V typ Reference DC Input Current Drift ±0.01 nA/V/°C typ Normal-Mode Rejection2 @ 50 Hz 100 dB min 50 Hz ± 1 Hz, SF Word = 82 @ 60 Hz 100 dB min 60 Hz ± 1 Hz, SF Word = 68 Common-Mode Rejection2 Input Range = ±2.56V @ DC 110 dB typ Analog Input = 1 V @ 50 Hz 110 dB typ 50 Hz ± 1 Hz, 20 Hz Update Rate @ 60 Hz 110 dB typ 60 Hz ± 1 Hz, 20 Hz Update Rate LOGIC INPUTS5 All Inputs Except SCLK and XTAL12 V , Input Low Voltage 0.8 V max DV = 5 V INL DD V , Input Low Voltage 0.4 V max DV = 3 V INL DD V , Input High Voltage 2.0 V min DV = 3 V or 5 V INH DD –4– REV. 0

AD7708/AD7718 Parameter B Grade Unit Test Conditions LOGIC INPUTS (Continued) SCLK Only (Schmitt-Triggered Input)2 V 1.4/2 V min/V max DV = 5 V T(+) DD V 0.8/1.4 V min/V max DV = 5 V T(–) DD V – V 0.3/0.85 V min/V max DV = 5 V T(+) T(–) DD V 0.95/2 V min/V max DV = 3 V T(+) DD V 0.4/1.1 V min/V max DV = 3 V T(–) DD V –V 0.3/0.85 V min/V max DV = 3 V T(+) T(–) DD XTAL1 Only2 V , Input Low Voltage 0.8 V max DV = 5 V INL DD V , Input High Voltage 3.5 V min DV = 5 V INH DD V , Input Low Voltage 0.4 V max DV = 3 V INL DD V , Input High Voltage 2.5 V min DV = 3 V INH DD Input Currents ±10 µA max Logic Input = DV DD –70 µA max Logic Input = DGND, Typical –40 µA @ 5 V and –20 µA at 3 V Input Capacitance 10 pF typ All Digital Inputs LOGIC OUTPUTS (Excluding XTAL2)5 V , Output High Voltage2 DV – 0.6 V min DV = 3 V, I = 100 µA OH DD DD SOURCE V , Output Low Voltage2 0.4 V max DV = 3 V, I = 100 µA OL DD SINK V , Output High Voltage2 4 V min DV = 5 V, I = 200 µA OH DD SOURCE V , Output Low Voltage2 0.4 V max DV = 5 V, I = 1.6 mA OL DD SINK Floating State Leakage Current ±10 µA max Floating State Output Capacitance ±10 pF typ Data Output Coding Binary Unipolar Mode Offset Binary Bipolar Mode SYSTEM CALIBRATION2 Full-Scale Calibration Limit 1.05 × FS V max Zero-Scale Calibration Limit –1.05 × FS V min Input Span 0.8 × FS V min 2.1 × FS V max START-UP TIME From Power-On 300 ms typ From Power-Down Mode 1 ms typ Oscillator Enabled 300 ms typ Oscillator Powered Down POWER REQUIREMENTS Power Supply Voltages AV and DV can be operated independently of each other. DD DD AV –AGND 2.7/3.6 V min/max AV = 3 V nom DD DD 4.75/5.25 V min/max AV = 5 V nom DD DV –DGND 2.7/3.6 V min/max DV = 3 V nom DD DD 4.75/5.25 V min DV = 5 V nom DD DI (Normal Mode) 0.55 mA max DV = 3 V, 0.43 mA typ DD DD 0.65 mA max DV = 5 V, 0.5 mA typ DD AI (Normal Mode) 1.1 mA max AV = 3 V or 5 V, 0.85 mA typ DD DD DI (Power-Down Mode) 10 µA max DV = 3 V, 32.768 kHz Osc. Running DD DD 2 µA max DV = 3 V, Oscillator Powered Down DD 30 µA max DV = 5 V, 32.768 kHz Osc. Running DD 8 µA max DV = 5 V, Oscillator Powered Down DD AI (Power-Down Mode) 1 µA max AV = 3 V or 5 V DD DD Power Supply Rejection (PSR) Input Range = ±2.56V, AIN = 1 V Chop Disabled 70 dB min 95 dB typ Chop Enabled 100 dB typ NOTES 1Temperature range is –40°C to +85°C. 2Not production tested, guaranteed by design and/or characterization data at release. 3Following a self-calibration this error will be in the order of the noise for the programmed gain and update selected. A system calibration will completely remove this error. 4Recalibration at any temperature will remove these errors. 5I/O Port Logic Levels are with respect to AV andAGND. DD Specifications are subject to change without notice. REV. 0 –5–

AD7708/AD7718 AD7708 SPECIFICATIONS1 (AV = 2.7 V to 3.6V or 4.75 V to 5.25 V, DV = 2.7 V to 3.6V or 4.75 V to 5.25 V, DD DD REFIN(+) = 2.5 V; REFIN(–) = AGND; AGND = DGND = 0 V; XTAL1/XTAL2 = 32.768 kHz Crystal Input Buffers Enabled. All specifications T to MIN T unless otherwise noted.) MAX Parameter B Grade Unit Test Conditions AD7708 (CHOP DISABLED) Output Update Rate 16.06 Hz min CHOP = 1 1.365 kHz max No Missing Codes2 16 Bits min Resolution 13 Bits p-p ±20 mV Range, SF Word = 69 16 Bits p-p ±2.56V Range, SF Word = 69 Output Noise and Update Rates See Tables in ADC Description Integral Nonlinearity ±15 ppm of FSR max 2ppm Typical Offset Error3 ±0.65 LSB typ Following a Self-Calibration Offset Error Drift vs. Temp4 ±200 nV/°C typ Full-Scale Error3 ±0.75 LSB typ Gain Drift vs. Temp4 ±0.5 ppm/°C typ Negative Full-Scale Error ±0.003 % FSR typ ANALOG INPUTS Differential Input Full-Scale Voltage ±1.024 × REFIN/GAIN V nom REFIN Refers to Both REFIN1 and REFIN2. REFIN = REFIN(+) – REFIN(–) GAIN = 1 to 128 Absolute AIN Voltage Limits AGND + 100 mV V min AIN1–AIN10 and AINCOM with AV – 100 mV V max NEGBUF = 1 DD Absolute AINCOM Voltage Limits AGND – 30 mV V min NEGBUF = 0 AV + 30 mV V max DD Analog Input Current AIN1–AIN10 and AINCOM with NEGBUF = 1 DC Input Current2 ±1 nA max DC Bias Current Drift ±5 pA/°C typ AINCOM Input Current NEGBUF = 0 DC Input Current2 ±125 nA/V typ ±2.56V Range DC Bias Current Drift ±2 pA/V/°C typ Normal-Mode Rejection2 @ 50 Hz 100 dB min 50 Hz± 1 Hz, SF Word = 82 @ 60 Hz 100 dB min 60 Hz± 1 Hz, SF Word = 68 Common-Mode Rejection @ DC 90 dB min 100 dB typ, Analog Input = 1 V, Input Range = ±2.56V 110 dB typ on ±20 mV Range @ 50 Hz 100 dB typ 50 Hz ±1 Hz, SF Word = 82 @ 60 Hz 100 dB typ 60 Hz ±1 Hz, SF Word = 68 REFERENCE INPUTS (REFIN1 AND REFIN2) REFIN(+) to REFIN(–) Voltage 2.5 V nom REFIN Refers to Both REFIN1 and REFIN2 REFIN(+) to REFIN(–) Range2 1 V min AV V max DD REFIN Common-Mode Range AGND – 30 mV V min AV + 30 mV V max DD Reference DC Input Current 0.5 µA/V typ Reference DC Input Current Drift ±0.1 nA/V/°C typ Normal-Mode Rejection2 @ 50 Hz 100 dB min 50 Hz ± 1 Hz, SF Word = 82 @ 60 Hz 100 dB min 60 Hz ± 1 Hz, SF Word = 68 Common-Mode Rejection Input Range = ±2.56V @ DC 100 dB typ Analog Input = 1 V. Input Range = ±2.56V @ 50 Hz 100 dB typ @ 60 Hz 100 dB typ –6– REV. 0

AD7708/AD7718 Parameter B Grade Unit Test Conditions AD7708 (CHOP ENABLED) Output Update Rate 5.4 Hz min CHOP = 1 105 Hz max 0.732 ms Increments No Missing Codes2 16 Bits min 20 Hz Update Rate Resolution 13 Bits p-p ±20 mV Range, 20 Hz Update Rate 16 Bits p-p ±2.56V Range, 20 Hz Update Rate Output Noise and Update Rates See Tables in ADC Description Integral Nonlinearity ±15 ppm of FSR max 2 ppm Typical Offset Error3 ±3 µV typ Calibration is Accurate to ±0.5 LSB Offset Error Drift vs. Temp4 10 nV/°C typ Full-Scale Error3 ±0.75 LSB typ Includes Positive and Negative ERRORS Gain Drift vs. Temp4 ±0.5 ppm/°C typ ANALOG INPUTS Differential Input Full-Scale Voltage ±1.024 × REFIN/GAIN V nom REFIN Refers to Both REFIN1 and REFIN2. REFIN = REFIN(+) REFIN(–) GAIN = 1 to 128 Range Matching ±2 µV typ Analog Input = 18 mV Absolute AIN Voltage Limits AGND + 100 mV V min AIN1–AIN10 and AINCOM with AV – 100 mV V max NEGBUF = 1 DD Absolute AINCOM Voltage Limits AGND – 30 mV V min NEGBUF = 0 AV + 30 mV V max DD Analog Input Current AIN1–AIN10 and AINCOM with NEGBUF = 1 DC Input Current2 ±1 nA max DC Input Current Drift ±5 pA/°C typ AINCOM Input Current NEGBUF = 0 DC Input Current2 ±125 nA/V typ DC Bias Current Drift ±2 pA/V/°C typ Normal-Mode Rejection2 @ 50 Hz 100 dB min 50Hz± 1 Hz, SF Word= 82 @ 60 Hz 94 dB min 60Hz± 1 Hz, SF Word= 68 Common-Mode Rejection @ DC 90 dB min 100 dB typ, Analog Input = 1 V, Input Range = ±2.56V 110 dB typ on ±20 mV Range @ 50 Hz2 100 dB min 50 Hz ± 1 Hz, 20 Hz Update Rate @ 60 Hz2 100 dB min 60 Hz ± 1 Hz, 20 Hz Update Rate REFERENCE INPUTS (REFIN1 AND REFIN2) REFIN(+) to REFIN(–) Voltage 2.5 V nom REFIN Refers to Both REFIN1 and REFIN2 REFIN(+) to REFIN(–) Range2 1 V min AV V max DD REFIN Common-Mode Range AGND – 30 mV V min AV + 30 mV V max DD Reference DC Input Current2 ±0.5 µA/V typ Reference DC Input Current Drift ±0.01 nA/V/°C typ Normal-Mode Rejection2 @ 50 Hz 100 dB min 50Hz± 1 Hz, SF Word = 82 @ 60 Hz 100 dB min 60Hz± 1 Hz, SF Word = 68 Common-Mode Rejection Input Range = ±2.56V @ DC 110 dB typ Analog Input = 1 V @ 50 Hz 110 dB typ 50 Hz ± 1 Hz, 20 Hz Update Rate @ 60 Hz 110 dB typ 60 Hz ± 1 Hz, 20 Hz Update Rate LOGIC INPUTS5 All Inputs Except SCLK and XTAL12 V , Input Low Voltage 0.8 V max DV = 5 V INL DD 0.4 V max DV = 3 V DD V , Input High Voltage 2.0 V min DV = 3 V or 5 V INH DD REV. 0 –7–

AADD77770188–SPECIFICATIONS1 (AV = 2.7 V to 3.6V or 4.75 V to 5.25 V, DV = 2.7 V to 3.6V or 4.75 V to 5.25 V, REFIN(+) = DD DD 2.5 V ; REFIN(–) = AGND; AGND = DGND = 0 V; XTAL1/XTAL2 = 32.768 kHz Crystal Input Buffer Enabled. All specifications T to T unless otherwise noted.) MIN MAX Parameter B Grade Unit Test Conditions LOGIC INPUTS (Continued) SCLK Only (Schmitt-Triggered Input)2 V 1.4/2 V min/V max DV = 5 V T(+) DD V 0.8/1.4 V min/V max DV = 5 V T(–) DD V –V 0.3/0.85 V min/V max DV = 5 V T(+) T(–) DD V 0.95/2 V min/V max DV = 3 V T(+) DD V 0.4/1.1 V min/V max DV = 3 V T(–) DD V –V 0.3/0.85 V min/V max DV = 3 V T(+) T(–) DD XTAL1 Only2 V , Input Low Voltage 0.8 V max DV = 5 V INL DD V , Input High Voltage 3.5 V min DV = 5 V INH DD V , Input Low Voltage 0.4 V max DV = 3 V INL DD V , Input High Voltage 2.5 V min DV = 3 V INH DD Input Currents ±10 µA max Logic Input = DV DD –70 µA max Logic Input = DGND, Typical –40 µA @ 5 V and –20 µA at 3 V Input Capacitance 10 pF typ All Digital Inputs LOGIC OUTPUTS (Excluding XTAL2)5 V , Output High Voltage2 DV – 0.6 V min DV = 3 V, I = 100 µA OH DD DD SOURCE V , Output Low Voltage2 0.4 V max DV = 3 V, I = 100 µA OL DD SINK V , Output High Voltage2 4 V min DV = 5 V, I = 200 µA OH DD SOURCE V , Output Low Voltage2 0.4 V max DV = 5 V, I = 1.6 mA OL DD SINK Floating State Leakage Current ±10 µA max Floating State Output Capacitance ±10 pF typ Data Output Coding Binary Unipolar Mode Offset Binary Bipolar Mode SYSTEM CALIBRATION2 Full-Scale Calibration Limit 1.05 × FS V max Zero-Scale Calibration Limit –1.05 × FS V min Input Span 0.8 × FS V min 2.1 × FS V max START-UP TIME From Power-On 300 ms typ From Power-Down Mode 1 ms typ 300 ms typ Oscillator Powered Down POWER REQUIREMENTS Power Supply Voltages AV and DV can be operated independently of each other. DD DD AV –AGND 2.7/3.6 V min/max AV = 3 V nom DD DD 4.75/5.25 V min/max AV = 5 V nom DD DV –DGND 2.7/3.6 V min/max DV = 3 V nom DD DD 4.75/5.25 V min DV = 5 V nom DD DI (Normal Mode) 0.55 mA max DV = 3 V, 0.43 mA typ DD DD 0.65 mA DV = 5 V, 0.5 mA typ DD AI (Normal Mode) 1.1 mA AV = 3 V or 5 V, 0.85 mA typ DD DD DI (Power-Down Mode) 10 µA max DV = 3 V, 32.768 kHz Osc. Running DD DD 2 µA max DV = 3 V, Oscillator Powered Down DD 30 µA max DV = 5 V, 32.768 kHz Osc. Running DD 8 µA max DV = 5 V, Oscillator Powered Down DD AI (Power-Down Mode) 1 µA max AV = 3 V or 5 V DD DD Power Supply Rejection (PSR) Input Range = ±2.56V, AIN = 1 V Chop Disabled 70 dB min 95 dB typ Chop Enabled 100 dB typ NOTES 1Temperature range is –40°C to +85°C. 2Not production tested, guaranteed by design and/or characterization data at release. 3Following a self-calibration this error will be in the order of the noise for the programmed gain and update selected. A system calibration will completely remove this error. 4Recalibration at any temperature will remove these errors. 5I/O Port Logic Levels are with respect to AV andAGND. DD Specifications are subject to change without notice. –8– REV. 0

AD7708/AD7718 TIMING CHARACTERISTICS1, 2 (AV = 2.7 V to 3.6V or AV = 5 V (cid:4) 5%; DV = 2.7 V to 3.6V or DV = 5 V (cid:4) 5%; AGND = DD DD DD DD DGND = 0 V; XTAL = 32.768 kHz; Input Logic 0 = 0 V, Logic 1 = DV unless otherwise noted. DD Limit at T , T MIN MAX Parameter (B Version) Unit Conditions/Comments t 32.768 kHz typ Crystal Oscillator Frequency 1 t 50 ns min RESET Pulsewidth 2 Read Operation t 0 ns min RDY to CS Setup Time 3 t 0 ns min CS Falling Edge to SCLK Active Edge Setup Time3 4 t 4 0 ns min SCLK Active Edge to Data Valid Delay3 5 60 ns max DV = 4.5 V to 5.5 V DD 80 ns max DV = 2.7 V to 3.6V DD t 4, 5 0 ns min CS Falling Edge to Data Valid Delay3 5A 60 ns max DV = 4.5 V to 5.5 V DD 80 ns max DV = 2.7 V to 3.6V DD t 100 ns min SCLK High Pulsewidth 6 t 100 ns min SCLK Low Pulsewidth 7 t 0 ns min CS Rising Edge to SCLK Inactive Edge Hold Time3 8 t 6 10 ns min Bus Relinquish Time after SCLK Inactive Edge3 9 80 ns max t 100 ns max SCLK Active Edge to RDY High3, 7 10 Write Operation t 0 ns min CS Falling Edge to SCLK Active Edge Setup Time3 11 t 30 ns min Data Valid to SCLK Edge Setup Time 12 t 25 ns min Data Valid to SCLK Edge Hold Time 13 t 100 ns min SCLK High Pulsewidth 14 t 100 ns min SCLK Low Pulsewidth 15 t 0 ns min CS Rising Edge to SCLK Edge Hold Time 16 NOTES 1Sample tested during initial release to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of DV ) and timed from a voltage DD level of 1.6V. 2See Figures 1 and 2. 3SCLK active edge is falling edge of SCLK. 4These numbers are measured with the load circuit of Figure 1 and defined as the time required for the output to cross the V or V limits. OL OH 5This specification only comes into play if CS goes low while SCLK is low. It is required primarily for interfacing to DSP machines. 6These numbers are derived from the measured time taken by the data output to change 0.5V when loaded with the load circuit of Figure 1. The measured number is then extrapolated back to remove effects of charging or discharging the 50 pF capacitor. This means that the times quoted in the timing characteristics are the true bus relinquish times of the part and as such are independent of external bus loading capacitances. 7RDY returns high after the first read from the device after an output update. The same data can be read again, if required, while RDY is high, although care should be taken that subsequent reads do not occur close to the next output update. Specifications subject to change without notice. ISINK1(10.06(cid:3)mAA WWIITTHH DDVVDDDD == 35VV) TO OUTPUT 1.6V PIN 50pF ISOURCE (200(cid:3)A WITH DVDD = 5V 100(cid:3)A WITH DVDD = 3V) Figure 1.Load Circuit for Timing Characterization REV. 0 –9–

AD7708/AD7718 ABSOLUTE MAXIMUM RATINGS* Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . 150°C (TA = 25°C unless otherwise noted) SOIC Package AV to AGND . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V θ Thermal Impedance . . . . . . . . . . . . . . . . . . . 71.4°C/W DD JA AV to DGND . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V θ Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 23°C/W DD JC DV to AGND . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V TSSOP Package DD DV to DGND . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V θ Thermal Impedance . . . . . . . . . . . . . . . . . . . 97.9°C/W DD JA AGND to DGND . . . . . . . . . . . . . . . . . . –0.05 V to +0.05 V θ Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 14°C/W JC AV to DV . . . . . . . . . . . . . . . . . . . . . . . . . –5 V to +5 V Lead Temperature, Soldering DD DD Analog Input Voltage to AGND . . . . –0.3 V to AV +0.3 V Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . . 215°C DD Reference Input Voltage to AGND . . –0.3 V to AV +0.3 V Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220°C DD Total AIN/REFIN Current (Indefinite) . . . . . . . . . . . . 30 mA *Stresses above those listed under Absolute Maximum Ratings may cause perma- Digital Input Voltage to DGND . . . . –0.3 V to DVDD +0.3 V nent damage to the device. This is a stress rating only; functional operation of the Digital Output Voltage to DGND . . . –0.3 V to DV +0.3 V device at these or any other conditions above those listed in the operational DD Operating Temperature Range . . . . . . . . . . . –40°C to +85°C sections of this specification is not implied. Exposure to absolute maximum rating Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C conditions for extended periods may affect device reliability. ORDERING GUIDE Temperature Package Package Model Range Description Option AD7708BR –40°C to +85°C SOIC R-28 AD7708BRU –40°C to +85°C TSSOP RU-28 EVAL-AD7708EB Evaluation Board AD7718BR –40°C to +85°C SOIC R-28 AD7718BRU –40°C to +85°C TSSOP RU-28 EVAL-AD7718EB Evaluation Board CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily WARNING! accumulate on the human body and test equipment and can discharge without detection. Although the AD7708/AD7718 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. ESD SENSITIVE DEVICE –10– REV. 0

AD7708/AD7718 CS t11 t14 t16 SCLK t t 15 12 t 13 DIN MSB LSB Figure 2.Write Cycle Timing Diagram RDY t3 t10 CS t4 t6 t8 SCLK t t7 t6 5 t5A t9 DOUT MSB LSB Figure 3.Read Cycle Timing Diagram REV. 0 –11–

AD7708/AD7718 PIN FUNCTION DESCRIPTIONS Pin No Mnemonic Function 1 AIN7 Analog Input Channel 7. Programmable-gain analog input that can be used as a pseudo- differential input when used with AINCOM, or as the positive input of a fully-differential input pair when used with AIN8. (See ADC Control Register section.) 2 AIN8 Analog Input Channel 8. Programmable-gain analog input that can be used as a pseudo- differential input when used with AINCOM, or as the negative input of a fully-differential input pair when used with AIN7. (See ADC Control Register section.) 3 AV Analog Supply Voltage DD 4 AGND Analog Ground 5 REFIN1(–) Negative Reference Input. This reference input can lie anywhere between AGND and AV – 1 V. DD 6 REFIN1(+) Positive reference input. REFIN(+) can lie anywhere between AV and AGND. The nominal DD reference voltage [REFIN(+)–REFIN(–)] is 2.5 V but the part is functional with a reference range from 1 V to AV . DD 7 AIN1 Analog Input Channel 1. Programmable-gain analog input that can be used as a pseudo- differential input when used with AINCOM, or as the positive input of a fully-differential input pair when used with AIN2. (See ADC Control Register Section.) 8 AIN2 Analog Input Channel 2. Programmable-gain analog input that can be used as a pseudo- differential input when used with AINCOM, or as the negative input of a fully-differential input pair when used with AIN1. (See ADC Control Register section.) 9 AIN3 Analog Input Channel 3. Programmable-gain analog input that can be used as a pseudo- differential input when used with AINCOM, or as the positive input of a fully-differential input pair when used with AIN4. (See ADC Control Register section.) 10 AIN4 Analog Input Channel 4. Programmable-gain analog input that can be used as a pseudo- differential input when used with AINCOM, or as the negative input of a fully-differential input pair when used with AIN3. (See ADC Control Register section.) 11 AIN5 Analog Input Channel 5. Programmable-gain analog input that can be used as a pseudo- differential input when used with AINCOM, or as the positive input of a fully-differential input pair when used with AIN6. (See ADC Control Register section ADCCON.) 12 AINCOM All analog inputs are referenced to this input when configured in pseudo-differential input mode. 13 REFIN2(+)/AIN9 Positive reference input/analog input. This input can be configured as a reference input with the same characteristics as REFIN1(+) or as an additional analog input. When configured as an analog input this pin provides a programmable-gain analog input that can be used as a pseudo- differential input when used with AINCOM, or as the positive input of a fully-differential input pair when used with AIN10. (See ADC Control Register section.) 14 REFIN2(–)/AIN10 Negative reference input/analog input. This pin can be configured as a reference or analog input. When configured as a reference input it provides the negative reference input for REFIN2. When configured as an analog input it provides a programmable-gain analog input that can be used as a pseudo-differential input when used with AINCOM, or as the negative input of a fully- differential input pair when used with AIN9. (See ADC Control Register section.) 15 AIN6 Analog Input Channel 6. Programmable-gain analog input that can be used as a pseudo- differential input when used with AINCOM, or as the negative input of a fully-differential input pair when used with AIN5. (See ADC Control Register section.) 16 P2 P2 can act as a general-purpose Input/Output bit referenced between AV and AGND. There DD is a weak pull-up to AV internally on this pin. DD 17 AGND It is recommended that this pin be tied directly to AGND. 18 P1 P1 can act as a general-purpose Input/Output bit referenced between AV and AGND. There DD is a weak pull-up to AV internally on this pin. DD 19 RESET Digital input used to reset the ADC to its power-on-reset status. This pin has a weak pull-up internally to DV . DD 20 SCLK Serial clock input for data transfers to and from the ADC. The SCLK has a Schmitt-trigger input making an opto-isolated interface more robust. The serial clock can be continuous with all data transmitted in a continuous train of pulses. Alternatively, it can be a noncontinuous clock with the information being transmitted to or from the AD7708/AD7718 in smaller batches of data. –12– REV. 0

AD7708/AD7718 Pin No Mnemonic Function 21 CS Chip Select Input. This is an active low logic input used to select the AD7708/AD7718. CS can be used to select the AD7708/AD7718 in systems with more than one device on the serial bus or as a frame synchronization signal in communicating with the device. CS can be hardwired low, allowing the AD7708/AD7718 to be operated in 3-wire mode with SCLK, DIN, and DOUT used to interface with the device. 22 RDY RDY is a logic low status output from the AD7708/AD7718. RDY is low when valid data exists in the data register for the selected channel. This output returns high on completion of a read operation from the data register. If data is not read, RDY will return high prior to the next update indicating to the user that a read operation should not be initiated. The RDY pin also returns low following the completion of a calibration cycle. RDY does not return high after a calibration until the mode bits are written to enabling a new conversion or calibration. 23 DOUT Serial data output with serial data being read from the output shift register of the ADC. The output shift register can contain data from any of the on-chip data, calibration or control registers. 24 DIN Serial Data Input with serial data being written to the input shift register on the AD7708/AD7718 Data in this shift register is transferred to the calibration or control registers within the ADC depending on the selection bits of the Communications register. 25 DGND Ground Reference Point for the Digital Circuitry. 26 DV Digital Supply Voltage, 3 V or 5 V Nominal. DD 27 XTAL2 Output from the 32 kHz Crystal Oscillator or Resonator Inverter. 28 XTAL1 Input to the 32 kHz Crystal Oscillator or Resonator Inverter. PIN CONFIGURATION AIN7 1 28 XTAL1 AIN8 2 27 XTAL2 AVDD 3 26 DVDD AGND 4 25 DGND AD7708/ REFIN1(–) 5 AD7718 24 DIN REFIN1(+) 6 TOP VIEW 23 DOUT AIN1 7 (Not to Scale)22 RDY AIN2 8 21CS AIN3 9 20 SCLK AIN4 10 19 RESET AIN5 11 18 P1 AINCOM 12 17 AGND REFIN2(+)/AIN9 13 16 P2 REFIN2(–)/AIN10 14 15 AIN6 REV. 0 –13–

AD7708/AD7718–Typical Performance Characteristics 8389600 26 AVDD = DVDD = 5V REFIN1(+)–REFIN1(–) = 2.5V 8389400 INPUT RANGE = (cid:4)20mV UPDATE RATE = 19.79Hz CHOP = 0 24 8389200 Min – 8389000 ES 22 D D A O E RE 8388800 NG C COD 8388600 MISSI 20 O 8388400 N 18 8388200 TA = 25(cid:5)C 8388000 RMS NOISE = 0.58(cid:3)V rms VREF = 2.5V 16 0 100 200 300 400 500 600 700 800 900 1000 0 10 20 30 40 50 60 70 80 90 100 110 READING NUMBER UPDATE RATE – Hz TPC 1.AD7718 Typical Noise Plot on ±20 mV Input Range TPC 4.AD7718 No-Missing Codes Performance with 19.79 Hz Update Rate 9 32772 AVDD = DVDD = 5V 8 32771 INPUT RANGE = (cid:4)20mV UPDATE RATE = 19.79Hz 7 32770 6 D32769 A 5 E E R32768 4 OD C32767 3 32766 2 1 32765 VREF = 2.5V TA = 25C 0 32764 9299795 7 71 4951461 53 0 0 100 200 300 400 500 600 700 800 900 1000 3849471 5 82 5704704 83 1 80838484858586 86 8687 87878888888989 8990 91 READING NUMBER 8888888 8 88 8888888 88 8 3333333 3 33 3333333 33 3 8888888 8 88 8888888 88 8 TPC 2.AD7718 Noise Distribution Histogram TPC 5.AD7708 Typical Noise Plot on ±20 mV Input Range 3.0 700 2.5 (cid:4)2.56V RANGE 600 500 V 2.0 (cid:3) E OISE – 1.5 AIVNVRPEDUFD T == R 2D.A5VNVDGD E= =5 V(cid:4)2.56V RRENC400 RMS N 1.0 UTAP D=A 2T5E(cid:5)C RATE = 19.79Hz (cid:4)20mV RANGE OCCU300 200 0.5 100 0 0 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 32766 32767 32768 32769 32770 32771 VREF – V CODE TPC 3.RMS Noise vs. Reference Input TPC 6.AD7708 Noise Histogram (AD7718 andAD7708) –14– REV. 0

AD7708/AD7718 ADC CIRCUIT INFORMATION filter whose primary function is to remove the quantization noise The AD7708/AD7718 incorporates a 10-channel multiplexer introduced at the modulator. The cutoff frequency and deci- with a sigma-delta ADC, on-chip programmable gain amplifier mated output data rate of the filter are programmable via the SF and digital filtering intended for the measurement of wide word loaded to the filter register. The complete signal chain is dynamic range, low frequency signals such as those in weigh-scale, chopped resulting in excellent dc offset and offset drift specifica- strain-gauge, pressure transducer, or temperature measurement tions and is extremely beneficial in applications where drift, noise applications. The AD7708 offers 16-bit resolution while the rejection, and optimum EMI rejection are important factors. AD7718 offers 24-bit resolution. The AD7718 is a pin-for-pin With chopping, the ADC repeatedly reverses its inputs. The compatible version of the AD7708. The AD7718 offers a direct decimated digital output words from the Sinc3 filters, therefore, upgradable path from a 16-bit to a 24-bit system without requiring have a positive offset and negative offset term included. As a any hardware changes and only minimal software changes. result, a final summing stage is included so that each output word from the filter is summed and averaged with the previous These parts can be configured as four/five fully-differential filter output to produce a new valid output result to be written input channels or as eight/ten pseudo-differential input chan- to the ADC data register. The programming of the Sinc3 deci- nels referenced to AINCOM. The channel is buffered and can be programmed for one of eight input ranges from ±20 mV to mation factor is restricted to an 8-bit register SF, the actual ±2.56V. Buffering the input channel means that the part can decimation factor is the register value times 8. The decimated output rate from the Sinc3 filter (and the ADC conversion rate) handle significant source impedances on the analog input and will therefore be that R, C filtering (for noise rejection or RFI reduction) can be placed on the analog inputs if required. These input channels 1 1 are intended to convert signals directly from sensors without the f = × × f need for external signal conditioning. ADC 3 8×SF MOD where The ADC employs a sigma-delta conversion technique to realize up to 24 bits of no missing codes performance. The sigma-delta f in the ADC conversion rate. ADC modulator converts the sampled input signal into a digital pulse SF is the decimal equivalent of the word loaded to the filter train whose duty cycle contains the digital information. A Sinc3 register. programmable low-pass filter is then employed to decimate the f is the modulator sampling rate of 32.768 kHz. modulator output data stream to give a valid data conversion result MOD at programmable output rates. The signal chain has two modes The chop rate of the channel is half the output data rate: of operation, CHOP enabled and CHOP disabled. The CHOP bit in the mode register enables and disables the chopping scheme. f = 1 CHOP 2× f Signal Chain Overview (CHOP Enabled, CHOP = 0) ADC With CHOP = 0, chopping is enabled, this is the default and gives As shown in the block diagram, the Sinc3 filter outputs alter- optimum performance in terms of drift performance. With chopping nately contain +V and –V , where V is the respective OS OS OS enabled, the available output rates vary from 5.35Hz (186.77 ms) channel offset. This offset is removed by performing a running to 105.03 Hz (9.52 ms).A block diagram of the ADC input average of two. This average by two means that the settling time channel with chop enabled is shown in Figure 4. to any change in programming of the ADC will be twice the The sampling frequency of the modulator loop is many times normal conversion time, while an asynchronous step change on higher than the bandwidth of the input signal. The integrator in the analog input will not be fully reflected until the third subse- the modulator shapes the quantization noise (which results from quent output. the analog-to-digital conversion) so that the noise is pushed 2 toward one-half of the modulator frequency. The output of the t = =2×t sigma-delta modulator feeds directly into the digital filter. The SETTLE fADC ADC digital filter then band-limits the response to a frequency signifi- The allowable range for SF is 13 to 255 with a default of 69 cantly lower than one-half of the modulator frequency. In this (45H). The corresponding conversion rates, conversion times, manner, the 1-bit output of the comparator is translated into a and settling times are shown in Table I. Note that the conver- band limited, low noise output from the AD7708/AD7718 ADC. sion time increases by 0.732 ms for each increment in SF. The AD7708/AD7718 filter is a low-pass, Sinc3 or (sinx/x)3 f f f f f CHOP IN MOD CHOP ADC AN IANLPOUGT MUX BUF PGA M(cid:1)O-(cid:2)D0 XOR (8 (cid:6)1 SF(cid:1)(3 3 (cid:6)(8 (cid:6) SF ) 12(cid:1) DOIUGTITPAULT SINC 3 FILTER AIN + VOS AIN – VOS Figure 4.ADC Channel Block Diagram with CHOP Enabled REV. 0 –15–

AD7708/AD7718 Table I. ADC Conversion and Settling Times for Various 0 SF Words with CHOP = 0 –20 SF Data Update Rate Settling Time –40 Word f (Hz) t (ms) ADC SETTLE –60 B 13 105.3 19.04 – d –80 2237 5590..3566 3339..6595 ATION –100 45 30.3 65.9 NU–120 E T 69 (Default) 19.79 101.07 AT–140 91 15 133.1 –160 182 7.5 266.6 –180 255 5.35 373.54 –200 0 50 100 150 200 250300 350 400 450 500 550 600650700 The overall frequency response is the product of a sinc3 and a FREQUENCY – Hz sinc response. There are sinc3 notches at integer multiples of 3 × fADC and there are sinc notches at odd integer multiples SOFU T=P 1U3T DATA RATE = 105Hz of f /2. The 3 dB frequency for all values of SF obeys the INPUT BANDWIDTH = 25.2Hz ADC FIRST NOTCH = 52.5Hz following equation: 50Hz REJECTION = –23.6dB, 50Hz(cid:4)1Hz REJECTION = –20.5dB 60Hz REJECTION = –14.6dB, 60Hz(cid:4)1Hz REJECTION = –13.6dB f (3 dB) = 0.24 × f ADC Figure 5.Filter Profile with SF = 13 Normal-mode rejection is the major function of the digital filter on the AD7708/AD7718. The normal mode 50 ±1 Hz rejection 0 with an SF word of 82 is typically –100dB. The 60 ± 1 Hz rejection with SF = 68 is typically –100dB. Simultaneous 50 Hz –20 and 60 Hz rejection of better than 60dB is achieved with an SF –40 of 69. Choosing an SF word of 69 places notches at both 50 Hz and 60 Hz. Figures 5 to 9 show the filter rejection for a selection dB –60 of SF words. N – The frequency response of the filter H (f) is as follows: ATIO –80 U  1 ×sin(SF×8×π× f/fMOD) 3×1×sin(2×π×f/fOUT)  ATTEN–100 SF×8 sin(π× f/f )  2 sin(π× f/f )  –120 MOD OUT where –140 f = 32,768 Hz, MOD –160 SF = value programmed into SF Register, 0 10 20 30 40 50 60 70 80 90 100 FREQUENCY – Hz f = f /(SF × 8 × 3). OUT MOD SF = 82 The following plots show the filter frequency response for a OUTPUT DATA RATE = 16.65Hz INPUT BANDWIDTH = 4Hz variety of update rates from 5Hz to 105Hz. 50Hz REJECTION = –171dB, 50Hz(cid:4)1Hz REJECTION = –100dB 60Hz REJECTION = –58dB, 60Hz(cid:4)1Hz REJECTION = –53dB Figure 6.Filter Profile with SF = 82 –16– REV. 0

AD7708/AD7718 0 0 –20 –20 –40 –40 B ON – d –60 N – dB –60 UATI –80 ATIO –80 N U TE–100 EN–100 AT TT A –120 –120 –140 –140 –160 –160 0 10 20 30 40 50 60 70 80 90 100 0 10 20 30 40 50 60 70 80 90 100 FREQUENCY – Hz FREQUENCY – Hz SF = 255 SF = 68 OUTPUT DATA RATE = 5.35Hz OUTPUT DATA RATE = 20.07Hz 6I5N00PHHUzz TRR BEEAJJEENCCDTTWIIOOIDNNT ==H ––=97 143.dd2BB8,,H 65z00HHzz(cid:4)(cid:4)11HHzz RREEJJEECCTTIIOONN == ––9683ddBB I56N00PHHUzz TRR BEEAJJEENCCDTTWIIOOIDNNT ==H ––=71 444.7d8dB2B,H 5,z 60H0Hz(cid:4)z(cid:4)11HHz zR REEJEJECCTTIOIONN = = – –5140.61ddBB Figure 7.Filter Profile with SF = 255 Figure 9.Filter Profile with SF = 68 0 ADC NOISE PERFORMANCE CHOP ENABLED (CHOP = 0) –20 Tables II to V show the output rms noise and output peak-to- peak resolution in bits (rounded to the nearest 0.5 LSB) for a –40 selection of output update rates. The numbers are typical and dB –60 generated at a differential input voltage of 0 V with AVDD = N – DVDD = 5 V and using a 2.5 V reference. The output update TIO –80 rate is selected via the SF7–SF0 bits in the Filter Register. It is A U important to note that the peak-to-peak resolution figures repre- N–100 E T sent the resolution for which there will be no code flicker within T A –120 a six-sigma limit. The output noise comes from two sources. The first is the electrical noise in the semiconductor devices (device –140 noise) used in the implementation of the modulator. Secondly, when the analog input is converted into the digital domain, –160 0 10 20 30 40 50 60 70 80 90 100 quantization noise is added. The device noise is at a low level FREQUENCY – Hz and is independent of frequency. The quantization noise starts at SF = 69 OUTPUT DATA RATE = 19.8Hz an even lower level but rises rapidly with increasing frequency to INPUT BANDWIDTH = 4.74Hz become the dominant noise source. The numbers in the tables FIRST NOTCH = 9.9Hz 50Hz REJECTION = –66dB, 50Hz(cid:4)1Hz REJECTION = –60dB are given for the bipolar input ranges. For the unipolar ranges 60Hz REJECTION = –117dB, 60Hz(cid:4)1Hz REJECTION = –94dB the rms noise numbers will be the same as the bipolar range, but Figure 8.Filter Profile with Default SF = 69 Giving Filter the peak-to-peak resolution is now based on half the signal range Notches at Both 50 Hz and 60 Hz which effectively means losing one bit of resolution. REV. 0 –17–

AD7708/AD7718 Table II. Typical Output RMS Noise vs. Input Range and Update Rate for AD7718 with Chop Enabled (CHOP = 0); Output RMS Noise in (cid:3)V SF Data Update Input Range Word Rate (Hz) (cid:4)20 mV (cid:4)40 mV (cid:4)80 mV (cid:4)160 mV (cid:4)320 mV (cid:4)640 mV (cid:4)1.28 V (cid:4)2.56V 13 105.3 1.50 1.50 1.60 1.75 3.50 4.50 6.70 11.75 23 59.36 1.0 1.02 1.06 1.15 1.22 1.77 3.0 5.08 27 50.56 0.95 0.95 0.98 1.00 1.10 1.66 5.0 69 19.79 0.60 0.65 0.65 0.65 0.65 0.95 1.40 2.30 255 5.35 0.35 0.35 0.37 0.37 0.37 0.51 0.82 1.25 Table III. Peak-to-Peak Resolution vs. Input Range and Update Rate for AD7718 with Chop Enabled (CHOP = 0); Peak-to-Peak Resolution in Bits SF Data Update Input Range Word Rate (Hz) (cid:4)20 mV (cid:4)40 mV (cid:4)80 mV (cid:4)160 mV (cid:4)320 mV (cid:4)640 mV (cid:4)1.28 V (cid:4)2.56V 13 105.3 12 13 14 15 15 15.5 16 16 23 59.36 12.5 13.5 14.5 15 16 17 17 17 27 50.56 12.5 13.5 14.5 15.5 16.5 17 17 17 69 19.79 13 14 15 16 17 17.5 18 18.5 255 5.35 14 15 16 17 18 18.5 18.8 19.2 Table IV. Typical Output RMS Noise vs. Input Range and Update Rate for AD7708 with Chop Enabled (CHOP = 0); Output RMS Noise in (cid:3)V SF Data Update Input Range Word Rate (Hz) (cid:4)20 mV (cid:4)40 mV (cid:4)80 mV (cid:4)160 mV (cid:4)320 mV (cid:4)640 mV (cid:4)1.28 V (cid:4)2.56V 13 105.3 1.50 1.50 1.60 1.75 3.50 4.50 6.70 11.75 23 59.36 1.0 1.02 1.06 1.15 1.22 1.77 3.0 5.08 27 50.56 0.95 0.95 0.98 1.00 1.10 1.66 5.0 69 19.79 0.60 0.65 0.65 0.65 0.65 0.95 1.40 2.30 255 5.35 0.35 0.35 0.37 0.37 0.37 0.51 0.82 1.25 Table V. Peak-to-Peak Resolution vs. Input Range and Update Rate for AD7708 with Chop Enabled (CHOP = 0); Peak-to-Peak Resolution in Bits SF Data Update Input Range Word Rate (Hz) (cid:4)20 mV (cid:4)40 mV (cid:4)80 mV (cid:4)160 mV (cid:4)320 mV (cid:4)640 mV (cid:4)1.28 V (cid:4)2.56V 13 105.3 12 13 14 15 15 15.5 16 16 23 59.35 12.5 13.5 14.5 15 16 16 16 16 27 50.56 12.5 13.5 14.5 15.5 16 16 16 16 69 19.79 13 14 15 16 16 16 16 16 255 5.35 14 15 16 16 16 16 16 16 –18– REV. 0

AD7708/AD7718 SIGNAL CHAIN OVERVIEW CHOP DISABLED Table VI. ADC Conversion and Settling Times for Various (CHOP = 1) SF Words with CHOP = 1 With CHOP =1 chopping is disabled. With chopping disabled SF Data Update Rate Settling Time the available output rates vary from 16.06 Hz (62.26ms) to Word f (Hz) t (ms) ADC SETTLE 1365.33 Hz (0.73 ms). The range of applicable SF words is from 3 to 255. When switching between channels with chop disabled, 03 1365.33 2.20 the channel throughput is increased by a factor of two over the 68 60.2 49.8 case where chop is enabled. When used in multiplexed applica- 69 (Default) 59.36 50.54 tions operation with chop disabled will offer the best throughput 75 54.6 54.93 time when cycling through all channels. The drawback with 82 49.95 60 chop disabled is that the drift performance is degraded and 151 27.13 110.6 calibration is required following a gain change or significant 255 16.06 186.76 temperature change. A block diagram of the ADC input The frequency response of the digital filter H (f) is as follows: channel with chop disabled is shown in Figure 10. The signal chain includes a mux, buffer, PGA, sigma-delta modu- lator, and digital filter. The modulator bit stream is applied to  1 × sin(SF×8×π × f/fMOD) 3 a Sinc3 filter. The programming of the Sinc3 decimation SF×8 sin(π× f/f )  MOD factor is restricted to an 8-bit register SF, the actual decima- tion factor is the register value times 8. The decimated output where rate from the Sinc3 filter (and the ADC conversion rate) will there- f = 32,768 Hz, MOD fore be: SF = value programmed into SF SFR. f The following shows plots of the filter frequency response using fADC = 8×MOSDF different SF words for output data rates of 16 Hz to 1.36 kHz. There are sinc3 notches at integer multiples of the update rate. where The 3 dB frequency for all values of SF obeys the following fADC is the ADC conversion rate, equation: SF is the decimal equivalent of the word loaded to the filter f (3 dB) = 0.262 × f register, valid range is from 3 to 255, ADC f is the modulator sampling rate of 32.768 kHz. The following plots show frequency response of the AD7708/ MOD AD7718 digital filter for various filter words. The AD7708/ The settling time to a step input is governed by the digital filter. AD7718 are targeted at multiplexed applications. One of the A synchronized step change will require a settling time of three key requirements in these applications is to optimize the SF times the programmed update rate, a channel change can be word to obtain the maximum filter rejection at 50 Hz and 60 Hz treated as a synchronized step change. An unsynchronized step while minimizing the channel throughput rate. Figure 12 shows change will require four outputs to reflect the new analog input the AD7708/AD7718 optimized throughput while maximizing at its output. 50 Hz and 60 Hz rejection. This is achieved with an SF word of 3 75. In Figure 13, by using a higher SF word of 151, 50 Hz and tSETTLE = f =3×tADC 60 Hz rejection can be maximized at 60dB with a channel ADC throughput rate of 110 ms. An SF word of 255 gives maximum The allowable range for SF is 3 to 255 with a default of 69 rejection at both 50 Hz and 60 Hz but the channel throughput (45H). The corresponding conversion rates, conversion times, rate is restricted to 186ms as shown in Figure 14. and settling times are shown in Table VI. Note that the conver- sion time increases by 0.245 ms for each increment in SF. f f f IN MOD ADC AN IANLPOUGT MUX BUF PGA (cid:1)-(cid:2) SINC3 FILTER DOIUGTITPAULT MOD0 Figure 10.ADC Channel Block Diagram with CHOP Disabled REV. 0 –19–

AD7708/AD7718 0 0 –20 –20 –40 –40 –60 –60 B B – d –80 – d –80 N N TIO–100 TIO–100 A A NU–120 NU–120 E E T T AT–140 AT–140 –160 –160 –180 –180 –200 –200 0 10 20 30 40 50 60 70 80 90 100 0 10 20 30 40 50 60 70 80 90 100 FREQUENCY – Hz FREQUENCY – Hz SF = 68 SF = 151 OUTPUT DATA RATE = 60.2Hz OUTPUT DATA RATE = 27.12Hz SETTLING TIME = 49.8ms SETTLING TIME = 110ms INPUT BANDWIDTH = 15.5Hz INPUT BANDWIDTH = 27.12Hz 50Hz REJECTION = –43dB, 50Hz(cid:4)1Hz REJECTION = –40dB 50Hz REJECTION = –65.4dB, 50Hz(cid:4)1Hz REJECTION = –60dB 60Hz REJECTION = –147dB, 60Hz(cid:4)1Hz REJECTION = –101dB 60Hz REJECTION = –63dB, 60Hz(cid:4)1Hz REJECTION = –60dB Figure 11.Frequency Response Operating with the Figure 13.Optimizing Filter Response for Maximum SF Word of 68 Simultaneous 50 Hz and 60 Hz Rejection 0 0 –20 –20 –40 –40 –60 –60 B B – d –80 – d –80 N N ATIO–100 ATIO–100 NU–120 NU–120 E E T T AT–140 AT–140 –160 –160 –180 –180 –200 –200 0 10 20 30 40 50 60 70 80 90 100 0 10 20 30 40 50 60 70 80 90 100 FREQUENCY – Hz FREQUENCY – Hz SF = 75 SF = 255 OUTPUT DATA RATE = 54.6Hz OUTPUT DATA RATE = 16.06Hz SETTLING TIME = 55ms SETTLING TIME = 186ms INPUT BANDWIDTH = 14.3Hz INPUT BANDWIDTH = 4.21Hz 50Hz REJECTION = –62.5dB, 50Hz(cid:4)1Hz REJECTION = –57dB 50Hz REJECTION = –87dB, 50Hz(cid:4)1Hz REJECTION = –77dB 60Hz REJECTION = –63dB, 60Hz(cid:4)1Hz REJECTION = –60dB 60Hz REJECTION = –72dB, 60Hz(cid:4)1Hz REJECTION = –68dB Figure 12.Optimizing Filter Response for Throughput Figure 14.Frequency with Maximum SF Word = 255 while Maximizing the Simultaneous 50 Hz and 60 Hz Rejection ADC NOISE PERFORMANCE CHOP DISABLED (CHOP = 1) Tables VII to X show the output rms noise and output peak-to- when the analog input is converted into the digital domain, peak resolution in bits (rounded to the nearest 0.5 LSB) for quantization noise is added. The device noise is at a low level some typical output update rates. The numbers are typical and and is independent of frequency. The quantization noise starts generated at a differential input voltage of 0 V. The output update at an even lower level but rises rapidly with increasing frequency rate is selected via the SF7–SF0 bits in the Filter Register. It is to become the dominant noise source. The numbers in the important to note that the peak-to-peak resolution figures represent tables are given for the bipolar input ranges. For the unipolar the resolution for which there will be no code flicker within a ranges the rms noise numbers will be the same as the bipolar six-sigma limit. The output noise comes from two sources. The range, but the peak-to-peak resolution is now based on half the first is the electrical noise in the semiconductor devices (device signal range which effectively means losing 1 bit of resolution. noise) used in the implementation of the modulator. Secondly, –20– REV. 0

AD7708/AD7718 Table VII. Typical Output RMS Noise vs. Input Range and Update Rate for AD7718 with Chop Disabled (CHOP = 1); Output RMS Noise in (cid:3)V SF Data Update Input Range Word Rate (Hz) (cid:4)20 mV (cid:4)40 mV (cid:4)80 mV (cid:4)160 mV (cid:4)320 mV (cid:4)640 mV (cid:4)1.28 V (cid:4)2.56V 03 1365.33 30.31 29.02 58.33 112.7 282.44 361.72 616.89 1660 13 315.08 2.47 2.49 2.37 3.87 7.18 12.61 16.65 32.45 66 62.06 0.743 0.852 0.9183 0.8788 0.8795 1.29 1.99 3.59 69 59.38 0.961 0.971 0.949 0.922 0.923 1.32 2.03 3.73 81 50.57 0.894 0.872 0.872 0.806 0.793 1.34 2.18 2.96 255 16.06 0.475 0.468 0.434 0.485 0.458 0.688 1.18 1.78 Table VIII. Peak-to-Peak Resolution vs. Input Range and Update Rate for AD7718 with Chop Disabled (CHOP = 1); Peak-to-Peak Resolution in Bits SF Data Update Input Range Word Rate (Hz) (cid:4)20 mV (cid:4)40 mV (cid:4)80 mV (cid:4)160 mV (cid:4)320 mV (cid:4)640 mV (cid:4)1.28 V (cid:4)2.56V 03 1365.33 8 9 9 9 9 9 9 9 13 315.08 11 12 14 14 14 14 15 15 66 62.06 13 14 15 16 17 17 18 18 69 59.36 13 14 15 16 17 17 18 18 81 50.57 13 14 15 16 17 17 18 18 255 16.06 14 15 16 17 18 18 19 19 Table IX. Typical Output RMS Noise vs. Input Range and Update Rate for AD7708 with Chop Disabled (CHOP = 1); Output RMS Noise in (cid:3)V SF Data Update Input Range Word Rate (Hz) (cid:4)20 mV (cid:4)40 mV (cid:4)80 mV (cid:4)160 mV (cid:4)320 mV (cid:4)640 mV (cid:4)1.28 V (cid:4)2.56V 03 1365.33 30.31 29.02 58.33 112.7 282.44 361.72 616.89 1660 13 315.08 2.47 2.49 2.37 3.87 7.18 12.61 16.65 32.45 66 62.06 0.743 0.852 0.9183 0.8788 0.8795 1.29 1.99 3.59 69 59.38 0.961 0.971 0.949 0.922 0.923 1.32 2.03 3.73 81 50.57 0.894 0.872 0.872 0.806 0.793 1.34 2.18 2.96 255 16.06 0.475 0.468 0.434 0.485 0.458 0.688 1.18 1.78 Table X. Peak-to-Peak Resolution vs. Input Range and Update Rate for AD7708 with Chop Disabled (CHOP = 1); Peak-to-Peak Resolution in Bits SF Data Update Input Range Word Rate (Hz) (cid:4)20 mV (cid:4)40 mV (cid:4)80 mV (cid:4)160 mV (cid:4)320 mV (cid:4)640 mV (cid:4)1.28 V (cid:4)2.56V 03 1365.33 8 9 9 9 9 9 9 9 13 315.08 11 12 14 14 14 14 15 15 66 62.06 13 14 15 16 16 16 16 16 69 59.36 13 14 15 16 16 16 16 16 81 50.57 13 14 15 16 16 16 16 16 255 16.06 14 15 16 16 16 16 16 16 REV. 0 –21–

AD7708/AD7718 ON-CHIP REGISTERS port. The filter register is a read/write register used to program The AD7708 and AD7718 are controlled and configured via the data update rate of the converter. The ADC Data register is a number of on-chip registers which are shown in Figure 15. a read only register that contains the result of a data conversion The first of these registers is the communications register on the selected channel. The ADC offset registers are read/write which is used to control all operations on these converters. All registers that contain the offset calibration data. There are five communications with these parts must start with a write to offset registers, one for each of the fully differential input channels. the communications register to specify the next operation to When configured for pseudo-differential input mode the chan- be performed. After a power-on or RESET, the device defaults nels share offset registers. The ADC gain registers are read/write to waiting for a write to the communications register. The registers that contain the gain calibration data. There are five STATUS register contains information pertaining to the operat- ADC gain registers, one for each of the fully differential input ing conditions of the converter. The STATUS register is a read channels. When configured for pseudo differential input mode only register. The MODE register is used to configure the con- the channels share gain registers. The ADC contains Test registers version mode, calibration, chop enable/disable, reference select, for factory use only, the user is advised not to alter the oper- channel configuration and buffered or unbuffered operation on ating conditions of these registers. The ID register is a read only the AINCOM analog input. The MODE register is a read/write register and is used for silicon identification purposes. The follow- register. The ADC Control register is a read/write register used ing sections contains more in-depth detail on all of these registers. to select the active channel and program its input range and In the following descriptions, SET implies a Logic 1 state and bipolar/unipolar operation. The I/O control register is a read/ CLEARED implies a Logic 0 state unless otherwise stated. write register used to configure the operation of the 2-pin I/O COMMUNICATIONS REGISTER DIN DIN WEN R/W 0 0 A3 A2 A1 A0 DOUT DOUT STATUS REGISTER DIN DOUT MODE REGISTER DIN DOUT ADC CONTROL REGISTER DIN DOUT I/O CONTROL REGISTER REGISTER SELECT DIN DECODER DOUT FILTER REGISTER DOUT ADC DATA REGISTER DIN DOUT ADC OFFSET REGISTER DIN DOUT ADC GAIN REGISTER DIN DOUT TEST REGISTER DOUT ID REGISTER Figure 15.On-Chip Registers –22– REV. 0

AD7708/AD7718 Table XI. Registers—Quick Reference Guide Power-On/Reset Register Name Type Size Default Value Function Communications Write Only 8 Bits Not Applicable All operations to other registers are initiated through the Communications Register. This controls whether CR7 CR6 CR5 CR4 CR3 CR2 CR1 CR0 subsequent operations are read or write operations and also selects the register for that subsequent WEN R/W 0(0) 0(0) A3(0) A2(0) A1(0) A0(0) operation. Status Register Read Only 8 Bits 00 Hex Provides status information on conversions, calibra- tions and error conditions. MSB LSB RDY 0 CAL 0 ERR 0 0 LOCK Mode Register Read/Write 8 Bits 00 Hex Controls functions such as mode of operation, chan- nel configuration, oscillator operation in power-down. MSB LSB CHOP NEGBUF REFSEL CHCON OSCPD MD2 MD1 MD0 ADC (ADCCON) Control Register Read/Write 8 Bits 07 Hex This register is used to select the active channel input, configure the operating input range, and select MSB LSB unipolar or bipolar operation. CH3 CH2 CH1 CH0 U/B RN2 RN1 RN0 I/O (IOCON) I/O Control Register Read/Write 8 Bits 00 Hex This register is used to control and configure the I/O port. MSB LSB 0 0 P2DIR P1DIR 0 0 P2DAT P1DAT Filter Register Read/Write 8 Bits 45 Hex This register determines the amount of averaging performed by the sinc filter and consequently deter- MSB LSB mines the data update rate of the AD7708/AD7718. The filter register determines the update rate for SF7 SF6 SF5 SF4 SF3 SF2 SF1 SF0 operation with CHOP enabled and CHOP disabled. AD7718 ADC (DATA) Data Register Read Only 24 Bits 000000 Hex Provides the most up-to-date conversion result for the selected channel on the AD7718. AD7708 (DATA) Data Register Read Only 16 Bits 0000 Hex Provides the most up-to-date conversion result for the selected channel on the AD7708. REV. 0 –23–

AD7708/AD7718 Table XI. Registers—Quick Reference Guide (continued) Power-On/Reset Register Name Type Size Default Value Function AD7718 Offset Register Read/Write 24 Bits 800 000 Hex Contains a 24-bit word which is the offset calibration coefficient for the part. The contents of this register are used to provide offset correction on the output from the digital filter. There are five Offset Registers on the part and these are associated with input chan- nels as outlined in the ADCCON register. AD7718 Gain Register Read/Write 24 Bits 5XXXX5 Hex Contains a 24-bit word which is the gain calibration coefficient for the part. The contents of this register are used to provide gain correction on the output from the digital filter. There are five Gain Registers on the part and these are associated with input chan- nels as outlined in the ADCCON register. AD7708 Offset Register Read/Write 16 Bits 8000 Hex Contains a 16-bit word which is the offset calibration coefficient for the part. The contents of this register are used to provide offset correction on the output from the digital filter. There are five Offset Registers on the part and these are associated with input chan- nels as outlined in the ADCCON register. AD7708 Gain Register Read/Write 16 Bits 5XXX Hex Contains a 16-bit word which is the gain calibration coefficient for the part. The contents of this register are used to provide gain correction on the output from the digital filter. There are five Gain Registers on the part and these are associated with input chan- nels as outlined in the ADCCON register. AD7708 ID Register Read 8 Bits 5X Hex Contains an 8-bit byte which is the identifier for the part. AD7718 ID Register Read 8 Bits 4X Hex Contains an 8-bit byte which is the identifier for the part. Test Registers Read/Write 16 Bits 0000 Hex Controls the test modes of the part that are used when testing the part. The user is advised not to change the contents of these registers. –24– REV. 0

AD7708/AD7718 Communications Register (A3, A2, A1, A0 = 0, 0, 0, 0) The Communications Register is an 8-bit write-only register. All communications to the part must start with a write operation to the Communications Register. The data written to the Communications Register determines whether the next operation is a read or write operation, the type of read operation, and on which register this operation takes place. For read or write operations, once the subse- quent read or write operation to the selected register is complete, the interface returns to where it expects a write operation to the Communications Register. This is the default state of the interface and, on power-up or after a RESET, the AD7708/AD7718 is in this default state waiting for a write operation to the Communications Register. In situations where the interface sequence is lost, a write operation of at least 32 serial clock cycles with DIN high returns the AD7708/AD7718 to this default state by resetting the part. Table XII outlines the bit designations for the Communications Register. CR0 through CR7 indicate the bit location, CR denoting the bits are in the Communications Register. CR7 denotes the first bit of the data stream. CR7 CR6 CR5 CR4 CR3 CR2 CR1 CR0 WEN(0) R/W(0) 0(0) 0(0) A3(0) A2(0) A1(0) A0(0) Table XII. Communications Register Bit Designations Bit Bit Location Mnemonic Description CR7 WEN Write Enable Bit. A 0 must be written to this bit so the write operation to the Communications Register actually takes place. If a 1 is written to this bit, the part will not clock on to subsequent bits in the regis ter. It will stay at this bit location until a 0 is written to this bit. Once a 0 is written to the WEN bit, the next seven bits will be loaded to the Communications Register. CR6 R/W A zero in this bit location indicates that the next operation will be a write to a specified register. A one in this position indicates that the next operation will be a read from the designated register. CR5 0 A zero must be written to this bit position to ensure correct operation of the AD7708/AD7718. CR4 0 A zero must be written to this bit position to ensure correct operation of the AD7708/AD7718. CR3–CR0 A3–A0 Register Address Bits. These address bits are used to select which of the AD7708/AD7718’s registers are being accessed during this serial interface communication. A3 is the MSB of the three selection bits. Table XIII. Register Selection Table A3 A2 A1 A0 Register 0 0 0 0 Communications Register during a Write Operation 0 0 0 0 Status Register during a Read Operation 0 0 0 1 Mode Register 0 0 1 0 ADC Control Register 0 0 1 1 Filter Register 0 1 0 0 ADC Data Register 0 1 0 1 ADC Offset Register 0 1 1 0 ADC Gain Register 0 1 1 1 I/O Control Register 1 0 0 0 Undefined 1 0 0 1 Undefined 1 0 1 0 Undefined 1 0 1 1 Undefined 1 1 0 0 Test 1 Register 1 1 0 1 Test 2 Register 1 1 1 0 Undefined 1 1 1 1 ID Register REV. 0 –25–

AD7708/AD7718 Status Register (A3, A2, A1, A0 = 0, 0, 0, 0; Power-On-Reset = 00Hex) The ADC Status Register is an 8-bit read-only register. To access the ADC Status Register, the user must write to the Communica- tions Register selecting the next operation to be a read and load Bits A3-A0 with 0, 0, 0,0. Table XIV outlines the bit designations for the Status Register. SR0 through SR7 indicate the bit location, SR denoting the bits are in the Status Register. SR7 denotes the first bit of the data stream. The number in brackets indicates the power-on/reset default status of that bit. SR7 SR6 SR5 SR4 SR3 SR2 SR1 SR0 RDY(0) 0(0) CAL(0) 0(0) ERR(0) 0(0) 0(0) LOCK(0) Table XIV. Status Register Bit Designations Bit Bit Location Mnemonic Description SR7 RDY Ready Bit for the ADC Set when data is transferred to the ADC data registers or on completion of calibration cycle. The RDY bit is cleared automatically a period of time before the data register is updated with a new conversion result or after the ADC data register has been read. This bit is also cleared by a write to the mode bits to indicate a conversion or calibration. The RDY pin is the complement of the RDY bit. SR6 0 Bit is automatically cleared. Reserved for future use SR5 CAL Calibration Status Bit Set to indicate completion of calibration. It is set at the same time that the RDY is set high. Cleared by a write to the mode bits to start another ADC conversion or calibration. SR4 0 This bit is automatically cleared. Reserved for future use SR3 ERR ADC Error Bit Set to indicate that the result written to the ADC data register has been clamped to all zeros or all ones. After a calibration this bit also flags error conditions that caused the calibration registers not to be written. Error sources include Overrange. Cleared by a write to the mode bits to initiate a conversion or calibration. SR2 0 This bit is automatically cleared. Reserved for future use SR1 0 This bit is automatically cleared. Reserved for future use SR0 LOCK PLL Lock Status Bit. Set if the PLL has locked onto the 32.768 kHz crystal oscillator clock. If the user is worried about exact sampling frequencies etc., the LOCK bit should be interrogated and the result discarded if the LOCK bit is zero. –26– REV. 0

AD7708/AD7718 Mode Register (A3, A2, A1, A0 = 0, 0, 0, 1; Power-On-Reset = 00Hex) The Mode Register is an 8-bit register from which data can be read or to which data can be written. This register configures the operating modes of the AD7708/AD7718. TableXV outlines the bit designations for the Mode Register. MR7 through MR0 indi- cate the bit location, MR denoting the bits are in the Mode Register. MR7 denotes the first bit of the data stream. The number in brackets indicates the power-on/reset default status of that bit. MR7 MR6 MR5 MR4 MR3 MR2 MR1 MR0 CHOP(0) NEGBUF(0) REFSEL(0) CHCON(0) OSCPD(0) MD2(0) MD1(0) MD0(0) Table XV. Mode Register Bit Designations Bit Bit Location Mnemonic Description MR7 CHOP If this bit is cleared, chopping is enabled. When this bit is set chopping is disabled. The default is for chop enabled. MR6 NEGBUF This bit controls the operation of the input buffer on the AINCOM input when a channel is config- ured for pseudo-differential mode of operation. If cleared, the analog negative input (AINCOM) is unbuffered allowing it to be tied to AGND in single-ended input configuration. If this bit is set the analog negative input (AINCOM) is buffered, placing a restriction on its common-mode input range. MR5 REFSEL If this bit is cleared, the reference selected is REFIN1(+) and REFIN1(–) for the active channel. If this bit is set, the reference selected is REFIN2(+) and REFIN2(–) for the active channel. The con- tents of the CHCON bit overrides the REFSEL bit. If the ADC is configured in five fully-differential or 10 pseudo-differential input channel mode, the REFSEL bit setting is irrelevant as only one reference input is available. V Select implemented using the REFSEL bit enables the user to REF perform both absolute and ratiometric measurements. MR4 CHCON When cleared the device is configured as an 8-input channel converter, configured as eight pseudo- differential input channels with respect to AINCOM or four differential input arrangements with two reference input selection options. When set the device is configured as a 10 pseudo- differential input or a five differential input channel arrangement with a single reference input option. MR3 OSCPD Oscillator Power-Down Bit. If this bit is set, placing the AD7708/AD7718 in standby mode will stop the crystal oscillator reducing the power drawn by these parts to a minimum. The oscillator will require 300 ms to begin oscillating when the ADC is taken out of standby mode. If this bit is cleared, the oscillator is not shut off when the ADC is put into standby mode and will not require the 300 ms start-up time when the ADC is taken out of standby. MR2–MR0 MD2–MD0 ADC Mode Bits. These bits select the operational mode of the ADC as follows: MD2 MD1 MD0 0 0 0 Power-Down Mode (Power-On Default) 0 0 1 Idle Mode In Idle Mode the ADC filter and modulator are held in a reset state although the modulator clocks are still provided. 0 1 0 Single Conversion Mode In Single Conversion Mode, a single conversion is performed on the enabled channels. On comple- tion of the conversion the ADC data registers are updated, the relevant flags in the STATUS register are written, and idle mode is reentered with the MD2–MD0 being written accordingly to 001. 0 1 1 Continuous Conversion In continuous conversion mode, the ADC data registers are regularly updated at the selected update rate (see Filter register). 1 0 0 Internal Zero-Scale Calibration Internal short automatically connected to the enabled channel(s) 1 0 1 Internal Full-Scale Calibration External V is connected automatically to the ADC input for this calibration. REF 1 1 0 System Zero-Scale Calibration User should connect system zero-scale input to the channel input pins as selected by CH3–CH0 bits in the control registers. 1 1 1 System Full-Scale Calibration User should connect system full-scale input to the channel input pins as selected by CH3–CH0 bits in the control registers. REV. 0 –27–

AD7708/AD7718 Operating Characteristics when Addressing the Mode and Control Registers 1. Any change to the MD bits will immediately reset the ADCs. A write to the MD2–MD0 bits with no change is also treated as a reset. 2. Once the MODE has been written with a calibration mode, the RDY bit (STATUS) is immediately reset and the calibration commences. On completion the appropriate calibration registers are written, the bit in STATUS register is updated and the MD2–MD0 bits are reset to 001 to indicate the ADC is back in idle mode. 3. Calibrations are performed with the maximum allowable SF value with chop enabled. SF register is reset to user configuration after calibration with chop enabled. Calibrations are performed with the selected value of SF when chop is disabled. ADC Control Register (ADCCON): (A3, A2, A1, A0 = 0, 0, 1, 0; Power-On-Reset = 07 Hex) The ADC Control Register is an 8-bit register from which data can be read or to which data can be written. This register is used to configure the ADC for range, channel selection, and unipolar or bipolar coding. TableXVI outlines the bit designations for the ADC control register ADCCON7 through ADCCON0 indicate the bit location, ADCCON denoting the bits are in the ADC Control Register. ADCCON7 denotes the first bit of the data stream. The number in brackets indicates the power-on/reset default status of that bit. ADCCON7 ADCCON6 ADCCON5 ADCCON4 ADCCON3 ADCCON2 ADCCON1 ADCCON0 CH3 (0) CH2 (0) CH1 (0) CH0 (0) U/B (0) RN2 (1) RN1 (1) RN0 (1) Table XVI. ADC Control Register (ADCCON) Bit Designations Bit Bit Location Mnemonic Description ADCCON7 CH3 ADC Channel Selection Bits. Written by the user to select either pseudo-differential or fully- ADCCON6 CH2 differential input pairs used by the ADC as follows: ADCCON5 CH1 ADCCON4 CH0 8-Channel Configuration 10-Channel Configuration (CHCON = 0) (CHCON = 1) Positive Negative Cal Register Positive Negative Cal Register CH3 CH2 CH1 CH0 Input Input Pair Input Input Pair 0 0 0 0 AIN1 AINCOM 1 AIN1 AINCOM 1 0 0 0 1 AIN2 AINCOM 2 AIN2 AINCOM 2 0 0 1 0 AIN3 AINCOM 3 AIN3 AINCOM 3 0 0 1 1 AIN4 AINCOM 4 AIN4 AINCOM 4 0 1 0 0 AIN5 AINCOM 1 AIN5 AINCOM 5 0 1 0 1 AIN6 AINCOM 2 AIN6 AINCOM 1 0 1 1 0 AIN7 AINCOM 3 AIN7 AINCOM 2 0 1 1 1 AIN8 AINCOM 4 AIN8 AINCOM 3 1 0 0 0 AIN1 AIN2 1 AIN1 AIN2 1 1 0 0 1 AIN3 AIN4 2 AIN3 AIN4 2 1 0 1 0 AIN5 AIN6 3 AIN5 AIN6 3 1 0 1 1 AIN7 AIN8 4 AIN7 AIN8 4 1 1 0 0 AIN2 AIN2 1 AIN9 AIN10 5 1 1 0 1 AINCOM AINCOM 1 AINCOM AINCOM 1 1 1 1 0 REFIN(+) REFIN(–) 1 AIN9 AINCOM 4 1 1 1 1 OPEN OPEN 1 AIN10 AINCOM 5 ADCCON3 U/B Unipolar/Bipolar Bit. Set by user to enable unipolar coding i.e., zero differential input will result in 000000hex output and a full-scale differential input will result in FFFFFF Hex output when operated in 24-bit mode. Cleared by user to enable bipolar coding, Negative full-scale differential input will result in an output code of 000000 Hex, zero differential input will result in an output code of800000Hex and a positive full-scale differential input will result in an output code of FFFFFF Hex. –28– REV. 0

AD7708/AD7718 Table XVI. ADC Control Register (ADCCON) Bit Designations (continued) AD0C2 RN2 ADC Range Bits AD0C1 RN1 Written by the user to select the ADC input range as follows AD0C0 RN0 RN2 RN1 RN0 Selected ADC Input Range (VREF = 2.5 V) 0 0 0 ±20 mV 0 0 1 ±40 mV 0 1 0 ±80 mV 0 1 1 ±160 mV 1 0 0 ±320 mV 1 0 1 ±640 mV 1 1 0 ±1.28 V 1 1 1 ±2.56V Filter Register (A3, A2, A1, A0 = 0, 0, 1, 1; Power-On Reset = 45Hex) The Filter Register is an 8-bit register from which data can be read or to which data can be written. This register determines the amount of averaging performed by the sinc filter. Table XVII outlines the bit designations for the Filter Register. FR7 through FR0 indicate the bit location, FR denoting the bits are in the Filter Register. FR7 denotes the first bit of the data stream. The number in brackets indicates the power-on/reset default status of that bit. The number in this register is used to set the decimation factor and thus the output update rate for the ADCs. The filter register cannot be written to by the user the ADC is active. The update rate is used for the ADCs is calculated as follows: 1 ( ) f = × f CHOP Enabled CHOP=0 ADC MOD 3 1 ( ) f = × f CHOP Disabled CHOP=1 ADC MOD 8×SF where f = ADC Output Update Rate, ADC f = Modulator Clock Frequency = 32.768 kHz, MOD SF = Decimal Value Written to SF Register. Table XVII. Filter Register Bit Designations FR7 FR6 FR5 FR4 FR3 FR2 FR1 FR0 SF7(0) SF6(1) SF5(0) SF4(0) SF3(0) SF2(1) SF1(0) SF0(1) The allowable range for SF is 13 decimal to 255 decimal with chop enabled, and the allowable SF range when chop is disabled is 03 decimal to 255 decimal. Examples of SF values and corresponding conversion rate (f ) and time (t ) are shown in Table XVIII. ADC ADC It should be noted that optimum performance is obtained when operating with chop enabled. When chopping is enabled (CHOP = 0), the filter register is loaded with FF HEX during a calibration cycle. With chop disabled (CHOP =1), the value in the filter register is used during calibration. Table XVIII. Update Rate vs. SF Word CHOP Enabled CHOP Disabled SF (Dec) SF (Hex) f (Hz) t (ms) f (Hz) t (ms) ADC ADC ADC ADC 03 03 N/A N/A 1365.33 0.732 13 0D 105.3 9.52 315 3.17 69 45 19.79 50.34 59.36 16.85 255 FF 5.35 186.77 16.06 62.26 REV. 0 –29–

AD7708/AD7718 I/O Control Register (IOCON): (A3, A2, A1, A0 = 0, 1, 1, 1; Power-On-Reset = 00Hex) The IOCON Register is an 8-bit register from which data can be read or to which data can be written. This register is used to con- trol and configure the I/O port. Table XIX outlines the bit designations for this register. IOCON7 through IOCON0 indicate the bit location, IOCON denoting the bits are in the I/O Control Register. IOCON7 denotes the first bit of the data stream. The num- ber in brackets indicates the power-on/reset default status of that bit. A write to the IOCON register has immediate effect and does not reset the ADCs. IOCON7 IOCON6 IOCON5 IOCON4 IOCON3 IOCON2 IOCON1 IOCON0 (0) 0(0) P2DIR(0) P1DIR(0) 0(0) 0(0) P2DAT(0) P1DAT(0) Table XIX. IOCON (I/O Control Register) Bit Designations Bit Bit Location Mnemonic Description IOCON7 0 This bit should always be cleared. Reserved for future use. IOCON6 0 This bit should always be cleared. Reserved for future use. IOCON5 P2DIR P2, I/O Direction Control Bit. Set by user to enable P2 as an output. Cleared by user to enable P2 as an input. There are weak pull-ups internally when enabled as an input. IOCON4 P1DIR P1, I/O Direction Control Bit. Set by user to enable P1 as an output. Cleared by user to enable P1 as an input. There are weak pull-ups internally when enabled as an input. IOCON3 0 This bit should always be cleared. Reserved for future use. IOCON2 0 This bit should always be cleared. Reserved for future use. IOCON1 P2DAT Digital I/O Port (P1) Data Bit. The readback value of this bit indicates the status of the pin regardless of whether this pin is configured as an input or an output. The value written to this data bit will appear at the output port when the I/O pin is enabled as an output. IOCON0 P1DAT Digital I/O port (P1) Data Bit. The readback value of this bit indicates the status of the pin, regardless of whether this pin is configured as an input or an output. The value written to this data bit will appear at the output port when the I/O pin is enabled as an output. ADC Data Result Register (DATA): (A3, A2, A1, A0 = 0, 1, 0, 0; Power-On-Reset = 000000Hex) The conversion result for the selected ADC channel is stored in the ADC data register (DATA). This register is 16 bits wide on the AD7708 and 24 bits wide on the AD7718. This is a read only register. On completion of a read from this register the RDY bit in the status register is cleared. These ADCs can be operated in either unipolar or bipolar mode of operation. Unipolar Mode In unipolar mode of operation the output coding is straight binary. With an analog input voltage of 0 V the output code is 0000Hex for the AD7708 and 000000Hex for the AD7718. With an analog input voltage of 1.024 V /Gain the output code is FFFFHex REF for the AD7708 and FFFFFF Hex for the AD7718. The output code for any analog input voltage can be represented as follows: Code = (AIN × GAIN × 2N)/(1.024 × V ) REF where AIN is the analog input voltage and N = 16 for the AD7708 and N = 24 for the AD7718. –30– REV. 0

AD7708/AD7718 Bipolar Mode With an analog input voltage of (–1.024 V /GAIN), the output code is 0000 Hex using the AD7708 and 000000H using the AD7718. REF With an analog input voltage of 0 V, the output code is 8000Hex for the AD7708 and 800000Hex for the AD7718. With an analog input voltage of (+1.024 V /GAIN), the output code is FFFF Hex for the AD7708 and FFFFFF Hex for the AD7718. Note the REF analog inputs are pseudo bipolar inputs and the analog input voltage must remain within the common-mode input range at all times. The output code for any analog input voltage can be represented as follows: Code = 2N–1 × [(AIN × GAIN/1.024 × V ) + 1] REF where AIN is the analog input voltage, N = 16 for the AD7708, and N = 24 for the AD7718. ADC Offset Calibration Coefficient Registers (OF0): (A3, A2, A1, A0 = 0, 1, 0, 1; Power-On-Reset = 8000(00)Hex) The offset calibration registers are 16-bit registers on the AD7708 and 24-bit registers on the AD7718. These registers hold the offset calibration coefficient for the ADC. The power-on-reset value of the internal zero-scale calibration coefficient registers is 8000(00). There are five offset registers available, one for each of the fully differential input channels. Calibration register pairs are shared when operating in pseudo-differential input mode. However, these bytes will be automatically overwritten if an internal or system zero-scale calibration is initiated by the user via MD2–MD0 bits in the MODE register. The channel bits, in association with the communication register address for the OF0 register, allow access to this register. This register is a read/write register. The calibration register can only be written to if the ADC is inactive (MD bits in the mode register = 000 or 001). Reading of the calibration register does not clear the RDY bit. ADC Gain Calibration Coefficient Register (GNO): (A3, A2, A1, A0 = 0, 1, 1, 0; Power-On-Reset = 5XXX(X5) Hex) The gain calibration registers are 16-bit registers on the AD7708 and 24-bit registers on the AD7718. These registers are configured at power-on with factory-calculated internal full-scale calibration coefficients. There are five full-scale registers available, one for each of the fully differential input channels. Calibration register pairs are shared when operating in pseudo-differential input mode. Every device will have different default coefficients. However, these bytes will be automatically overwritten if an internal or system full-scale calibration is initiated by the user via MD2–MD0 bits in the MODE register. The channel bits, in association with the communication register address, allow access to the data contained in the GN0 register. This is a read/write register. The calibration registers can only be written to if the ADC is inactive (MD bits in the mode register = 000 or 001). Reading of the calibration registers does not clear the RDY bit. A calibration (self or system) is required when operating with chop mode disabled. ID Register (ID): (A3, A2, A1, A0 = 1, 1, 1, 1; Power-On-Reset = 4X Hex (AD7718) and 5X Hex (AD7708) This register is a read only 8-bit register. The contents are used to determine the die revision of the silicon. Table XX indicates the bit locations for the AD7708. Table XX. ID Register Bit Designation ID7 ID6 ID5 ID4 ID3 ID2 ID1 ID0 0 1 0 0/1 X X X X User Nonprogrammable Test Registers The AD7708 and AD7718 contain two test registers. The bits in these test registers control the test modes of these ADCs which are used for the testing of the device. The user is advised not to change the contents of these registers. REV. 0 –31–

AD7708/AD7718 Configuring the AD7708/AD7718 All user-accessible registers on the AD7708 and AD7718 are CALIBRATION ROUTINE accessed via the serial interface. Communication with any of these registers is initiated by first writing to the Communica- tions Register. Figures 16, 17, and 18 show flow diagrams for WRITE TO ADCCON SELECTING CHANNEL AND CONFIGURING initializing the ADC, a sequence for calibrating the ADC chan- INPUT RANGE AND UNIPOLAR/BIPOLAR MODE nels, and a routine that cycles through and reads all channels. Figure 16 shows a flowchart detailing necessary programming steps required to initialize the ADC. The following are the general programming steps required: WRITE TO MODE REGISTER SELECTING ZERO-SCALE CALIBRATION 1. Configure and initialize the microcontroller or microprocessor serial port. 2. Initialize the AD7708/AD7718 by configuring the following registers: MD BITS = 001? a. IOCON to configure the digital I/O port. b.FILTER to configure the update rate for each channel. NO YES c. ADCCON to select the active input channel, select the analog input range, and select unipolar or bipolar WRITE TO MODE REGISTER SELECTING FULL-SCALE CALIBRATION operation. d.MODE to configure the operating mode. The mode register selects chop or nonchop operation, buffered/ unbuffered operation of the AINCOM input, 8-/10- MD BITS channel mode of operation and reference select along = 001? with the selection of conversion, calibration or idle modes of operation. NO YES All operations consist of a write to the communications register to specify the next operation as a write to a specified register. YES CAL Data is then written to the specified register. When each sequence ANOTHER CHANNEL is complete, the ADC defaults to waiting for another write to the communications register to specify the next operation. NO END START Figure 17.Calibrating the AD7708/AD7718 POWER-ON/RESET FOR AD7708/AD7718 Figure 17 shows a flowchart detailing necessary programming steps required when calibrating the AD7708/AD7718. The AD7708/AD7718 have dedicated calibration register pairs for CONFIGURE AND INITIALIZE (cid:3)C/(cid:3)P SERIAL PORT each of the fully-differential input channels. Having a dedicated register pair per channel allows each channel to be calibrated as part of the initialization and the ADC picks up the relevant WRITE TO COMMUNICATIONS REGISTER SELECTING coefficients for each channel during normal operation. When NEXT OPERATION TO BE A WRITE TO THE IOCON operating is pseudo-differential mode channels share calibration REGISTER AND CONFIGURE THIS REGISTER register pairs. Channels that share coefficients should be config- ured with the same operating conditions to avoid having to calibrate each time a channel is switched, especially with chop WRITE TO COMMUNICATIONS REGISTER SETTING UP mode disabled. The AD7708/AD7718 are factory-calibrated NEXT OPERATION TO BE A WRITE TO THE FILTER REGISTER. SET SF WORD FOR REQUIRED with chop mode enabled and, therefore, if the ADC is operated UPDATE RATE at the same conditions as the factory-calibration field calibra- tions will not be required. Extremely low offset error and offset and gain drift errors are a by product of the chopping scheme. WRITE TO COMMUNICATIONS REGISTER SETTING UP When operating with chop mode disabled, the user can achieve NEXT OPERATION TO BE A WRITE TO THE ADC CONTROL REGISTER. CONFIGURE ADCCON faster throughput times. An offset calibration is required with chop disabled when a gain or temperature change occurs. The following are the general programming steps required when WRITE TO COMMUNICATIONS REGISTER SETTING UP calibrating a channel on the AD7708/AD7718. NEXT OPERATION TO BE A WRITE TO THE MODE REGISTER. CALIBRATE AND SELECT MODE OF OPERATION Figure 16.Initializing AD7708/AD7718 –32– REV. 0

AD7708/AD7718 1. Write to the ADCCON register to select the channel to be 4. When the data is read, increment the channel address pointer calibrated, its input range, and operation in unipolar or to select the next channel, poll the RDY pin, or RDY bit in bipolar mode. the status register, and again read the data. Continue until all channels have been read. 2. Write to the mode register selecting chop or nonchop mode of operation, select the reference, buffered/unbuffered opera- tion on the AINCOM, and select zero-scale offset calibration. CYCLE THROUGH AND Zero-scale calibration can be either self-calibration, where READ ALL CHANNELS the ADC determines the zero point internal to the ADC, or a system calibration where the user must supply the zero-scale voltage to the input for the duration of the calibration. WRITE TO MODE REGISTER SELECTING CONTINUOUS CONVERSION MODE 3. The calibration is initiated following the write to the mode register. The user then needs to determine when the calibra- tion is complete. This can be performed in two ways, by WRITE TO ADCCON SELECTING CHANNEL N polling the RDY pin or flag or by monitoring the MD2, AND ITS OPERATING RANGE MD1, MD0 bits in the mode register. These bits are reset to 0, 0, 1 when the calibration is complete. The flowchart uses POLL RDY PIN polling of the mode bits in the mode register to determine when the calibration is complete. 4. The next step is to perform the full-scale calibration. Full-scale calibration can be a self-calibration or system calibration. RDY Using system calibration the user must supply the full-scale LOW? signal to the analog inputs for the duration of the calibration. Again the MD2, MD1, MD0 bits in the mode register are NO YES monitored to determine when the calibration is complete. WRITE TO COMMUNICATIONS REGISTER SETTING UP Figure 18 shows a flowchart detailing the necessary program- NEXT OPERATION TO BE A READ OF DATA REGISTER ming steps required to cycle through and read data results from AND THEN READ DATA RESULT all channels in a multiplexed application. This flowchart assumes that all channels have been previously calibrated. The following are the general programming steps required when reading all INCREMENT CHANNEL ADDRESS (N = N+1) channels in a multiplexed application. 1. The AD7708/AD7718 is put into continuous conversion mode. In this mode the part continually converts on the NO ALL specified channel and the RDY line indicates when valid CHANNELS READ data is available to be read from the data register. 2. The ADCCON register is written to select the channel for conversion, its input range and operation is unipolar/ YES bipolar mode. END 3. In this flowchart hardware polling of the RDY line is per- formed to determine when it is valid to read data from the Figure 18.Multichannel Read Operation converter. When RDY is low, valid data is available in the data register. The RDY line is set high on a channel change and will not go low until a new valid data word is available. Alternatively, the RDY bit in the status register can be polled in software to determine when to read data from the converter. REV. 0 –33–

AD7708/AD7718 DIGITAL INTERFACE either via a software error or by some glitch in the system, it can As previously outlined, the AD7708/AD7718’s programmable be reset back to a known state. This state returns the interface functions are controlled using a set of on-chip registers. Data is to where the ADC is expecting a write operation to its Commu- written to these registers via the part’s serial interface and read nications Register. This operation resets the contents of all access to the on-chip registers is also provided by this interface. registers to their power-on-reset values. All communications to the part must start with a write operation Some microprocessor or microcontroller serial interfaces have a to the Communications Register. After power-on or RESET, single serial data line. In this case, it is possible to connect the the device expects a write to its Communications Register. The ADC’s DOUT and DIN lines together and connect them to the data written to this register determines whether the next operation single data line of the processor. A 10 kΩ pull-up resistor should to the part is a read or a write operation and also determines to be used on this single data line. In this case, if the interface is which register this read or write operation occurs. Therefore, lost, because the read and write operations share the same line, write access to any of the other registers on the part starts with a the procedure to reset it back to a known state is somewhat write operation to the Communications Register followed by a different than previously described. It requires a read operation write to the selected register. A read operation from any other of 24 serial clocks followed by a write operation where a Logic register on the part (including the output data register) starts 1 is written for at least 32 serial clock cycles to ensure that the with a write operation to the Communications Register followed serial interface is back into a known state. by a read operation from the selected register. The AD7708/AD7718s serial interface consists of five signals, MICROCOMPUTER/MICROPROCESSOR INTERFACING CS, SCLK, DIN, DOUT and RDY. The DIN line is used for The flexible serial interface allows for easy interface to most transferring data into the on-chip registers while the DOUT line microcomputers and microprocessors. The flowcharts of Figures is used for accessing data from the on-chip registers. SCLK is 16, 17, and 18 outline the sequence that should be followed the serial clock input for the device and all data transfers (either when interfacing a microcontroller or microprocessor to the on DIN or DOUT) take place with respect to this SCLK signal. AD7708/AD7718. Figures 19, 20, and 21 show some typical The RDY line is used as a status signal to indicate when data is interface circuits. ready to be read from the devices’s data register. RDY goes low The serial interface on the AD7708/AD7718 is capable of oper- when a new data word is available in the output register. It is ating from just three wires and is compatible with SPI interface reset high when a read operation from the data register is complete. protocols. The three-wire operation makes the part ideal for It also goes high prior to the updating of the output register to isolated systems where minimizing the number of interface lines indicate when not to read from the device to ensure that a data minimizes the number of opto-isolators required in the system. read is not attempted while the register is being updated. CS is The serial clock input is a Schmitt-triggered input to accommo- used to select the device. It can be used to decode these devices in date slow edges from optocouplers. The rise and fall times of systems where a number of parts are connected to the serial bus. other digital inputs to the AD7708/AD7718 should be no slower Figures 2 and 3 show timing diagrams for interfacing to the than 1µs. AD7708/AD7718 with CS used to decode the part. Figure 3 is Most of the registers on the AD7708/AD7718 are 8-bit regis- for a read operation from the AD7708/AD7718 output shift ters, which facilitates easy interfacing to the 8-bit serial ports of register while Figure 2 shows a write operation to the input shift microcontrollers. The Data Register on the AD7718 is 24 bits register. It is possible to read the same data twice from the out- wide, the ADC data register on the AD7708 is 16 bits wide, and put register even though the RDY line returns high after the first the offset and gain registers are 16-bit registers on the AD7708 read operation. Care must be taken, however, to ensure that the and 24-bit registers on the AD7718; however, data transfers to read operations have been completed before the next output these registers can consist of multiple 8-bit transfers to the serial update is about to take place. port of the microcontroller. DSP processors and microproces- The serial interface can operate in three-wire mode by tying the sors generally transfer 16 bits of data in a serial data operation. CS input low. In this case, the SCLK, DIN and DOUT lines Some of these processors, such as the ADSP-2105, have the are used to communicate with the device and the status of the facility to program the amount of cycles in a serial transfer. This RDY bit can be obtained by interrogating the STATUS Regis- allows the user to tailor the number of bits in any transfer to ter. This scheme is suitable for interfacing to microcontrollers. If match the register length of the required register in the AD7708/ CS is required as a decoding signal, it can be generated from a AD7718. port bit. For microcontroller interfaces, it is recommended that Even though some of the registers on the AD7708/AD7718 are the SCLK idles high between data transfers. only eight bits in length, communicating with two of these The AD7708/AD7718 can also be operated with CS used as a registers in successive write operations can be handled as a frame synchronization signal. This scheme is suitable for DSP single 16-bit data transfer if required. For example, if the Filter interfaces. In this case, the first bit (MSB) is effectively clocked Register is to be updated, the processor must first write to the out by CS since CS would normally occur after the falling edge Communications Register (saying that the next operation is a of SCLK in DSPs. The SCLK can continue to run between write to the Filter Register) and then write eight bits to the Filter data transfers provided the timing numbers are obeyed. Register. If required, this can all be done in a single 16-bit transfer because once the eight serial clocks of the write opera- The serial interface can be reset by exercising the RESET input tion to the Communications Register have been completed, on the part. It can also be reset by writing a series of 1s on the the part immediately sets itself up for a write operation to the DIN input. If a Logic 1 is written to the AD7708/AD7718 DIN Filter Register. line for at least 32 serial clock cycles, the serial interface is reset. This ensures that in three-wire systems, if the interface is lost –34– REV. 0

AD7708/AD7718 AD7708/AD7718 to 68HC11 Interface AD7708/AD7718-to-8051 Interface Figure 19 shows an interface between the AD7708/AD7718 and An interface circuit between the AD7708/AD7718 and the the 68HC11 microcontroller. The diagram shows the minimum 8XC51 microcontroller is shown in Figure 20. The diagram (3-wire) interface with CS on the AD7708/AD7718 hardwired shows the minimum number of interface connections with CS low. In this scheme, the RDY bit of the Status Register is on the AD7708/AD7718 hardwired low. In the case of the monitored to determine when the Data Register is updated. 8XC51 interface the minimum number of interconnects is just An alternative scheme, which increases the number of inter- two. In this scheme, the RDY bit of the Status Register is face lines to four, is to monitor the RDY output line from the monitored to determine when the Data Register is updated. The AD7708/AD7718. The monitoring of the RDY line can be done alternative scheme, which increases the number of interface in two ways. First, RDY can be connected to one of the 68HC11’s lines to three, is to monitor the RDY output line from the port bits (such as PC0), which is configured as an input. This AD7708/AD7718. The monitoring of the RDY line can be done port bit is then polled to determine the status of RDY. The in two ways. First, RDY can be connected to one of the 8XC51’s second scheme is to use an interrupt driven system, in which port bits (such as P1.0) which is configured as an input. This case the RDY output is connected to the IRQ input of the port bit is then polled to determine the status of RDY. The 68HC11. For interfaces that require control of the CS input on second scheme is to use an interrupt-driven system, in which the AD7708/AD7718, one of the port bits of the 68HC11 (such case the RDY output is connected to the INT1 input of the as PC1), which is configured as an output, can be used to drive 8XC51. For interfaces that require control of the CS input on the CS input. the AD7708/AD7718, one of the port bits of the 8XC51 (such as P1.1), which is configured as an output, can be used to drive VDD the CS input. The 8XC51 is configured in its Mode 0 serial 68HC11 VDD AD7708/ interface mode. Its serial interface contains a single data line. As AD7718 a result, the DOUT and DIN pins of the AD7708/AD7718 should SS be connected together with a 10 kΩ pull-up resistor. The serial RESET clock on the 8XC51 idles high between data transfers. The 8XC51 outputs the LSB first in a write operation, while the SCK SCLK AD7708/AD7718 expects the MSB first so the data to be trans- mitted has to be rearranged before being written to the output MISO DOUT serial register. Similarly, the AD7708/AD7718 outputs the MSB first during a read operation while the 8XC51 expects the LSB first. Therefore, the data read into the serial buffer needs to be MOSI DIN rearranged before the correct data word from the AD7708/ AD7718 is available in the accumulator. CS 8XC51 DVDD AD7708/ AD7718 Figure 19.AD7708/AD7718-to-68HC11 Interface DVDD RESET The 68HC11 is configured in the master mode with its CPOL 10k(cid:7) bit set to a Logic 1 and its CPHA bit set to a Logic 1. When the 68HC11 is configured like this, its SCLK line idles high between P3.0 DOUT data transfers. The AD7708/AD7718 is not capable of full duplex operation. If the AD7708/AD7718 is configured for a write DIN operation, no data appears on the DOUT lines even when the SCLK input is active. Similarly, if the AD7708/AD7718 is config- P3.1 SCLK ured for a read operation, data presented to the part on the DIN line is ignored even when SCLK is active. CS Figure 20.AD7708/AD7718-to-8XC51 Interface REV. 0 –35–

AD7708/AD7718 AD7708/AD7718-to-ADSP-2103/ADSP-2105 Interface BASIC CONFIGURATION Figure 21 shows an interface between the AD7708/AD7718 and The basic connection diagram for the AD7708/AD7718 in 10- the ADSP-2103/ADSP-2105 DSP processor. In the interface channel mode is shown in Figure 22. This shows both the AV DD shown, the RDY bit of the Status Register is again monitored to and DV pins of the converters being driven from the analog DD determine when the Data Register is updated. The alternative 5V supply. Some applications will have AV and DV driven DD DD scheme is to use an interrupt-driven system, in which case the from separate supplies. AV and DV can be operated inde- DD DD RDY output is connected to the IRQ2 input of the ADSP-2103/ pendently of each other, allowing the device to be operated with ADSP-2105. The serial interface of the ADSP-2103/ADSP-2105 5 V analog supply and 3 V digital supply or vice versa. The parts is set up for alternate framing mode. The RFS and TFS pins of can be operated in 8- or 10-channel configurations. In 8-channel the ADSP-2103/ADSP-2105 are configured as active low outputs mode the user has two reference input options. This allows the and the ADSP-2103/ADSP-2105 serial clock line, SCLK, is also user to operate some channels in ratiometric mode and others configured as an output. The CS for the AD7708/AD7718 is in absolute measurement mode. In 10-channel mode only one active when either the RFS or TFS outputs from the ADSP-2103/ reference option is available. An AD780/REF195, precision 2.5 V ADSP-2105 are active. The serial clock rate on the ADSP- reference, provides the reference source for the part. A quartz 2103/ADSP-2105 should be limited to 3MHz to ensure correct crystal or ceramic resonator provides the 32.768 kHz master operation with the AD7708/AD7718. clock source for the part. In some cases, it will be necessary to connect capacitors on the crystal or resonator to ensure that it does not oscillate at overtones of its fundamental operating fre- DVDD AD7708/ quency. The values of capacitors will vary, depending on the ADSP-2103/ manufacturer’s specifications. AD7718 ADSP-2105 RESET ANALOG 5V SUPPLY 10(cid:3)F 0.1(cid:3)F 0.1(cid:3)F RFS TFS CS AVDD DVDD 5V AIN1 RESET DR DOUT AIN2 CHIP AIN3 CS SELECT AD7708/ DT DIN AIN4 AD7718 DOUT R(REECAEDIV)E AIN5 SCLK SCLK AIN6 SERIAL DIN DATA AIN7 (WRITE) IFnigteurrfea c2e1.AD7708/AD7718-to-ADSP-2103/ADSP-2105 AIN8 SCLK SCELROICAKL AIN9 AIN10 P1 AINCOM P2 ANALOG 5V SUPPLY 10(cid:3)F REF1IN(+) MCLKIN 0.1(cid:3)F 32kHz CRYSTAL MCLKOUT REF1IN(–) VIN VOUT AD780/ REF195 AGND DGND GND Figure 22.Basic Configuration for 10-Channel Mode –36– REV. 0

AD7708/AD7718 Analog Input Channels The input multiplexer on AD7708/AD7718 can be configured REFIN1(+) REFIN1(+) as either an 8- or 10-input channel device. This configuration is REFIN1(–) REFIN1(–) selected using the CHCON bit in the MODE register. With CHCON = 0 (Figure 23), the user has eight input channels; these AIN1 AIN1 AD7708/ can be configured as eight pseudo-differential input channels with AIN2 AIN2 AD7718 respect to AINCOM or four fully-differential input channels. AIN3 AIN3 In this configuration the user can select REFIN1 or REFIN 2 as AIN4 AIN4 the reference for the selected channel using the REFSEL bit in AIN5 AIN5 the mode register. AIN6 AIN6 AIN7 AIN7 AIN8 AIN8 REFIN1(+) REFIN1(+) AIN9 AIN9 REFIN1(–) REFIN1(–) AIN10 AIN10 AIN1 AIN1 AINCOM AINCOM AD7708/ AIN2 AIN2 AD7718 AIN3 AIN3 Figure 24.Analog Input and Reference Options with AIN4 AIN4 CHCON = 1 AIN5 AIN5 Single-Ended Operation AIN6 AIN6 The NEGBUF bit in the mode register is used to control the AIN7 AIN7 operation of the input buffer on the AINCOM pin when config- AIN8 AIN8 ured for pseudo-differential mode of operation. If cleared, the analog negative input (AINCOM) is unbuffered. It should be AINCOM AINCOM noted that the unbuffered input path on the AINCOM provides REFIN2(+) REFIN2(+) a dynamic load to the driving source. Therefore, resistor/capacitor combinations on this input pin can cause dc gain errors depend- REFIN2(–) REFIN2(–) ing on the output impedance of the source that is driving the AINCOM input. AINCOM is tied to AGND for single-ended Figure 23.Analog Input and Reference Options with operation. This enables all pseudo-differential inputs to act as CHCON = 0 single-ended analog inputs. All analog inputs still operate in With CHCON = 1 (Figure 24), the user has 10 input channels buffered mode and their common-mode and absolute input that can be configured as 10 pseudo-differential input channels voltage is restricted to a range between AGND + 100 mV and with respect to AINCOM or as five fully-differential input chan- AV – 100 mV. DD nels. The contents of the CHCON bit overrides the REFSEL Chop Mode of Operation (CHOP = 0) bit. If the ADC is configured in five fully-differential or 10 pseudo- The signal chain on the AD7708/AD7718 can be operated with differential input channel mode, the REFSEL bit setting is chopping enabled or disabled. Chopping is enabled or disabled irrelevant as only REFIN1 is available. Channel selection Bits using the CHOP bit in the mode register. The default mode of CH3, CH2, CHI, and CH0 in the ADCCON register select the operation is for chop enabled (CHOP = 0). Optimum perfor- input channel. mance in terms of minimizing offset error and offset and gain The input multiplexer switches the selected input channel to the drift performance is achieved when chopping is enabled. The on-chip buffer amplifier and sigma-delta converter. When the digital filter decimation rate, and consequently the output data analog input channel is switched, the settling time of the part rate, is programmable via the SF word loaded to the filter register. must elapse before a new valid word is available from the ADC. Output data rates vary from 5.35Hz (186.77 ms) to 105.03Hz If any two inputs are configured as a differential input pair, this f (9.52 ms). The output data rate f = MOD . input is buffered and the common-mode and absolute input volt- ADC 24×SF age is restricted to a range between AGND + 100 mV and AVDD The overall frequency response from the digital filter with chop- – 100 mV. Care must be taken in setting up the common-mode ping enabled is the product of a sinc3 and a sinc response. There voltage and input voltage range to ensure that these limits are are sinc3 notches at integer multiples of 3 × f and there are ADC not exceeded, otherwise there will be a degradation in linearity sinc notches at odd integer multiples of f /2. Normal mode ADC and noise performance. rejection is the major function of the digital filter on the AD7708/ AD7718. The normal mode 50 ±1 Hz rejection with an SF word of 82 is typically –100dB. The 60 ± 1 Hz rejection with SF = 68 is typically –100dB. Simultaneous 50 Hz and 60 Hz rejection of better than 60dB is achieved with an SF of 69 and gives a data update rate of 19.8 Hz and a channel settling time of 101 ms. The AD7708/AD7718 are factory-calibrated so field calibration will only be required if the ADC is operated at temperatures that differ substantially from the factory-calibration conditions. REV. 0 –37–

AD7708/AD7718 Nonchop Mode of Operation (CHOP = 1) 19.372 Chopping is enabled and disabled using the CHOP bit in the 19.371 mode register. Chopping is disabled by loading a 1 to the chop bit in the mode register. With chopping disabled the available V19.370 output rates vary from 16.06 Hz (62.26ms) to 1365.33 Hz (0.73 ms). – m The range of applicable SF words is from 3 to 255. When the GE 19.369 A chopping is disabled the channel output data rate is increased by a LT factor of 3 compared to the situation when chopping is enabled T VO19.368 U and using the same SF word. When used in multiplexed NP19.367 applications, operation with chop disabled will offer the best C I D throughput time when cycling through all channels. The drawback A19.366 with chop disabled is that the drift performance is degraded 19.365 and calibration is required following a gain change or significant temperature change. The output update and filter decimation 19.364 0 100 200 300 400 500 600 700 800 rate is again controlled by the SF word loaded to the filter SAMPLE COUNT register. The digital filter frequency response places sinc3 V V V V V V V V m m m m m m 8 6 notches at integer multiples of the update rate. The output ADC RANGE (cid:4)20 (cid:4)40 (cid:4)80 160 320 640 (cid:4)1.2 (cid:4)2.5 (cid:4) (cid:4) (cid:4) f update rate f = MOD . The AD7708/AD7718 are targeted Figure 25.ADC Range Matching ADC 8×SF The PGA setting is then switched to 64 and 100 more results at multiplexed applications and therefore operating with chop are gathered, and so on until the last 100 samples are gathered disabled optimizes channel throughput time. One of the key with a PGA setting of 1. From Figure 25, the variation in the sample requirements in these applications is the selection of an SF word mean through each range, i.e., the range matching, is seen to be so as to obtain the maximum filter rejection at 50 Hz and 60 Hz of the order of 2µV. When operating with chop mode disabled while minimizing the channel throughput rate. This is achieved (CHOP = 1), new calibration data is needed (but not necessarily with an SF word of 75 giving 57 dB rejection at 50 Hz, and a new calibration) to remove offset error when switching channels. 60dB rejection at 60 Hz while offering a channel throughput time of 55 ms. Using a higher SF word of 151, 50 Hz and Bipolar/Unipolar Configuration 60 Hz rejection can be maximized at 60dB with a channel The analog inputs on the AD7708/AD7718 can accept either throughput rate of 110 ms. An SF word of 255 gives maximum unipolar or bipolar input voltage ranges. Bipolar input ranges rejection at both 50 Hz and 60 Hz but the channel throughput does not imply that the part can handle negative voltages with rate is restricted to 186ms. Table XXI shows a quick comparison respect to system AGND. Signals in pseudo-differential mode of normal mode 50 Hz and 60 Hz rejection, settling time, and are referenced to AINCOM, while in fully differential mode they update rate for a selection of SF words with chop both enabled are referenced to the negative input of the differential input. For and disabled. example, if AINCOM is 2.5 V and the AD7708/AD7718 AIN1 analog input is configured for an analog input range of 0 mV to Programmable Gain Amplifier +20 mV, the input voltage range on the AIN1 input is 2.5 V to The output from the buffer is applied to the input of the program- 2.52 V. If AINCOM is 2.5 V and the AD7708/AD7718 is con- mable gain amplifier (PGA). The PGA gain range is programmed figured for an analog input range of ±1.28 V, the analog input via the range bits in the ADCCON register. The PGA has eight range on the AIN1 input is 1.22 V to 3.78 V (i.e., 2.5 V ± ranges. With an external 2.5 V reference applied, and a PGA 1.28 V). Bipolar or unipolar options are chosen by programming setting of 128, the unipolar analog input range is 0 mV to 20mV, while the bipolar analog input range is ±20 mV. With a PGA U/B bit in the ADCCON register. Programming for either unipolar or bipolar operation does not change any of the input setting of 1, the unipolar and bipolar input ranges are 2.56V. signal conditioning; it simply changes the data output coding When operating with chop mode enabled (CHOP = 0), the ADC range-matching specification of 2 µV (typ) across all ranges and the points on the transfer function where calibrations occur. means that calibration need only be carried out on a single Data Output Coding range and does not have to be repeated when the PGA range is When the AD7718 is configured for unipolar operation, the out- changed. This is a significant advantage when compared with put coding is natural (straight) binary with a zero differential similar ADCs available on the market. Typical matching across input voltage resulting in a code of 000 . . . 000, a midscale ranges is shown in Figure 25. Here, the ADC is configured in voltage resulting in a code of 100 . . . 000, and a full-scale input fully-differential, bipolar mode with an external 2.5 V reference, voltage resulting in a code of 111 . . . 111. The output code for while an analog input voltage of just greater than 19 mV is forced any analog input voltage can be represented as follows: on its analog inputs. The ADC continuously converts the dc Code = (AIN × GAIN × 224)/(1.024 × V ) REF voltage at an update rate of 5.35Hz, i.e., SF = FFhex, 800 where conversion results in total are gathered. The first 100 results are gathered with the ADC operating with a PGA setting of 128. AIN is the analog input voltage, GAIN is the PGA gain, i.e., 1 on the 2.5 V range and 128 on the 20 mV range. –38– REV. 0

AD7708/AD7718 The output code for any analog input voltage on the AD7708 the ADC is configured in five fully-differential or 10 pseudo- can be represented as follows: differential input channel mode, the REFSEL bit setting is Code = (AIN × GAIN × 216)/(1.024 × V ) irrelevant as only one reference input is available. REF The common-mode range for these differential inputs is from where AGND to AV . The reference inputs are unbuffered and DD AIN is the analog input voltage, therefore excessive R-C source impedances will introduce gain GAIN is the PGA gain, i.e., 1 on the 2.5 V range and 128 on errors. The nominal reference voltage for specified operation, the 20 mV range. VREF, (REFIN1(+)–REFIN1(–) or REFIN2(+)–REFIN2(–)), When an ADC is configured for bipolar operation, the coding is is 2.5 V, but the AD7708/AD7718 is functional with reference offset binary with a negative full-scale voltage resulting in a code voltages from 1 V to AV . In applications where the excitation DD of 000 . . . 000, a zero differential voltage resulting in a code of (voltage or current) for the transducer on the analog input also 100 . . . 000, and a positive full-scale voltage resulting in a code drives the reference voltage for the part, the effect of the low of 111 . . . 111. The output code from the AD7718 for any frequency noise in the excitation source will be removed as the analog input voltage can be represented as follows: application is ratiometric. If the AD7708/AD7718 is used in a nonratiometric application, a low noise reference should be Code = 223 × [(AIN × GAIN/(1.024 × V )) + 1] REF used. Recommended reference voltage sources for the AD7708/ where AD7718 include the AD780, REF43, and REF192. It should AIN is the analog input voltage, also be noted that the reference inputs provide a high impedance, GAIN is the PGA gain, i.e., 1 on the ±2.5 V range and 128 on dynamic load. Because the input impedance of each reference the ±20 mV range. input is dynamic, resistor/capacitor combinations on these inputs can cause dc gain errors, depending on the output impedance of The output code from the AD7708 for any analog input voltage the source that is driving the reference inputs. Reference voltage can be represented as follows: sources, like those recommended above (e.g., AD780) will typically Code = 215 × [(AIN × GAIN/(1.024 × V )) + 1] have low output impedances and are therefore tolerant of having REF where decoupling capacitors on the REFIN(+) without introducing gain errors in the system. Deriving the reference input voltage across AIN is the analog input voltage, an external resistor will mean that the reference input sees a GAIN is the PGA gain, i.e., 1 on the ±2.5 V range and 128 on significant external source impedance. External decoupling on the ±20 mV range. the REFIN(+) and REFIN(–) pins would not be recommended Oscillator Circuit in this type configuration. The AD7708/AD7718 is intended for use with a 32.768 kHz RESET Input watch crystal or ceramic resonator. A PLL internally locks onto The RESET input on the AD7708/AD7718 resets all the logic, a multiple of this frequency to provide a stable 4.194304 MHz the digital filter and the analog modulator while all on-chip clock for the ADC. The modulator sample rate is the same as registers are reset to their default state. RDY is driven high and the oscillator frequency. the AD7708/AD7718 ignores all communications to any of its The start-up time associated with 32 kHz crystals is typically registers while the RESET input is low. When the RESET input 300 ms. The OSPD bit in the mode register can be used to returns high the AD7708/AD7718 operates with its default setup prevent the oscillator from powering down when the AD7708/ conditions and it is necessary to set up all registers and carry out AD7718 is placed in power-down mode. This avoids having to a system calibration if required after a RESET command. wait 300 ms after exiting power-down to start a conversion at Power-Down Mode the expense of raising the power-down current. Loading 0, 0, 0 to the MD2, MD1, MD0 bits in the ADC mode Reference Input register places the ADC in device power-down mode. Device The AD7708/AD7718 has a fully differential reference input power-down mode is the default condition for the AD7708/ capability. When the AD7708/AD7718 is configured in 8-channel AD7718 on power-up. The ADC retains the contents of all its mode (CHCON = 0) the user has the option of selecting one of on-chip registers (including the data register) while in power- two reference options. This allows the user to configure some down. The device power-down mode does not affect the digital channels, for example, for ratiometric operation while others can interface, but does affect the status of the RDY pin. Writing the be configured for absolute value measurements. The REFSEL bit AD7708/AD7718 into power-down will reset the RDY line high. in the mode register allows selection of the required reference. Placing the part in power-down mode reduces the total current If the REFSEL bit is cleared, the reference selected is REFIN1(+) (AI + DI ) to 31µA max when the part is operated at 5 V DD DD –REFIN1(–) for the active channel. If this bit is set, the refer- and the oscillator allowed to run during power-down mode. ence selected is REFIN2(+) – REFIN2(–) for the active channel. With the oscillator shut down the total I is typically 9 µA. DD When the AD7708/AD7718 is configured in 10-channel mode (CHCON = 1) the user has only one reference option (REFIN1). The contents of the CHCON bit overrides the REFSEL bit. If REV. 0 –39–

AD7708/AD7718 Calibration calibration. System software should monitor the RDY bit in the The AD7708/AD7718 provides four calibration modes that can STATUS register to determine end of calibration via a polling be programmed via the mode bits in the mode register. One of sequence or interrupt driven routine. the major benefits of the AD7708/AD7718 is that it is factory- Grounding and Layout calibrated with chopping enabled as part of the final test process Since the analog inputs and reference inputs are differential, with the generated coefficients stored within the ADC. At power- most of the voltages in the analog modulator are common-mode on, the factory gain calibration coefficients are automatically voltages. The excellent common-mode rejection of the part will loaded to the gain calibration registers on the AD7708/AD7718. remove common-mode noise on these inputs. The analog and This gives excellent offset and drift performance and it is digital supplies to the AD7708/AD7718 are independent and envisaged that in the majority of applications the user will not separately pinned out to minimize coupling between the analog need to perform any field calibrations. Also, because factory and digital sections of the device. The AD7708/AD7718 can be gain calibration coefficients (generated at 25°C ambient) are operated with 5 V analog and 3 V digital supplies or vice versa. automatically present at power-on, an internal full-scale calibration The digital filter will provide rejection of broadband noise on will only be required if the part is being operated at temperatures the power supplies, except at integer multiples of the modulator significantly different from 25°C. sampling frequency. The digital filter also removes noise from When chopping is disabled (CHOP =1) the AD7708/AD7718 the analog and reference inputs provided these noise sources do requires an offset calibration or new calibration coefficients on not saturate the analog modulator. As a result, the AD7708/ range changing or when significant temperature changes occur AD7718 is more immune to noise interference than a conventional as the signal chain is no longer chopped and offset and drift high-resolution converter. However, because the resolution of the errors are no longer removed as part of the conversion process. AD7708/AD7718 is so high and the noise levels from the converter so low, care must be taken with regard to grounding The factory-calibration values for any one channel will be over- and layout. written if any one of the four calibration options is initiated. The AD7708/AD7718 offers “internal” or “system” calibration The printed circuit board that houses the ADC should be designed facilities. For full calibration to occur, the calibration logic must so the analog and digital sections are separated and confined to record the modulator output for two different input conditions. certain areas of the board. This facilitates the use of ground planes These are “zero-scale” and “full-scale” points. These points that can be easily separated. A minimum etch technique is are derived by performing a conversion on the different input generally best for ground planes as it gives the best shielding. voltages provided to the input of the modulator during calibration. Although the AD7708/AD7718 has separate pins for analog and The result of the “zero-scale” calibration conversion is stored in digital ground, the AGND and DGND pins are tied together the Offset Calibration Registers for the appropriate channel. internally via the substrate. Therefore, the user must not tie The result of the “full-scale” calibration conversion is stored these two pins to separate ground planes unless the ground in the Gain Calibration Registers. With these readings, the planes are connected together near the AD7708/AD7718. calibration logic can calculate the offset and the gain slope for In systems where the AGND and DGND are connected some- the input-to-output transfer function of the converter. During an where else in the system, i.e., the systems power supply, they “internal” zero-scale or full-scale calibration, the respective should not be connected again at the AD7708/AD7718 or a “zero” input and “full-scale” input are automatically connected ground loop will result. In these situations it is recommended that to the ADC input pins internally to the device. A “system” cali- ground pins of the AD7708/AD7718 be tied to the AGND plane. bration, however, expects the system zero-scale and system full-scale voltages to be applied to the external ADC pins In any layout it is implicit that the user keep in mind the flow of before the calibration mode is initiated. In this way external currents in the system, ensuring that the paths for all currents ADC errors are taken into account and minimized as a result are as close as possible to the paths the currents took to reach of system calibration. It should also be noted that to optimize their destinations. Avoid forcing digital currents to flow through calibration accuracy, all AD7708/AD7718 ADC calibrations the AGND. are carried out automatically at the slowest update rate with Avoid running digital lines under the device as these will couple chop enabled. When chop mode is disabled calibrations are noise onto the die. The analog ground plane should be allowed carried out at the update rate defined by the SF word in the to run under the AD7708/AD7718 to prevent noise coupling. filter register. The power supply lines to the AD7708/AD7718 should use as Internally in the AD7708/AD7718, the coefficients are normalized wide a trace as possible to provide low impedance paths and before being used to scale the words coming out of the digital reduce the effects of glitches on the power supply line. Fast filter. The offset calibration coefficient is subtracted from the switching signals like clocks should be shielded with digital result prior to the multiplication by the gain coefficient. With ground to avoid radiating noise to other sections of the board chopping disabled AD7708/AD7718 ADC specifications will and clock signals should never be run near the analog inputs. only apply after a zero-scale calibration at the operating point of Avoid crossover of digital and analog signals. Traces on opposite interest. From an operational point of view, a calibration should sides of the board should run at right angles to each other. This will be treated like another ADC conversion. A zero-scale calibration reduce the effects of feedthrough through the board. A microstrip (if required) should always be carried out before a full-scale technique is by far the best, but is not always possible with a double-sided board. In this technique, the component side of the board is dedicated to ground planes while signals are placed on the solder side. –40– REV. 0

AD7708/AD7718 Good decoupling is important when using high resolution ADCs. The buffer on the negative analog input can be bypassed allowing All analog supplies should be decoupled with 10µF tantalum in the AD7708/AD7718 be operated as eight or ten single-ended parallel with 0.1µF capacitors to AGND. To achieve the best input channels. The PGA allows the user to connect transducers from these decoupling components, they have to be placed directly to the input of the AD7708/AD7718. The program- as close as possible to the device, ideally right up against the mable gain front end on the AD7708/AD7718 allows the part to device. All logic chips should be decoupled with 0.1µF ceramic handle unipolar analog input ranges from 0mV to +20mV to capacitors to DGND. In systems where a common supply 0V to +2.5V and bipolar inputs of ±20mV to ±2.5V. Because voltage is used to drive both the AV and DV of the AD7708/ the part operates from a single supply these bipolar ranges are DD DD AD7718, it is recommended that the system’s AV supply is with respect to a biased-up differential input. DD used. This supply should have the recommended analog supply Data Acquisition decoupling capacitors between the AV pin of the AD7708/ DD The AD7708/AD7718, with its different configuration options AD7718 and AGND and the recommended digital supply (five fully-differential input or 10 pseudo-differential input decoupling capacitor between the DV pin of the AD7708/ DD channels with one reference input or four fully-differential input AD7718 and DGND. or eight pseudo-differential input channels with two reference inputs), is suited to low bandwidth, high resolution data acquisi- APPLICATIONS tion systems. In addition, the 3-wire digital interface allows this The AD7708/AD7718 provides a low cost, high resolution data acquisition front end to be isolated with just three opto- analog-to-digital function. The AD7708 offers 16-bit resolution isolators. The entire system can be operated from a single 3 V while the AD7718 offers 24-bit resolution. The AD7708 and or 5 V supply, provided that the input signals to the AD7708/ AD7718 are pin and function compatible. The AD7718 allows a AD7718’s analog inputs are all of positive polarity. direct upgradable path from a 16-bit to a 24-bit system with minimal software and no hardware changes. Because the analog- 5V to-digital function is provided by a sigma-delta architecture, it makes the part more immune to noisy environments, thus mak- AVDD DVDD AIN1 ing the part ideal for use in sensor measurement and in industrial AIN2 MCLKIN and process control applications. There are two modes of operation AIN3 associated with the AD7708/AD7718, chop enabled (CHOP = 0) AIN4 32kHz or chop disabled (CHOP = 1). With chop enabled the signal chain AIN5 AIN6 MCLKOUT is chopped and the device is factory-calibrated at final test in this mode. Field calibration can be avoided due to the extremely AIN7 AD7708/ AIN8 AD7718 low offset and gain drifts exhibited by the converter in this AIN9 RESET mode. While operating in this mode gives optimum performance AIN10 in terms of offset error and offset and gain drift performance, it 5V AINCOM RDY DOUT MICRO- oWffiethrs clhimopitpedin gth droisuagbhlepdu,t twhhee snig cnyacll icnhga tinhr iosu ngoht aclhl ochpapnende alsn.d VIN VOUT REFIN1(+) DCISN CONTROLLER therefore the user needs to ensure that the ADC is calibrated on AD780 SCLK range changes and if there is a significant temperature change GND as the gain and offset drift performance is degraded. REF1IN(–) The key advantage in using the AD7708/AD7718 with chopping AGND DGND disabled is in channel cycling applications where system through- put is of prime importance. The max conversion rate with chop disabled is 1.36 kHz compared with 105Hz with chop enabled. Figure 26.Data Acquisition Using the AD7708/AD7718 The AD7708/AD7718 also provides a programmable gain ampli- Programmable Logic Controllers fier, a digital filter, and system calibration options. Thus, it The AD7708/AD7718 is also suited to programmable logic provides far more system level functionality than off-the-shelf controller applications. In such applications, the ADC is required integrating ADCs without the disadvantage of having to sup- to handle signals from a variety of different transducers. The ply a high quality integrating capacitor. In addition, using the AD7708/AD7718’s programmable gain front end allows the AD7708/AD7718 in a system allows the system designer to part to either handle low level signals directly from a transducer achieve a much higher level of resolution because noise perfor- or full-scale signals that have already been conditioned. The faster mance of the AD7708/AD7718 is significantly better than that throughput rate and settling time of the part when operated with of integrating ADCs. chopping disabled makes this the optimum mode of operation in The on-chip PGA allows the AD7708/AD7718 to handle an PLC applications as an important feature in these applications is analog input voltage range as low as 10 mV full scale with VREF loop response time. The configuration of the AD7708/AD7718 = 1.25V. The AD7708/AD7718 can be operated in 8-channel in PLC applications is similar to that outlined for a data acquisi- mode with two reference input options or 10-channel mode with tion system and is shown in Figure 26. In this application the one reference input. Eight-channel mode allows both ratiometric AD7708/AD7718 is configured in 10-channel mode, (CHCON or absolute measurements to be performed on any channel using = 1) and can be operated as 10 pseudo-differential inputs with the two reference input options. The differential analog inputs respect to AINCOM or as five fully-differential input channels. of the part allow this analog input range to have an absolute value anywhere between AGND +100 mV and AV – 100 mV. DD REV. 0 –41–

AD7708/AD7718 Converting Single-Ended Inputs Combined Ratiometric and Absolute Value Measurement The AD7708/AD7718 generally operates in buffered mode. This System places a restriction of AGND + 100 mV to AVDD – 100mV on The AD7708/AD7718 when operated with CHCON = 0 can be the absolute and common-mode voltages that can be applied to configured for operation as four fully-differential analog inputs or any input on the AD7708/AD7718. eight pseudo-differential analog inputs with two fully-differential Some applications may require the measurement of analog reference inputs. Having the ability to use either REFIN1 or inputs with respect to AGND. To enable the AD7708/AD7718 REFIN2 with any channel during the conversion process allows to be used in these single-ended applications, the buffer on the the end user to make both absolute and ratiometric measure- AINCOM can be bypassed. The NEGBUF bit in the mode ments as shown in Figure 27. In this example a fully-differential register controls the operation of the input buffer on the AINCOM analog input (AIN1–AIN2) is being converted from a bridge trans- input when a channel is configured for pseudo-differential mode of ducer in a ratiometric manner using REFIN1 as the reference operation. If cleared, the analog negative input (AINCOM) is input for this channel. AIN3 is configured as a pseudo-differential unbuffered, allowing it to be tied to AGND in single-ended input channel using REFIN2 to perform an absolute measurement input configuration. If this bit is set, the analog negative input on the potentiometer. The REFSEL bit in the mode register is (AINCOM) is buffered, placing a restriction on its common- used to select which reference is used with the active channel mode input range. When AINCOM is unbuffered, signals with a during the conversion process. When the AD7708/AD7718 is common-mode range from AGND – 30 mV to AVDD + 30 mV configured with CHCON = 1, only one reference (REFIN1) is can be accommodated on this input allowing the end user to available. The contents of the CHCON bit override the REFSEL connect the AINCOM input to AGND and perform single- bit. If the ADC is configured in five fully-differential or 10 ended measurements with respect to this input. This unbuffered pseudo-differential input channel mode, the REFSEL bit setting input path on the AINCOM provides a dynamic load to the is irrelevant as only REFIN1 is available. driving source. Therefore, resistor/capacitor combinations on this input pin can cause dc gain errors, depending on the output impedance of the source that is driving the AINCOM input. All analog inputs still operate in buffered mode and their com- REFIN1(+) mon-mode and absolute input voltage is restricted to a range AIN1 between AGND + 100 mV and AV – 100 mV. AIN2 DD REFIN1(–) AD7718 EXCITATION VOLTAGE = 4V REFIN2(+) WIPER AIN3 AINCOM REFIN2(–) GND Figure 27.Absolute and Ratiometric Measurement System Using AD7718 –42– REV. 0

AD7708/AD7718 Optimizing Throughput while Maximizing 50 Hz and 60 Hz cycling through all channels. The drawback with chopping Rejection in a Multiplexed Data Acquisition System disabled is that the drift performance is degraded and calibra- The AD7708/AD7718 can be optimized for one of two modes tion is required following gain and temperature changes. One of operation. Operating the AD7708/AD7718 with chopping of the key requirements in these applications is to optimize the SF enabled (CHOP = 0) optimizes the AD7708/AD7718 for analog word to obtain the maximum filter rejection at 50 Hz and 60 Hz performance over channel throughput. Output data rates vary while minimizing the channel throughput rate. This is achieved from 5.35Hz (186.77 ms) to 105.03 Hz (9.52 ms). Optimum with an SF word of 75 giving 57 dB rejection at 50 Hz and performance, in terms of minimizing offset error and offset and 60dB rejection at 60 Hz while offering a channel throughput gain drift performance, is achieved as a result of chopping the time of 55 ms. signal chain. Using a higher SF word of 151, 50 Hz and 60 Hz rejection can With chopping disabled the available output rates vary from be maximized at 60dB with a channel throughput rate of 110 ms. 16.06 Hz (62.26ms) to 1365.33 Hz (0.73 ms). The range of An SF word of 255 gives maximum rejection at both 50 Hz applicable SF words is from 3 to 255. When the chopping is and 60 Hz, but the channel throughput rate is restricted to disabled the channel output data rate is increased by a factor of 186ms. Table XXI gives a quick comparison of normal mode 50 Hz 3 compared to the situation when chopping is enabled is and 60 Hz rejection, settling time, and update rate for a selec- disabled. When used in multiplexed applications, operation tion of SF words with both chopping enabled and disabled. with chop disabled will offer the best throughput time when Table XXI. Normal Mode 50 Hz and 60 Hz Rejection vs. Settling Time and Update Rate for a Selection of SF Words CHOP Disabled CHOP Enabled 50 Hz(cid:4) 1 Hz 60 Hz(cid:4) 1 Hz 50 Hz(cid:4) 1 Hz 60 Hz(cid:4) 1 Hz SF Rejection Rejection Rejection Rejection Word f (Hz) t (ms) (dB) (dB) f (Hz) t (ms) (dB) (dB) ADC SETTLE ADC SETTLE 03 1365.33 2.20 0.05 0.08 N/A N/A N/A N/A 13 315.08 9.52 1 1.5 105.03 19.04 21 13.6 69 59.36 50.54 42 94 19.79 101 60 94 75 54.6 54.93 57 60 18.2 110 62 66 82 49.95 60 100 16.65 180 100 53 151 27.13 110.6 60 60 9.04 221 72 63 255 16.06 186.76 77 68 5.35 373.5 93 68 REV. 0 –43–

AD7708/AD7718 OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 28-Lead Plastic SOIC (R-28) 0) 0.7125 (18.10) 1( 0.6969 (17.70) 7/0 – 1 – 28 15 31 0.2992 (7.60) 8 1 0.2914 (7.40) 0 C 0.4193 (10.65) 1 14 0.3937 (10.00) PIN 1 0.1043 (2.65) 0.0291 (0.74) 0.0926 (2.35) 0.0098 (0.25)(cid:6) 45(cid:5) 8(cid:5) 00..00101480 ((00..3100)) 0(B.10.S52C070) 00..00119328 ((00..4395)) SPELAANTIENG 00..00102951 ((00..3223)) 0(cid:5) 00..00510507 ((10..2470)) 28-Lead Plastic TSSOP (RU-28) 0.386 (9.80) 0.378 (9.60) 28 15 0.177 (4.50) 0.169 (4.30) 0.256 (6.50) 0.246 (6.25) 1 14 PIN 1 0.006 (0.15) 0.0433 (1.10) 0.002 (0.05) MAX 8(cid:5) SEPALTAINNGE 0.02B56S C(0.65) 00..00101785 ((00..3109)) 00.0.0003759 ((00.0.2900))0(cid:5) 00..002280 ((00..7500)) A. S. U. N D I E T N RI P –44– REV. 0

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