LC2MOS 20-Bit A/D Converter AD7703 FEATURES FUNCTIONAL BLOCK DIAGRAM Monolithic 16-Bit ADC 0.0015% Linearity Error AVSS DVSS SC1 SC2 On-Chip Self-Calibration Circuitry 7 6 4 17 Programmable Low-Pass Filter AD7703 0.1 Hz to 10 Hz Corner Frequency DVDD 15 0 Vto +2.5 V or (cid:1)2.5 V Analog Input Range CALIBRATION CALIBRATION 4 kSPS Output Data Rate AVDD 14 SRAM MICROCONTROLLER 13 CAL Flexible Serial Interface Ultralow Power AIN 9 20-BIT CHCAORNGVEE RBTAELRANCE A/D 12 BP/UP APPLICATIONS IWndeuigshtr Siacla Pleroscess Control VREF 10 MOADNUALLAOTGOR 6-POLLOEW G-PAAUSSSSIAN 11 SLEEP DIGITAL FILTER Portable Instrumentation Remote Data Acquisition AGND 8 CLOCK 20 SDATA SERIAL INTERFACE GENERATOR DGND 5 LOGIC 19 SCLK 3 2 1 16 18 CLKIN CLKOUT MODE CS DRDY GENERAL DESCRIPTION PRODUCT HIGHLIGHTS The AD7703 is a 20-bit ADC that uses a S-D conversion tech- 1. The AD7703 offers 20-bit resolution coupled with outstanding nique. The analog input is continuously sampled by an analog 0.0003% accuracy. modulator whose mean output duty cycle is proportional to the 2. No missing codes ensures true, usable, 20-bit dynamic range, input signal. The modulator output is processed by an on-chip removing the need for programmable gain and level-setting digital filter with a six-pole Gaussian response, which updates the circuitry. output data register with 16-bit binary words at word rates up to 3. The effects of temperature drift are eliminated by on-chip 4kHz. The sampling rate, filter corner frequency, and output self-calibration, which removes zero and gain error. External word rate are set by a master clock input that may be supplied circuits can also be included in the calibration loop to remove externally, or by a crystal controlled on-chip clock oscillator. system offsets and gain errors. The inherent linearity of the ADC is excellent and endpoint accu- 4. Flexible synchronous/asynchronous interface allows the racy is ensured by self-calibration of zero and full scale, which AD7703 to interface directly to the serial ports of industry- may be initiated at any time. The self-calibration scheme can standard microcontrollers and DSP processors. also be extended to null system offset and gain errors in the input channel. 5. Low operating power consumption and an ultralow power standby mode make the AD7703 ideal for loop-powered The output data is accessed through a flexible serial port, which remote sensing applications, or battery-powered portable has an asynchronous mode compatible with UARTs and two instruments. synchronous modes suitable for interfacing to shift registers or the serial ports of industry-standard microcontrollers. CMOS construction ensures low power dissipation, and a power- down mode reduces the idle power consumption to only 10 µW. REV.E Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. under any patent or patent rights of Analog Devices. Trademarks and Tel: 781/329-4700 www.analog.com registered trademarks are the property of their respective companies. Fax: 781/326-8703 © 2003 Analog Devices, Inc. All rights reserved.

AD7703–SPECIFICATIONS (T = 25(cid:2)C; AV = DV = +5 V; AV = DV = –5 V; V = +2.5 V; f = 4.096 MHz; A DD DD SS SS REF CLKIN BP/UP = +5 V; MODE = +5 V; A Source Resistance = 1 k(cid:3)1 with 1 nF to AGND at A ; unless otherwise noted.) IN IN Parameter A/S Version2 B Version2 C Version2 Unit Test Conditions/Comments STATIC PERFORMANCE Resolution 20 20 20 Bits Integral Nonlinearity, T to T ±0.0015 ±0.0007 ±0.0003 % FSR typ MIN MAX 25°C ±0.003 ±0.0015 ±0.0008 % FSR max T to T ±0.003 ±0.0015 ±0.0012 % FSR max MIN MAX Differential Nonlinearity, T to T ±0.5 ±0.5 ±0.5 LSB typ Guaranteed No Missing Codes MIN MAX Positive Full-Scale Error3 ±4 ±4 ±4 LSB typ ±16 ±16 ±16 LSB max Full-Scale Drift4 ±19/±37 ±19 ±19 LSB typ Unipolar Offset Error3 ±4 ±4 ±4 LSB typ ±16 ±16 ±16 LSB max Unipolar Offset Drift4 ±26 ±26 ±26 LSB typ Temp Range: 0°C to +70°C ±67 +48/–400 ±67 ±67 LSB typ Specified Temp Range Bipolar Zero Error3 ±4 ±4 ±4 LSB typ ±16 ±16 ±16 LSB max Bipolar Zero Drift4 ±13 ±13 ±13 LSB typ Temp Range: 0°C to +70°C ±34 +24/–200 ±34 ±34 LSB typ Specified Temp Range Bipolar Negative Full-Scale Errors3 ±8 ±8 ±8 LSB typ ±32 ±32 ±32 LSB max Bipolar Negative Full-Scale Drift4 ±10/±20 ±10 ±10 LSB typ Noise (Referred to Output) 1.6 1.6 1.6 LSB rms typ DYNAMIC PERFORMANCE Sampling Frequency, f f /256 f /256 f /256 Hz S CLKIN CLKIN CLKIN Output Update Rate, f f /1024 f /1024 f /1024 Hz OUT CLKIN CLKIN CLKIN Filter Corner Frequency, f f /409,600 f /409,600 f /409,600 Hz –3 dB CLKIN CLKIN CLKIN Settling Time to ±0.0007% FS 507904/f 507904/f 507904/f sec For Full-Scale Input Step CLKIN CLKIN CLKIN SYSTEM CALIBRATION Positive Full-Scale Calibration Range V + 0.1 V + 0.1 V + 0.1 V max System calibration applies to REF REF REF Positive Full-Scale Overrange V + 0.1 V + 0.1 V + 0.1 V max unipolar and bipolar ranges. REF REF REF Negative Full-Scale Overrange –(V + 0.1) –(V + 0.1) –(V + 0.1) V max After calibration, if A > V , REF REF REF IN REF Maximum Offset Calibration Ranges5, 6 the device will output all 1s. Unipolar Input Range –(V + 0.1) –(V + 0.1) –(V + 0.1) V max If A < 0 (unipolar) or –V REF REF REF IN REF Bipolar Input Range –0.4 V to +0.4 V –0.4 V to +0.4 V –0.4 V to +0.4 V V max (bipolar), the device will REF REF REF REF REF REF Input Span7 0.8 V 0.8 V 0.8 V V min output all 0s. REF REF REF 2 V + 0.2 2 V + 0.2 2 V + 0.2 V max REF REF REF ANALOG INPUT Unipolar Input Range 0 to 2.5 0 to 2.5 0 to 2.5 V Bipolar Input Range ±2.5 ±2.5 ±2.5 V Input Capacitance 20 20 20 pF typ Input Bias Current1 1 1 1 nA typ LOGIC INPUTS All Inputs Except CLKIN V , Input Low Voltage 0.8 0.8 0.8 V max INL V , Input High Voltage 2.0 2.0 2.0 V min INH CLKIN V , Input Low Voltage 0.8 0.8 0.8 V max INL V , Input High Voltage 3.5 3.5 3.5 V min INH I , Input Current 10 10 10 µA max IN LOGIC OUTPUTS V , Output Low Voltage 0.4 0.4 0.4 V max I = 1.6 mA OL SINK V , Output High Voltage DV – 1 DV – 1 DV – 1 V min I = 100 µA OH DD DD DD SOURCE Floating State Leakage Current ±10 ±10 ±10 µA max Floating State Output Capacitance 9 9 9 pF typ POWER REQUIREMENTS Power Supply Voltages Analog Positive Supply (AV ) 4.5/5.5 4.5/5.5 4.5/5.5 V min/V max For Specified Performance DD Digital Positive Supply (DV ) 4.5/AV 4.5/AV 4.5/AV V min/V max DD DD DD DD Analog Negative Supply (AV ) –4.5/–5.5 –4.5/–5.5 –4.5/–5.5 V min/V max SS Digital Negative Supply (DV ) –4.5/–5.5 –4.5/–5.5 –4.5/–5.5 V min/V max SS Calibration Memory Retention Power Supply Voltage 2.0 2.0 2.0 V min –2– REV. E

AD7703 Parameter A/S Version2 B Version2 C Version2 Unit Test Conditions/Comments POWER REQUIREMENTS DC Power Supply Currents8 Analog Positive Supply (AI ) 2.7 2.7 2.7 mA max Typically 2 mA DD Digital Positive Supply (DI ) 2 2 2 mA max Typically 1 mA DD Analog Negative Supply (AI ) 2.7 2.7 2.7 mA max Typically 2 mA SS Digital Negative Supply (DI ) 0.1 0.1 0.1 mA max Typically 0.03 mA SS Power Supply Rejection9 Positive Supplies 70 70 70 dB typ Negative Supplies 75 75 75 dB typ Power Dissipation Normal Operation 37 37 37 mW max SLEEP = Logic 1, Typically 25 mW Standby Operations10 SLEEP = Logic 0, A, B, C 20 20 20 µW max Typically 10 µW S 40 40 40 µW max NOTES 1The A pin presents a very high impedance dynamic load that varies with clock frequency. A ceramic 1 nF capacitor from the A pin to AGND is necessary. IN IN Source resistance should be 750 (cid:1) or less. 2Temperature ranges are as follows: A, B, C Versions: –40°C to +85°C; S Version: –55°C to +125°C. 3Applies after calibration at the temperature of interest. Full-scale error applies for both unipolar and bipolar input ranges. 4Total drift over the specified temperature range after calibration at power-up at 25°C. This is guaranteed by design and/or characterization. Recalibration at any temperature will remove these errors. 5In Unipolar mode, the offset can have a negative value (–V ) such that the Unipolar mode can mimic Bipolar mode operation. REF 6The specifications for input overrange and for input span apply additional constraints on the offset calibration range. 7For Unipolar mode, input span is the difference between full scale and zero scale. For Bipolar mode, input span is the difference between positive and negative full-scale points. When using less than the maximum input span, the span range may be placed anywhere within the range of ±(V + 0.1). REF 8All digital outputs unloaded. All digital inputs at 5 V CMOS levels. 9Applies in 0.1 Hz to 10 Hz bandwidth. PSRR at 60 Hz will exceed 120 dB due to the digital filter. 10CLKIN is stopped. All digital inputs are grounded. Specifications subject to change without notice. ABSOLUTE MAXIMUM RATINGS1 NOTES (T = 25°C, unless otherwise noted.) 1Stresses above those listed under Absolute Maximum Ratings may cause A permanent damage to the device. This is a stress rating only; functional operation DVDD to AGND . . . . . . . . . . . . . . . . . . . . . . . .–0.3 V to +6 V of the device at these or any other conditions above those listed in the DV to AV . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +0.3 V operational sections of this specification is not implied. Exposure to absolute DD DD DV to AGND . . . . . . . . . . . . . . . . . . . . . . . . +0.3 V to –6 V maximum rating conditions for extended periods may affect device reliability. SS 2Transient currents of up to 100 mA will not cause SCR latch-up. AV to AGND . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +6 V DD AV to AGND . . . . . . . . . . . . . . . . . . . . . . . . +0.3 V to –6 V SS ORDERING GUIDE AGND to DGND . . . . . . . . . . . . . . . . . . . . . –0.3 V to +0.3 V Digital Input Voltage to DGND . . . . –0.3 V to DVDD + 0.3 V Linearity Analog Input Voltage to AGND . . . AVSS – 0.3 V to AVDD + 0.3 V Temperature Error Package Input Current to Any Pin Except Supplies2 . . . . . . . . ±10 mA Model Range (% FSR) Options* Operating Temperature Range Industrial (A, B, C Versions) . . . . . . . . . . . –40°C to +85°C AD7703AN –40°C to +85°C 0.003 N-20 Extended (S Version) . . . . . . . . . . . . . . . . –55°C to +125°C AD7703BN –40°C to +85°C 0.0015 N-20 Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C AD7703CN –40°C to +85°C 0.0012 N-20 Lead Temperature (Soldering, 10 secs) . . . . . . . . . . . . . 300°C AD7703AR –40°C to +85°C 0.003 R-20 Power Dissipation (DIP Package) to 75°C . . . . . . . . .450 mW AD7703BR –40°C to +85°C 0.0015 R-20 Derates above 75°C by . . . . . . . . . . . . . . . . . . . . . 10 mW/°C AD7703CR –40°C to +85°C 0.0012 R-20 Power Dissipation (SOIC Package) to 75°C . . . . . . . 250 mW AD7703AQ –40°C to +85°C 0.003 Q-20 Derates above 75°C by . . . . . . . . . . . . . . . . . . . . . . 15 mW/°C AD7703BQ –40°C to +85°C 0.0015 Q-20 AD7703CQ –40°C to +85°C 0.0012 Q-20 AD7703SQ –55°C to +125°C 0.003 Q-20 *N = Plastic DIP; R = SOIC; Q = CERDIP. CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD7703 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. REV. E –3–

AD7703 TIMING CHARACTERISTICS1, 2 (AVDD = DVDD = +5 V (cid:1) 10%; AVSS = DVSS = –5 V (cid:1) 10%; AGND = DGND = O V; f = 4.096 MHz; Input Levels: Logic O = O V, Logic 1 = DV ; unless otherwise noted.) CLKIN DD Limit at T , T Limit at T , T MIN MAX MIN MAX Parameter (A, B Versions) (S, T Versions) Unit Conditions/Comments f 3, 4 200 200 kHz min Master Clock Frequency: Internal Gate Oscillator CLKIN 5 5 MHz max Typically 4.096 MHz 200 200 kHz min Master Clock Frequency: Externally Supplied 5 5 MHz max t5 50 50 ns max Digital Output Rise Time. Typically 20 ns. r t5 50 50 ns max Digital Output Fall Time. Typically 20 ns. f t 0 0 ns min SC1, SC2 to CAL High Setup Time 1 t 50 50 ns min SC1, SC2 Hold Time after CAL Goes High 2 t 6 1000 1000 ns min SLEEP High to CLKIN High Setup Time 3 SSC MODE t 7 3/f 3/f ns max Data Access Time (CS Low to Data Valid) 4 CLKIN CLKIN t 100 100 ns max SCLK Falling Edge to Data Valid Delay (25 ns typ) 5 t 250 250 ns min MSB Data Setup Time. Typically 380 ns. 6 300 300 ns max SCLK High Pulsewidth. Typically 240 ns. 7 t 790 790 ns max SCLK Low Pulsewidth. Typically 730 ns. 8 t 8 l/f + 200 l/f + 200 ns max SCLK Rising Edge to Hi-Z Delay (l/f + 100 nstyp) 9 CLKIN CLKIN CLKIN t 8, 9 4/f + 200 4/f + 200 ns max CS High to Hi-Z Delay 10 CLKIN CLKIN SEC MODE f 5 5 MHz max Serial Clock Input Frequency SCLK t 35 35 ns min SCLK Input High Pulsewidth 11 t 160 160 ns min SCLK Low Pulsewidth 12 t 7, 10 160 160 ns max Data Access Time (CS Low to Data Valid). Typically 80ns. 13 t 11 150 150 ns max SCLK Falling Edge to Data Valid Delay. Typically 75ns. 14 t 8 250 250 ns max CS High to Hi-Z Delay 15 t 8 200 200 ns max SCLK Falling Edge to Hi-Z Delay. Typically 100 ns. 16 NOTES 1Sample tested at 25°C to ensure compliance. All input signals are specified with t = t = 5 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V. r f 2See Figures 1 to 6. 3CLKIN duty cycle range is 20% to 80%. CLKIN must be supplied whenever the AD7703 is not in SLEEP mode. If no clock is present in this case, the device can draw higher current than specified and possibly become uncalibrated. 4The AD7703 is production tested with f at 4.096 MHz. It is guaranteed by characterization to operate at 200 kHz. CLKIN 5Specified using 10% and 90% points on waveform of interest. 6In order to synchronize several AD7703s together using the SLEEP pin, this specification must be met. 7t and t are measured with the load circuit of Figure 1 and defined as the time required for an output to cross 0.8 V or 2.4 V. 4 13 8t, t , t , and t are derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 1. The measured number 9 10 15 16 is then extrapolated back to remove the effects of charging or discharging the 100 pF capacitor. This means that the time quoted in the Timing Characteristics is the true bus relinquish time of the part and as such is independent of external bus loading capacitance. 9If CS is returned high before all 20 bits are output, the SDATA and SCLK outputs will complete the current data bit and then go to high impedance. 10If CS is activated asynchronously to DRDY, CS will not be recognized if it occurs when DRDY is high for four clock cycles. The propagation delay time may be as great as four CLKIN cycles plus 160 ns. To guarantee proper clocking of SDATA when using asynchronous CS, the SCLK input should not be taken high sooner than four CLKIN cycles plus 160 ns after CS goes low. 11SDATA is clocked out on the falling edge of the SCLK input. Specifications subject to change without notice. CAL 1IO.6LmA t1 t2 SC1, SC2 SC1, SC2 VALID TO OUTPUT +2.1V PIN CL Figure 2. Calibration Control Timing 100pF IOH 200(cid:2)A CLKIN Figure 1.Load Circuit for Access Time and Bus Relinquish Time t3 SLEEP Figure 3. Sleep Mode Timing –4– REV. E

AD7703 CS CS t10 t15 HI-Z HI-Z SDATA VDAALTIAD SDATA VDAALTIAD Figure 4.SSC Mode Data Hold Time Figure 5b.SEC Mode Data Hold Time CLKIN DRDY CS t CS 7 t t HI-Z 8 HI-Z 12 SCLK t 11 SCLK t4 t9 t 8 t13 t14 t16 t5 SDATA HI-Z DB19 DB18 DB1 DB0 HI-Z SDATA HI-Z DB19 DB18 DB1 DB0 HI-Z Figure 5a.SEC Mode Timing Diagram Figure 6.SSC Mode Timing Diagram DEFINITION OF TERMS Positive Full-Scale Overrange Linearity Error Positive full-scale overrange is the amount of overhead available This is the maximum deviation of any code from a straight line to handle input voltages greater than +V (for example, noise REF passing through the endpoints of the transfer function. The peaks or excess voltages due to system gain errors in system endpoints of the transfer function are zero-scale (not to be calibration routines) without introducing errors due to overloading confused with bipolar zero), a point 0.5 LSB below the first code the analog modulator or overflowing the digital filter. transition (000 . . . 000 to 000 . . . 001) and full-scale, a point Negative Full-Scale Overrange 1.5 LSB above the last code transition (111 . . . 110 to 111 . . . This is the amount of overhead available to handle voltages below 111). The error is expressed as a percentage of full scale. –V without overloading the analog modulator or overflowing REF Differential Linearity Error the digital filter. Note that the analog input will accept negative This is the difference between any code’s actual width and the voltage peaks even in the Unipolar mode. ideal (1 LSB) width. Differential linearity error is expressed in Offset Calibration Range LSB. A differential linearity specification of ±1 LSB or less In the system calibration modes (SC2 low), the AD7703 calibrates guarantees monotonicity. its offset with respect to the A pin. The offset calibration range IN Positive Full-Scale Error specification defines the range of voltages, expressed as a Positive full-scale error is the deviation of the last code transition percentage of V , that the AD7703 can accept and still accurately REF (111 . . . 110 to 111 . . . 111) from the ideal (V ±3/2 LSB). calibrate offset. REF It applies to both positive and negative analog input ranges and Full-Scale Calibration Range is expressed in microvolts. This is the range of voltages that the AD7703 can accept in the Unipolar Offset Error system calibration mode and still correctly calibrate full scale. Unipolar offset error is the deviation of the first code transition Input Span from the ideal (AGND + 0.5 LSB) when operating in the In system calibration schemes, two voltages applied in sequence Unipolar mode. to the AD7703’s analog input define the analog input range. The Bipolar Zero Error input span specification defines the minimum and maximum This is the deviation of the midscale transition (0111 . . . 111 to input voltages from zero to full scale that the AD7703 can accept 1000 . . . 000) from the ideal (AGND – 0.5 LSB) when operating and still accurately calibrate gain. The input span is expressed in the Bipolar mode. It is expressed in microvolts. as a percentage of V REF. Bipolar Negative Full-Scale Error This is the deviation of the first code transition from the ideal (–V + 0.5 LSB) when operating in the Bipolar mode. REF REV. E –5–

AD7703 PIN CONFIGURATION Table I. Bit Weight Table (2.5 V Reference Voltage) DIP, CERDIP, SOIC Unipolar Mode Bipolar Mode MODE 1 20 SDATA ppm ppm CLKOUT 2 19 SCLK (cid:4)V LSB % FS FS LSB % FS FS CLKIN 3 18 DRDY 0.596 0.25 0.0000238 0.24 0.13 0.0000119 0.12 SC1 4 AD7703 17 SC2 1.192 0.5 0.0000477 0.48 0.26 0.0000238 0.24 DGND 5 TOP VIEW 16 CS 2.384 1.00 0.0000954 0.95 0.5 0.0000477 0.48 DVSS 6 (Not to Scale) 15 DVDD 4.768 2.00 0.0001907 1.91 1.00 0.0000954 0.95 AVSS 7 14 AVDD 9.537 4.00 0.0003814 3.81 2.00 0.0001907 1.91 AGND 8 13 CAL AIN 9 12 BP/UP VREF 10 11 SLEEP PIN FUNCTION DESCRIPTIONS Pin No. Mnemonic Description 1 MODE Selects the Serial Interface Mode. If MODE is tied to DGND, the Synchronous External Clocking (SEC) mode is selected. SCLK is configured as an input, and the output appears without formatting, the MSB coming first. If MODE is tied to +5 V, the AD7703 operates in the Synchronous Self-Clocking (SSC) mode. SCLK is configured as an output, with a clock frequency for f /4 and 25% duty cycle. CLKIN 2 CLKOUT Clock Output to Generate an Internal Master Clock by Connecting a Crystal between CLKOUT and CLKIN. If an external clock is used, CLKOUT is not connected. 3 CLKIN Clock Input for External Clock. 4, 17 SC1, SC2 System Calibration Pins. The state of these pins, when CAL is taken high, determines the type of calibration performed. 5 DGND Digital Ground. Ground reference for all digital signals. 6 DV Digital Negative Supply, –5 V Nominal. SS 7 AV Analog Negative Supply, –5 V Nominal. SS 8 AGND Analog Ground. Ground reference for all analog signals. 9 A Analog Input. IN 10 V Voltage Reference Input, 2.5 V Nominal. This determines the value of positive full scale in the Unipolar REF mode and the value of both positive and negative full scale in the Bipolar mode. 11 SLEEP Sleep Mode Pin. When this pin is taken low, the AD7703 goes into a low power mode with typically 10µW power consumption. 12 BP/UP Bipolar/Unipolar Mode Pin. When this pin is low, the AD7703 is configured for a unipolar input range going from AGND to V . When Pin 12 is high, the AD7703 is configured for a bipolar input range, ±V . REF REF 13 CAL Calibration Mode Pin. When CAL is taken high for more than four cycles, the AD7703 is reset and performs a calibration cycle when CAL is brought low again. The CAL pin can also be used as a strobe to synchronize the operation of several AD7703s. 14 AV Analog Positive Supply, 5 V Nominal. DD 15 DV Digital Positive Supply, 5 V Nominal. DD 16 CS Chip Select Input. When CS is brought low, the AD7703 will begin to transmit serial data in a format determined by the state of the MODE pin. 18 DRDY Data Ready Output. DRDY is low when valid data is available in the output register. It goes high after trans- mission of a word is completed. It also goes high for four clock cycles when a new data-word is being loaded into the output register, to indicate that valid data is not available, irrespective of whether data transmission is complete or not. 19 SCLK Serial Clock Input/Output. The SCLK pin is configured as an input or output, dependent on the type of serial data transmission that has been selected by the MODE pin. When configured as an output in the Synchronous Self-Clocking mode, it has a frequency of f /4 and a duty cycle of 25%. CLKIN 20 SDATA Serial Data Output. The AD7703’s output data is available at this pin as a 20-bit serial word. –6– REV. E

AD7703 GENERAL DESCRIPTION 4. A 1-bit A/D converter (comparator) The AD7703 is a 20-bit A/D converter with on-chip digital 5. A 1-bit DAC filtering, intended for the measurement of wide dynamic range, 6. A digital low-pass filter low frequency signals such as those representing chemical, physical, or biological processes. It contains a charge-balancing ((cid:1)-(cid:2)) ADC, calibration microcontroller with on-chip static S/H AMP COMPARATOR RAM, clock oscillator, and serial communications port. ANALOG LOW-PASS The analog input signal to the AD7703 is continuously sampled FILTER DFIIGLTITEARL at a rate determined by the frequency of the master clock, CLKIN. A charge-balancing A/D converter ((cid:1)-(cid:2) modulator) converts DAC DIGITAL DATA the sampled signal into a digital pulse train whose duty cycle contains the digital information. A six-pole Gaussian digital low-pass filter processes the output of the (cid:1)-(cid:2) modulator and Figure 8.General (cid:1)-(cid:2) ADC updates the 20-bit output register at a 4 kHz rate. The output In operation, the analog signal sample is fed to the subtracter, data can be read from the serial port randomly or periodically at along with the output of the 1-bit DAC. The filtered difference any rate up to 4 kHz. signal is fed to the comparator, whose output samples the differ- ence signal at a frequency many times that of the analog signal +5V sampling frequency (oversampling). ANALOG AVDD DVDD SUPPLY 10(cid:1)F 0.1(cid:1)F 0.1(cid:1)F Oversampling is fundamental to the operation of (cid:1)-(cid:2) ADCs. SLEEP Using the quantization noise formula for an ADC MODE VOLTAGE 2.5V DRDY DATA READY SNR = (6.02 ¥ number of bits + 1.76) dB REFERENCE VRAEFD7703 CS R(TERAADNSMIT) a 1-bit ADC or comparator yields an SNR of 7.78 dB. SCLK SERIAL CLOCK The AD7703 samples the input signal at 16 kHz, which spreads SREALNEGCET BP/UP SDATA SERIAL DATA the quantization noise from 0 kHz to 8 kHz. Since the specified analog input bandwidth of the AD7703 is only 0 Hz to 10 Hz, the CALIBRATE CAL CLKIN noise energy in this bandwidth would be only 1/800 of the total ANALOG AIN CLKOUT quantization noise, even if the noise energy were spread evenly INPUT SC1 throughout the spectrum. It is reduced still further by analog ANALOG AGND SC2 filtering in the modulator loop, which shapes the quantization GROUND 0.1(cid:1)F DGND noise spectrum to move most of the noise energy to frequencies –5V AVSS DVSS 0.1(cid:1)F above 10 Hz. The SNR performance in the 0 Hz to 10 Hz range ANALOG is conditioned to the 20-bit level in this fashion. SUPPLY 10(cid:1)F The output of the comparator provides the digital input for the 1-bit DAC, so the system functions as a negative feedback loop Figure 7.Typical System Connection Diagram that minimizes the difference signal. The digital data that repre- The AD7703 can perform self-calibration using the on-chip sents the analog input voltage is in the duty cycle of the pulse train calibration microcontroller and SRAM to store calibration appearing at the output of the comparator. It can be retrieved as parameters. A calibration cycle may be initiated at any time a parallel binary data-word using a digital filter. using the CAL control input. (cid:1)-(cid:2) ADCs are generally described by the order of the analog Other system components may also be included in the calibra- low-pass filter. A simple example of a first-order, (cid:1)-(cid:2) ADC is tion loop to remove offset and gain errors in the input channel. shown in Figure 8. This contains only a first-order, low-pass filter or integrator. It also illustrates the derivation of the alter- For battery operation, the AD7703 also offers a standby mode native name for these devices: charge-balancing ADCs. that reduces idle power consumption to typically 10 µW. The AD7703 uses a second-order, (cid:1)-(cid:2) modulator and a sophis- THEORY OF OPERATION ticated digital filter that provides a rolling average of the sampled The general block diagram of a (cid:1)-(cid:2) ADC is shown in Figure 8. output. After power-up or if there is a step change in the input It contains the following elements: voltage, there is a settling time that must elapse before valid data is obtained. 1. A sample-hold amplifier 2. A differential amplifier or subtracter 3. An analog low-pass filter REV. E –7–

AD7703 DIGITAL FILTERING The output settling of the AD7703 in response to a step input The AD7703’s digital filter behaves like an analog filter, with a change is shown in Figure 10. The Gaussian response has fast few minor differences. settling with no overshoot, and the worst-case settling time to ±0.0007% is 125 ms with a 4.096 MHz master clock frequency. First, since digital filtering occurs after the analog-to-digital conversion, it can remove noise injected during the conversion process. Analog filtering cannot do this. On the other hand, analog filtering can remove noise superim- 100 posed on the analog signal before it reaches the ADC. Digital filtering cannot do this and noise peaks riding on signals near E 80 U full scale have the potential to saturate the analog modulator and L A V digital filter, even though the average value of the signal is within L A 60 limits. To alleviate this problem, the AD7703 has overrange FIN headroom built into the (cid:1)-(cid:2) modulator and digital filter that OF allows overrange excursions of 100 mV. If noise signals are larger NT 40 E than this, consideration should be given to analog input filtering, C R E or to reducing the gain in the input channel so that a full-scale P 20 input (2.5 V) gives only a half-scale input to the AD7703 (1.25V). This will provide an overrange capability greater than 100% at 0 the expense of reducing the dynamic range by one bit (50%). 0 40 80 120 160 TIME – ms FILTER CHARACTERISTICS Figure 10.AD7703 Step Response The cutoff frequency of the digital filter is f /409600. At the CLK maximum clock frequency of 4.096 MHz, the cutoff frequency USING THE AD7703 of the filter is 10 Hz and the data update rate is 4 kHz. SYSTEM DESIGN CONSIDERATIONS The AD7703 operates differently from successive approximation Figure 9 shows the filter frequency response. This is a six-pole ADCs or integrating ADCs. Since it samples the signal continu- Gaussian response that provides 55 dB of 60 Hz rejection for a ously, like a tracking ADC, there is no need for a start convert 10 Hz cutoff frequency. If the clock frequency is halved to give a command. The 20-bit output register is updated at a 4 kHz rate, 5 Hz cutoff, 60 Hz rejection is better than 90 dB. and the output can be read at any time, either synchronously or asynchronously. 20 0 CLOCKING fCLK = 4MHz The AD7703 requires a master clock input, which may be an exter- –20 nal TTL/CMOS compatible clock signal applied to the CLKIN –40 pin (CLKOUT not used). Alternatively, a crystal of the correct N – dB–60 fCLK = 2MHz fwrehqenu etnhec yc lcoacnk bcier ccuoitn wneilcl tfeudn cbtieotnw eaes na CcrLysKtaIl Nco anntrdo lCleLd KosOciUllaTto,r. GAI–80 Figure 11 shows a simple model of the on-chip gate oscillator –100 and Table II gives some typical capacitor values to be used with various resonators. –120 fCLK = 1MHz –140 R1 –160 5M(cid:3) 1 10 100 FREQUENCY – Hz 2 Figure 9.Frequency Response of AD7703 Filter 10pF C2* gm = 1500(cid:4)MHO X1 Since the AD7703 contains this low-pass filtering, there is a 3 settling time associated with step function inputs, and data will 10pF C1* be invalid after a step change until the settling time has elapsed. AD7703 The AD7703 is, therefore, unsuitable for high speed multiplex- *SEE TABLE II ing, where channels are switched and converted sequentially at high rates, as switching between channels can cause a step change Figure 11.On-Chip Gate Oscillator in the input. However, slow multiplexing of the AD7703 is possible, provided that the settling time is allowed to elapse before data for the new channel is accessed. –8– REV. E

AD7703 Table II. Resonator Loading Capacitors low capacitance/voltage coefficient. The device also achieves low input drift through the use of chopper-stabilized techniques in Resonators C1 (pF) C2 (pF) its input stage. To ensure excellent performance over time and Ceramic temperature, the AD7703 uses digital calibration techniques 200 kHz 330 470 that minimize offset and gain error to typically ±4 LSB. 455 kHz 100 100 1.0 MHz 50 50 AUTOCALIBRATION 2.0 MHz 20 20 The AD7703 offers both self-calibration and system-calibration facilities. For calibration to occur, the on-chip microcontroller Crystal must record the modulator output for two different input condi- 2.000 MHz 30 30 tions. These are the zero-scale and full-scale points. In Unipolar 3.579 MHz 20 20 self-calibration mode, the zero-scale point is V and the 4.096 MHz None None AGND full-scale point is V . With these readings, the microcontroller REF can calculate the gain slope for the input to output transfer The input sampling frequency, output data rate, filter character- function of the converter. In Unipolar mode, the slope factor is istics, and calibration time are all directly related to the master determined by dividing the span between zero and full scale by clock frequency, fCLKIN, by the ratios given in the Specification 220. In Bipolar mode, it is determined by dividing the span by table under Dynamic Performance. Therefore, the first step in 219 since the inputs applied represent only half the total codes. system design with the AD7703 is to select a master clock fre- In both Unipolar and Bipolar modes, the slope factor is saved quency suitable for the bandwidth and output data rate required and used to calculate the binary output code when an analog by the application. input is applied to the device. Table IV gives the output code size after calibration. ANALOG INPUT RANGES System calibration allows the AD7703 to compensate for system The AD7703 performs conversion relative to an externally gain and offset errors. A typical circuit where this might be used supplied reference voltage that allows easy interfacing to ratio- is shown in Figure 12. metric systems. In addition, either unipolar or bipolar input voltage ranges may be selected using the BP/UP input. With System calibration performs the same slope factor calculations BP/UP tied low, the input range is unipolar and the span is as self-calibration but uses voltage values presented by the system (VREF to VAGND), where VAGND is the voltage at the device AGND to the AIN pin for the zero- and full-scale points. There are two pin. With BP/UP tied high, the input range is bipolar and the system calibration modes. span is 2VREF. In the Bipolar mode, both positive and negative The first mode offers system level calibration for system offset full scale are directly determined by VREF. This offers superior and system gain. This is a two step operation. The zero-scale tracking of positive and negative full scale and better midscale point must be presented to the converter first. It must be applied (bipolar zero) stability than bipolar schemes that simply scale to the converter before the calibration step is initiated and remain and offset the input range. stable until the step is complete. The DRDY output from the The digital output coding for the unipolar range is unipolar binary; device will signal when the step is complete by going low. After for the bipolar range it is offset binary. Bit weights for the Unipolar the zero-scale point is calibrated, the full-scale point is applied and Bipolar modes are shown in Table I. and the second calibration step is initiated. Again, the voltage must remain stable throughout the calibration step. ACCURACY The two step calibration mode offers another feature. After the S-D ADCs, like VFCs and other integrating ADCs, do not sequence has been completed, additional offset calibrations can be contain any source of nonmonotonicity and inherently offer performed by themselves to adjust the zero reference point to a no-missing-codes performance. new system zero reference value. This second system calibration The AD7703 achieves excellent linearity by the use of high mode uses an input voltage for the zero-scale calibration point quality, on-chip silicon dioxide capacitors, which have a very but uses the VREF value for the full-scale point. SYSTEM SCLK REF HI SDATA ANALOG SIGNAL AIN MUX CONDITIONING AIN CAL MICRO- SC1 COMPUTER SYSTEM A0 A1 AD7703 SC2 REF LO Figure 12. Typical Connections for System Calibration REV. E –9–

AD7703 Initiating Calibration When self-calibration is completed, DRDY falls and the output Table III illustrates the calibration modes available in the AD7703. port is updated with a data-word that represents the analog input Not shown in the table is the function of the BP/UP pin, which signal. When a system calibration step is completed, DRDY will determines whether the converter has been calibrated to mea- fall and the output port will be updated with the appropriate data sure bipolar or unipolar signals. A calibration step is initiated by value (all 0s for the zero-scale point and all 1s for the full-scale bringing the CAL pin high for at least four CLKIN cycles and point). In the system calibration mode, the digital filter must then bringing it low again. The states of SC1 and SC2 along settle before the output code will represent the value of the with the BP/UP pin will determine the type of calibration to be analog input signal. Tables IV and V indicate the output code performed. All three signals should be stable before the CAL size and output coding of the AD7703 in its various modes. In pin is taken positive. The SC1 and SC2 inputs are latched when these tables, S is the measured system offset in volts and OFF CAL goes high. The BP/UP input is not latched and, therefore, S is the measured system gain at the full-scale point in volts. GAIN must remain in a fixed state throughout the calibration and Span and Offset Limits measurement cycles. Any time the state of the BP/UP is changed, Whenever a system calibration mode is used, there are limits a new calibration cycle must be performed to enable the AD7703 on the amount of offset and span that can be accommodated. to function properly in the new mode. The range of input span in both the Unipolar and Bipolar When a calibration step is initiated, the DRDY signal will go high modes has a minimum value of 0.8 V and a maximum REF and remain high until the step is finished. Table III shows the value of 2(V + 0.1 V). REF number of clock cycles each calibration requires. Once a calibra- The amount of offset that can be accommodated depends on tion step is initiated, it must finish before a new calibration step whether the Unipolar or Bipolar mode is being used. In Unipolar can be executed. In the two step system calibration mode, the mode, the system calibration modes can handle a maximum offset calibration step must be initiated before initiating the gain offset of 0.2 V and a minimum offset of –(V + 0.1 V). calibration step. REF REF Therefore the AD7703 in the Unipolar mode can be calibrated to mimic bipolar operation. Table III. Calibration Truth Table* Calibration Zero-Scale Full-Scale Calibration CAL SC1 SC2 Type Calibration Calibration Sequence Time 0 0 Self-Calibration V V One Step 3,145,655 Clock Cycles AGND REF 1 1 System Offset A First Step 1,052,599 Clock Cycles IN 0 1 System Gain A Second Step 1,068,813 Clock Cycles IN 1 0 System Offset A V One Step 2,117,389 Clock Cycles IN REF *DRDY remains high throughout the calibration sequence. In the Self-Calibration mode, DRDY falls once the AD7703 has settled to the analog input. In all other modes, DRDY falls as the device begins to settle. Table IV. Output Code Size After Calibration 1 LSB Calibration Mode Zero Scale Gain Factor Unipolar Bipolar (V –V ) 2(V –V ) Self-Calibration V V REF AGND REF AGND AGND REF 1048576 1048576 (S –S ) 2(S –S ) System Calibration S S GAIN OFF GAIN OFF OFF GAIN 1048576 1048576 –10– REV. E

AD7703 Table V. Output Coding Input Voltage, Unipolar Mode Input Voltage, Bipolar Mode System Calibration Self-Calibration Output Codes Self-Calibration System Calibration >(SGAIN –1.5 LSB) >(VREF – 1.5 LSB) FFFFF >(VREF –1.5 LSB) >(SGAIN – 1.5 LSB) FFFFF S – 1.5 LSB V – 1.5 LSB V – 1.5 LSB S – 1.5 LSB GAIN REF REF GAIN FFFFE 80000 (S – S )/2 – 0.5 LSB (V – V )/2 – 0.5 LSB V – 0.5 LSB S – 0.5 LSB GAIN OFF REF AGND AGND OFF 7FFFF 00001 S + 0.5 LSB V + 0.5 LSB –V + 0.5 LSB –S + 2 S + 0.5 LSB OFF AGND REF GAIN OFF 0 0000 <(SOFF + 0.5 LSB) <(VAGND + 0.5 LSB) 00000 <(–VREF + 0.5 LSB) <(–SGAIN +2 SOFF + 0.5 LSB) In the Bipolar mode, the system offset calibration range is accordingly. The value of the voltage on the sample capacitor is restricted to ±0.4 V . It should be noted that the span restric- updated at a rate determined by the master clock; therefore, the REF tions limit the amount of offset that can be calibrated. The span amount of offset drift that occurs will be proportional to the range of the converter in Bipolar mode is equidistant around the elapsed time between samples. Thus, to minimize offset drift at voltage used for the zero-scale point. When the zero-scale point higher temperatures, higher CLKIN rates are recommended. is calibrated, it must not cause either of the two endpoints of the Gain drift within the converter depends mainly upon the tem- bipolar transfer function to exceed the positive or the negative perature tracking of the internal capacitors. It is not affected by input overrange points (+V + 0.1) V or (–V + 0.1) V. If REF REF leakage currents so it is significantly less than offset drift. The the span range is set to a minimum (0.8 V ), the offset voltage REF typical gain drift of the AD7703 is less than 40 LSB over the can move +0.4 V without causing the endpoints of the trans- REF specified temperature range. fer function to exceed the overrange points. Alternatively, if the Measurement errors due to offset drift or gain drift can be span range is set to 2V , the input offset cannot move more REF eliminated at any time by recalibrating the converter. Using the than +0.1 V or –0.1 V before an endpoint of the transfer func- system calibration mode can also minimize offset and gain errors tion exceeds the input overrange limit. in the signal conditioning circuitry. Integral and differential linearity are not significantly affected by temperature changes. POWER-UP AND CALIBRATION A calibration cycle must be carried out after power-up to initial- 160 ize the device to a consistent starting condition and correct calibration. The CAL pin must be held high for at least four CLKIN = 4.096MHz clock cycles, after which calibration is initiated on the falling 80 edge of CAL and takes a maximum of 3,145,655 clock cycles s B (approximately 768 ms with a 4.096 MHz clock). See Table III. LS 0 – The type of calibration cycle initiated by CAL is determined by ET S the SC1 and SC2 inputs, in accordance with Table III. FF –80 O Drift Considerations AR The AD7703 uses chopper stabilization techniques to minimize OL–160 P input offset drift. Charge injection in the analog switches and BI leakage currents at the sampling node are the primary sources of –240 offset voltage drift in the converter. Figure 13 indicates the typical offset due to temperature changes after calibration at 25°C. Drift –320 is relatively flat up to 75°C. Above this temperature, leakage –55 –35 –15 5 25 45 65 85 105 125 TEMPERATURE – (cid:2)C current becomes the main source of offset drift. Since leakage current doubles approximately every 10°C, the offset drifts Figure 13. Typical Bipolar Offset vs. Temperature after Calibration at 25°C REV. E –11–

AD7703 INPUT SIGNAL CONDITIONING An RC filter may be added in front of the AD7703 to reduce Reference voltages from 1 V to 3 V may be used with the AD7703, high frequency noise. With an external capacitor added from with little degradation in performance. Input ranges that cannot A to AGND, the following equation will specify the maximum IN be accommodated by this range of reference voltages may be allowable source resistance: achieved by input signal conditioning. This may take the form of 62 gtSiaooinun r ttcooe r aRecdecusoicmsetm aan olcaderagteer ai nspmuatl lveor ltsaiggnea rla rnagneg.e, or passive attenua- RS(MAX)= fCLKIN ¥(CIN +CEXT)¥lnÈÍÍ100mV ¥V(CINC+INCEXT)˘˙˙ If passive attenuators are used in front of the AD7703, care must Í E ˙ be taken to ensure that the source impedance is sufficiently low. ÎÍ ˚˙ The dc input resistance for the AD7703 is over 1 GW. In paral- The practical limit to the maximum value of source resistance is lel with this, there is a small dynamic load that varies with the thermal (Johnson) noise. A practical resistor may be modeled as clock frequency (see Figure 14). an ideal (noiseless) resistor in series with a noise voltage source or in parallel with a noise current source: VIN R1 AIN AD7703 V n = 4kTRf Volts i n = 4kTf/R Amperes R2 CEXT 1G(cid:3) CIN where k is Boltzmann’s constant (1.38 ¥ 10–23 J/K), and T is 10pF temperature in degrees Kelvin (°C + 273). VOS 100mV Active signal conditioning circuits such as op amps generally do AGND not suffer from problems of high source impedance. Their open- loop output resistance is normally only tens of ohms and, in any case, most modern general-purpose op amps have sufficiently fast Figure 14. Equivalent Input Circuit and Input Attenuator closed-loop settling time for this not to be a problem. Offset volt- Each time the analog input is sampled, a 10 pF capacitor draws a age in op amps can be eliminated in a system calibration routine. charge packet of maximum 1 pC (10 pF ¥ 100 mV) from the Antialias Considerations analog source with a frequency f /256. For a 4.096 MHz CLKIN The digital filter of the AD7703 does not provide any rejection CLKIN, this yields an average current draw of 16 nA. After at integer multiples of the sampling frequency (nf /256, each sample, the AD7703 allows 62 clock periods for the input CLKIN where n = 1, 2, 3 . .. ). voltage to settle. The equation that defines settling time is With a 4.096 MHz master clock, there are narrow (±10 Hz) V O =VIN[1–e–t/RC] bands at 16 kHz, 32 kHz, 48 kHz, and so on, where noise passes where V , is the final settled value, V , is the value of the input unattenuated to the output. O IN signal, R is the value of the input source resistance, and C is the However, due to the AD7703’s high oversampling ratio of 800 10 pF sample capacitor. The value of t is equal to 62/fCLKIN. (16 kHz to 20 Hz), these bands occupy only a small fraction of The following equation can be developed, which gives the maxi- the spectrum, and most broadband noise is filtered. mum allowable source resistance, R , for an error of V : S(MAX) E The reduction in broadband noise is given by 62 R S(MAX) = fCLKIN ¥(10 pF)¥ln(100mV /VE) e out =ein 2fC/fS =0.035ein where e and e are rms noise terms referred to the input, f is Provided the source resistance is less than this value, the analog in out C the filter –3 dB corner frequency (f /409600), and f is the input will settle within the desired error band in the requisite 62 CLKIN S sampling frequency (f /256). clock periods. Insufficient settling leads to offset errors. These CLKIN can be calibrated in system calibration schemes. Since the ratio of f to f is fixed, the digital filter reduces S CLKIN broadband white noise by 96.5% independent of the master If a limit of 600 nV (0.25 LSB at 20 bits) is set for the maximum clock frequency. offset voltage, then the maximum allowable source resistance is 125 kW from the above equation, assuming that there is no external stray capacitance. –12– REV. E

AD7703 VOLTAGE REFERENCE CONNECTIONS provide rejection of broadband noise on the power supplies, The voltage applied to the V pin defines the analog input except at integer multiples of the sampling frequency. There- REF range. The specified reference voltage is 2.5 V, but the AD7703 fore, the two analog supplies should be individually decoupled will operate with reference voltages from 1 V to 3 V with little to AGND using 100 nF ceramic capacitors to provide power degradation in performance. supply noise rejection at these frequencies. The two digital supplies should similarly be decoupled to DGND. The reference input presents exactly the same dynamic load as the analog input, but in the case of the reference input, source The positive digital supply (DV ) must never exceed the positive DD resistance and long settling time introduce gain errors rather analog supply (AV ) by more than 0.3 V. Power supply sequenc- DD than offset errors. Fortunately, most precision references have ing is, therefore, important. If separate analog and digital supplies sufficiently low output impedance and wide enough bandwidth are used, care must be taken to ensure that the analog supply is to settle to the required accuracy within 62 clock cycles. powered up first. The digital filter of the AD7703 removes noise from the reference It is also important that power is applied to the AD7703 before input, just as it does with noise at the analog input, and the same signals at V , A , or the logic input pins in order to avoid REF IN limitations apply regarding lack of noise rejection at integer any possibility of latch-up. If separate supplies are used for multiples of the sampling frequency. Note that the reference the AD7703 and the system digital circuitry, the AD7703 should should be chosen to minimize noise below 10 Hz. The AD7703 be powered up first. typically exhibits 1.6 LSB rms noise in its measurements. This A typical scheme for powering the AD7703 from a single set of specification assumes a clean reference. Many monolithic band gap ±5 V rails is shown in Figure 7. In this circuit, AV and DV references are available, which can supply the 2.5 V needed for DD DD are brought along separate tracks from the same 5 V supply. the AD7703. However, some of these are not specified for noise, Thus, there is no possibility of the digital supply coming up especially in the 0.1 Hz to 10 Hz bandwidth. If the reference noise before the analog supply. in this bandwidth is excessive, it can degrade the performance of the AD7703. Recommended references are the AD580 and the SLEEP MODE LT1019. Both of these 2.5 V references typically have less than The low power standby mode is initiated by taking the SLEEP 10 µV p-p noise in the 0.1 Hz to 10 Hz band. input low, which shuts down all analog and digital circuits and reduces power consumption to 10 µW. When coming out of POWER SUPPLIES AND GROUNDING SLEEP mode, it is sometimes possible (when using a crystal to AGND is the ground reference voltage for the AD7703, and is generate CLKIN, for example) to lose the calibration coeffi- completely independent of DGND. Any noise riding on the AGND cients. Therefore, it is advisable as a safeguard to always do a input with respect to the system analog ground will cause con- calibration cycle after coming out of SLEEP mode. version errors. AGND should, therefore, be used as the system ground and also as the ground for the analog input and the DIGITAL INTERFACE reference voltage. The AD7703’s serial communications port allows easy inter- The analog and digital power supplies to the AD7703 are inde- facing to industry-standard microprocessors. Two different pendent and separately pinned out to minimize coupling between modes of operation are available, optimized for different types analog and digital sections of the device. The digital filter will of interface. REV. E –13–

AD7703 Synchronous Self-Clocking Mode (SSC) and the data-word currently in the output register will be trans- The SSC mode (MODE pin high) allows easy interfacing to mitted, MSB first. After the LSB has been transmitted, DRDY serial-parallel conversion circuits in systems with parallel data will go high until the new data-word becomes available. If CS, communication. This mode allows interfacing to 74XX299 having been brought low, is taken high again at any time during Universal Shift registers without any additional decoding. The data transmission, SDATA and SCLK will go three-state after SSC mode can also be used with microprocessors such as the the current bit finishes. If CS is subsequently brought low, 68HC11 and 68HC05, which allow an external device to clock transmission will resume with the next bit during the subse- their serial port. quent digital computation period. If transmission has not been initiated and completed by the time the next data-word is avail- Figure 15 shows the timing diagram for the SSC mode. Data is able, DRDY will go high for four clock cycles then low again as clocked out by an internally generated serial clock. The AD7703 the new word is loaded into the output register. divides each sampling interval into 16 distinct periods. Eight periods of 64 clock pulses are for analog settling and eight peri- A more detailed diagram of the data transmission in the SSC ods of 64 clock pulses are for digital computation. The status of mode is shown in Figure 16. Data bits change on the falling CS is polled at the beginning of each digital computation period. If edge of SCLK and are valid on the rising edge of SCLK. it is low at any of these times, then SCLK will become active 1024 CLKIN CYCLES 64 CLKIN 64 CLKIN CYCLES CYCLES INTERNAL ANALOG TIME 0 DIGITAL TIME 0 DIGITAL TIME 7 STATUS 72 CLKIN CYCLES DRDY (O) CS POLLED CS (I) HI-Z HI-Z SCLK (O) MSB LSB HI-Z HI-Z SDATA (O) Figure 15. Timing Diagram for SSC Transmission Mode CLKIN (I) 72 CLKIN CYCLES DRDY (O) CS (I) HI-Z HI-Z SDATA (O) DB19 (MSB) DB18 DB17 DB2 DB1 DB0 (LSB) HI-Z HI-Z SCLK (O) Figure 16. SSC Mode Showing Data Timing Relative to SCLK –14– REV. E

AD7703 Synchronous External Clock Mode (SEC) DIGITAL NOISE AND OUTPUT LOADING The SEC mode (MODE pin grounded) is designed for direct As mentioned earlier, the AD7703 divides its internal timing interface to the synchronous serial ports of industry-standard into two distinct phases, analog sampling and settling and digi- microprocessors such as the 68HC11 and 68HC05. The SEC tal computation. In the SSC mode, data is transmitted only mode also allows customized interfaces, using I/O port pins, to during the digital computation periods, to minimize the effects microprocessors that do not have a direct fit with the AD7703’s of digital noise on analog performance. In the SEC mode, data other mode. transmission is externally controlled, so this automatic safeguard does not exist. To compensate, synchronize the AD7703 to the As shown in Figure 17, a falling edge on CS enables the serial digital system clock via CLKIN when used in the SEC mode. data output with the MSB initially valid. Subsequent data bits change on the falling edge of an externally supplied SCLK. After Whatever mode of operation is used, resistive and capacitive the LSB has been transmitted, DRDY and SDATA go three-state. loads on digital outputs should be minimized in order to reduce If CS is low and the AD7703 is still transmitting data when a crosstalk between analog and digital portions of the circuit. For new data-word becomes available, the old data-word continues this reason, connection to low power CMOS logic such as one to be transmitted and the new data is lost. of the 4000 series or 74C families is recommended. If CS is taken high at any time during data transmission, SDATA will go three-state immediately. If CS returns low, the AD7703 will continue transmission with the same data bit. If transmis- sion has not been initiated and completed by the time the next data-word becomes available, and if CS is high, DRDY returns high for four clock cycles, then falls as the new word is loaded into the output register. DRDY (O) CS (I) SCLK (O) HI-Z HI-Z SDATA (O) DB19 (MSB) DB18 DB17 DB2 DB1 DB0 (LSB) Figure 17. Timing Diagram for SEC Mode REV. E –15–

AD7703 OUTLINE DIMENSIONS 20-Lead Plastic Dual In-Line Package [PDIP] 20-Lead Ceramic Dual In-Line Package [CERDIP] (N-20) (Q-20) Dimensions shown in inches and (millimeters) Dimensions shown in inches and (millimeters) 0.985 (25.02) 0.005 0.098 (2.49) 0.965 (24.51) (0.13) MAX 0.310 (7.87) E) 0.945 (24.00) 00..229855 ((77..4294)) MPIINN 1 20 11 0.220 (5.59) 4/03( 20 11 0.275 (6.99) 1 10 0– – 0.180 (4M.5A7X) 1 0.015 (0.38) M10IN 000...333210500 (((877...286672))) 00..115305 ((33..8413)) 0.200 (5M.0A8X) 1.060 (26.92) MAX 00..000M61.I105N5 ((010 ..(53328.8))1) 00..322900 ((87..1337)) C01165 0.120 (3.05) 0.015 (0.38) 0.200 (5.08) 15 0.008 (0.20) 0.150 (3.81) 0.125 (3.18) 0.100 0.070 (1.78)SEATING 0 0.130 (3.30) 0.015 (0.38) 0.023 (0.58) (2.54) 0.030 (0.76)PLANE 0.110 (2.79) 000...000211284 (((000...543666))) (0B2.1.S50C40) 000...000654005 (((111...521274))) SPELAANTIENG 00..001008 ((00..2250)) 0.0C(1IN4O N(P0TA.3RR6OE)LNLTIHNEGS DEISM)E ABNRSSECIO RNOSU ANRDEE DIN-O INFFC HINECSH; MEIQLULIIMVAELTEENRTSS D FIMOERNSIONS COMPLIANT TO JEDEC STANDARDS MO-095-AE REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN 20-Lead Standard Small Outline Package [SOIC] Wide Body (R-20) Dimensions shown in millimeters and (inches) 13.00 (0.5118) 12.60 (0.4961) 20 11 7.60 (0.2992) 7.40 (0.2913) 10.65 (0.4193) 1 10 10.00 (0.3937) 2.65 (0.1043) 0.75 (0.0295) 0.30 (0.0118) 2.35 (0.0925) 0.25 (0.0098)(cid:2) 45(cid:1) 0.10 (0.0039) 8(cid:1) COPL0A.1N0ARITY (0B1.0.S25C700) 00..5313 ((00..00210310)) SPELAANTIENG 00..3223 ((00..00102961)) 0(cid:1) 10..2470 ((00..00510507)) COMPLIANT TO JEDEC STANDARDS MS-013AC CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN Revision History Location Page 4/03—Data Sheet changed from REV. D to REV. E. Updated format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Universal Changes to SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 Updated OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 –16– REV. E

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